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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1

A 9-GS/s 1.125-GHz BW Oversampling

Continuous-Time Pipeline ADC
Achieving −164-dBFS/Hz NSD
Hajime Shibata, Member, IEEE, Victor Kozlov, Member, IEEE, Zexi Ji, Student Member, IEEE,
Asha Ganesan, Member, IEEE, Haiyang Zhu, Member, IEEE, Donald Paterson, Member, IEEE,
Jialin Zhao, Member, IEEE, Sharvil Patil, Member, IEEE, and Shanthi Pavan, Senior Member, IEEE

Abstract— An oversampled continuous-time (CT) pipeline

ADC clocked at 9 GHz achieving 1.125-GHz bandwidth
and −164 dBFS/Hz average small-signal noise density is
presented. In contrast to traditional discrete-time (DT) pipeline
ADCs, the system processes the signals in CT form throughout
all the pipeline stages and thus sampling-induced artifacts such
as aliasing and high-peak ADC driving current are mitigated.
Despite the oversampled nature of the ADC, its digitization
bandwidth is on par with that of traditional non-interleaved
DT pipeline ADCs since CT signal processing is not constrained
by settling time requirements. The ADC was fabricated in a
28-nm CMOS process technology and consumes 2.3 W.
Index Terms— Analog-to-digital converter, continuous-
time (CT) ADC, oversampling ADC, pipeline ADC, residue
cancellation. Fig. 1. DT and CT  ADC input structures.

I. I NTRODUCTION
introduces artifacts such as signal aliasing and noise folding,
T HE advance of digital wireless and wired communica-
tion systems including fifth generation mobile networks
and data over cable service interface specification (DOCSIS)
and requires a high-peak ADC driving current to charge the
sampling capacitor. To mitigate these issues, the ADC is
now requires approximately 1 GHz of digitization bandwidth. typically driven by an anti-aliasing filter followed by a buffer
In such systems, maximizing the ADC’s dynamic range (sub- providing the peak driving current. These two blocks increase
ject to a power constraint) maximizes the receiver’s perfor- both system power consumption and system noise.
mance. Although  ADCs are known to provide an efficient In high-dynamic-range and wide-bandwidth applications,
tradeoff between dynamic range and power consumption, an active anti-aliasing filter is especially costly in terms of
the need for oversampling ratios (OSRs) greater than 8 has, power consumption. Therefore off-chip LC or surface acoustic
until now, put them at a disadvantage compared to Nyquist wave passive filters are common in these applications, which
ADCs in terms of raw digitization bandwidth [1]–[5]. unfortunately prevent on-chip integration of the entire signal
In typical Nyquist ADCs, the input signal is sampled at processing chain.
the front end by a switched-capacitor circuit, and all internal The ADC driver often requires a significant fraction of the
signals are processed in discrete time (DT). The sampler ADC’s power consumption [6]–[9]. For example, the buffer
used in [8] requires 282 of 513 mW total power dissipation.
Manuscript received April 22, 2017; revised July 12, 2017; accepted Part of the reason is that the high-speed buffer is usually a
August 14, 2017. This paper was approved by Guest Editor Seung-Tak Ryu. Class-A or Class-AB amplifier, and thus the high-peak current
(Corresponding author: Hajime Shibata.)
H. Shibata, V. Kozlov, and S. Patil are with Analog Devices Canada, needed by a switched-capacitor sampler necessitates higher
Toronto, ON M5G2C8, Canada (e-mail: Hajime.Shibata@analog.com). power consumption.
Z. Ji was with Analog Devices Canada, Toronto, ON M5G2C8, Canada. In  ADCs, both issues are alleviated by replacing the
He is now with the Massachusetts Institute of Technology, Cambridge,
MA 02139 USA. DT loop filter with a continuous-time (CT) implementation, as
A. Ganesan, H. Zhu, and D. Paterson are with Analog Devices Inc., shown in Fig. 1. In the CT implementation, sampling occurs
Wilmington, MA 01887 USA. at the end of the gain chain, thereby providing inherent anti-
J. Zhao is with Analog Devices Inc., San Jose, CA 95134 USA.
S. Pavan is with Analog Devices Canada, Toronto, ON M5G2C8, Canada, aliasing. Also, the resistive input structure reduces the peak
on leave from the Indian Institute of Technology, Madras, Chennai 600036, ADC driving current.
India. An ADC driving current comparison between CT and DT
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. structures is shown in Fig. 2. A DT system requires the
Digital Object Identifier 10.1109/JSSC.2017.2747128 charging current to almost decay to zero in a half clock cycle,
0018-9200 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE JOURNAL OF SOLID-STATE CIRCUITS

node because CT systems are not constrained by settling

time requirements [4], [7], [13]. As a result, the digitization
bandwidth of this non-interleaved CT pipeline is comparable
to that of non-interleaved DT pipeline ADCs.
The paper is organized as follows. In Section II, an oversam-
pling CT pipeline ADC is introduced and its signal processing
is discussed. The circuit implementation details are explained
in Section III. Measurement results and comparisons with
state-of-the-art ADCs are presented in Section IV. Conclusions
are given in Section V.

II. OVERSAMPLED C ONTINUOUS -T IME P IPELINED

A NALOG - TO -D IGITAL C ONVERSION
Fig. 2. DT and CT ADCs driving current comparison. The same SNR A. Signal Processing in Pipeline ADCs
requires the same charge transfer per cycles.
A block diagram of a generic (N +1)-stage pipeline ADC is
shown in Fig. 3. N linear cascade-connected gain blocks are
driven by the input signal and the DAC output signals. The
typically necessitating a time constant τ that is less than 10%
output (X n ) of the nth stage drives both the (n +1)th stage and
of the clock cycle. Consequently, to achieve the same input-
a coarse quantizer (flash ADC) whose digital output drives the
referred noise in the DT and CT cases, calculations show [10]
(n + 1)th DAC. For the sake of simplicity, let us assume that
that the peak current in the DT system is approximately
each stage has the same transfer function H .
10 times higher than that in the CT system. To first order,
Based on the block diagram in Fig. 3, the first and the
the same ratio applies to the power consumption of the
(n + 1)th stage output signals X 1 and X n+1 can be written as
operational amplifiers inside the ADC.
An important observation regarding the input structures X 1 = H (X 0 − G DAC D0 ) (1)
in Fig. 1 is that the CT benefits belong to the input struc- X n+1 = H (X n − G DAC Dn ) (2)
ture itself, not the ADC architecture. This suggests that the
other ADC architectures might similarly benefit by replacing where G DAC is a transfer function of the DAC and
DT blocks with CT ones. n = 1, …, N. The coarse quantizer in the last stage quantizes
Gubbins et al. [11] reported a CT input pipeline ADC, the signal X N to the digital signal D N with a quantization
which consists of a CT residue-generation stage followed noise e N . Thus
by a traditional DT pipeline ADC. This pioneering work
DN = X N + eN . (3)
demonstrated the CT benefits in a pipeline ADC architecture.
A prediction filter was introduced to align a timing mismatch The purpose of the ADC is to reconstruct the analog input
between the forward path and the feedforward path. However, signal X 0 in the digital domain using the digital signals
the use of the prediction filter is not practical for wide- D0 , …, D N . Substituting (2) and (3) into (1) and solving for
bandwidth applications because the positive phase needed to the input signal X 0 yields
realize the prediction has to be rolled back to a negative phase

N−1
Dk DN eN
at a high frequency to satisfy causality, which in turn requires a X 0 = G DAC + N − N. (4)
wideband opamp. Also, the rolled-back phase introduces much Hk H H
k=0
larger phase error for out-of-band signals; the anti-alias filter
Within the bandwidth given by OSR = 4, |G DAC | ≈ 1. Thus
is obliged to attenuate these signals to prevent out-of-range
the input signal can be estimated as
residues. Furthermore, the high-pass magnitude response of
Gubbins’s prediction filter also makes the anti-aliasing filter  Dk
N−1   N
1 DN eN Dk eN
preceding the ADC more challenging to implement. Last, X0 = k
+ N
− N
≈ k
− N . (5)
H G DAC H H H H
the gain of the first stage in Gubbins’s design is limited to k=0 k=0
1.3 even with a 9-level quantizer. This low gain diminishes As shown in (5), the input signal X 0 can be reconstructed
the benefits of pipelining since the noise and nonlinearity of within an error of e N /H N using the DAC driving signals,
the back-end stages are suppressed by the first-stage gain. D0 , D1, , …, D N−1 , and the output signal of the final
This paper presents a CT pipeline ADC which processes quantizer, D N .
the input and residue signals with CT circuitry throughout the In traditional pipeline ADCs, this signal processing through
entire pipeline [12]. The combination of CT signal process- the gain blocks is performed in DT. However, this processing
ing with the pipeline architecture realizes an ADC system does not require any DT properties, and the same signal
inheriting the CT benefits of low-peak driving current and processing can be performed in CT. With CT signal process-
inherent anti-aliasing while achieving a digitization bandwidth ing, the stage gain H has to be linear and time invariant,
more than double that of existing CT  ADCs. Empirically, which requires the stage output signals X 1 , X 2 , …, X N to be
the clock frequency of a CT system can be approximately within the linear range of the amplifiers used to generate them.
three times that of a DT system operating in the same process In practice, this requirement is met if each stage output lies
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SHIBATA et al.: 9-GS/s 1.125-GHz BW OVERSAMPLING CT PIPELINE ADC 3

Fig. 3. Signal processing in pipeline ADCs.

Fig. 4. Stages 1 and 2 of a DT pipeline ADC.

Fig. 6. V -to-I , DAC output, and residue current signals in the primitive
CT pipeline ADC shown in Fig. 5.

This problem has two sources: 1) transfer function mismatch

between the main V -to-I signal and the flash-DAC paths [11]
and 2) DAC image signals. These two issues are discussed in
Fig. 5. Primitive CT pipelined ADC derived by removing S/H block from
the DT pipeline ADC in Fig. 4. detail in the following.
To illustrate the transfer function mismatch issue, the three
current signals, the input current IVI , the DAC output current
within the input full scale of the subsequent stage at all-time IDAC and their difference, the residue current IRES , which is
instants. By fulfilling this requirement, a CT pipeline ADC the difference between the input, and the DAC currents, are
can be constructed. depicted in Fig. 6. The system is clocked at 10 GHz and a
1-GHz full-scale sinusoidal signal is applied as an input signal.
Pipeline ADCs use feedforward cancellation to generate
B. Oversampling Continuous-Time Pipeline ADC
a residue, requiring that the signal through the V -to-I path
In this section, a CT pipeline stage structure is introduced and the DAC output signal be matched. However, as shown
using a DT pipeline stage structure as a starting point and in Fig. 6, the phase mismatch between the input and the
modifying the structure to satisfy the linear and time-invariant DAC output signal can cause a large residue that exceeds the
requirement. input signal amplitude. This phase mismatch occurs because
A DT pipeline ADC can be implemented, as shown the flash-DAC path effectively has a 1.5 TCK delay, which
in Fig. 4. Note that in contrast to the conventional arrangement consists of TCK delay for the flash-to-DAC logic propagation
in which each stage is implemented with switched-capacitor and 0.5 TCK effective delay by the non-return-to-zero DAC
circuits, the circuit in Fig. 4 uses CT residue amplification and waveform, whereas the main V -to-I path has no delay.
each stage has a sampler at its input. Removing the samplers The main V -to-I path has no delay since its transfer
result in the primitive CT pipeline ADC shown in Fig. 5. Since function is simply
the input sampler is removed, sampling-induced artifacts are
1
alleviated. This configuration works when the input signal G 0 (s) = . (6)
is small and its frequency is low. However, when a high- R
frequency large-amplitude signal is provided, the back-end In contrast, in the flash-DAC path, the DAC updates one clock
stage saturates, and the overall ADC performance deteriorates. cycle after the flash samples the input, and the DAC holds the
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4 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 7. Intermediate CT pipeline stage with a delay alignment.

Fig. 9. Input signal, DAC output signal, and residue signal in the frequency
domain.

Fig. 8. Input, DAC output, and residue current signals in the intermediate
CT pipeline ADC shown in Fig. 7.

Fig. 10. CT pipeline stage with delay alignment and low-pass filtering of
same value for an additional clock cycle. The net flash-DAC the DAC image.
transfer function is then represented as
IFS 1 − exp(−TCK s)
G FD (s) = exp(−TCK s) (7) envelope due to the non-return-to-zero time-domain DAC
VFS s
output waveform. In the residue waveform, the input signal
where IFS and VFS are DAC and flash full-scale ranges, component at 1 GHz is well suppressed. However, the DAC
respectively, and are designed such that VFS /IFS = R in order image signals remain without cancellation and dominate the
to cancel the input signal component in the residue. residue amplitude, as shown in Fig. 9.
This delay mismatch issue has already been discussed [11] In CT ADCs, the input signal can be reconstructed by
and resolved by attaching a prediction filter or a negative-delay digitizing the first Nyquist component alone; higher Nyquist
filter at the flash input. However, extending the bandwidth components are not necessary. Therefore, these DAC images
of negative-delay filters is difficult due to the requirement of can simply be removed by introducing low-pass filtering in the
causality. This limitation can be overcome by using a positive residue-amplifying transimpedance amplifier (TIA), as shown
delay in the V -to-I path, as shown in Fig. 7 [4], [14], [15]. in Fig. 10. The unity-gain frequency of the low-pass filter
This approach guarantees wide-bandwidth operation since a can be set at f S /2. With first-order low-pass filtering, the
positive delay can be implemented by passive components stage output voltage is bounded as shown in Fig. 11 and the
such as a transmission line or passive all-pass filters. By intro- saturation of the TIA can be avoided. A CT pipeline ADC
ducing the delay, the input signal and the DAC signal are now can then be made by cascading a sufficient number of these
well aligned and the residue remains small, especially in the stages.
middle of the clock cycle, as shown in Fig. 8. The input-referred quantization and the thermal noise con-
In a DT pipeline ADC, the residue amplitude is ideally tributions of the back-end stages increase with frequency due
bounded within 1/M of the full scale if an M-level flash and to the low-pass characteristics of the TIA. Therefore, a CT
DAC are used for the cancellation. However, the CT residue pipeline ADC behaves like a noise-shaped oversampled ADC.
amplitude at the clock edges is still higher than in the DT case Since each stage provides high gain up to about a quarter of
due to the saw-tooth residue waveform. the Nyquist frequency, an OSR of 4 is practical.
To understand the CT residue better, consider the frequency-
domain representations of the input signal, the DAC output
signal, and the residue signal shown in Fig. 9. The DAC C. Delay Line and Stage Transfer Function
generates a quantized version of the input signal in the first To realize the required 1.5 TCK delay with a transmission
Nyquist zone along with the image signals following a sinc line for a system clocked at f S = 1/TCK = 10 GHz, the trace
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SHIBATA et al.: 9-GS/s 1.125-GHz BW OVERSAMPLING CT PIPELINE ADC 5

Fig. 11. Time-domain waveform of the input current signal, DAC output
current signal, and the stage voltage output signal with and without the Fig. 13. Phase comparison of V -to-I paths, G DLY,RC and G DLY,LC , and
low-pass filtering. flash-DAC transconductance G FD .

Fig. 12. (a) RC lattice and (b) four-stage LC-lattice delay line structures
providing a differential impedance of R.
Fig. 14. Residue cancellation transfer functions G RES,LC and G RES,RC
normalized by a fixed conductance G 0 .
length on silicon is
1.5TCK c The quality of the cancellation can be evaluated by the
lTL = √ = 22 mm (8)
εr magnitude response of the residue signal provided into the
where c is the speed of light and εr is the relative dielectric TIA summing node. Such residue transfer function can be
constant of silicon. This length is not practical for integration represented as
even if the trace is folded. To make the implementation practi- G RES (s) = G DLY (s)−G FD (s) (11)
cal, a cascaded LC-lattice delay line or an RC-lattice delay line,
shown in Fig. 12, can be used. The transconductance transfer where G DLY (s) is either G DLY,LC(s) or G DLY,RC(s) depending
functions of the LC and RC delay structures in Fig. 12 are on the type of the delay element. The frequency responses
 s 4
of (11) normalized by G 0 (s) are shown in Fig. 14. At the
1 1− √LC frequency f S /8, which is the band edge frequency for
G DLY,LC (s) = (9) OSR = 4, the LC and RC-lattice delay yield gains
R 1+ √s
LC
of −31 and −19 dB, respectively. These residue signal mag-
1 1 − 4sRC
G DLY,RC (s) = . (10) nitudes after cancellation are close to the quantization noise
R 1 + 4sRC level of a 4-bit quantizer (about −24 dB), so either the LC
The phase responses of (9), (10), and G FD (s) normalized by delay line or the RC delay line could be used, although the LC
G 0 (s) are shown in Fig. 13. It can be confirmed that both filter would be preferred for its better out-of-band cancellation
G DLY,RC(s) and G DLY,LC(s) match to G FD (s) for frequencies provided the increased silicon area is acceptable.
below f S /8. The LC lattice can be cascaded to extend the The cancellation error increases toward high frequencies
phase-matched bandwidth beyond that of the RC-lattice delay since the sinc roll off of G FD (s) is not matched by the
line. The RC lattice, however, can be implemented with less magnitude response of the V -to-I delay path. The low-pass
silicon area. filtering introduced in the TIA in Section II-B helps reduce
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6 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 16. Input signal, DAC output signal, and residue signal in frequency
Fig. 15. Residue amplifier transfer function G 0 HTIA , and the overall stage domain with input signal at 0.9 f S .
transfer functions TSTG = G RES HTIA with the RC lattice, G RES,RC HTIA ,
and LC lattice, G RES,LC HTIA .

this component of the residue. The frequency response of the

overall stage transfer function
TSTG (s) = G RES (s)HTIA (s) (12)
where HTIA (s) is the transimpedance of the TIA is also shown
in Fig. 15. It is assumed that the residue amplifier has a first-
order low-pass filtering transfer function G 0 (s)HTIA (s) with
dc gain of 8 and a unity-gain frequency of f S /2. With this
low-pass filtering, the main image components at f S in the
first stage are suppressed by 6 dB.
As discussed in Section II-A, X 1 , X 2 , . . . , X N have to be
bounded within the full scale of the next stage to make a
CT pipeline ADC properly operate. Using the stage transfer
function TSTG (s), the last stage output can be represented as
Fig. 17. Maximum out-of-band blocker level over frequencies using a
N
X N (s) = TSTG (s) X 0 (s) (13) behavioral CT pipeline ADC. Out-of-band region and the regions aliased back
to the out-of-band region are grayed out.
for an (N + 1)-stage CT pipeline ADC assuming the quan-
tization noise is sufficiently low. Therefore in the case of an
this is similar to the case in Fig. 9, but here the input signal
infinitely cascaded CT pipeline ADC, G RES (s) and HTIA (s)
is 0 dBFS and is located at 0.9 f S (i.e., in the second Nyquist
must satisfy |TSTG (s)| ≤ 1 in the first Nyquist zone for X N (s)
zone). The flash in Stage 1 down converts/aliases the input
to be bounded. In practice, a weak peaking of |TSTG (s)| can
signal to a 0-dBFS signal at 0.1 f S , and this aliased signal is
be acceptable, such as 4-dB gain peaking at 0.4 f S with the
injected into the main path by the DAC in Stage 1. The injected
RC-lattice-based residue generation, because of the following
alias is not cancelled by the signal in the forward path (as it is
three factors. First, the number of stages connected in cascade
at 0.9 f S ) and propagates into the residue current; it is clearly
is not large. Second, the stage input signal is wideband only
visible in the spectrum of the residue in Fig. 16. This large
in the back-end stages. Last, a second (parasitic) pole reduces
alias falls in the bandwidth of the Stage-1 TIA and is thus
the peaking.
amplified by it; this saturates the TIA output and degrades
the ADC output. The case described in the above example
D. Out-of-Band Blocker Immunity extends to all instances where a large-amplitude alias of the
A CT pipeline ADC can be designed to digitize signals input signal falls in the bandwidth of the TIA. Such aliases
up to 0 dBFS at any frequency in the first Nyquist zone result when large (e.g., 0 dBFS) out-of-band signals located
if |T STG (s)| ≤ 1 is satisfied as discussed in Section II-C. at multiples of f S are applied. The CT pipeline ADC clearly
However, for inputs in the second and higher Nyquist zones, cannot withstand such blockers, and they have to be suppressed
the residue cancellation does not hold. Thus, the maximum up-front to prevent saturation of the ADC internal nodes.
allowable input amplitude has to be reduced to avoid saturation The above point was verified through simulations. The
of the ADC internal nodes, X 1 , X 2 , . . . , X N , especially for simulated maximum allowable input signal level that avoids
inputs whose frequencies are multiple of f S . saturation of internal nodes in a behavioral CT pipeline ADC
Fig. 16 shows exemplary plots of the input signal, the DAC is shown in Fig 17. The behavioral ADC consists of five stages
output signal, and the residue signal in the frequency domain; including four residue cancellation stages and one flash stage.
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SHIBATA et al.: 9-GS/s 1.125-GHz BW OVERSAMPLING CT PIPELINE ADC 7

Fig. 18. Input signal reconstruction in the digital domain.

The residue cancellation stage has a dc gain of 18 dB, defined as

17-level quantizer, and first-order low-pass filtering TIA as 1
in Section II-B. The flash generates a digital output code TDRF(N),CT (s) = (16)
TF (s) G DAC (s)HTIA(s)
within ±8, and the system is assumed to be saturated when any
stage generates the maximum code of 8 for three consecutive and the intermediate reconstruction filters have transfer func-
cycles. As shown in Fig. 17, the ADC digitizes any signal up to tions given by
0 dBFS in the first Nyquist zone, but the maximum allowable 1
TDRF(k),CT (s) = (17)
input signal level decreases in the second Nyquist zone as we G DLY (s)HTIA (s)
move toward f S . This, as discussed above, is expected: inputs where k = 1, 2, …, N − 1. Then, for an (N + 1)-stage CT
near f S create aliases that fall in the bandwidth of the TIA, pipeline ADC, the reconstructed output Y0 is the cascaded
and these aliases, after being gained up by the TIA, saturate sum of the stage outputs filtered by the appropriate number of
the subsequent stages. The maximum allowable signal level reconstruction filter blocks; it is expressed as
recovers between f S to 1.5 f S , since inputs near 1.5 f S create
aliases that fall out of the TIA bandwidth and are not amplified Y0 = D0 +TDRF1,CT D 1 + TDRF1,CT TDRF2,CT D2
by the TIA; thus no overload occurs. + . . . + TDRF1,CT · · ·TDRF(N),CT D N
This out-of-band blocker immunity behavior can be  
N k
improved by pre-filtering the ADC input. A first-order pre- = D0 + Dk TDRF(i),CT . (18)
filter with the pole located at f S /8 reduces the amplitude of k=1 i=1
the signal that is aliased back to f S /8 by 17 dB. In practice,
Substituting (14) to (17) into (18) yields
the flash will also have a low-pass response, which has the
beneficial effect of increasing out-of-band blocker immunity. G DLY 1
Y0 = X0 + N−1 N
eN
Out-of-band signals that do not cause saturation are attenuated G DAC TF G DAC G DLY HTIA
by the inherent anti-aliasing of the CT pipeline, which will be 
N
G DLY
discussed in Section II-F. = X 0 +e N TDRF(i),CT . (19)
G DAC
i=1

E. Signal Reconstruction in Digital Domain As shown in (19), the ADC output equals the input sig-
A CT pipeline ADC system diagram that includes the digital nal X 0 multiplied by a fixed coefficient G DLY /G DAC , which
reconstruction processing is shown in Fig. 18. The flash in is approximately unity in the signal band, plus-shaped quan-
each stage is modeled by a transfer function TF , and the tization noise as discussed in Section II-A. Equation (19)
aliasing and quantization noise at stage n + 1 is modeled by also shows that all quantization error and aliasing terms are
the additive term en where n = 0, 1, 2, …, N. The digital cancelled except for the term contributed by the last stage, e N .
output, Dn , of Stage n + 1 flash can then be expressed as Since |TF G DAC /G DLY | is approximately unity in the signal
band, (19) indicates that the in-band components of e N are
Dn = T F X n + e n (14) suppressed by a factor of (G DLY HTIA ) N .
The above observations of (19) still hold when the recon-
and the stage output X m+1 can be expressed as struction filters are implemented in DT if the DT filters
are derived by impulse-invariant transformation. The impulse-
X m+1 = HTIA (G DLY X m − G DAC Dm ) (15)
invariant transformation, A, from a CT function f CT (s) to a
where m = 0, 1, 2, …, N − 1. DT function f DT (z) can be defined as
Based on the discussion in Section II-A, assuming all the ∞

blocks in Fig. 18 can be effectively modeled in CT and all f DT (e j 2π f )= A[ f CT ( j 2π f )] = f CT ( j 2π( f + k f S )).
the optional filters TOPT0 to TOPT(N−1) are all unity with no k=−∞
delay, the transfer functions for the last reconstruction filter is (20)
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8 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Applying (20) where the sampling is introduced

in (16) and (17), the equivalent DT reconstruction filters can
be derived as
TDRF(N),DT (z)
1
= (21)
A[G DAC (s)HTIA (s)]
TDRF(k),DT (z)
A[{G DLY (s)HTIA(s)} N−k−1 G DAC (s)HTIA (s)]
= (22)
A[{G DLY (s)HTIA (s)} N−k G DAC (s)HTIA (s)]
where k = 1, 2, …, N − 1. Note that the reconstruction filters
TDRF1 , …, TDRF(N) Z can be anti-causal. However, sufficient
delays or filtering can be introduced in the optional filters
TOPT0 to TOPT(N−1) to recover causality.
The discussion above assumes that the analog transfer Fig. 19. Simulated signal transfer function of the ADC (TADC ) and the
digital reconstruction filter response from the last flash to the reconstructed
functions are characterized and reflected accurately in the N
digital reconstruction filter transfer functions. In circuit sim- output ( TDRF(k) ). Out-of-band region and the regions aliased back to the
k=1
ulations, these analog transfer functions can be simulated. out-of-band region are grayed out.
In measurements, a known signal such as a pseudo-random
signal can be injected into the DAC to characterize the transfer
functions [16]. The simulated TADC magnitude increases slightly from
dc to f S /2, following the first term in (19). For inputs
in the second Nyquist zone, the TADC magnitude drops
F. Inherent Anti-Aliasing
sharply; aliases that fall in the signal bandwidth—dc to f S /8
The CT pipeline ADC includes multiple flashes, each of (OSR = 4)—are rejected by more than 63 dB. This behavior
which samples and quantizes its input signal. This process is repeated in a mirror fashion in the third and higher Nyquist
is modeled by (19); the aliases and quantization noise are zones.
represented using the additive signals e0 , e1 , . . . , e N . Equa-
tion (19) shows that in the ADC output Y0 ,all the intermediate
additive signals except e N (i.e., e0 , e1 , . . . , e N−1 ) are cancelled G. Comparison of CT Pipeline and DT Pipeline ADCs
by the digital reconstruction filter. Therefore, only the aliases In this section, CT and DT pipeline ADCs are briefly com-
added in the last stage (flash) can be observed at the ADC pared. As we have seen, a DT pipeline ADC uses switched-
output, after they are shaped by the digital reconstruction filter capacitor circuits, whereas a CT pipeline ADC employs a

N delay line and an active-RC filter as building blocks. Since no
TDRF(k) . Since the latter is high pass in nature, the observed
k=1 sampling happens in the gain blocks, the CT pipeline inherits
aliased signal at the ADC output is also high-pass shaped. the CT benefits of low ADC driving current and inherent
When the ADC is under normal operation, the signal X N anti-aliasing.
at the input of the last flash is bounded within its input range, The digitization bandwidth of the ADC is defined by the
so that the additive term e N is also bounded. Thus, the mag- sampling frequency f S and the OSR. Empirically, CT ADCs

N
can be clocked approximately three times faster than their
nitude of the in-band alias at the ADC output |e N TDRF(k) |
k=1 DT counterparts in the same process node [13]. The stage
is also bounded by the magnitude of the digital reconstruction filtering in a CT pipeline ADC dictates a minimum OSR
filter response at that frequency. of approximately four, while a DT pipeline can, in theory,
To verify this, a behavioral CT pipeline was simulated with operate with OSR = 1. However, since an anti-aliasing filter
a transient analysis. The simulated system consisted of four has to be attached to suppress out-of-band components, even
residue-generation stages and a transmission line as a delay a DT pipeline needs some oversampling in practice. In typical
element. The simulated magnitude response of Nyquist ADC applications, OSR ranges from 1.25 to 3.3 when
Y0 (e j 2π f TCK ) used with a sharp off-chip filter. To make a fair compari-
TADC ( j 2π f ) = (23) son, this paper assumes an application OSR of 1.5 for all
X 0 ( j 2π f )
Nyquist ADCs. With the above assumptions, the digitization
is shown in Fig. 19 as long as the digital reconstruction filter’s bandwidth or a DT pipeline ADC is f S,DT /3 = 0.33 f S,DT,
N
whereas the digitization bandwidth of a CT pipeline
magnitude response | TDRF(k) |. As shown in Fig. 19, |TADC |
k=1 is f S,CT /8 = 3 f S,DT /8 = 0.38 f S,DT . This claim will be

N confirmed in Section IV with measurement results.
is bounded by | TDRF(k) |, confirming the above argument.
k=1
The requirements for the pre-filtering can also be discussed
The aliased response has a large variation in frequencies using the application OSR. Let us assume 80-dB alias rejection
more than f S because the aliased tones are masked by the with 0.3-dB passband ripple is needed in the system. In the
quantization noise in those frequencies. case of a DT ADC with 1.5 application OSR, the transition
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SHIBATA et al.: 9-GS/s 1.125-GHz BW OVERSAMPLING CT PIPELINE ADC 9

Fig. 20. CT pipeline ADC system.

Fig. 21. Simplified schematic of Stages 1 and 2.

frequency ratio from the band edge frequency to the The other drawback of the CT pipeline is the digital
associated aliasing frequency in the second Nyquist zone signal reconstruction. Since the inter-stage gain has a low-
is 2 OSR−1 = 2. Thus, a ninth-order Chebyshev or sixth- pass response, reconstruction requires a multi-tap digital filter
order elliptic low-pass filter is needed in the DT system. for each stage, in contrast to the one-tap digital filter needed
In contrast in a system using a CT pipeline ADC with OSR by DT pipelines. This difference could increase the power
of 4, the transition frequency ratio is 7. Also, thanks to consumption needed for signal reconstruction in the CT case.
the inherent alias attenuation of 63 dB (see Section II-F) In [16], two 12-tap finite-impulse response (FIR) filters run-
offered by the CT pipeline ADC, the required alias attenuation ning at a quarter rate (2 GS/s) are used for a CT MASH 
of the pre-filter is reduced to 80 dB − 63 dB = 17 dB. ADC with an OSR of eight. The 12-tap FIR filters consume
This requirement can easily be satisfied by a second-order approximately 2.2 mW/tap/GS/s in a 28-nm implementation.
Butterworth low-pass filter. If a similar FIR filter is used for the four back-end stages in
One might think that comparator metastability-induced error a five-stage CT pipeline ADC, the overall filter consisting of
can be higher in an oversampled CT pipeline ADC than a DT four 10-tap FIR filters running at a half rate (4.5 GS/s) will
pipeline for the same application BW since a higher clock require approximately 400 mW in a 28-nm implementation.
frequency is required. In CT ADCs, approximately 50% of The pros and cons of the CT and DT pipeline ADC discussed
the clock cycle can be allocated for the regeneration; on the in this section are summarized in Table I.
other hand, this is approximately 10% of the clock cycle in a
non-interleaved DT pipeline ADC as regeneration is typically III. C IRCUIT I MPLEMENTATION
expected to be completed in the clock’s non-overlap time [17].
Therefore, the absolute time period allocated for comparator A. ADC System
regeneration can be longer and metastability-induced error can A block diagram of the implemented CT pipeline ADC is
be smaller in CT ADCs for the same application BW. shown in Fig. 20. The ADC consists of seven CT residue-
The narrow clock frequency of a CT pipeline ADC can generation stages. The stage digital outputs are stored in an
be a potential drawback if wide clock frequency tunability is on-chip SRAM and read out through a serial interface. The
needed. If the clock frequency changes by more than 20% simplified schematics of Stages 1 and 2 are shown in Fig. 21.
(typical), component values have to be re-adjusted as in CT Each stage has a 17-level flash ADC, a 17-level unit-element
 ADCs. When an LC lattice is used as a delay ele- current-steering DAC, a passive V -to-I delay structure, and a
ment, the clock frequency adjustability is limited since tuning TIA with low-pass filtering. The first stage has an additional
inductor values is generally difficult. This clock frequency voltage buffer driving the flash to minimize kickback noise.
flexibility is a benefit of DT ADCs. However, noise spectral Flashes and DACs are clocked at 9 GHz. Each stage generates
density (NSD) also changes depending on the clock frequen- a 17-level output with a 2-level dither signal. Stages 2 to 7 use
cies in DT ADCs, which are not desirable in communication identical circuit blocks. Supply voltages of 1.8, 1, and −1 V
applications. are provided to the ADC.
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10 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 22. Simplified schematic of the operational amplifier used in the TIA. Common-mode feedback circuits are omitted for simplicity.

Fig. 23. One slice of flash-to-DAC section.

TABLE I feedback resistors and capacitors. Each transconductance stage

C OMPARISON S UMMARY B ETWEEN CT AND DT P IPELINE ADC S in the opamp contains either a differential pair or a pseudo-
differential pair. The feedback resistors and capacitors are dig-
itally programmed to adjust the gain and the cut-off frequency
of the TIA.
The flash and DAC consist of 16 identical slices. One of the
16 slices is shown in Fig. 23. The flash consists of parallel-
connected comparators and the comparator core schematic is
shown on the left side. The latter is driven by the differential
input and reference voltage signals and the comparator offset is
corrected by calibration DACs. The output data are propagated
to the DAC section through an SR latch and inverter chains.
An extra half-LSB weighted slice is added to inject dither,
which is used to characterize the transfer function for signal
reconstruction.
In the DAC slice, the input signal is retimed at the clock
rising edge, and the DAC output current is updated one clock
period after flash sampling. The DAC generates a push–pull
B. ADC Sub-Blocks current from −1 and +1.8 V supplies to minimize the thermal
noise. The DAC implements static and timing error calibration
The TIA, DAC, and flash designs are based on [4] circuits to lower distortion.
with modifications. The TIA consists of a fifth-order multi- The delay in the first stage is implemented with a four-
path multi-stage feedforward opamp shown in Fig. 22 with stage cascaded LC-lattice all-pass filter to achieve wideband
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SHIBATA et al.: 9-GS/s 1.125-GHz BW OVERSAMPLING CT PIPELINE ADC 11

Fig. 24. Chip micrograph of the ADC.

cancellation, while RC-lattice all-pass filters are used in stages

2 to 7 to minimize area. The capacitor in the LC lattice and Fig. 25. Measured single-tone spectrum with −80-dBFS signal at 1135 MHz.
Average small-signal NSD is −164 dBFS/Hz.
the resistor and the capacitor in the RC lattice are digitally
programmable to compensate ±20% process variation and
allow the delay to match the effective delay in the flash-DAC
path.
IV. M EASUREMENT R ESULTS
The CT pipeline ADC was fabricated in a 28-nm CMOS
process technology. The chip micrograph is shown in Fig. 24;
Stage 1 is placed on the rightmost edge and Stages 2 to 7 are
sequentially placed toward the left side. The LC delay line is
located to the right of Stage 1. Stages 2 to 7 use the same
layout. The ADC occupies 5.1 mm2 . All blocks in Stages
6 and 7, and the TIA and DAC in Stage 5 were disabled
for all the measurements because the quantization noise is
well suppressed with this four-TIA configuration so that the
system we report on is a 5-stage pipeline ADC. The 10-tap
FIR filters for each stage were used for signal reconstruction
and the coefficients were foreground calibrated. All the data Fig. 26. Measured single-tone spectrum with the 0-dBFS signal at 1135 MHz.
was captured using an on-chip memory and the reconstruction Average large-signal NSD is −156 dBFS/Hz.
calculations were performed by a host computer. The single-
ended input signals were generated by R&S SMA100A signal
generators with appropriate bandpass filters to remove residual
noise and spurs. The single-ended input signal was converted
to a differential signal with a wideband balun. The 9-GHz
clock signal was generated using a Keysight E8257D.
Figs. 25 and 26 show spectra reconstructed from the
ADC digital outputs at 9 GHz f S with −80- and 0-dBFS
single-tone signals at 1130 MHz. With an ADC passband of
10 to 1135 MHz the conversion bandwidth is 1125 MHz. The
passband was set to start at 10 MHz due to a high near-dc noise
of the operational amplifier used in this design. The measured
average NSDs with −80-and 0-dBFS signals at 1135 MHz are
−164 and −156 dBFS/Hz, respectively. NSD increases toward
high frequencies because the gain of the first stage drops
with frequency and thus back-end noise contributes more to Fig. 27. Single-tone spectrum with the signal applied at 200 MHz.
the NSD. Approximately −80 dBFS level spurs are observed
in the large-signal case. There are mostly generated by the when a −1-dBFS single-tone signal is applied at 200 MHz.
staircase transfer function of the flash in Stage 1 and remain When two −7 dBFS tones are applied at 980 and 1020 MHz
at the ADC output due to a limited analog-to-digital transfer (Fig. 28), the system shows −84-dBFS IMD3. For the
function matching accuracy. 200 MHz input, the distortion is caused by a protection
Single-tone measurement results are shown in Fig. 27. The clamp diode at the ADC input. For the 1 GHz two-tone
HD2 and HD3 levels are −79-and −86 dBFS, respectively, input, DAC inter-symbol interference error caused by threshold
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12 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 28. Two-tone spectrum with signals applied at 980 and 1020 MHz. Fig. 30. SNR and SNDR versus amplitude with 200-MHz input signal.

Fig. 29. SNR versus amplitude plots with 200-MHz and 1-GHz input signals. Fig. 31. Measured SNR, SNDR, and SFDR over signal frequency along with
the simulated SNR using a behavioral model with 100-fs RMS clock jitter.
voltage mismatches in the DAC switches [18], which are not
calibrated, is the main source of the distortion.
SNR versus signal amplitude plots for single-tone inputs at
200 MHz and 1 GHz are shown in Fig. 29. The peak SNR for
200 MHz and 1 GHz cases are, respectively, 70 and 66 dB,
respectively, which correspond to −160- and −156-dBFS/Hz
large-signal average NSD over the 1125-MHz bandwidth. The
plot also confirms that the ADC achieves 73-dB dynamic
range or −164-dBFS/Hz small-signal average NSD. The 3-dB
difference between the dynamic range and the peak SNR in
the 200 MHz case is caused by DAC nonlinearity (spread out
by a dynamic element matching). The peak SNR difference
between the 200 MHz and 1 GHz cases is primarily due to
clock jitter.
Fig. 30 plots the SNR and signal-to-(noise + distortion)
ratio (SNDR) versus the amplitude of a single-tone input at Fig. 32. Measured inherent anti-aliasing with −4-dBm input signal.
200 MHz. The peak SNDR is 68 dB, which is 2 dB worse
than the peak SNR. Fig. 31 shows the measured SNR, SNDR,
and spurious-free dynamic range (SFDR) with different input at 1 GHz. As discussed in Section II-F, a CT pipeline provides
frequencies along with a simulated SNR using a behavioral inherent anti-aliasing, and that claim is supported by this
model assuming 100-fs RMS clock jitter. SNR and SNDR measurement result. As shown in Fig. 32, the ADC achieves
decrease when the input frequency increases due to the clock more than 68 dB alias rejection in the second- and third-
jitter. As Fig. 31 shows, the measurements are consistent with Nyquist zones. This result is 5 dB better than the behavioral
100 fs of clock jitter. The worst case SFDR is 73 dB. simulation results shown in Fig. 19 because the flash has its
Fig. 32 shows the measured anti-aliasing performance with own low-pass frequency response, which is not modeled in
a −4-dBm input signal, which corresponds to −10 dBFS the behavioral simulation. Also, the measurement parasitics
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SHIBATA et al.: 9-GS/s 1.125-GHz BW OVERSAMPLING CT PIPELINE ADC 13

Fig. 33. Maximum allowable signal generator amplitude and Stage 1 flash Fig. 35. Single-tone spectrum with 6-dBm signal applied at 8347.36 MHz
output D0 versus frequency. showing the aliasing behavior. The clock frequency is 8847.36 MHz.

input signals, respectively, both having 6-dBm signal generator

output level, which corresponds to 0 dB0FS at 1 GHz. This
measurement was performed without a bandpass filter at the
ADC input so that the measured in-band NSDs and spurs are
higher than those in the other measured results. As shown
in Fig. 34, the ADC properly digitizes the 0 dBFS 2.5-GHz
input signal. Note that the harmonic distortion in the spectrum
is from the signal generator (recall that in this test there is
no bandpass filter at the ADC input). Fig. 35 shows that
the input signal at 8347.36 MHz is aliased to 500 MHz
in the ADC output. Fig. 36 shows the digital output data in
the time domain when the spectrum shown in Fig. 35 was
measured. The Stage 1 digital output shown in Fig. 36 (a)
Fig. 34. Single-tone spectrum with 0 dBFS (6 dBm) signal applied illustrates that the aliased signal at 500 MHz is generated
at 2.5 GHz. Signal generator output is not bandpass filtered. by the flash in Stage 1. The aliased signal is amplified by
the TIA without any cancellation since there is no input
including cable and board trace loss, balun frequency response, signal at 500 MHz. This amplified signal appears at the
and reflections are not de-embedded and could affect the Stage 2 digital output in Fig. 36 (b). Since the input signal
measurement accuracy by approximately 20 dB at f S . level is below the blocker immunity level, the ADC internal
To evaluate the out-of-band signal immunity of the ADC, nodes are not saturated and the aliased signal is properly
amplitude sweeps were performed at different frequencies to digitized in Stage 2. Following digital reconstruction, the alias
determine the input signal level which saturates the ADC for is attenuated by 73 dB, thereby demonstrating the inherent
each frequency. The result is summarized in Fig. 33 showing anti-aliasing.
the signal generator output level as Ain and associated Stage 1 The performance of the ADC is compared in Table II with
flash output D0 amplitude level. The ADC is regarded as recently published ADCs having similar performance along
saturated when the maximum digital output code is generated with the related work of [11] and [19].
at any stage for eight consecutive samples. The clock signal Digitization bandwidth is the most important metric for
is at 8847.36 MHz and generated by an Analog Devices wideband ADCs. As discussed in Section II-G, an appli-
ADF4159 evaluation board, and the signal is generated by cation OSR of 1.5 for Nyquist ADCs is assumed for the
a Keysight E8257D in this testing. As shown by the Ain plot comparison, which explains the application bandwidth row
in Fig. 33, the ADC is immune to more than 0 dBFS or 6-dBm in Table II. Our ADC achieves a bandwidth of 1125 MHz,
signal up to f S /2. The ADC saturates with a −3-dBm signal which is 2.4 times wider than earlier reported CT  ADCs
near f S , which corresponds to the amplitude level of −9 dBFS using the same circuit blocks [4], and 1.4 times wider than
at 1GHz. This is better than the behavioral simulation results the non-interleaved pipeline ADC implemented in a 28-nm
in Fig. 17 because of the pre-filtering introduced by the flash technology [7].
buffer and the board parasitics; the combination of these Noise, resolution, and dynamic range are other important
two effects is approximated by the difference between the metrics for wideband high-dynamic-range ADCs. To compare
Ain and D0 magnitude plots in Fig. 33. the SNR and DR among ADCs with different bandwidth,
Figs. 34 and 35 show the ADC output spectra of the they are normalized to give the small-signal and large-
out-of-band blocker testing with 2.5-GHz and 8347.36-MHz signal NSD in dBFS/Hz. Our ADC achieved −164-dBFS/Hz
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14 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 36. ADC (a) Stage 1 and (b) Stage 2 digital output signals with 6-dBm signal applied at 8347.36 MHz. The clock frequency is 8847.36 MHz.
TABLE II
ADC P ERFORMANCE C OMPARISONS . ∗ DRF P OWER C ONSUMPTION I S AN E STIMATED VALUE

small-signal NSD and −160-dBFS/Hz large-signal NSD with

a low-frequency input; both are the best in Table II. The large-
signal NSD with a high input frequency is −156-dBFS/Hz,
which is one of the best in Table II.
The ADC consumes 2.33 W, of which 0.81, 0.77, 0.60, and
0.16 W are dissipated in flashes, clock, AMPs, and DACs,
respectively, as shown in Fig. 37. Note that the power scaling
of the back-end stages was not applied in this prototype. Even
without power optimization, this design achieved a thermal
noise Figure-of-Merit (FOM) of 160 dB, which is better than
Fig. 37. ADC power consumption allocations.
any other 28-nm ADC in Table II and only 4 dB worse than
the 16-nm ADC [6].
Fig. 38 shows the thermal noise power-efficiency FOM The plot confirms that this ADC achieves the widest bandwidth
versus application bandwidth plot based on the ADC data among CT ADCs, and the widest application bandwidth ADC
points available in [20] and recent additional publications. among non-interleaved ADCs having FOMS > 150 dB.
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SHIBATA et al.: 9-GS/s 1.125-GHz BW OVERSAMPLING CT PIPELINE ADC 15

[4] Y. Dong et al., “A 72 dB-DR 465 MHz-BW continuous-time 1-2 MASH

ADC in 28 nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 12,
pp. 2917–2927, Dec. 2016.
[5] S.-J. Huang, N. Egan, D. Kesharwani, F. Opteynde, and M. Ashburn,
“A 125 MHz-BW 71.9 dB-SNDR VCO-based CT  ADC with
segmented phase-domain ELD compensation in 16 nm CMOS,” in IEEE
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017,
pp. 470–471.
[6] J. Wu et al., “A 4 GS/s 13 b pipelined ADC with capacitor and
amplifier sharing in 16 nm CMOS,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 466–467.
[7] A. M. A. Ali et al., “A 14-bit 2.5 GS/s and 5 GS/s RF sampling ADC
with background calibration and dither,” in IEEE Symp. VLSI Circuits
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asynchronous pipelined-SAR ADC,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 276–277.
[9] S. Devarajan et al., “A 12 b 10 GS/s interleaved pipeline ADC in 28 nm
CMOS technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig.
Fig. 38. FOM S versus application bandwidth. Data points are cate- Tech. Papers, Feb. 2017, pp. 288–289.
gorized in DT all, DT pipeline without time interleaving, DT pipeline [10] R. Schreier, J. Silva, J. Steensgaard, and G. C. Temes, “Design-
with time interleaving, CT all, and CT pipeline ADCs. Data points with oriented estimation of thermal noise in switched-capacitor circuits,”
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V. C ONCLUSION pp. 1456–1468, Aug. 2010.
[12] H. Shibata, V. Kozlov, Z. Ji, A. Ganesan, H. Zhu, and D. Paterson,
In this paper, we described the CT oversampled pipeline “A 9 GS/s 1 GHz-BW oversampled continuous-time pipeline ADC
ADC architecture and presented design details and measure- achieving −161 dBFS/Hz NSD,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 278–279.
ment results for a 28-nm prototype. Two techniques were [13] T. Caldwell, D. Alldred, R. Schreier, H. Shibata, and Y. Dong, “Advances
introduced to realize the CT pipeline ADC. One is to replace in high-speed continuous-time delta-sigma modulators,” in Proc. IEEE
switched-capacitor circuits with CT delay lines and resistors. Custom Integr. Circuits Conf., Sep. 2014, pp. 1–8.
[14] Y. Dong, W. Yang, R. Schreier, A. Sheikholeslami, and S. Korrapati,
The other is to add a low-pass filtering to suppress the DAC “A continuous-time 0–3 MASH ADC achieving 88 dB DR with 53 MHz
images. These two techniques enable CT signal processing BW in 28 nm CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 12,
within a pipeline ADC, thereby simultaneously achieving CT pp. 2868–2877, Dec. 2014.
[15] D.-Y. Yoon, S. Ho, and H.-S. Lee, “A continuous-time
benefits and a wide digitization bandwidth. sturdy-MASH  modulator in 28 nm CMOS,” IEEE J. Solid-State
The prototype ADC was implemented in a 28-nm CMOS Circuits, vol. 50, no. 12, pp. 2880–2890, Dec. 2015.
process. When clocked at 9 GHz and operated at an [16] Y. Dong et al., “Adaptive digital noise-cancellation filtering using cross-
correlators for continuous-time MASH ADC in 28 nm CMOS,” in Proc.
OSR of four, the ADC achieves 1.125-GHz bandwidth, IEEE Custom Integr. Circuits Conf., Apr. 2017, pp. 1–4.
−164-dBFS/Hz average small-signal NSD, and 160-dB [17] S. Guhados, P. J. Hurst, and S. H. Lewis, “A pipelined ADC with
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[18] L. Risbo, R. Hezar, B. Kelleci, H. Kiper, and M. Fares, “Digital
ACKNOWLEDGMENT approaches to ISI-mitigation in high-resolution oversampled multi-
The authors would like to thank R. Schreier for his level D/A converters,” IEEE J. Solid-State Circuits, vol. 46, no. 12,
pp. 2892–2903, Dec. 2011.
mentorship and technical advice on the reconstruction filter; [19] A. Hart and S. P. Voinigescu, “A 1 GHz bandwidth low-pass  ADC
A. Ahmed, N. Caporale, J. Rioux, N. Khan, H. Liu, and with 20–50 GHz adjustable sampling rate,” IEEE J. Solid-State Circuits,
S. Nami for their layout expertise; and W. Ismail, J. Wang, vol. 44, no. 5, pp. 1401–1414, May 2009.
[20] B. Murmann. ADC Performance Survey 1997–2016. Accessed:
M. Baxter, and A. D. Muro for their evaluation support. They Aug. 21, 2016. [Online]. Available: https://web.stanford.edu/~murmann/
would also like to thank W. Yang, D. Alldred, T. Caldwell, adcsurvey.html
Z. Li, Y. Dong, J. Silva, and F. Murden for technical discus-
sions; and J. Gealow, P. Ferguson, and G. Manganaro for their
encouragement and support.

R EFERENCES
[1] M. Bolatkale, L. J. Breems, R. Rutten, and K. A. A. Makinwa, Hajime Shibata (S’99–M’02) received the B.E. and
“A 4 GHz continuous-time  ADC with 70 dB DR and M.E. degrees in electrical engineering from the Uni-
−74 dBFS THD in 125 MHz BW,” IEEE J. Solid-State Circuits, vol. 46, versity of Electro-Communications, Tokyo, Japan,
no. 12, pp. 2857–2868, Dec. 2011. in 1997 and 1999, respectively, and the Dr. Eng.
[2] H. Shibata et al., “A DC-to-1 GHz tunable RF  ADC achieving degree from the Tokyo Institute of Technology,
DR = 74 dB and BW = 150 MHz at f0 = 450 MHz using 550 mW,” Tokyo, in 2002.
IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2888–2897, Dec. 2012. Since 2002, he has been with Analog Devices,
[3] S.-H. Wu, T. -K. Kao, Z.-M. Lee, P. Chen, and J.-Y. Tsai, where he is currently focusing on continuous-time
“A 160 MHz-BW 72 dB-DR 40 mW continuous-time  modulator  and continuous-time pipeline analog-to-digital
in 16 nm CMOS with analog ISI-reduction technique,” in IEEE Int. converter designs.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, Dr. Shibata was a co-recipient of the Beatrice
pp. 280–281. Winner Award at ISSCC 2006.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

16 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Victor Kozlov (M’16) received the B.A.Sc. (Hons.) Jialin Zhao (M’09) received the M.S. and Ph.D.
and M.S. degrees in electrical engineering from degrees in electrical engineering from the University
the University of Toronto, Toronto, ON, Canada, of Notre Dame, Notre Dame, IN, USA, in 2004 and
in 2012 and 2015, respectively. 2007, respectively.
He is currently a Design Engineer with Analog From 2006 to 2008, he was a Device Modeling
Devices, Toronto, where he focused on high-speed Engineer with Analog Devices, Wilmington, MA,
continuous-time delta-sigma converters. USA, focused on PSP MOSFET model for next gen-
eration CMOS. In 2008, he joined Mediatek Wire-
less Inc., Woburn, MA, USA, where he focused on
wide-bandwidth continuous-time delta-sigma mod-
ulator for wireless communication chipsets. He is
currently a Design Engineer with Analog Devices, San Jose, CA, USA.
Zexi Ji (S’17) received the B.A.Sc. degree in engi-
neering science with a major in electrical and com-
puter engineering from the University of Toronto,
Toronto, ON, Canada, in 2016. He is currently pur-
suing the S.M. degree in electrical engineering and
computer science with the Massachusetts Institute of
Technology, Cambridge, MA, USA. Sharvil Patil (S’12–M’17) received the B.E. (Hons.)
He was an IC Design Intern at Analog Devices, degree from the Birla Institute of Technology and
Toronto Design Center, Toronto, from 2014 to 2015. Science, Pilani, India, in 2009, and the M.S. and
Ph.D. degrees from Columbia University, New York,
NY, USA, in 2012 and 2017, respectively.
Between 2010 and 2011, he was with ST Micro-
Asha Ganesan (S’08–M’12) received the B.E. electronics, India, where he designed high-speed
degree in electronics and communication engineer- digital-to-analog converters. He is currently with
ing from the College of Engineering, Guindy, Chen- Analog Devices, Inc., Toronto, ON, Canada, where
nai, India, in 2012, and the master’s degree in he designs high-speed data converters.
electrical and computer engineering from Cornell
University, Ithaca, NY, USA, in 2015.
She was an Applications Engineer with Cypress
Semiconductor Corporation, Bengaluru, India. She
joined Analog Devices, Inc., Wilmington, MA,
USA, in 2015, focused on designing signal process-
ing and calibration based digital blocks.
Shanthi Pavan (M’04–SM’12) received the B.Tech.
degree in electronics and communication engineer-
Haiyang Zhu (M’11) received the B.S. and M.S. ing from the Indian Institute of Technology, Madras,
degrees in electrical engineering from Shanghai Chennai, India, in 1995, and the M.S and Sc.D.
Jiao Tong University, Shanghai, China, in 2000 and degrees from Columbia University, New York, NY,
2003, respectively, the Ph.D. degree in electrical USA, in 1997 and 1999, respectively.
engineering from Northeastern University, Boston, From 1997 to 2000, he was with Texas Instru-
MA, USA, in 2016. ments, Warren, NJ, USA, where he focused on
He has been with Analog Devices, Inc., high-speed analog filters and data converters. From
Wilmington, MA, USA, since 2006, focusing on 2000 to 2002, he involved in microwave ICs for data
designing high-speed data converters. communication at Bigbear Networks, Sunnyvale,
Dr. Zhu was a co-recipient of the 2013 IEEE CA, USA. Since 2002, he has been with the Indian Institute of Technology-
Journal of Solid-State Circuits Best Paper Award. Madras, where he is currently a Professor of electrical engineering. His
current research interests include high-speed analog circuit design and signal
processing.
Donald Paterson (M’96) received the B.Sc. degree Dr. Pavan was a recipient of several awards, including the Shanti Swarup
in electronics and physics from the University of Bhatnagar Award in Engineering Sciences in 2012, the IEEE Circuits and Sys-
Edinburgh, Edinburgh, U.K., in 1987. tems Society Darlington Best Paper Award in 2009, and the Swarnajayanthi
He has been with Analog Devices Inc., Fellowship (from the Government of India in 2010). He has been the
Wilmington, MA, since 1996, where his focus Editor-in-Chief of the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS :
in the High Speed Converter group has been on PART I—R EGULAR PAPERS in 2014 and 2015, and earlier served on the
highly integrated mixed-signal chips for imaging Editorial Board of the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS
and communications applications. PART II—E XPRESS B RIEFS in 2006 and 2007. He served on the Technical
Program Committee of the ISSCC, and as a Distinguished Lecturer of the
IEEE Solid State Circuits Society. He is a fellow of the Indian National
Academy of Engineering.