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    (D, T, RS, JK) Along With Testbench.: ASSIGNMENT: Design & Verify The Operation Flip-Flops

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    Akshat
    The document describes Verilog code and testbenches for 4 types of flip-flops: D flip-flop, T flip-flop, JK flip-flop, and SR flip-flop. For each type, it provides the Verilog code for the flip-flop module and a testbench module to test its operation. It then lists the output of running the testbenches through a simulator.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    (D, T, RS, JK) Along With Testbench.: ASSIGNMENT: Design & Verify The Operation Flip-Flops

    Uploaded by

    Akshat
    85 views9 pages
    The document describes Verilog code and testbenches for 4 types of flip-flops: D flip-flop, T flip-flop, JK flip-flop, and SR flip-flop. For each type, it provides the Verilog code for the flip-flop module and a testbench module to test its operation. It then lists the output of running the testbenches through a simulator.

    Original Title

    19EC037-flipflop

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    The document describes Verilog code and testbenches for 4 types of flip-flops: D flip-flop, T flip-flop, JK flip-flop, and SR flip-flop. For each type, it provides the Verilog code for the flip-flop module and a testbench module to test its operation. It then lists the output of running the testbenches through a simulator.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    85 views9 pages

    (D, T, RS, JK) Along With Testbench.: ASSIGNMENT: Design & Verify The Operation Flip-Flops

    Uploaded by

    Akshat
    The document describes Verilog code and testbenches for 4 types of flip-flops: D flip-flop, T flip-flop, JK flip-flop, and SR flip-flop. For each type, it provides the Verilog code for the flip-flop module and a testbench module to test its operation. It then lists the output of running the testbenches through a simulator.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 9

    19EC037 EC382

    ASSIGNMENT : Design & verify the operation flip-flops


    (D,T,RS,JK) along with testbench.
    1. D-Flip Flop
    VERILOG CODE :
    module dff (clk, reset, d, q, qb);
    input clk;
    input reset;
    input d;
    output q;
    output qb;

    reg q;

    assign qb = ~q;

    always @(posedge clk or posedge reset)


    begin
    if (reset) begin
    q <= 1'b0;
    end else begin
    q <= d;
    end
    end
    endmodule
    19EC037 EC382

    TESTBENCH :
    module dff_test;

    reg clk;
    reg reset;
    reg d;
    wire q;
    wire qb;

    dff DFF(.clk(clk), .reset(reset), .d(d), .q(q), .qb(qb));

    initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1);

    $display("Reset flop.");
    clk = 0;
    reset = 1;
    d = 1'bx;
    display;

    $display("Release reset.");
    d = 1;
    reset = 0;
    display;

    $display("Toggle clk.");
    19EC037 EC382

    clk = 1;
    display;
    end

    task display;
    #1 $display("d:%0h, q:%0h, qb:%0h",
    d, q, qb);
    endtask

    endmodule

    OUTPUT :
    19EC037 EC382

    2. T-Flip Flop
    VERILOG CODE :
    module tff(input reset, input clk, output reg q);
    always @(posedge clk)
    if (reset)
    q<=1'b0;
    else
    q<=~q;
    endmodule
    TESTBENCH :
    module tff_test;
    reg clk, reset;
    wire q;

    tff TFF(.clk(clk), .reset(reset),.q(q));

    initial
    begin
    $dumpfile("dumpy.vcd");
    $dumpvars(1);
    reset=1'b1;
    clk=1'b0;
    #5 reset=1'b0;
    #30 $finish;
    end

    always #1 clk=~clk;
    19EC037 EC382

    endmodule

    OUTPUT :
    19EC037 EC382

    3. JK Flip flop
    VERILOG CODE :
    module jkff(input reset, input clk, input j, input k, output reg q, output qb);
    assign qb=~q;
    always @(posedge clk)
    if (reset) q<=1'b0; else
    case ({j, k})
    2'b00: q<=q;
    2'b01: q<=1'b0;
    2'b10: q<=1'b1;
    2'b11: q<=~q;
    endcase
    endmodule
    TESTBENCH :
    module jkff_test;

    reg clk=0;
    reg j=0;
    reg k=0;
    reg reset=1;
    wire q, qb;

    jkff dut(reset, clk,j,k,q,qb);

    initial
    begin
    $dumpfile("dumpjk.vcd");
    19EC037 EC382

    $dumpvars(1);
    j=1'b1; // set your JK here
    k=1'b1;
    #5 reset=1'b0;
    #25 $finish;
    end
    always #1 clk=~clk;
    endmodule

    OUTPUT :
    19EC037 EC382

    4. SR Flip flop
    VERILOG CODE :
    module srff(input reset, input clk, input s, input r, output reg q, output qb);
    assign qb=~q;
    always @(posedge clk)
    if (reset) q<=1'b0; else
    case ({s, r})
    2'b00: q<=q;
    2'b01: q<=1'b0;
    2'b10: q<=1'b1;
    2'b11: q<=~q;
    endcase
    endmodule
    TESTBENCH :
    module srff_tb();
    wire q,qb;
    reg s,r,,clk,rst;
    srff srff_ins(s,r,clk,rst,q,qb);
    initial begin
    clk=0;
    forever #5 clk=~clk;
    end
    initial begin
    rst=1;
    #10 rst=0;
    #80 rst=1;
    #10 rst=0;
    19EC037 EC382

    end
    initial begin
    s=0; r=0;
    #15 s=0; r=1;
    #15 s=1; r=0;
    #15 s=1; r=1;
    #15 s=0; r=0;
    end
    endmodule
    OUTPUT :

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