Digital Electronics Circuits: Experiment: 9
Digital Electronics Circuits: Experiment: 9
Digital Electronics Circuits: Experiment: 9
EXPERIMENT: 9
STUDY OF COUNTERS
I. STUDY OF ASYNCHRONOUS COUNTER
AIM: To design and test 3-bit binary asynchronous counter using flip-flop IC
7476 for the given sequence.
LEARNING OBJECTIVE:
To learn about Asynchronous Counter and its application
To learn the design of asynchronous up counter and down counter
COMPONENTS REQUIRED:
IC 7476, Patch Cords & IC Trainer Kit
THEORY:
A counter in which each flip-flop is triggered by the output goes to previous
flip-flop. As all the flip-flops do not change state simultaneously spike occur at the
output. To avoid this, strobe pulse is required. Because of the propagation delay
the operating speed of asynchronous counter is low. Asynchronous counter are
easy and simple to construct.
Design:
MOD-8 UP COUNTER
PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Rig up the circuit as shown in the logic circuit diagram.
4. Apply various input data to the logic circuit via the input logic switches.
5. Note down the corresponding output and verify the truth table.
Note: Write the pin numbers of each gate and also write the intermediate expressions.
RESULT:
AIM:
To design and test 3-bit binary synchronous counter using flip-flop IC 7476 for the
given sequence.
LEARNING OBJECTIVE:
To learn about synchronous Counter and its application
To learn the design of synchronous counter
COMPONENTS REQUIRED:
IC 7476, Patch Cords & IC Trainer Kit
THEORY:
A counter in which each flip-flop is triggered by the output goes to previous flip-
flop. As all the flip-flops do not change states simultaneously in asynchronous counter,
spike occur at the output. To avoid this, strobe pulse is required. Because of the propagation
delay the operating speed of asynchronous counter is low. This problem can be solved by
triggering all the flip-flops in synchronous with the clock signal and such counters are called
synchronous counters.
Design:
MOD 5 COUNTERS:
Present
TRUTH TABLE: count next count
QC QB QA QC QB QA QC QB QA
0 0 0 0 0 0 0 0 1
0 0 1 0 0 1 0 1 0
0 1 0 0 1 0 0 1 1
0 1 1 0 1 1 1 0 0
1 0 0 1 0 0 0 0 0
0 0 0
JK FF excitation table:
Q Q+ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0