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Computer Architecture

This document provides questions for a quiz on cache memory and virtual memory. It includes questions that assess understanding of cache mapping, determining cache hit/miss rates, calculating average memory access time (AMAT), and analyzing page table and translation lookaside buffer (TLB) behavior for a given address stream with different page sizes. Students are asked to provide detailed explanations for their answers in a submitted report.

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quoc le
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36 views

Computer Architecture

This document provides questions for a quiz on cache memory and virtual memory. It includes questions that assess understanding of cache mapping, determining cache hit/miss rates, calculating average memory access time (AMAT), and analyzing page table and translation lookaside buffer (TLB) behavior for a given address stream with different page sizes. Students are asked to provide detailed explanations for their answers in a submitted report.

Uploaded by

quoc le
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Ho Chi Minh City University of Technology COMPUTER ARCHITECTURE

Faculty of Computer Science and Engineering Practical session - Semester 211

WEEK 4
Memory:
Cache and Virtual memory

1 Introduction
1.1 Aims
• Understand principle of mapping in cache.
• Practice determining memory accessing time and performance.

1.2 Documents and lab materials


The same as week 1.

1.3 Report requirements


• For questions (if any), write your answers in a report (.pdf format), remember to include your name
and student ID. Name the report file with format <student ID>-<lab number> (ex: 2012345-
lab1.zip) (ex: 2012345-lab4.pdf) and submit to BK-elearning by the deadline.

2 Quiz
Answer below questions with detailed explanation.

2.1 Question 1
Given the main memory that has an address space of 32 bit, a cache with the size of 1 MB, 1 block is
256B, the accessing unit of the system is 1 byte. Determine the bit-width of tag, index, byte-offset with
below configurations:
a. Directed map.
b. 4-way set associative.
c. Full associative.

Computer Architecture - Semester 211 1/3


Faculty of Computer Science and Engineering Department of Computer Engineering

2.2 Question 2
Given the main memory that has the capacity of 256MB, a cache with the size of 256KB, 1 block is
64 words, the accessing unit of the system is 2 bytes. Determine the bit-width of tag, index, byte-offset
with below configurations:
a. Directed map.
b. 4-way set associative.
c. Full associative.

2.3 Question 3
A program accesses data in main memory with the sequence below (word address): 0,
4, 1, 5, 65, 46, 1, 70, 2, 0
Know that the system is 256B cache, 4-word block, 1-byte accessing unit. Hit time = 6 cycles, RAM
(main memory) access time = 10ns, the system works with the frequency of 2GHz.
Determine the number of HIT/MISS when executing the program, then calculate the AMAT (Average
memory access time) with the below configurations:
a. Directed map.
b. 2-way set associative.
c. Full associative.

2.4 Question 4
Given L1 cache hit time is 10 cycles, L2 cache hit time is 15 cycles, time to access RAM (main
memory) is 100 cycles. L1 miss rate is 25%, L2 miss rate is 5%. Determine AMAT of the system.

2.5 Question 5
Determine average CPI of a pipeline system that its Instruction memory miss rate is 5% and its Data
memory miss rate is 10%. Know that the program has 1000 instructions included 100 load/store
instructions and miss penalty is 100 cycles.

Computer Architecture - Semester 211 2/3


2.6 Question 6*
Virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. The
following data constitutes a stream of virtual addresses as seen on a system. Assume 4 KB pages, a 4-entry
fully associative TLB, and true LRU (Least Recently Used) replacement. If pages must be brought in from
disk, increment the next largest page number.

Valid Tag Physical Page Number Valid Physical Page/Disk


1 11 12 1 5
1 7 4 0 Disk
1 3 6 0 Disk
Table
0 4 1: TLB 9 1 6
1 9
Stream of virtual addresses: 1 11
4669, 2227, 13916, 34587, 48870, 12608, 49225 0 Disk
1 4
0 Disk
0 Disk
Table 2: Page table
1 3
a. Given the address stream shown, and the initial TLB and 1 page table states 12 provided above.
Determine the final state of the system. Also list for each reference if it is a hit in the TLB, a hit in the
page table, or a page fault.
b. Repeat task a., but this time use 16 KB pages instead of 4 KB pages. What would be some of the
advantages of having a larger page size? What are some of the disadvantages?
c. Show the fi nal contents of the TLB if it is 2-way set associative, direct mapped.

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