Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 42 views

    Combinational Logic (Seven Segment Driver)

    Uploaded by

    Honney Sunny K K
    This document describes building a seven segment display decoder using a Xilinx CPLD. It provides instructions on the 5 steps of the digital logic design process: 1) high level preparation including defining inputs, outputs and creating a truth table, 2) design entry by entering the design into Xilinx software, 3) design verification through simulation, 4) design adaptation to program the CPLD, and 5) design implementation by programming the CPLD. It also provides two challenge options - creating a two digit seven segment display using a specific part.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    Combinational Logic (Seven Segment Driver)

    Uploaded by

    Honney Sunny K K
    42 views4 pages
    This document describes building a seven segment display decoder using a Xilinx CPLD. It provides instructions on the 5 steps of the digital logic design process: 1) high level preparation including defining inputs, outputs and creating a truth table, 2) design entry by entering the design into Xilinx software, 3) design verification through simulation, 4) design adaptation to program the CPLD, and 5) design implementation by programming the CPLD. It also provides two challenge options - creating a two digit seven segment display using a specific part.

    Original Description:

    Original Title

    7

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document describes building a seven segment display decoder using a Xilinx CPLD. It provides instructions on the 5 steps of the digital logic design process: 1) high level preparation including defining inputs, outputs and creating a truth table, 2) design entry by entering the design into Xilinx software, 3) design verification through simulation, 4) design adaptation to program the CPLD, and 5) design implementation by programming the CPLD. It also provides two challenge options - creating a two digit seven segment display using a specific part.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    42 views4 pages

    Combinational Logic (Seven Segment Driver)

    Uploaded by

    Honney Sunny K K
    This document describes building a seven segment display decoder using a Xilinx CPLD. It provides instructions on the 5 steps of the digital logic design process: 1) high level preparation including defining inputs, outputs and creating a truth table, 2) design entry by entering the design into Xilinx software, 3) design verification through simulation, 4) design adaptation to program the CPLD, and 5) design implementation by programming the CPLD. It also provides two challenge options - creating a two digit seven segment display using a specific part.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    Chapter 4

    Combinational Logic (Seven Segment


    Driver)

    41
    CHAPTER 4. COMBINATIONAL LOGIC (SEVEN SEGMENT DRIVER)

    4.1 Section Overview


    Being able to display numbers is useful. Seven segment displays are used in alarm clocks, VCRs, and microwaves.
    Section four builds a seven-segment display decoder, which is described in example 2.10 of the ECE 271 textbook .

    4.2 Objectives
    In this section, the following items will be covered:

    1. Define the problem, what is the controller really doing?

    2. Define the inputs to the combinational logic.

    3. Define the outputs from the combinational logic.

    4.3 Materials
    1. Xilinx ISE 12 software (Currently installed on the lab computers)

    2. Digital Logic Board (d logic.2 board)

    3. Small breadboard, buffer chip (octal latch), and resistors

    4. MAN 6980 seven segment display

    4.4 Procedure
    There are 5 steps to digital logic design:

    Figure 4.1: Use this process for designing the seven segment display.

    1. High Level Preparation: Figure 4.2 shows all of the different outputs that the seven segment decoder should
    produce. Shade in the segments that should be on for each input, 0-F.

    Figure 4.2: The decoder should produce all 16 outputs

    42 ECE 272 Manual 2011


    c Oregon State University
    4.4. PROCEDURE

    Make a block diagram

    Add the power source used for each of the three blocks.

    Label all Port and Port pins that are used for this project on the block diagram.

    Label which inputs on the buffer chip are connected to T, U, V, W, X, Y, and Z.

    Figure 4.3: This is the block diagram for the remote control

    Make a functional truth table

    Use the shading in Figure 4.2 to fill in the functional truth table below.
    Input Hex Inputs, ABCD SegA SegB SegC SegD SegE SegF SegG
    0 0000 1 1 1 1 1 1 0
    1 0001
    2 0010
    3 0011
    4 0100
    5 0101
    6 0110
    7 0111
    8 1000
    9 1001
    A 1010
    B 1011
    C 1100
    D 1101
    E 1110
    F 1111

    Minimize the logic

    Use seven K-maps to make minimized logic for SegA , SegB , SegC , SegD , SegE , SegF , and SegG . Write
    out the minimized Boolean Equations for each output.
    2. Design Entry: Enter the design using the same process as in Section 2.

    A larger workspace in Xilinx will be needed to fit the entire minimized schematic. To change
    the schematic size click Edit → Change Sheet Size... In the dialog box use the dropdown
    menu to select a larger sheet size.

    2011
    c Oregon State University ECE 272 Manual 43
    CHAPTER 4. COMBINATIONAL LOGIC (SEVEN SEGMENT DRIVER)

    3. Design Verification: Simulate the desgin to verify correct operation of the digital logic. Use Section 3 as a guide
    for this process.
    4. Design Adaptation to Target Device: Follow the same process for using PACE and iMPACT as in Section 2.
    5. Design Implementation: Program the Xilinx CPLD with the Universal Programmer software.

    TA Signature:
    (Seven Segment display is working and all lab steps are shown)

    4.5 Study Questions


    1. When is a simulation necessary? Was it useful for this section?
    2. Attach the detailed block diagram, digital logic schematic, and simulation results for this project.

    4.6 Challenge - Extra Credit


    4.6.1 Option 1

    Make a two digit seven segment display. Use the MAN 6940 seven segment display, which has two digits. Each digit
    has an independent common cathode. There should be eight inputs to this decoder. There should be seven outputs
    for the seven segments, and two outputs for the two common cathodes. Design the electrical circuits for driving the
    common cathodes and the digital logic for displaying the turning on the correct segments when the corresponding
    common cathode is enabled.

    4.6.2 Option 2

    Design and simulate the Xilinx for a two digit seven segment display. Create your outputs as if they were going to be
    used by the pins on the MAN 6940.

    44 ECE 272 Manual 2011


    c Oregon State University

    You might also like