2020 IEEE International Conference for Innovation in Technology (INOCON)

Bengaluru, India. Nov 6-8, 2020

Implementation of AES Algorithm on FPGA

and on software
Joseph Sunil1, Suhas H S2, Sumanth B K3,S. Santhameena4
1,2,3,4
Dept. of ECE, PES University, Bengaluru, India
1
josephsunil52@gmail.com,2chuvvis@gmail.com,3sumanth.kalikeri@gmail.com,4santhameena.s@pes.edu

Abstract—AES (Advanced Encryption Standard) is an implementation worked well for implementation of

algorithm which is used to protect electronic data. The AES MixColumns and Inverse MixColumns.
can be implemented in software as well as hardware. However
implementing in Field Programmable Gate Array (FPGA) is Using [3], we interfaced our design to communicate with
much faster than implementing in software. In this project we the PC. We looked up to section 5 of the manual i.e. USB-
have done a comparison between software implementation of UART Bridge (Serial Port) to achieve this.
AES algorithm and FPGA implementation of AES Algorithm.
Joan Boyar and Rene Peralta in [4] focus on a technique
We have used XILINX Vivado 2017.4 software for coding the
algorithm and simulating the same. We used Verilog as the
for optimization of combinational logic and have come up
HDL language for coding the AES algorithm. The algorithm with an optimized combinational logic for realizing S-box
was also implemented on ARTIX-7 FPGA. used in AES algorithm. However this approach used up
twice the amount of LUT slices for only a slight reduction in
Keywords— AES, Security, FPGA, Verilog, HDL, Timing propagation delay.
Analysis, Comparison, Encryption, Decryption
III. AES ALGORITHM
I. INTRODUCTION AES Algorithm implements confusion and diffusion of
Hundreds of millions of online transactions take place on data effectively. Since it does this process on binary data it
an average day. As a result, the need for online security is is easier for machines to do the process quickly. AES uses
more now than ever. There are several ways of encrypting a input data size of 128 bits and key sizes of 128/192/256 bits.
transaction and AES is one of them. Number of rounds changes according to the key size and
also the Key Expansion process is a little different for larger
The Advanced Encryption Standard (AES) is a
Keys. In our project we have implemented the AES-128.
symmetric block cipher chosen by the U.S. government to
protect classified information. AES is implemented in The flowchart of AES algorithm is shown in Fig 1.
software and hardware throughout the world to encrypt IV. AES ALGORITHM FLOWCHART
sensitive data. It is essential for government computer
security, cyber security and electronic data protection.
According to www.eetimes.com, it would take a
supercomputer around 10^18 years to crack AES-128 using
brute force method. So, we can safely assume that AES is
one of the most secure forms of encryption available today.
Although software encryption is quite cheap and easy to
implement it is not as fast as implemented on hardware as
many factors influence the speed (speed of compiler,
operating system, firmware, processor speed etc.) Since in
FPGA a separate dedicated processor can be configured, it is
much faster than software encryption. In hardware
encryption on the other hand, the above factors won’t come
into picture and the speed purely depends on hardware
components which is generally fast. This makes hardware
encryption faster.
II. RELATED WORK
The logical operations required to implement AES
Algorithm on hardware are focused by [1]. We used the
Pseudo codes present in [1] and came up with verilog code to
implement the same for Artix-7 FPGA.
We tried to optimize the straight forward code using [2]
and found that the LUT approach used here did not work
best for all processes and the gate implementation approach Fig. 1. Flowchart of AES Algorithm
worked better for some processes. For eg : LUT approach
worked well with less delay for S-Boxes whereas gate

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 V. BLOCK DIAGRAM B. Intshift
A. Encryption This module takes the 8 bit input and shifts the 8 bit data
parallel into a 128 bit register. Thus we successfully send the
128 bit plain text into the board to be encrypted.
C. AES_TOP
This is the main module of our project which does the
encryption process. Here we used a hardcoded Key for easy
implementation.
D. Stringoutshift
This module does the reverse of Intshift module that is
sends the 128 bit encrypted data 8 bit at a time to the
transmitter module. We also configured it to send hardcoded
prompts for the end user at the beginning of the operation for
Fig. 2. Block Diagram Of Encryption the ease of user according to the state the design is at the
moment like “Enter plaintext:” , “Encryption key:”.
The data to be encrypted i.e. the plaintext (128 bit) and E. Transmitter
the key (128 bit) are the inputs which are fed to the board
and the output is the required cipher text (128bit) as shown in It takes the 8 bit data from String out Shift module and
Fig 2. sends it to PC through UART port.

B. Decryption F. state_machine
Module used to properly receive plaintext and key from
the user input as shown in Fig 5.

Fig. 3. Block Diagram of Decryption Fig. 5. State Machine

The data to be decrypted i.e. the cipher text (128 bit) and We see that there are 3 states. The design is configured to
the key (128 bit) are the inputs which are fed to the board initialize with Receive PT state.
and the output is the required plaintext (128bit) as shown in
Fig 3. This state is used to get user input and store in FPGA
(Plain text).
VI. IMPLEMENTATION OF ENCRYPTION ON ARTIX-7
When the user presses Enter key it is detected by the state
FPGA BOARD (BLOCK DIAGRAM) machine and it transitions to Receive Key state.
This state is used to get user input and store in FPGA
(Key).
When the user again presses Enter key it is detected by
the state machine and it transitions to Process state.
This state waits for the Encryption/Decryption process to
finish and sends the output.
After the output is sent the state transfers from Process
state to Receive state.
The PC receives the data and shows it on screen. For this
Fig. 4. Elaborated design of encryption design on Basys-3 Board we used the open source TERA TERM software. Both
Receiver and Transmitter work at a baud rate of 9600 baud
A. Receiver with 1 Start bit, 8 data bits and 1 stop bit. This design does
The Receiver module receives serial data from the PC not incorporate parity bits which are standard in some UART
through the UART port and converts each character sent to 8 Protocols.
bit binary data.

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 VII. FPGA IMPLEMENTATION (BOARD TO BOARD) The Encryption process is shown in Fig 9 and the output
is represented in a hexadecimal format. The highlighted part
corresponds to the Encrypted output in the hexadecimal
format.

Fig. 6. Picture depicting setup for board to board communication

The two FPGAs are connected to each other using UART

as shown in the Fig 6 and are interfaced with the laptop using Fig. 10. Picture depicting decryption process(hex output)
Tera Term. The elaborated design is shown in Fig 7 on
Basys-3 Board for board to board communication. The Decryption process is shown in Fig 10 and the output
is represented in a hexadecimal format. The highlighted part
corresponds to the Decrypted output in the hexadecimal
format.
VIII. RESULTS
A. Simulated Results
Here we simulated with the following data :
Plain Text : Bruce Wayne
Plain Text (HEX) : 4272756365205761796E65
Key (HEX): B9CEF3DF1E2157EEAF1F997B124C8C B4
Fig. 7. Elaborated design of decryption design on Basys-3 Board for
board to board communication
Output:D59AB8BB53B55CD77193B1B7C5CE3244 (HEX)
B. Encryption Results

Fig. 8. Picture depicting encryption process

Fig. 11. Timing Simulation of the Synthesized Design (Encryption)
The Encryption process is depicted in Fig 8 and the
output is represented in a string format. From Fig 11 we got the propagation delay of the whole
Encryption process as 40.26 ns.

Fig. 9. Picture depicting encryption process(hex output) Fig. 12. Timing Simulation of the Synthesized Design in Ascii (Encryption)

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 From Fig 12 we got the propagation delay of the whole E. Software Implementation result
Encryption process as 40.26 ns in the hexadecimal format
C. Decryption Results

Fig. 16. AES Implemented using Python language and its result for the
above data
Fig. 13. Timing Simulation of the Synthesized Design (Decryption)
The AES algorithm was implemented on python as well
From Fig 13 we got the propagation delay of the whole and the corresponding results are shown above. It took 51ms
Decryption process as 80.36 ns. to encrypt the plaintext and 7ms to decrypt the encrypted
text.
IX. CONCLUSION AND FUTURE WORK
We were successfully able to Implement AES Algorithm
on Artix - 7. We achieved a much lower propagation delay of
around 40.26 ns and 80.36 ns for Encryption and Decryption
respectively whereas it took around 5ms for encryption as
well as decryption when implemented through software. The
asynchronous implementation of AES algorithm on FPGA
resulted in a much faster rate of encryption and decryption as
compared to the traditional synchronous implementation.
Moreover, combining the Shiftrows and Subbytes operations
together and utilization of more number of S-boxes (due to
asynchronous approach) also accelerated the rate of
Encryption and decryption. We were also able to connect
Fig. 14. Timing Simulation of the Synthesized Design in Ascii
(Decryption)
two FPGAs together and transmit data between them. One
FPGA handled the encryption whereas the second FPGA
The propagation delay of Decryption is almost twice of handled decryption.
Encryption this is mainly for 2 reasons: This setup is not limited to AES-128. It can be further
1. The Inverse Mix Columns operation is a complex extended to implement AES-192 and AES-256. The number
design with many sequential operations than Mix of S-boxes can be reduced to save space, but the tradeoff
Columns operation. would be slower encryption rate. Moreover, this
implementation can be extended to any type of file (audio,
2. To execute round 1 of Decryption we need the last video, etc.) and is not limited to texts.
Key generated from the Key expansion process
therefore round 1 has to wait for the last key to be REFERENCES
generated thus increasing the delay. [1] Advanced encryption standard (AES). Technical Report Federal
Information Processing Standards Publications (FIPS PUBS) 197,
D. Simulation of Encryption on Artix-7 FPGA Board Available from https://www.nist.gov/publications/advanced-
encryption-standard-aes.
[2] N. S. S. Srinivas and M. Akramuddin, "FPGA based hardware
implementation of AES Rijndael algorithm for Encryption and
Decryption", 2016 International Conference on Electrical,
Electronics, and Optimization Techniques (ICEEOT), Chennai, 2016.
[3] Basys3 FPGA Board Reference Manual Overview:
https://reference.digilentinc.com/_media/basys3:basys3_rm.pdf
[4] Joan Boyar and Rene Peralta, “New logic minimization techniques
with applications to cryptology.” Cryptology ePrint Archive, Report
2009/191, 2009.
Fig. 15. Simulation of sending 128 bit data from PC to the Board and [5] Chodowiec P, Gaj K. Very compact FPGA implementation of the
getting Encrypted 128 bit data from the board back to the PC. AES algorithm. Proc. of Cryptographic Hardware and Embedded
System Workshop, 2003;319–333.
The Fig 15 depicts the transmission of 128 bit data from [6] Granado-Criado JM. A new methodology to implement the AES
PC to the FPGA. The FPGA then encrypts the 128 bit data algorithm using partial and dynamic reconfiguration. Integration, the
and sends back the corresponding encrypted output back to VLSI Journal 2010;43(1):72–80.
the laptop.

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