Si4734/35-C40

B ROADCAST AM/FM R ADIO R ECEIVER

Features
 Worldwide FM band support  AM/FM/SW/LW digital tuning
(64–108 MHz)  EN55020 compliant
 Worldwide AM band support  No manual alignment necessary
(520–1710 kHz)  Programmable reference clock
 SW band support  Volume control
(2.3–26.1 MHz)  Adjustable soft mute control
 LW band support  RDS/RBDS processor (Si4735)
(153–279 kHz)  Optional digital audio out (Si4735)
Ordering Information:
 Excellent real-world performance  2-wire and 3-wire control interface
See page 32.
 Freq synthesizer with integrated VCO  Integrated LDO regulator
 Advanced seek tuning  2.0 to 5.5 V supply voltage (SSOP) Pin Assignments
 Automatic frequency control (AFC)  2.7 to 5.5 V supply voltage (QFN)
 Automatic gain control (AGC) Si4734/35 (QFN)
 Wide range of ferrite loop sticks and
 Digital FM stereo decoder

GPO3/DCLK
air loop antennas supported

GPO2/INT
 Programmable AVC max gain  QFN and SSOP packages

GPO1


DFS
Programmable de-emphasis

NC
 RoHS compliant
 Seven selectable AM channel filters NC 1 20 19 18 17 16
FMI 2 15 DOUT
Applications
RFGND 3 GND 14 LOUT
 Table and portable radios  Modules AMI 4 PAD 13 ROUT
 Stereos  Clock radios RST 5 12 GND
 Mini/micro systems  Mini HiFi 6 11 VDD
7 8 9 10
 CD/DVD players  Entertainment systems

VIO
SEN

SCLK

RCLK
SDIO
 Boom boxes

Si4734/35 (SSOP)
Description
DOUT 1 24 LOUT
The Si4734/35 is the first digital CMOS AM/FM radio receiver IC that integrates DFS 2 23 ROUT
the complete tuner function from antenna input to audio output.
GPO3/DCLK 3 22 DBYP

Functional Block Diagram GPO2/INT 4 21 VDD

GPO1 5 20 VIO

FM / SW NC 6 19 RCLK
ANT Si4734/35
NC 7 18 SDIO
FMI DOUT FMI SCLK
RDS
DIGITAL
8 17
LNA (Si4735)
AUDIO DFS RFGND 9 16 SEN
(Si4735)
AGC LOW-IF GPO/DCLK NC RST
10 15
NC 11 14 GND
AM / LW AMI ADC DAC ROUT
AMI 12 13 GND
ANT
LNA DSP
RFGND
ADC DAC LOUT This product, its features, and/or its
AGC
2.7–5.5 V (QFN) architecture is covered by one or more of
2.0–5.5 V (SSOP) VDD the following patents, as well as other
CONTROL
GND LDO AFC VIO patents, pending and issued, both foreign
INTERFACE
1.85-3.6 V
and domestic: 7,127,217; 7,272,373;
7,272,375; 7,321,324; 7,355,476;
RST
SEN
SCLK
SDIO
RCLK

7,426,376; 7,471,940; 7,339,503;

7,339,504.

Rev. 1.0 12/09 Copyright © 2009 by Silicon Laboratories Si4734/35-C40

Si4734/35-C40

2 Rev. 1.0
 Si4734/35-C40
TABLE O F C ONTENTS

Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3. Typical Application Schematic (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Bill of Materials (QFN/SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.5. SW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6. LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.7. Digital Audio Interface (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.8. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.9. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.10. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.11. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.12. RDS/RBDS Processor (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.13. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.14. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.18. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.19. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.20. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7. Pin Descriptions: Si4734/35-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8. Pin Descriptions: Si4734/35-GU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.1. Si4734/35 Top Mark (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.2. Top Mark Explanation (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.3. Si4734/35 Top Mark (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.4. Top Mark Explanation (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11. Package Outline: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12. PCB Land Pattern: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13. Package Outline: Si4734/35 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14. PCB Land Pattern: Si4734/35 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
15. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Rev. 1.0 3
Si4734/35-C40
1. Electrical Specifications

Table 1. Recommended Operating Conditions1

Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage2 VDD 2.7 — 5.5 V
Interface Supply Voltage VIO 1.85 — 3.6 V
Power Supply Powerup Rise Time VDDRISE 10 — — µs
Interface Power Supply Powerup Rise Time VIORISE 10 — — µs
Ambient Temperature TA –20 25 85 C
Note:
1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
VDD = 3.3 V and 25 C unless otherwise stated.
2. SSOP devices operate down to VDD = 2 V at 25 °C.

Table 2. Absolute Maximum Ratings1,2

Parameter Symbol Value Unit
Supply Voltage VDD –0.5 to 5.8 V
Interface Supply Voltage VIO –0.5 to 3.9 V
Input Current3 IIN 10 mA
Input Voltage3 VIN –0.3 to (VIO + 0.3) V
Operating Temperature TOP –40 to 95 C
Storage Temperature TSTG –55 to 150 C
RF Input Level4 0.4 VPK
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4734/35 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. At RF input pins, FMI and AMI.

4 Rev. 1.0
 Si4734/35-C40

Table 3. DC Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

FM Mode
Supply Current1 IFM — 19.2 22 mA
2
Supply Current IFM Low SNR level — 19.9 23 mA
RDS Supply Current1 IFM — 19.2 23 mA

AM/SW/LW Mode
Supply Current1 IAM Analog Output Mode — 15.4 20.5 mA
Supplies and Interface
Interface Supply Current IIO — 320 600 µA
VDD Powerdown Current IDDPD — 10 20 µA
VIO Powerdown Current IIOPD SCLK, RCLK inactive — 1 10 µA
3
High Level Input Voltage VIH 0.7 x VIO — VIO + 0.3 V
3
Low Level Input Voltage VIL –0.3 — 0.3 x VIO V
3
High Level Input Current IIH VIN = VIO = 3.6 V –10 — 10 µA
3
Low Level Input Current IIL VIN = 0 V, –10 — 10 µA
VIO = 3.6 V
High Level Output Voltage4 VOH IOUT = 500 µA 0.8 x VIO — — V
4
Low Level Output Voltage VOL IOUT = –500 µA — — 0.2 x VIO V
Notes:
1. Specifications are guaranteed by characterization.
2. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.

Rev. 1.0 5
Si4734/35-C40

Table 4. Reset Timing Characteristics1,2.3

(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Min Typ Max Unit

RST Pulse Width and GPO1, GPO2/INT Setup to RST tSRST 100 — — µs

GPO1, GPO2/INT Hold from RST tHRST 30 — — ns

Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.

tSRST tHRST

70%
RST
30%

70%
GPO1
30%

GPO2/ 70%

INT 30%

Figure 1. Reset Timing Parameters for Busmode Select

6 Rev. 1.0
 Si4734/35-C40

Table 5. 2-Wire Control Interface Characteristics1,2,3

(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fSCL 0 — 400 kHz
SCLK Low Time tLOW 1.3 — — µs
SCLK High Time tHIGH 0.6 — — µs
SCLK Input to SDIO  Setup tSU:STA 0.6 — — µs
(START)
SCLK Input to SDIO  Hold tHD:STA 0.6 — — µs
(START)
SDIO Input to SCLK  Setup tSU:DAT 100 — — ns
SDIO Input to SCLK  Hold4,5 tHD:DAT 0 — 900 ns
SCLK input to SDIO  Setup tSU:STO 0.6 — — µs
(STOP)
STOP to START Time tBUF 1.3 — — µs
SDIO Output Fall Time tf:OUT — 250 ns
Cb
20 + 0.1 -----------
1pF

SDIO Input, SCLK Rise/Fall Time tf:IN — 300 ns

tr:IN Cb
20 + 0.1 -----------
1pF

SCLK, SDIO Capacitive Loading Cb — — 50 pF

Input Filter Pulse Suppression tSP — — 50 ns
Notes:
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4734/35 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.

Rev. 1.0 7
Si4734/35-C40

tSU:STA tHD:STA tLOW tHIGH tr:IN tf:IN tSP tSU:STO tBUF

70%
SCLK
30%

70%
SDIO
30%

START tHD:DAT tSU:DAT tf:IN,

tr:IN STOP START
tf:OUT

Figure 2. 2-Wire Control Interface Read and Write Timing Parameters

SCLK

A6-A0,
SDIO D7-D0 D7-D0
R/W

START ADDRESS + R/W ACK DATA ACK DATA ACK STOP

Figure 3. 2-Wire Control Interface Read and Write Timing Diagram

8 Rev. 1.0
 Si4734/35-C40

Table 6. 3-Wire Control Interface Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fCLK 0 — 2.5 MHz
SCLK High Time tHIGH 25 — — ns
SCLK Low Time tLOW 25 — — ns
SDIO Input, SEN to SCLKSetup tS 20 — — ns
SDIO Input to SCLKHold tHSDIO 10 — — ns
SEN Input to SCLKHold tHSEN 10 — — ns
SCLKto SDIO Output Valid tCDV Read 2 — 25 ns
SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns
SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.

70%
SCLK
30%

tR tF
tS tHSDIO tHIGH tLOW tHSEN
70%
SEN tS
30%

70% A6-A5,
SDIO A7 R/W, A0 D15 D14-D1 D0
30% A4-A1

Address In Data In

Figure 4. 3-Wire Control Interface Write Timing Parameters

70%
SCLK
30%

tS tHSDIO tCDV tHSEN

tCDZ
70%
SEN tS
30%

70% A6-A5,
SDIO A7 R/W, A0 D15 D14-D1 D0
30% A4-A1

Address In ½ Cycle Bus Data Out

Turnaround

Figure 5. 3-Wire Control Interface Read Timing Parameters

Rev. 1.0 9
Si4734/35-C40

Table 7. SPI Control Interface Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fCLK 0 — 2.5 MHz
SCLK High Time tHIGH 25 — — ns
SCLK Low Time tLOW 25 — — ns
SDIO Input, SEN to SCLKSetup tS 15 — — ns
SDIO Input to SCLKHold tHSDIO 10 — — ns
SEN Input to SCLKHold tHSEN 5 — — ns
SCLKto SDIO Output Valid tCDV Read 2 — 25 ns
SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns
SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.

70%
SCLK
30%

tR tF
tHIGH tLOW tHSDIO
tHSEN
70%
SEN tS
tS
30%

70%
SDIO C7 C6–C1 C0 D7 D6–D1 D0
30%

Control Byte In 8 Data Bytes In

Figure 6. SPI Control Interface Write Timing Parameters

70%
SCLK
30%

tCDV
tS
tHSDIO tHSEN
70%
SEN tS
30%
tCDZ

SDIO 70%
C7 C6–C1 C0 D7 D6–D1 D0
30%

Control Byte In Bus 16 Data Bytes Out

Turnaround (SDIO or GPO1)

Figure 7. SPI Control Interface Read Timing Parameters

10 Rev. 1.0
 Si4734/35-C40

Table 8. Digital Audio Interface Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

DCLK Cycle Time tDCT 26 — 1000 ns
DCLK Pulse Width High tDCH 10 — — ns
DCLK Pulse Width Low tDCL 10 — — ns
DFS Set-up Time to DCLK Rising Edge tSU:DFS 5 — — ns
DFS Hold Time from DCLK Rising Edge tHD:DFS 5 — — ns
DOUT Propagation Delay from DCLK Falling tPD:DOUT 0 — 12 ns
Edge

tDCH tDCL

DCLK

tDCT

DFS
tHD:DFS tSU:DFS

DOUT
tPD:OUT

Figure 8. Digital Audio Interface Timing Parameters, I2S Mode

Rev. 1.0 11
Si4734/35-C40

Table 9. FM Receiver Characteristics1,2

(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Input Frequency fRF 76 — 108 MHz
Sensitivity with Headphone (S+N)/N = 26 dB — 2.2 3.5 µV EMF
Network3,4,5
Sensitivity with 50  Network3,4,5,6 (S+N)/N = 26 dB — 1.1 — µV EMF
RDS Sensitivity6 f = 2 kHz, — 15 — µV EMF
RDS BLER < 5%
LNA Input Resistance6,7 3 4 5 k
6,7
LNA Input Capacitance 4 5 6 pF
Input IP36,8 100 105 — dBµV EMF
AM Suppression3,4,6,7 m = 0.3 40 50 — dB
Adjacent Channel Selectivity ±200 kHz 35 50 — dB
Alternate Channel Selectivity ±400 kHz 60 70 — dB
Spurious Response Rejection6 In-band 35 — — dB
Audio Output Voltage3,4,7 72 80 90 mVRMS
3,7,9 — — 1 dB
Audio Output L/R Imbalance
Audio Frequency Response Low6 –3 dB — — 30 Hz
Audio Frequency Response High6 –3 dB 15 — — kHz
Audio Stereo Separation7,9 32 42 — dB
3,4,5,7,10 55 63 — dB
Audio Mono S/N
4,5,6,7,10,11 — 58 — dB
Audio Stereo S/N
Audio THD3,7,9 — 0.1 0.5 %
De-emphasis Time Constant6 FM_DEEMPHASIS = 2 70 75 80 µs
FM_DEEMPHASIS = 1 45 50 54 µs
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF = 1 mV.
8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
9. f = 75 kHz.
10. At LOUT and ROUT pins.
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature (25°C).

12 Rev. 1.0
 Si4734/35-C40
Table 9. FM Receiver Characteristics1,2 (Continued)
(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Blocking Sensitivity3,4,5,6,12,13 f = ±400 kHz — 32 — dBµV
f = ±4 MHz — 38 — dBµV
Intermode Sensitivity 3,4,5,6,12,13
f = ±400 kHz, ±800 kHz — 40 — dBµV
f = ±4 MHz, ±8 MHz — 35 — dBµV
Audio Output Load Resistance6,10 RL Single-ended 10 — — k
Audio Output Load Capacitance6,10 CL Single-ended — — 50 pF
6
Seek/Tune Time RCLK tolerance — — 60 ms/channel
= 100 ppm
Powerup Time6 From powerdown — — 110 ms
RSSI Offset14 Input levels of 8 and –3 — 3 dB
60 dBµV at RF Input
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF = 1 mV.
8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
9. f = 75 kHz.
10. At LOUT and ROUT pins.
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature (25°C).

Rev. 1.0 13
Si4734/35-C40

Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,6

(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Input Frequency fRF 64 — 75.9 MHz
Sensitivity with Headphone (S+N)/N = 26 dB — 4.0 — µV EMF
Network3,4,5
LNA Input Resistance7 3 4 5 k
LNA Input Capacitance7 4 5 6 pF
8
Input IP3 100 105 — dBµV EMF
3,4,7 m = 0.3 40 50 — dB
AM Suppression
Adjacent Channel Selectivity ±200 kHz — 50 — dB
Alternate Channel Selectivity ±400 kHz — 70 — dB
3,4,7 72 80 90 mVRMS
Audio Output Voltage
3,7,9 — — 1 dB
Audio Output L/R Imbalance
Audio Frequency Response Low –3 dB — — 30 Hz
Audio Frequency Response High –3 dB 15 — — kHz
3,4,5,7,10 55 63 — dB
Audio Mono S/N
Audio THD3,7,9 — 0.1 0.5 %
De-emphasis Time Constant FM_DEEMPHASIS = 2 70 75 80 µs
FM_DEEMPHASIS = 1 45 50 54 µs
10 RL Single-ended 10 — — k
Audio Output Load Resistance
10 CL Single-ended — — 50 pF
Audio Output Load Capacitance
Seek/Tune Time RCLK tolerance — — 60 ms/channel
= 100 ppm
Powerup Time From powerdown — — 110 ms
RSSI Offset11 Input levels of 8 and –3 — 3 dB
60 dBµV EMF
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF = 1 mV.
8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
9. f = 75 kHz.
10. At LOUT and ROUT pins.
11. At temperature (25 °C).

14 Rev. 1.0
 Si4734/35-C40

Table 11. AM/SW/LW Receiver Characteristics1,2

(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Input Frequency fRF Long Wave (LW) 153 — 279 kHz
Medium Wave (AM) 520 — 1710 kHz
Short Wave (SW) 2.3 — 26.1 MHz
3,4,5,6
Sensitivity (S+N)/N = 26 dB — 25 35 µV EMF
Large Signal Voltage THD < 8% — 300 — mVRMS
Handling4,6,7
Power Supply Rejection Ratio6 ΔVDD = 100 mVRMS, 100 Hz — 40 — dB
Audio Output Voltage3,4,8 54 60 67 mVRMS
Audio S/N3,4,5,8 50 56 — dB
Audio THD3,4,8 — 0.1 0.5 %
Antenna Inductance6,9 Long Wave (LW) — 2800 — µH
Medium Wave (AM) 180 — 450 µH
Powerup Time6 From powerdown — — 110 ms
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 520 kHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 30% modulation, 2 kHz channel filter.
4. Analog audio output mode.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. See “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure” for evaluation method.
8. VIN = 5 mVrms.
9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.

Rev. 1.0 15
Si4734/35-C40

Table 12. Reference Clock and Crystal Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Reference Clock
RCLK Supported Frequencies1 31.130 32.768 40,000 kHz
2
RCLK Frequency Tolerance –100 — 100 ppm
REFCLK_PRESCALE 1 — 4095

REFCLK 31.130 32.768 34.406 kHz

Crystal Oscillator
Crystal Oscillator Frequency — 32.768 — kHz
Crystal Frequency Tolerance2 –100 — 100 ppm
Board Capacitance — — 3.5 pF
Notes:
1. The Si4734/35 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx
Programming Guide”.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing and AM seek/tune in SW
frequencies.

16 Rev. 1.0
 Si4734/35-C40
2. Typical Application Schematic (QFN)

GPO1
GPO2/INT

R1 DCLK
R2
DFS

20
19
18
17
16
NC

DFS
GPO1
GPO2
GPO3
DOUT 15 R3 DOUT
1
NC Optional: Digital Audio Output
FMI 2
C4 FMI
3
RFGND LOUT 14 LOUT
U1
L2 L1 ROUT 13 ROUT
Si4734/35-GM
GND 12
4
C5
AMI VDD 11
5 VBATTERY
RST
C1
2.7 to 5.5 V
RCLK
SCLK
SDIO
SEN

VIO
6
7
8
9
10

RST X1
GPO3 RCLK
SEN
SCLK
C2 C3
SDIO
RCLK
Optional: for crystal oscillator option
VIO
1.85 to 3.6 V
Notes:
1. Place C1 close to VDD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. Place Si4734/35 as close as possible to antenna and keep the FMI and AMI traces as short as possible.

Rev. 1.0 17
Si4734/35-C40
3. Typical Application Schematic (SSOP)

Optional: Digital Audio Output

R3
DOUT 1 24 LOUT
C4 R2
DFS 2 23 ROUT
R1 DBYP
GPO3/DCLK 3 22
C1
GPO2/INT 4 21 VDD 2.0 to 5.5 V
VIO 1.85 to 3.6 V
GPO1 5 20
NC 6 19 RCLK
NC 7 18 SDIO
FMI 8 17 SCLK
C4 RFGND 9 16 SEN
NC 10 15 RST
L2 L1
NC 11 14
AMI GND
12 13
C5

X1
GPIO3 RCLK

C2 C3

Optional: for crystal oscillator option

Notes:
1. Place C1 close to VDD and DBYP pins.
2. All grounds connect directly to GND plane on PCB.
3. Pins 6 and 7 are no connects, leave floating.
4. Pins 10 and 11 are unused. Tie these pins to GND.
5. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
6. Pin 8 connects to the FM antenna interface, and pin 12 connects to the AM antenna interface.
7. Place Si4734/35 as close as possible to antenna and keep the FMI and AMI traces as short as possible.

18 Rev. 1.0
 Si4734/35-C40
4. Bill of Materials (QFN/SSOP)

Component(s) Value/Description Supplier

C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata
C5 Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R Murata
L1 Ferrite loop stick, 180–450 µH Jiaxin
L2 4.7 µH Coilcraft
U1 Si4734/35 AM/FM Radio Tuner Silicon Laboratories
Optional Components
C2, C3 Crystal load capacitors, 22 pF, ±5%, COG Venkel
(Optional for crystal oscillator option)
C4 Noise mitigating capacitor, 2~5 pF(Optional for digital audio) Murata
X1 32.768 kHz crystal (Optional for crystal oscillator option) Epson
R1 Resistor, 2 k(Optional for digital audio) Venkel
R2 Resistor, 2 k(Optional for digital audio) Venkel
R3 Resistor, 600 (Optional for digital audio) Venkel

Rev. 1.0 19
Si4734/35-C40
5. Functional Description
5.1. Overview

FM / SW
ANT Si4734/35
FMI RDS DOUT
LNA DIGITAL
(Si4735)
AUDIO DFS
(Si4735)
AGC LOW-IF GPO/DCLK

AM / LW AMI ADC DAC ROUT

ANT
LNA DSP
RFGND
ADC DAC LOUT
AGC
2.7–5.5 V (QFN)
2.0–5.5 V (SSOP) VDD
CONTROL VIO
GND LDO AFC
INTERFACE 1.85-3.6 V

SEN
SCLK
SDIO
RST
RCLK

Figure 9. Functional Block Diagram

The Si4734/35 is the industry's first fully integrated, I2C-compatible 2-wire control interface, SPI, and a
100% CMOS AM/FM/SW/LW radio receiver IC. Offering Si4700/01 backwards-compatible 3-wire control
unmatched integration and PCB space savings, the interface.
Si4734/35 requires minimal external components and The Si4734/35 utilizes digital processing to achieve high
less than 20 mm2 of board area, excluding the antenna fidelity, optimal performance, and design flexibility. The
inputs. The Si4734/35 AM/FM/SW/LW radio provides chip provides excellent pilot rejection, selectivity, and
the space savings and low power consumption unmatched audio performance, and offers both the
necessary for portable devices while delivering the high manufacturer and the end-user extensive
performance and design simplicity desired for all programmability and flexibility in the listening
AM/FM/SW/LW solutions. experience.
Leveraging Silicon Laboratories' proven and patented The Si4735 incorporates a digital processor for the
Si4700/01 FM tuner's digital low intermediate frequency European Radio Data System (RDS) and the North
(low-IF) receiver architecture, the Si4734/35 delivers American Radio Broadcast Data System (RBDS),
superior RF performance and interference rejection in including all required symbol decoding, block
AM, FM, and short wave and long wave bands. The synchronization, error detection, and error correction
high integration and complete system production test functions. Using RDS, the Si4735 enables broadcast
simplifies design-in, increases system quality, and data such as station identification and song name to be
improves manufacturability. displayed to the user.
The Si4734/35 is a feature-rich solution including
advanced seek algorithms, soft mute, auto-calibrated
digital tuning, and FM stereo processing. In addition, the
Si4734/35 provides analog or digital audio output and a
programmable reference clock. The device supports

20 Rev. 1.0
 Si4734/35-C40
5.2. Operating Modes The Si4734/35 provides highly-accurate digital AM
tuning without factory adjustments. To offer maximum
The Si4734/35 operates in either an FM receive or an
flexibility, the receiver supports a wide range of ferrite
AM/SW/LW receive mode. In FM mode, radio signals
loop sticks from 180–450 µH. An air loop antenna is
are received on FMI and processed by the FM front-end
supported by using a transformer to increase the
circuitry. In AM/SW/LW mode, radio signals are received
effective inductance from the air loop. Using a 1:5 turn
on AMI and processed by the AM front-end circuitry. In
ratio inductor, the inductance is increased by 25 times
addition to the receiver mode, there is a clocking mode
and easily supports all typical AM air loop antennas
to choose to clock the Si4734/35 from a reference clock
which generally vary between 10 and 20 µH.
or crystal. On the Si4735, there is an audio output mode
to choose between an analog and/or digital audio 5.5. SW Receiver
output. In the analog audio output mode, ROUT and
The Si4734/35 is the first fully integrated IC to support
LOUT are used for the audio output pins. In the digital
AM and FM, as well as short wave (SW) band reception
audio mode, DOUT, DFS, and DCLK pins are used.
from 2.3 to 26.1 MHz fully covering the 120 meter to
Concurrent analog/digital audio output mode is also
11 meter bands. The Si4734/35 offers extensive
available requiring all five pins. The receiver mode and
shortwave features such as continuous digital tuning
the audio output mode are set by the POWER_UP
with minimal discrete components and no factory
command listed in Table 14, “Selected Si473x
adjustments. Other SW features include adjustable
Commands,” on page 27.
channel step sizes in 1 kHz increments, adjustable
5.3. FM Receiver channel bandwidth settings, advanced seek algorithm,
and soft mute.
The Si4734/35 FM receiver is based on the proven
Si4700/01 FM tuner. The receiver uses a digital low-IF The Si4734/35 uses the FM antenna to capture short
architecture allowing the elimination of external wave signals. These signals are then fed directly into
components and factory adjustments. The Si4734/35 the AMI pin in a wide band configuration. See “AN382:
integrates a low noise amplifier (LNA) supporting the Si4734/35 Designer’s Guide” for more details.
worldwide FM broadcast band (64 to 108 MHz). An 5.6. LW Receiver
AGC circuit controls the gain of the LNA to optimize
sensitivity and rejection of strong interferers. An image- The Si4734/35 supports the long wave (LW) band from
reject mixer downconverts the RF signal to low-IF. The 153 to 279 kHz. The highly integrated Si4734/35 offers
quadrature mixer output is amplified, filtered, and continuous digital tuning with minimal discrete
digitized with high resolution analog-to-digital components and no factory adjustments. The Si4734/35
converters (ADCs). This advanced architecture allows also offers adjustable channel step sizes in 1 kHz
the Si4734/35 to perform channel selection, FM increments, adjustable channel bandwidth settings,
demodulation, and stereo audio processing to achieve advanced seek algorithm, and soft mute.
superior performance compared to traditional analog The Si4734/35 uses a separate ferrite bar antenna to
architectures. capture long wave signals.
5.4. AM Receiver 5.7. Digital Audio Interface (Si4735 Only)
The highly-integrated Si4734/35 supports worldwide AM The digital audio interface operates in slave mode and
band reception from 520 to 1710 kHz using a digital supports three different audio data formats:
low-IF architecture with a minimum number of external
 I2S
components and no manual alignment required. This
 Left-Justified
digital low-IF architecture allows for high-precision
filtering offering excellent selectivity and SNR with  DSP Mode
minimum variation across the AM band. The DSP also 5.7.1. Audio Data Formats
provides adjustable channel step sizes in 1 kHz In I2S mode, by default the MSB is captured on the
increments, AM demodulation, soft mute, seven second rising edge of DCLK following each DFS
different channel bandwidth filters, and additional transition. The remaining bits of the word are sent in
features, such as a programmable automatic volume order, down to the LSB. The left channel is transferred
control (AVC) maximum gain allowing users to adjust first when the DFS is low, and the right channel is
the level of background noise. Similar to the FM transferred when the DFS is high.
receiver, the integrated LNA and AGC optimize
In Left-Justified mode, by default the MSB is captured
sensitivity and rejection of strong interferers allowing
on the first rising edge of DCLK following each DFS
better reception of weak stations.
transition. The remaining bits of the word are sent in

Rev. 1.0 21
Si4734/35-C40
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
5.7.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.

22 Rev. 1.0
 Si4734/35-C40

(OFALL = 1) INVERTED
DCLK

(OFALL = 0) DCLK

DFS LEFT CHANNEL RIGHT CHANNEL

I2S
(OMODE = 0000)
1 DCLK 1 DCLK

DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

Figure 10. I2S Digital Audio Format

(OFALL = 1) INVERTED
DCLK

(OFALL = 0) DCLK

DFS LEFT CHANNEL RIGHT CHANNEL

Left-Justified
(OMODE = 0110)
DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

Figure 11. Left-Justified Digital Audio Format

(OFALL = 0) DCLK

DFS

LEFT CHANNEL RIGHT CHANNEL

(OMODE = 1100) DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

(MSB at 1st rising edge)
MSB LSB MSB LSB
1 DCLK LEFT CHANNEL RIGHT CHANNEL
DOUT
1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n
(OMODE = 1000) (MSB at 2nd rising edge)
MSB LSB MSB LSB

Figure 12. DSP Digital Audio Format

5.8. Stereo Audio Processing 5.8.1. Stereo Decoder
The output of the FM demodulator is a stereo The Si4734/35's integrated stereo decoder
multiplexed (MPX) signal. The MPX standard was automatically decodes the MPX signal using DSP
developed in 1961, and is used worldwide. Today's techniques. The 0 to 15 kHz (L+R) signal is the mono
MPX signal format consists of left + right (L+R) audio, output of the FM tuner. Stereo is generated from the
left – right (L–R) audio, a 19 kHz pilot tone, and (L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
RDS/RBDS data as shown in Figure 13 below. used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
Modulation Level

The Si4735 uses frequency information from the 19 kHz

stereo pilot to recover the 57 kHz RDS/RBDS signal.
Mono Audio
Left + Right Stereo
5.8.2. Stereo-Mono Blending
Stereo Audio RDS/
Pilot Adaptive noise suppression is employed to gradually
Left - Right RBDS
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
0 15 19 23 38 53 57
reception conditions. Stereo/mono status can be
Frequency (kHz) monitored with the FM_RSQ_STATUS command. Mono
Figure 13. MPX Signal Spectrum operation can be forced with the
FM_BLEND_MONO_THRESHOLD property.

Rev. 1.0 23
Si4734/35-C40
5.9. De-emphasis 5.14. Seek
Pre-emphasis and de-emphasis is a technique used by Seek tuning will search up or down for a valid channel.
FM broadcasters to improve the signal-to-noise ratio of Valid channels are found when the receive signal
FM receivers by reducing the effects of high-frequency strength indicator (RSSI) and the signal-to-noise ratio
interference and noise. When the FM signal is (SNR) values exceed the set threshold. Using the SNR
transmitted, a pre-emphasis filter is applied to qualifier rather than solely relying on the more
accentuate the high audio frequencies. The Si4734/35 traditional RSSI qualifier can reduce false stops and
incorporates a de-emphasis filter which attenuates high increase the number of valid stations detected. Seek is
frequencies to restore a flat frequency response. Two initiated using the FM_SEEK_START and
time constants are used in various regions. The de- AM_SEEK_START commands. The RSSI and SNR
emphasis time constant is programmable to 50 or 75 µs threshold settings are adjustable using properties (see
and is set by the FM_DEEMPHASIS property. Table 15).
5.10. Stereo DAC 5.15. Reference Clock
High-fidelity stereo digital-to-analog converters (DACs) The Si4734/35 reference clock is programmable,
drive analog audio signals onto the LOUT and ROUT supporting RCLK frequencies in Table 12. Refer to
pins. The audio output may be muted. Volume is Table 3, “DC Characteristics,” on page 5 for switching
adjusted digitally with the RX_VOLUME property. voltage levels and Table 9, “FM Receiver
Characteristics,” on page 12 for frequency tolerance
5.11. Soft Mute information.
The soft mute feature is available to attenuate the audio An onboard crystal oscillator is available to generate the
outputs and minimize audible noise in very weak signal 32.768 kHz reference when an external crystal and load
conditions. The softmute attenuation level is adjustable capacitors are provided. Refer to "2. Typical Application
using the FM_SOFT_MUTE_MAX_ATTENUATION and Schematic (QFN)" on page 17. This mode is enabled
AM_SOFT_MUTE_MAX_ATTENUATION properties. using the POWER_UP command. Refer to Table 14,
“Selected Si473x Commands,” on page 27.
5.12. RDS/RBDS Processor (Si4735 Only)
The Si4734/35 performance may be affected by data
The Si4735 implements an RDS/RBDS* processor for activity on the SDIO bus when using the integrated
symbol decoding, block synchronization, error internal oscillator. SDIO activity results from polling the
detection, and error correction. tuner for status or communicating with other devices
The Si4735 device is user configurable and provides an that share the SDIO bus. If there is SDIO bus activity
optional interrupt when RDS is synchronized, loses while the Si4734/35 is performing the seek/tune
synchronization, and/or the user configurable RDS function, the crystal oscillator may experience jitter,
FIFO threshold has been met. which may result in mistunes, false stops, and/or lower
The Si4735 reports RDS decoder synchronization SNR.
status and detailed bit errors in the information word for For best seek/tune results, Silicon Laboratories
each RDS block with the FM_RDS_STATUS command. recommends that all SDIO data traffic be suspended
The range of reportable block errors is 0, 1–2, 3–5, or
during Si4734/35 seek and tune operations. This is
6+. More than six errors indicates that the
achieved by keeping the bus quiet for all other devices
corresponding block information word contains six or
on the bus, and delaying tuner polling until the tune or
more non-correctable errors or that the block checkword
seek operation is complete. The seek/tune complete
contains errors.
(STC) interrupt should be used instead of polling to
*Note: RDS/RBDS is referred to only as RDS throughout the
determine when a seek/tune operation is complete.
remainder of this document.
5.16. Control Interface
5.13. Tuning
A serial port slave interface is provided, which allows an
The tuning frequency is directly programmed using the
external controller to send commands to the Si4734/35
FM_TUNE_FREQ and AM_TUNE_FREQ commands.
and receive responses from the device. The serial port
The Si4734/35 supports channel spacing steps of
can operate in three bus modes: 2-wire mode, 3-wire
10 kHz in FM mode and 1 kHz in AM/SW/LW mode.
mode, or SPI mode. The Si4734/35 selects the bus
mode by sampling the state of the GPO1 and GPO2
pins on the rising edge of RST. The GPO1 pin includes
an internal pull-up resistor, which is connected while

24 Rev. 1.0
 Si4734/35-C40
RST is low, and the GPO2 pin includes an internal pull- For read operations, after the Si4734/35 has
down resistor, which is connected while RST is low. acknowledged the control byte, it will drive an 8-bit data
Therefore, it is only necessary for the user to actively byte on SDIO, changing the state of SDIO on the falling
drive pins which differ from these states. See Table 13. edge of SCLK. The user acknowledges each data byte
by driving SDIO low for one cycle, on the next falling
Table 13. Bus Mode Select on Rising Edge of edge of SCLK. If a data byte is not acknowledged, the
RST transaction will end. The user may read up to 16 data
bytes in a single 2-wire transaction. These bytes contain
Bus Mode GPO1 GPO2
the response data from the Si4734/35.
2-Wire 1 0
SPI 1 1 (must drive) A 2-wire transaction ends with the STOP condition,
3-Wire 0 (must drive) 0 which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer
After the rising edge of RST, the pins GPO1 and GPO2 to Table 5, “2-Wire Control Interface Characteristics” on
are used as general purpose output (O) pins, as page 7; Figure 2, “2-Wire Control Interface Read and
described in Section “5.17. GPO Outputs”. In any bus Write Timing Parameters,” on page 8, and Figure 3, “2-
mode, commands may only be sent after VIO and VDD Wire Control Interface Read and Write Timing Diagram,”
supplies are applied. on page 8.
In any bus mode, before sending a command or reading 5.16.2. 3-Wire Control Interface Mode
a response, the user must first read the status byte to When selecting 3-wire mode, the user must ensure that
ensure that the device is ready (CTS bit is high). a rising edge of SCLK does not occur within 300 ns
5.16.1. 2-Wire Control Interface Mode before the rising edge of RST.
When selecting 2-wire mode, the user must ensure that The 3-wire bus mode uses the SCLK, SDIO, and SEN_
SCLK is high during the rising edge of RST, and stays pins. A transaction begins when the user drives SEN
high until after the first start condition. Also, a start low. Next, the user drives a 9-bit control word on SDIO,
condition must not occur within 300 ns before the rising which is captured by the device on rising edges of
edge of RST. SCLK. The control word consists of a 9-bit device
The 2-wire bus mode uses only the SCLK and SDIO address (A7:A5 = 101b), a read/write bit (read = 1, write
pins for signaling. A transaction begins with the START = 0), and a 5-bit register address (A4:A0).
condition, which occurs when SDIO falls while SCLK is For write operations, the control word is followed by a
high. Next, the user drives an 8-bit control word serially 16-bit data word, which is captured by the device on
on SDIO, which is captured by the device on rising rising edges of SCLK.
edges of SCLK. The control word consists of a 7-bit For read operations, the control word is followed by a
device address, followed by a read/write bit (read = 1, delay of one-half SCLK cycle for bus turn-around. Next,
write = 0). The Si4734/35 acknowledges the control the Si4734/35 will drive the 16-bit read data word
word by driving SDIO low on the next falling edge of serially on SDIO, changing the state of SDIO on each
SCLK. rising edge of SCLK.
Although the Si4734/35 will respond to only a single A transaction ends when the user sets SEN high, then
device address, this address can be changed with the pulses SCLK high and low one final time. SCLK may
SEN pin (note that the SEN pin is not used for signaling either stop or continue to toggle while SEN is high.
in 2-wire mode). When SEN = 0, the 7-bit device
In 3-wire mode, commands are sent by first writing each
address is 0010001b. When SEN = 1, the address is
argument to register(s) 0xA1–0xA3, then writing the
1100011b.
command word to register 0xA0. A response is
For write operations, the user then sends an 8-bit data retrieved by reading registers 0xA8–0xAF.
byte on SDIO, which is captured by the device on rising
For details on timing specifications and diagrams, refer
edges of SCLK. The Si4734/35 acknowledges each
to Table 6, “3-Wire Control Interface Characteristics,” on
data byte by driving SDIO low for one cycle, on the next
page 9; Figure 4, “3-Wire Control Interface Write Timing
falling edge of SCLK. The user may write up to 8 data
Parameters,” on page 9, and Figure 5, “3-Wire Control
bytes in a single 2-wire transaction. The first byte is a
Interface Read Timing Parameters,” on page 9.
command, and the next seven bytes are arguments.

Rev. 1.0 25
Si4734/35-C40
5.16.3. SPI Control Interface Mode 5.18. Firmware Upgrades
When selecting SPI mode, the user must ensure that a The Si4734/35 contains on-chip program RAM to
rising edge of SCLK does not occur within 300 ns accommodate minor changes to the firmware. This
before the rising edge of RST. allows Silicon Labs to provide future firmware updates
SPI bus mode uses the SCLK, SDIO, and SEN pins for to optimize the characteristics of new radio designs and
read/write operations. The system controller can those already deployed in the field.
choose to receive read data from the device on either
SDIO or GPO1. A transaction begins when the system 5.19. Reset, Powerup, and Powerdown
controller drives SEN = 0. The system controller then Setting the RST pin low will disable analog and digital
pulses SCLK eight times, while driving an 8-bit control circuitry, reset the registers to their default settings, and
byte serially on SDIO. The device captures the data on disable the bus. Setting the RST pin high will bring the
rising edges of SCLK. The control byte must have one device out of reset.
of five values: A powerdown mode is available to reduce power
 0x48 = write a command (controller drives 8 consumption when the part is idle. Putting the device in
additional bytes on SDIO). powerdown mode will disable analog and digital circuitry
 0x80 = read a response (device drives 1additional while keeping the bus active.
byte on SDIO).
5.20. Programming with Commands
 0xC0 = read a response (device drives 16 additional
bytes on SDIO). To ease development time and offer maximum
customization, the Si4734/35 provides a simple yet
 0xA0 = read a response (device drives 1 additional
powerful software interface to program the receiver. The
byte on GPO1).
device is programmed using commands, arguments,
 0xE0 = read a response (device drives 16 additional
properties, and responses.
bytes on GPO1).
To perform an action, the user writes a command byte
For write operations, the system controller must drive
and associated arguments, causing the chip to execute
exactly 8 data bytes (a command and seven arguments)
the given command. Commands control an action such
on SDIO after the control byte. The data is captured by
as powerup the device, shut down the device, or tune to
the device on the rising edge of SCLK.
a station. Arguments are specific to a given command
For read operations, the controller must read exactly 1 and are used to modify the command. A partial list of
byte (STATUS) after the control byte or exactly 16 data commands is available in Table 14, “Selected Si473x
bytes (STATUS and RESP1–RESP15) after the control Commands,” on page 27.
byte. The device changes the state of SDIO (or GPO1, if
Properties are a special command argument used to
specified) on the falling edge of SCLK. Data must be
modify the default chip operation and are generally
captured by the system controller on the rising edge of
configured immediately after powerup. Examples of
SCLK.
properties are de-emphasis level, RSSI seek threshold,
Keep SEN low until all bytes have transferred. A and soft mute attenuation threshold. A partial list of
transaction may be aborted at any time by setting SEN properties is available in Table 15, “Selected Si473x
high and toggling SCLK high and then low. Commands Properties,” on page 28.
will be ignored by the device if the transaction is
Responses provide the user information and are
aborted.
echoed after a command and associated arguments are
For details on timing specifications and diagrams, refer issued. All commands provide a 1-byte status update,
to Figure 6 and Figure 7 on page 10. indicating interrupt and clear-to-send status information.
For a detailed description of the commands and
5.17. GPO Outputs
properties for the Si4734/35, see “AN332: Si47xx
The Si4734/35 provides three general-purpose output Programming Guide.”
pins. The GPO pins can be configured to output a
constant low, constant high, or high-impedance. The
GPO pins can be reconfigured as specialized functions.
GPO2/INT can be configured to provide interrupts and
GPO3 can be configured to provide external crystal
support or as DCLK in digital audio output mode.

26 Rev. 1.0
 Si4734/35-C40
6. Commands and Properties

Table 14. Selected Si473x Commands

Cmd Name Description
Powerup device and mode selection. Modes include AM or FM receive,
0x01 POWER_UP
analog or digital output, and reference clock or crystal support.
0x10 GET_REV Returns revision information on the device.
0x11 POWER_DOWN Powerdown device.
0x12 SET_PROPERTY Sets the value of a property.
0x13 GET_PROPERTY Retrieves a property’s value.
0x20 FM_TUNE_FREQ Selects the FM tuning frequency.
0x21 FM_SEEK_START Begins searching for a valid frequency.
Queries the status of the Received Signal Quality (RSQ) of the current
0x23 FM_RSQ_STATUS
channel.
Returns RDS information for current channel and reads an entry from the
0x24 FM_RDS_STATUS
RDS FIFO (Si4735 only).
0x40 AM_TUNE_FREQ Selects the AM/SW/LW tuning frequency.
0x41 AM_SEEK_START Begins searching for a valid frequency.
0x43 AM_RSQ_STATUS Queries the status of the RSQ of the current channel.

Rev. 1.0 27
Si4734/35-C40

Table 15. Selected Si473x Properties

Prop Name Description Default
0x1100 FM_DEEMPHASIS Sets de-emphasis time constant. Default is 75 µs. 0x0002
Sets RSSI threshold for stereo blend (full stereo above
FM_BLEND_STEREO_
0x1105 threshold, blend below threshold). To force stereo set this to 0. 0x0031
THRESHOLD
To force mono set this to 127. Default value is 49 dBµV.
Sets RSSI threshold for mono blend (full mono below threshold,
FM_BLEND_MONO_
0x1106 blend above threshold). To force stereo, set this to 0. To force 0x001E
THRESHOLD
mono, set this to 127. Default value is 30 dBµV.
FM_RSQ_INT_
0x1200 Configures interrupt related to RSQ metrics. 0x0000
SOURCE
Sets the attack and decay rates when entering and leaving soft
0x1300 FM_SOFT_MUTE_RATE 0x0040
mute.
FM_SOFT_MUTE_ Sets maximum attenuation during soft mute (dB). Set to 0 to
0x1302 0x0010
MAX_ATTENUATION disable soft mute. Default is 16 dB.
FM_SOFT_MUTE_
0x1303 Sets SNR threshold to engage soft mute. Default is 4 dB. 0x0004
SNR_THRESHOLD
FM_SEEK_BAND_
0x1400 Sets the bottom of the FM band for seek. Default is 8750. 0x222E
BOTTOM
0x1401 FM_SEEK_BAND_TOP Sets the top of the FM band for seek. Default is 10790. 0x2A26
FM_SEEK_FREQ_
0x1402 Selects frequency spacing for FM seek. 0x000A
SPACING
FM_SEEK_TUNE_ Sets the SNR threshold for a valid FM Seek/Tune. Default value
0x1403 0x0003
SNR_THRESHOLD is 3 dB.
FM_SEEK_TUNE_ Sets the RSSI threshold for a valid FM Seek/Tune. Default
0x1404 0x0014
RSSI_TRESHOLD value is 20 dBuV.
0x1500 RDS_INT_SOURCE Configures RDS interrupt behavior. 0x0000
Sets the minimum number of RDS groups stored in the receive
0x1501 RDS_INT_FIFO_COUNT 0x0000
RDS FIFO required before RDS RECV is set.
0x1502 RDS_CONFIG Configures RDS setting. 0x0000
Sets de-emphasis time constant. Can be set to 50 us. De-
0x3100 AM_DEEMPHASIS 0x0000
emphasis is disabled by default.
Selects the bandwidth of the channel filter for AM/SW/LW recep-
tion. The choices are 6, 4, 3, 2.5, 2, 1.8, or 1 kHz. In addition, a
0x3102 AM_CHANNEL_FILTER 0x0003
power line rejection filter can be applied. The default is the
2 kHz bandwidth filter without power line rejection.
AM_AUTOMATIC_VOLUME_
0x3103 Selects the maximum gain for automatic volume control. 0x1543
CONTROL_MAX_GAIN
Configures interrupt related to RSQ metrics. All interrupts are
0x3200 AM_RSQ_INTERRUPTS 0x0000
disabled by default.
Sets the rate of attack when entering or leaving soft mute. The
0x3300 AM_SOFT_MUTE_RATE 0x0040
default is 278 dB/s.
AM_SOFT_MUTE_MAX_
0x3302 Sets maximum attenuation during soft mute (dB). 0x0008
ATTENUATION
AM_SOFT_MUTE_SNR_ Sets SNR threshold to engage soft mute. Default is 0 dB, which
0x3303 0x0008
THRESHOLD disables soft mute.
AM_SEEK_BAND_
0x3400 Sets the bottom of the AM/SW/LW band for seek. Default is 520. 0x0208
BOTTOM

28 Rev. 1.0
 Si4734/35-C40
Table 15. Selected Si473x Properties (Continued)
Prop Name Description Default
0x3401 AM_SEEK_BAND_TOP Sets the top of the AM/SW/LW band for seek. 0x06AE
AM_SEEK_FREQ_ Selects frequency spacing for AM/SW/LW seek. Default is
0x3402 0x000A
SPACING 10 kHz spacing.
Sets the SNR threshold for a valid AM/SW/LW Seek/Tune. If the
AM_SEEK_SNR_
0x3403 value is zero, then SNR threshold is not considered when doing 0x0005
THRESHOLD
a seek. Default value is 5 dB.
Sets the RSSI threshold for a valid AM/SW/LW Seek/Tune. If
AM_SEEK_RSSI_
0x3404 the value is zero, then RSSI threshold is not considered when 0x0019
THRESHOLD
doing a seek. Default value is 25 dBµV.
0x4000 RX_VOLUME Sets the output volume. 0x003F
Mutes the audio output. L and R audio outputs may be muted
0x4001 RX_HARD_MUTE 0x0000
independently in FM mode.

Rev. 1.0 29
Si4734/35-C40
7. Pin Descriptions: Si4734/35-GM

GPO3/DCLK
GPO2/INT
GPO1

DFS
NC
NC 1 20 19 18 17 16
FMI 2 15 DOUT
RFGND 3 GND 14 LOUT
AMI 4 PAD 13 ROUT
RST 5 12 GND
6 7 8 9 10 11 VDD
SEN

SCLK

RCLK
VIO
SDIO

Pin Number(s) Name Description

1, 20 NC No connect. Leave floating.
2 FMI FM RF inputs. FMI should be connected to the antenna trace.
3 RFGND RF ground. Connect to ground plane on PCB.
4 AMI AM/SW/LW RF input.
5 RST Device reset (active low) input.
6 SEN Serial enable input (active low).
7 SCLK Serial clock input.
8 SDIO Serial data input/output.
9 RCLK External reference oscillator input.
10 VIO I/O supply voltage.
11 VDD Supply voltage. May be connected directly to battery.
12, GND PAD GND Ground. Connect to ground plane on PCB.
13 ROUT Right audio line output in analog output mode.
14 LOUT Left audio line output in analog output mode.
15 DOUT Digital output data in digital output mode.
16 DFS Digital frame synchronization input in digital output mode.
17 GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
18 GPO2/INT General purpose output or interrupt pin.
19 GPO1 General purpose output.

30 Rev. 1.0
 Si4734/35-C40
8. Pin Descriptions: Si4734/35-GU

DOUT 1 24 LOUT
DFS 2 23 ROUT

GPO3/DCLK 3 22 DBYP
GPO2/INT 4 21 VDD
GPO1 5 20 VIO
NC 6 19 RCLK
NC 7 18 SDIO
FMI 8 17 SCLK
RFGND 9 16 SEN
NC 10 15 RST
NC 11 14 GND
AMI 12 13 GND

Pin Number(s) Name Description

1 DOUT Digital output data in digital output mode.
2 DFS Digital frame synchronization input in digital output mode.
3 GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
4 GPO2/INT General purpose output or interrupt pin.
5 GPO1 General purpose output.
6,7 NC No connect. Leave floating.
8 FMI FM RF inputs. FMI should be connected to the antenna trace.
9 RFGND RF ground. Connect to ground plane on PCB.
10,11 NC Unused. Tie these pins to GND.
12 AMI AM/SW/LW RF input.
13,14 GND Ground. Connect to ground plane on PCB.
15 RST Device reset (active low) input.
16 SEN Serial enable input (active low).
17 SCLK Serial clock input.
18 SDIO Serial data input/output.
19 RCLK External reference oscillator input.
20 VIO I/O supply voltage.
21 VDD Supply voltage. May be connected directly to battery.
22 DBYP Dedicated bypass for VDD and VIO.
23 ROUT Right audio line output in analog output mode.
24 LOUT Left audio line output in analog output mode.

Rev. 1.0 31
Si4734/35-C40
9. Ordering Guide

Part Number* Description Package Operating

Type Temperature/Voltage
Si4734-C40-GM AM/FM/SW/LW Broadcast Radio Receiver QFN –20 to 85 °C
Pb-free 2.7 to 5.5 V
Si4734-C40-GU AM/FM/SW/LW Broadcast Radio Receiver SSOP –20 to 85 °C
Pb-free 2.0 to 5.5 V
Si4735-C40-GM AM/FM/SW/LW Broadcast Radio Receiver QFN –20 to 85 °C
with RDS/RBDS Pb-free 2.7 to 5.5 V
Si4735-C40-GU AM/FM/SW/LW Broadcast Radio Receiver SSOP –20 to 85 °C
with RDS/RBDS Pb-free 2.0 to 5.5 V
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. SSOP
devices operate down to VDD = 2 V at 25 °C.

32 Rev. 1.0
 Si4734/35-C40
10. Package Markings (Top Marks)
10.1. Si4734/35 Top Mark (QFN)

3440 3540
CTTT CTTT
YWW YWW
10.2. Top Mark Explanation (QFN)

Mark Method: YAG Laser

Line 1 Marking: Part Number 34 = Si4734, 35 = Si4735.
Firmware Revision 40 = Firmware Revision 4.0.
Line 2 Marking: Die Revision C = Revision C Die.
TTT = Internal Code Internal tracking code.
Line 3 Marking: Circle = 0.5 mm Diameter Pin 1 Identifier.
(Bottom-Left Justified)
Y = Year Assigned by the Assembly House. Corresponds to the last
WW = Workweek significant digit of the year and work week of the mold date.

Rev. 1.0 33
Si4734/35-C40
10.3. Si4734/35 Top Mark (SSOP)

4734C40GU
YYWWTTTTTT
10.4. Top Mark Explanation (SSOP)

Mark Method: YAG Laser

Part Number 4734 = Si4734; 4735 = Si4735.
Line 1 Marking: Die Revision C = Revision C die.
Firmware Revision 40 = Firmware Revision 4.0.
YY = Year
Line 2 Marking: WW = Work week Assigned by the Assembly House.
TTTTTT = Manufacturing code

34 Rev. 1.0
 Si4734/35-C40
11. Package Outline: Si4734/35 QFN
Figure 14 illustrates the package details for the Si4734/35. Table 16 lists the values for the dimensions shown in
the illustration.

Figure 14. 20-Pin Quad Flat No-Lead (QFN)

Table 16. Package Dimensions

Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.50 0.55 0.60 f 2.53 BSC
A1 0.00 0.02 0.05 L 0.35 0.40 0.45
b 0.20 0.25 0.30 L1 0.00 — 0.10
c 0.27 0.32 0.37 aaa — — 0.05
D 3.00 BSC bbb — — 0.05
D2 1.65 1.70 1.75 ccc — — 0.08
e 0.50 BSC ddd — — 0.10
E 3.00 BSC eee — — 0.10
E2 1.65 1.70 1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

Rev. 1.0 35
Si4734/35-C40
12. PCB Land Pattern: Si4734/35 QFN
Figure 15 illustrates the PCB land pattern details for the Si4734/35-C40-GM QFN. Table 17 lists the values for the
dimensions shown in the illustration.

Figure 15. PCB Land Pattern

36 Rev. 1.0
 Si4734/35-C40

Table 17. PCB Land Pattern Dimensions

Symbol Millimeters Symbol Millimeters
Min Max Min Max
D 2.71 REF GE 2.10 —
D2 1.60 1.80 W — 0.34
e 0.50 BSC X — 0.28
E 2.71 REF Y 0.61 REF
E2 1.60 1.80 ZE — 3.31
f 2.53 BSC ZD — 3.31
GD 2.10 —
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Notes: Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Notes: Stencil Design

1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.

Notes: Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.

Rev. 1.0 37
Si4734/35-C40
13. Package Outline: Si4734/35 SSOP
Figure 16 illustrates the package details for the Si4734/35. Table 18 lists the values for the dimensions shown in
the illustration.

Figure 16. 24-Pin SSOP

Table 18. Package Dimensions

Dimension Min Nom Max
A — — 1.75
A1 0.10 — 0.25
b 0.20 — 0.30
c 0.10 — 0.25
D 8.65 BSC
E 6.00 BSC
E1 3.90 BSC
e 0.635 BSC
L 0.40 — 1.27
L2 0.25 BSC
θ 0° — 8°
aaa 0.20
bbb 0.18
ccc 0.10
ddd 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.

38 Rev. 1.0
 Si4734/35-C40
14. PCB Land Pattern: Si4734/35 SSOP
Figure 17 illustrates the PCB land pattern details for the Si4734/35-C40-GU SSOP. Table 19 lists the values for the
dimensions shown in the illustration.

Figure 17. PCB Land Pattern

Table 19. PCB Land Pattern Dimensions

Dimension Min Max
C 5.20 5.40
E 0.65 BSC
X1 0.35 0.45
Y1 1.55 1.75
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly:
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.

Rev. 1.0 39
Si4734/35-C40
15. Additional Reference Resources
Contact your local sales representatives for more information or to obtain copies of the following references:
 EN55020 Compliance Test Certificate
 AN332: Si47xx Programming Guide
 AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines
 AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure

40 Rev. 1.0
 Si4734/35-C40
DOCUMENT CHANGE LIST
Revision 0.71 to Revision 1.0
 Updated patent information on page 1.
 Pin 22 changed from “GND” to “DBYP.”
 Updated Table 1 on page 4.
 Updated Table 3 on page 5.
 Updated Table 11 on page 15.
 Updated "3. Typical Application Schematic (SSOP)"
on page 18.
 Updated "4. Bill of Materials (QFN/SSOP)" on page
19.
 Updated "8. Pin Descriptions: Si4734/35-GU" on
page 31.
 Updated "9. Ordering Guide" on page 32.

Rev. 1.0 41
Si4734/35-C40
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: FMinfo@silabs.com
Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
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quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

42 Rev. 1.0