Differential/Single-Ended Input, Dual

2 MSPS, 12-Bit, 3-Channel SAR ADC

AD7266
FEATURES FUNCTIONAL BLOCK DIAGRAM
REF SELECT DCAPA AVDD DVDD
Dual 12-bit, 3-channel ADC
Throughput rate: 2 MSPS
Specified for VDD of 2.7 V to 5.25 V REF BUF
AD7266
Power consumption
VA1
9 mW at 1.5 MSPS with 3 V supplies VA2
27 mW at 2 MSPS with 5 V supplies 12-BIT
VA3 SUCCESSIVE OUTPUT
Pin-configurable analog inputs MUX T/H APPROXIMATION DRIVERS DOUTA
VA4
ADC
12-channel single-ended inputs VA5
6-channel fully differential inputs SCLK
VA6
CS
6-channel pseudo differential inputs RANGE
70 dB SNR at 50 kHz input frequency CONTROL SGL/DIFF
LOGIC A0
Accurate on-chip reference: 2.5 V A1
±0.2% maximum @ 25°C, 20 ppm/°C maximum VB1 A2

Dual conversion with read 437.5 ns, 32 MHz SCLK VB2

VDRIVE
High speed serial interface VB3
MUX 12-BIT
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible VB4 SUCCESSIVE OUTPUT
T/H APPROXIMATION DRIVERS DOUTB
−40°C to +125°C operation VB5 ADC
VB6
Shutdown mode: 1 μA maximum
32-lead LFCSP and 32-lead TQFP BUF

1 MSPS version, AD7265

04603-001
AGND AGND AGND DCAPB DGND DGND
GENERAL DESCRIPTION
Figure 1.
The AD72661 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V The AD7266 is available in a 32-lead LFCSP and a
power supply and features throughput rates up to 2 MSPS. The 32-lead TQFP.
device contains two ADCs, each preceded by a 3-channel
PRODUCT HIGHLIGHTS
multiplexer, and a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 30 MHz. 1. Two Complete ADC Functions Allow Simultaneous
Sampling and Conversion of Two Channels.
The conversion process and data acquisition use standard Each ADC has three fully/pseudo differential pairs, or six
control inputs allowing easy interfacing to microprocessors or single-ended channels, as programmed. The conversion
DSPs. The input signal is sampled on the falling edge of CS; result of both channels is simultaneously available on
conversion is also initiated at this point. The conversion time is separate data lines, or in succession on one data line if only
determined by the SCLK frequency. There are no pipelined one serial port is available.
delays associated with the part.
2. High Throughput with Low Power Consumption.
The AD7266 uses advanced design techniques to achieve very The AD7266 offers a 1.5 MSPS throughput rate with
low power dissipation at high throughput rates. With 5 V 11.4 mW maximum power dissipation when operating at 3 V.
supplies and a 2 MSPS throughput rate, the part consumes 3. The AD7266 offers both a standard 0 V to VREF input range
6.2 mA maximum. The part also offers flexible power/ and a 2 × VREF input range.
throughput rate management when operating in normal mode
4. No Pipeline Delay.
as the quiescent current consumption is so low.
The part features two standard successive approximation
The analog input range for the part can be selected to be a 0 V ADCs with accurate control of the sampling instant via a
to VREF (or 2 × VREF) range, with either straight binary or twos CS input and once off conversion control.
complement output coding. The AD7266 has an on-chip 2.5 V
1
reference that can be overdriven when an external reference is Protected by U.S. Patent No. 6,681,332
preferred. This external reference range is 100 mV to VDD.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 www.analog.com
Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005–2020 Analog Devices, Inc. All rights reserved.
AD7266

TABLE OF CONTENTS
Features .............................................................................................. 1  VDRIVE ............................................................................................ 18 
General Description ......................................................................... 1  Modes of Operation ....................................................................... 19 
Functional Block Diagram .............................................................. 1  Normal Mode ............................................................................. 19 
Product Highlights ........................................................................... 1  Partial Power-Down Mode ....................................................... 19 
Revision History ............................................................................... 2  Full Power-Down Mode............................................................ 20 
Specifications .................................................................................... 3  Power-Up Times ........................................................................ 21 
Timing Specifications .................................................................. 5  Power vs. Throughput Rate ...................................................... 21 
Absolute Maximum Ratings ........................................................... 6  Serial Interface ................................................................................ 22 
ESD Caution.................................................................................. 6  Microprocessor Interfacing .......................................................... 23 
Pin Configuration and Function Descriptions ............................ 7  AD7266 to ADSP-218x ............................................................. 23 
Typical Performance Characteristics ............................................. 9  AD7266 to ADSP-BF53x........................................................... 24 
Terminology .................................................................................... 11  AD7266 to TMS320C541 .......................................................... 24 
Theory of Operation ...................................................................... 13  AD7266 to DSP563xx ................................................................ 25 
Circuit Information ................................................................... 13  Application Hints ........................................................................... 26 
Converter Operation.................................................................. 13  Grounding and Layout .............................................................. 26 
Analog Input Structure.............................................................. 13  PCB Design Guidelines for LFCSP .......................................... 26 
Analog Inputs ............................................................................. 14  Evaluating the AD7266 Performance...................................... 26 
Analog Input Selection .............................................................. 17  Outline Dimensions ....................................................................... 27 
Output Coding............................................................................ 17  Ordering Guide .......................................................................... 27 
Transfer Functions ..................................................................... 18 
Digital Inputs .............................................................................. 18 

REVISION HISTORY
11/2020—Rev. B to Rev. C 11/2006—Rev. 0 to Rev. A
Changed CP-32-2 to CP-32-7 ...................................... Throughout Changes to Format ............................................................. Universal
Changes to Figure 2.......................................................................... 7 Changes to Reference Input/Output Section ................................4
Updated Outline Dimensions ....................................................... 27 Changes to Table 4 ............................................................................7
Changes to Ordering Guide .......................................................... 27 Changes to Terminology Section ................................................. 11
Changes to Figure 24 and Differential Mode Section ............... 15
Changes to Figure 29 ..................................................................... 16
5/2011—Rev. A to Rev. B Changes to Figure 39 ..................................................................... 21
Changes to Mnemonic Order for Pin 13 to Pin 18, Pin 23 to Changes to AD7265 to ADSP-BF53x Section ............................ 24
Pin 25, and Pin 28, Pin 30 in Table 4 ............................................. 7 Updated Outline Dimensions ...................................................... 27
Added EPAD Note ........................................................................... 7 Changes to Ordering Guide .......................................................... 27
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
4/2005—Revision 0: Initial Version

Rev. C | Page 2 of 28
 AD7266

SPECIFICATIONS
TA = TMIN to TMAX, VDD = 2.7 V to 3.6 V, fSCLK = 24 MHz, fS = 1.5 MSPS, VDRIVE = 2.7 V to 3.6 V; VDD = 4.75 V to 5.25 V,
fSCLK = 32 MHz, fS = 2 MSPS, VDRIVE = 2.7 V to 5.25 V; specifications apply using internal reference or external reference = 2.5 V ± 1%,
unless otherwise noted1.

Table 1.
Parameter Specification Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)2 71 dB min fIN = 50 kHz sine wave; differential mode
69 dB min fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
Signal-to-Noise + Distortion Ratio (SINAD)2 70 dB min fIN = 50 kHz sine wave; differential mode
68 dB min fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
Total Harmonic Distortion (THD)2 –77 dB max fIN = 50 kHz sine wave; differential mode
–73 dB max fIN = 50 kHz sine wave; single-ended and
pseudo differential modes
Spurious-Free Dynamic Range (SFDR)2 –75 dB max fIN = 50 kHz sine wave
Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz
Second-Order Terms –88 dB typ
Third-Order Terms –88 dB typ
Channel-to-Channel Isolation –88 dB typ
SAMPLE AND HOLD
Aperture Delay3 11 ns max
Aperture Jitter3 50 ps typ
Aperture Delay Matching3 200 ps max
Full Power Bandwidth 33/26 MHz typ @ 3 dB, VDD = 5 V/VDD = 3 V
3.5/3 MHz typ @ 0.1 dB, VDD = 5 V/VDD = 3 V
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity2 ±1 LSB max ±0.5 LSB typ; differential mode
±1.5 LSB max ±0.5 LSB typ; single-ended and pseudo
differential modes
Differential Nonlinearity2, 4 ±0.99 LSB max Differential mode
−0.99/+1.5 LSB max Single-ended and pseudo differential modes
Straight Binary Output Coding
Offset Error ±7 LSB max ±2 LSB typ
Offset Error Match ±2 LSB typ
Gain Error ±2.5 LSB max
Gain Error Match ±0.5 LSB typ
Twos Complement Output Coding
Positive Gain Error ±2 LSB max
Positive Gain Error Match ±0.5 LSB typ
Zero Code Error ±5 LSB max
Zero Code Error Match ±1 LSB typ
Negative Gain Error ±2 LSB max
Negative Gain Error Match ±0.5 LSB typ
ANALOG INPUT5
Single-Ended Input Range 0 V to VREF V RANGE pin low
0 V to 2 × VREF RANGE pin high
Pseudo Differential Input Range: VIN+ − VIN−6 0 to VREF V RANGE pin low
2 × VREF V RANGE pin high
Fully Differential Input Range: VIN+ and VIN− VCM ± VREF/2 V VCM = common-mode voltage7 = VREF/2
VIN+ and VIN− VCM ± VREF V VCM = VREF

Rev. C | Page 3 of 28
AD7266
Parameter Specification Unit Test Conditions/Comments
DC Leakage Current ±1 μA max
Input Capacitance 45 pF typ When in track
10 pF typ When in hold
REFERENCE INPUT/OUTPUT
Reference Output Voltage8 2.5 V min/V max ±0.2% max @ 25°C
Long-Term Stability 150 ppm typ For 1000 hours
Output Voltage Hysteresis2 50 ppm typ
Reference Input Voltage Range 0.1/VDD V min/V max See Typical Performance Characteristics section
DC Leakage Current ±2 μA max External reference applied to Pin DCAPA/Pin DCAPB
Input Capacitance 25 pF typ
DCAPA, DCAPB Output Impedance 10 Ω typ
Reference Temperature Coefficient 20 ppm/°C max
10 ppm/°C typ
VREF Noise 20 μV rms typ
LOGIC INPUTS
Input High Voltage, VINH 2.8 V min
Input Low Voltage, VINL 0.4 V max
Input Current, IIN ±15 nA typ VIN = 0 V or VDRIVE
Input Capacitance, CIN3 5 pF typ
LOGIC OUTPUTS
Output High Voltage, VOH VDRIVE − 0.2 V min
Output Low Voltage, VOL 0.4 V max
Floating State Leakage Current ±1 μA max
Floating State Output Capacitance3 7 pF typ
Output Coding Straight (natural) binary SGL/DIFF = 1 with 0 V to VREF range selected
Twos complement SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × VREF range
CONVERSION RATE
Conversion Time 14 SCLK cycles 437.5 ns with SCLK = 32 MHz
Track-and-Hold Acquisition Time3 90 ns max Full-scale step input; VDD = 5 V
110 ns max Full-scale step input; VDD = 3 V
Throughput Rate 2 MSPS max
POWER REQUIREMENTS
VDD 2.7/5.25 V min/V max
VDRIVE 2.7/5.25 V min/V max
IDD Digital I/Ps = 0 V or VDRIVE
Normal Mode (Static) 2.3 mA max VDD = 5.25 V
Operational, fS = 2 MSPS 6.4 mA max VDD = 5.25 V; 5.7 mA typ
fS = 1.5 MSPS 4 mA max VDD = 3.6 V; 3.4 mA typ
Partial Power-Down Mode 500 μA max Static
Full Power-Down Mode (VDD) 1 μA max TA = −40°C to +85°C
2.8 μA max TA > 85°C to 125°C
Power Dissipation
Normal Mode (Operational) 33.6 mW max VDD = 5.25 V
Partial Power-Down (Static) 2.625 mW max VDD = 5.25 V
Full Power-Down (Static) 5.25 μW max VDD = 5.25 V, TA = −40°C to +85°C
1
Temperature range is −40°C to +125°C.
2
See Terminology section.
3
Sample tested during initial release to ensure compliance.
4
Guaranteed no missed codes to 12 bits.
5
VIN− or VIN+ must remain within GND/VDD.
6
VIN− = 0 V for specified performance. For full input range on VIN− pin, see Figure 28 and Figure 29.
7
For full common-mode range, see Figure 24 and Figure 25.
8
Relates to Pin DCAPA or Pin DCAPB.

Rev. C | Page 4 of 28
 AD7266
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, internal/external reference = 2.5 V, TA = TMAX to TMIN, unless otherwise noted1.

Table 2.
Parameter Limit at TMIN , TMAX Unit Description
fSCLK2 1 MHz min TA = −40°C to +85°C
4 MHz min TA > 85°C to 125°C
32 MHz max
tCONVERT 14 × tSCLK ns max tSCLK = 1/fSCLK
437.5 ns max fSCLK = 32 MHz, VDD = 5 V, fSAMPLE = 2 MSPS
583.3 ns max fSCLK = 24 MHz, VDD = 3 V, fSAMPLE = 1.5 MSPS
tQUIET 30 ns min Minimum time between end of serial read and next falling edge of CS
t2 15/20 ns min VDD = 5 V/3 V, CS to SCLK setup time, TA = −40°C to +85°C
20/30 ns min VDD = 5 V /3 V, CS to SCLK setup time, TA > 85°C to 125°C
t3 15 ns max Delay from CS until DOUTA and DOUTB are three-state disabled
t43 36 ns max Data access time after SCLK falling edge, VDD = 3 V
27 ns max Data access time after SCLK falling edge, VDD = 5 V
t5 0.45 tSCLK ns min SCLK low pulse width
t6 0.45 tSCLK ns min SCLK high pulse width
t7 10 ns min SCLK to data valid hold time, VDD = 3 V
5 ns min SCLK to data valid hold time, VDD = 5 V
t8 15 ns max CS rising edge to DOUTA, DOUTB, high impedance
t9 30 ns min CS rising edge to falling edge pulse width
t10 5 ns min SCLK falling edge to DOUTA, DOUTB, high impedance
35 ns max SCLK falling edge to DOUTA, DOUTB, high impedance
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See Serial
Interface section and Figure 41 and Figure 42.
2
Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.
3
The time required for the output to cross 0.4 V or 2.4 V.

Rev. C | Page 5 of 28
AD7266

ABSOLUTE MAXIMUM RATINGS

Table 3. Stresses above those listed under Absolute Maximum Ratings
Parameter Rating may cause permanent damage to the device. This is a stress
VDD to AGND −0.3 V to +7 V rating only; functional operation of the device at these or any
DVDD to DGND −0.3 V to +7 V other conditions above those indicated in the operational
VDRIVE to DGND −0.3 V to DVDD section of this specification is not implied. Exposure to absolute
VDRIVE to AGND −0.3 V to AVDD maximum rating conditions for extended periods may affect
AVDD to DVDD −0.3 V to +0.3 V device reliability.
AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
ESD CAUTION
Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V
VREF to AGND −0.3 V to AVDD + 0.3 V
Input Current to Any Pin
Except Supplies1 ±10 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
LFCSP/TQFP
θJA Thermal Impedance 108.2°C/W (LFCSP)
55°C/W (TQFP)
θJC Thermal Impedance 32.71°C/W (LFCSP)
Lead Temperature, Soldering
Reflow Temperature (10 to 30 sec) 255°C
ESD 1.5 kV
1
Transient currents of up to 100 mA will not cause latch up.

Rev. C | Page 6 of 28
 AD7266

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DOUTA

DOUTB
VDRIVE

DOUTA

DOUTB
VDRIVE
DGND

DGND
SCLK

SCLK
DV DD

DVDD
CS

CS
A0

A0
32
31
30
29
28
27
26
25
32 31 30 29 28 27 26 25

DGND 1 24 A1 DGND 1 24 A1
REF SELECT 2 23 A2 PIN 1
REF SELECT 2 23 A2
AVDD 3 22 SGL/DIFF SGL/DIFF
AD7266 AVDD 3 22
DCAP A 4 21 RANGE AD7266
AGND 5 TOP VIEW 20 DCAP B DCAP A 4 21 RANGE
(Not to Scale) TOP VIEW
AGND 6 19 AGND AGND 5 (Not to Scale) 20 DCAP B
VA1 7 18 VB1 AGND 6 19 AGND
VA2 8 17 VB2
VA1 7 18 VB1
VA2 8 17 VB2
9
10
11
12
13
14
15
16
VA3
VA4
VA5
VA6
VB6
VB5
VB4
VB3

9 10 11 12 13 14 15 16

04603-041
VA3
VA4
VA5
VA6
VB6
VB5
VB4
VB3
NOTES

04603-002
1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE
LFCSP PACKAGE SHOULD BE SOLDERED TO PCB GROUND.

Figure 2. Pin Configuration (CP-32-7) Figure 3. Pin Configuration (SU-32-2)

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1, 29 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7266. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
2 REF SELECT Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used as
the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to decoupling
capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7266
through the DCAPA and/or DCAPB pins.
3 AVDD Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7266. The
AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis. This supply should be decoupled to AGND.
4, 20 DCAPA, Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to
DCAPB decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference can
be taken from these pins and applied externally to the rest of a system. The range of the external reference is
dependent on the analog input range selected.
5, 6, 19 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7266. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not
be more than 0.3 V apart, even on a transient basis.
7 to 12 VA1 to VA6 Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
13 to 18 VB6 to VB1 Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
21 RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input
channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is tied to a logic high when
CS goes low, the analog input range is 2 × VREF. See the Analog Input Selection section for details.
22 SGL/DIFF Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic
low selects differential operation while a logic high selects single-ended operation. See the Analog Input
Selection section for details.
23 to 25 A2 to A0 Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously
converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair
of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins
need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the
multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for
multiplexer address decoding.
26 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7266
and framing the serial data transfer.

Rev. C | Page 7 of 28
AD7266
Pin No. Mnemonic Description
27 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7266. This clock
is also used as the clock source for the conversion process.
28, 30 DOUTB, Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the
DOUTA falling edge of the SCLK input and 14 SCLKs are required to access the data. The data simultaneously appears on
both pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros
followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles
rather than 14, then two trailing zeros will appear after the 12 bits of data. If CS is held low for a further 16 SCLK
cycles on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data from a
simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one
serial port. See the Serial Interface section.
31 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This
pin should be decoupled to DGND. The voltage at this pin may be different than that at AVDD and DVDD but should
never exceed either by more than 0.3 V.
32 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7266. The DVDD
and AVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a
transient basis. This supply should be decoupled to DGND.
EPAD Exposed Pad. The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB ground.

Rev. C | Page 8 of 28
 AD7266

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.
–60
4096 POINT FFT
INTERNAL REFERENCE
–10 VDD = 5V, VDRIVE = 3V
FSAMPLE = 2MSPS
–70 FIN = 52kHz
SINAD = 71.4dB
–30 THD = –84.42dB
–80 DIFFERENTIAL MODE
EXTERNAL REFERENCE
–50
PSRR (dB)

–90

(dB)
–70
–100

–110 –90
100mV p-p SINE WAVE ON AVDD
NO DECOUPLING
SINGLE-ENDED MODE
–120 –110

04603-006
04603-003
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY (kHz) FREQUENCY (kHz)

Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 7. FFT

–50 1.0
VDD = 5V VDD = 5V, VDRIVE = 3V
–55 DIFFERENTIAL MODE
0.8

–60 0.6

–65 0.4
DNL ERROR (LSB)
ISOLATION (dB)

–70 0.2

–75 0

–80 –0.2

–85 –0.4

–90 –0.6

–95 –0.8

–100 –1.0
04603-004

04603-007
0 100 200 300 400 500 600 700 800 900 1000 0 500 1000 1500 2000 2500 3000 3500 4000
NOISE FREQUENCY (kHz) CODE

Figure 5. Channel-to-Channel Isolation Figure 8. Typical DNL

74 1.0
VDD = 5V RANGE = 0 TO VREF VDD = 5V, VDRIVE = 3V
DIFFERENTIAL MODE DIFFERENTIAL MODE
0.8
72
0.6
VDD = 3V
70 DIFFERENTIAL MODE 0.4
INL ERROR (LSB)

0.2
68
SINAD (dB)

0
66
–0.2

64 –0.4

–0.6
62
–0.8

60 –1.0
04603-008
04603-005

0 500 1000 1500 2000 2500 3000 0 500 1000 1500 2000 2500 3000 3500 4000
INPUT FREQUENCY (kHz) CODE

Figure 6. SINAD vs. Analog Input Frequency for Various Supply Voltages Figure 9. Typical INL

Rev. C | Page 9 of 28
AD7266
1.0 10000
VDD = 3V/5V INTERNAL 10000
DIFFERENTIAL
DIFFERENTIAL MODE REFERENCE MODE
0.8 9000 CODES

0.6 POSITIVE DNL 8000

LINEARITY ERROR (LSB)

0.4 7000

NO. OF OCCURRENCES
POSITIVE INL
0.2 6000

0 5000

–0.2 4000
NEGATIVE INL
–0.4 3000

–0.6 NEGATIVE DNL 2000

–0.8 1000

–1.0 0

04603-012
04603-009
0 0.5 1.0 1.5 2.0 2.5 2046 2047 2048 2049 2050
VREF (V) CODE

Figure 10. Linearity Error vs. VREF Figure 13. Histogram of Codes for 10k Samples in Differential Mode

10000
12.0 INTERNAL 9984 SINGLE-ENDED
REFERENCE CODES MODE
9000
11.5
8000
11.0
EFFECTIVE NUMBER OF BITS

VDD = 5V
NO. OF OCCURRENCES 7000
10.5 SINGLE-ENDED MODE
6000
10.0

VDD = 3V 5000
9.5
SINGLE-ENDED MODE
4000
9.0
VDD = 3V VDD = 5V 3000
8.5
DIFFERENTIAL MODE DIFFERENTIAL MODE
2000
8.0
1000
7.5 5 CODES 11 CODES
0

04603-042
7.0 2046 2047 2048 2049 2050
04603-010

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CODE
VREF (V)

Figure 11. Effective Number of Bits vs. VREF Figure 14. Histogram of Codes for 10k Samples in Single-Ended Mode

2.5010 –60
DIFFERENTIAL MODE
VDD = 3V/5V
–65
2.5005
–70

2.5000
–75
CMRR (dB)
VREF (V)

2.4995 –80

–85
2.4990
–90

2.4985
–95

2.4980 –100
04603-011
04603-011

0 20 40 60 80 100 120 140 160 180 200 0 200 400 600 800 1000 1200
CURRENT LOAD (A) RIPPLE FREQUENCY (kHz)

Figure 12. VREF vs. Reference Output Current Drive Figure 15. CMRR vs. Common-Mode Ripple Frequency

Rev. C | Page 10 of 28
 AD7266

TERMINOLOGY
Differential Nonlinearity (DNL) Signal-to-(Noise + Distortion) Ratio
Differential nonlinearity is the difference between the measured This ratio is the measured ratio of signal-to-(noise + distortion)
and the ideal 1 LSB change between any two adjacent codes in at the output of the ADC. The signal is the rms amplitude of
the ADC. the fundamental. Noise is the sum of all non-fundamental
Integral Nonlinearity (INL) signals up to half the sampling frequency (fS/2), excluding dc.
Integral nonlinearity is the maximum deviation from a straight The ratio is dependent on the number of quantization levels in
line passing through the endpoints of the ADC transfer the digitization process; the more levels, the smaller the
function. The endpoints of the transfer function are zero scale quantization noise. The theoretical signal-to-(noise +
with a single (1) LSB point below the first code transition, and distortion) ratio for an ideal N-bit converter with a sine wave
full scale with a 1 LSB point above the last code transition. input is given by

Offset Error Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Offset error applies to straight binary output coding. It is the Therefore, for a 12-bit converter, this is 74 dB.
deviation of the first code transition (00 . . . 000) to (00 . . . 001) Total Harmonic Distortion (THD)
from the ideal (AGND + 1 LSB). Total harmonic distortion is the ratio of the rms sum of
Offset Error Match harmonics to the fundamental. For the AD7266, it is defined as
Offset error match is the difference in offset error across all
V22  V32  V4 2  V52  V62
12 channels. THD(dB)  20 log
V1
Gain Error
Gain error applies to straight binary output coding. It is the where:
deviation of the last code transition (111 . . . 110) to (111 . . . V1 is the rms amplitude of the fundamental.
111) from the ideal (VREF − 1 LSB) after the offset error is
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
adjusted out. Gain error does not include reference error.
through the sixth harmonics.
Gain Error Match
Peak Harmonic or Spurious Noise
Gain error match is the difference in gain error across all
Peak harmonic, or spurious noise, is defined as the ratio of the
12 channels.
rms value of the next largest component in the ADC output
Zero Code Error spectrum (up to fS/2, excluding dc) to the rms value of the
Zero code error applies when using twos complement output fundamental. Normally, the value of this specification is
coding with, for example, the 2 × VREF input range as −VREF to determined by the largest harmonic in the spectrum, but for
+VREF biased about the VREF point. It is the deviation of the ADCs where the harmonics are buried in the noise floor, it is a
midscale transition (all 1s to all 0s) from the ideal VIN voltage noise peak.
(VREF).
Channel-to-Channel Isolation
Zero Code Error Match Channel-to-channel isolation is a measure of the level of
Zero code error match refers to the difference in zero code crosstalk between channels. It is measured by applying a full-
error across all 12 channels. scale (2 × VREF when VDD = 5 V, VREF when VDD = 3 V), 10 kHz
Positive Gain Error sine wave signal to all unselected input channels and
This applies when using twos complement output coding with, determining how much that signal is attenuated in the selected
for example, the 2 × VREF input range as −VREF to +VREF biased channel with a 50 kHz signal (0 V to VREF). The result obtained
about the VREF point. It is the deviation of the last code is the worst-case across all 12 channels for the AD7266.
transition (011…110) to (011…111) from the ideal (+VREF − Intermodulation Distortion
1 LSB) after the zero code error is adjusted out. With inputs consisting of sine waves at two frequencies, fa and
Track-and-Hold Acquisition Time fb, any active device with nonlinearities create distortion
The track-and-hold amplifier returns to track mode after the products at sum, and difference frequencies of mfa ± nfb where
end of conversion. Track-and-hold acquisition time is the time m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
required for the output of the track-and-hold amplifier to reach are those for which neither m nor n are equal to zero. For
its final value, within ±1/2 LSB, after the end of conversion. example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa − fb),
(fa + 2fb), and (fa − 2fb).

Rev. C | Page 11 of 28
AD7266
The AD7266 is tested using the CCIF standard where two input Power Supply Rejection Ratio (PSRR)
frequencies near the top end of the input bandwidth are used. Variations in power supply affect the full-scale transition but
In this case, the second-order terms are usually distanced in not the converter’s linearity. PSRR is the maximum change in
frequency from the original sine waves, while the third-order the full-scale transition point due to a change in power supply
terms are usually at a frequency close to the input frequencies. voltage from the nominal value (see Figure 4).
As a result, the second-order and third-order terms are Thermal Hysteresis
specified separately. The calculation of the intermodulation Thermal hysteresis is defined as the absolute maximum change
distortion is as per the THD specification, where it is the ratio of reference output voltage after the device is cycled through
of the rms sum of the individual distortion products to the rms temperature from either
amplitude of the sum of the fundamentals expressed in dBs.
T_HYS+ = +25°C to TMAX to +25°C
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at or
full-scale frequency, f, to the power of a 100 mV p-p sine wave T_HYS− = +25°C to TMIN to +25°C
applied to the common-mode voltage of VIN+ and VIN− of It is expressed in ppm by
frequency fS as
VREF (25C)  VREF (T _ HYS)
CMRR (dB) = 10 log(Pf/PfS) VHYS ( ppm)   10 6
VREF (25C)
where:
where:
Pf is the power at frequency f in the ADC output.
VREF (25°C) is VREF at 25°C.
PfS is the power at frequency fS in the ADC output.
VREF (T_HYS) is the maximum change of VREF at T_HYS+ or
T_HYS−.

Rev. C | Page 12 of 28
 AD7266

THEORY OF OPERATION
CIRCUIT INFORMATION When the ADC starts a conversion (see Figure 17), SW3 opens
The AD7266 is a fast, micropower, dual, 12-bit, single-supply, and SW1 and SW2 move to Position B, causing the comparator
ADC that operates from a 2.7 V to a 5.25 V supply. When to become unbalanced. Both inputs are disconnected once the
operated from a 5 V supply, the AD7266 is capable of conversion begins. The control logic and the charge redistribu-
throughput rates of 2 MSPS when provided with a 32 MHz tion DACs are used to add and subtract fixed amounts of
clock, and a throughput rate of 1.5 MSPS at 3 V. charge from the sampling capacitor arrays to bring the
comparator back into a balanced condition. When the
The AD7266 contains two on-chip, differential track-and-hold comparator is rebalanced, the conversion is complete. The
amplifiers, two successive approximation ADCs, and a serial control logic generates the ADC output code. The output
interface with two separate data output pins. It is housed in a impedances of the sources driving the VIN+ and VIN− pins must
32-lead LFCSP or a 32-lead TQFP, offering the user considerable be matched; otherwise, the two inputs will have different
space-saving advantages over alternative solutions. The serial settling times, resulting in errors.
clock input accesses data from the part but also provides the
clock source for each successive approximation ADC. The CAPACITIVE
DAC
analog input range for the part can be selected to be a 0 V to
CS COMPARATOR
B
VREF input or a 2 × VREF input, configured with either single-
VIN+
ended or differential analog inputs. The AD7266 has an on- A SW1
SW3 CONTROL
chip 2.5 V reference that can be overdriven when an external SW2 CS LOGIC
VIN– A
reference is preferred. If the internal reference is to be used B
elsewhere in a system, then the output needs to buffered first.
VREF

04603-014
CAPACITIVE
The AD7266 also features power-down options to allow power DAC

saving between conversions. The power-down feature is

Figure 17. ADC Conversion Phase
implemented via the standard serial interface, as described in
the Modes of Operation section. ANALOG INPUT STRUCTURE
CONVERTER OPERATION Figure 18 shows the equivalent circuit of the analog input
structure of the AD7266 in differential/pseudo differential
The AD7266 has two successive approximation ADCs, each
mode. In single-ended mode, VIN− is internally tied to AGND.
based around two capacitive DACs. Figure 16 and Figure 17
The four diodes provide ESD protection for the analog inputs.
show simplified schematics of one of these ADCs in acquisition
Care must be taken to ensure that the analog input signals
and conversion phase, respectively. The ADC is comprised of
never exceed the supply rails by more than 300 mV. This causes
control logic, a SAR, and two capacitive DACs. In Figure 16
these diodes to become forward-biased and starts conducting
(the acquisition phase), SW3 is closed, SW1 and SW2 are in
into the substrate. These diodes can conduct up to 10 mA
Position A, the comparator is held in a balanced condition, and
without causing irreversible damage to the part.
the sampling capacitor arrays acquire the differential signal on
the input. The C1 capacitors in Figure 18 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
CAPACITIVE lumped components made up of the on resistance of the
DAC
COMPARATOR
switches. The value of these resistors is typically about 100 Ω.
B CS
VIN+
The C2 capacitors are the ADC’s sampling capacitors with a
A SW1
CONTROL capacitance of 45 pF typically.
SW3
SW2 CS LOGIC
VIN– A For ac applications, removing high frequency components
B from the analog input signal is recommended by the use of an
VREF RC low-pass filter on the relevant analog input pins with
04603-013

CAPACITIVE
DAC optimum values of 47 Ω and 10 pF. In applications where
Figure 16. ADC Acquisition Phase harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source.
Large source impedances significantly affect the ac
performance of the ADC and may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application.

Rev. C | Page 13 of 28
AD7266
VDD
Figure 21 shows a graph of the THD vs. the analog input
frequency for various supplies while sampling at 2 MSPS. In
D
R1 C2 this case, the source impedance is 47 Ω.
VIN+
C1 D –50
FSAMPLE = 1.5MSPS/2MSPS
VDD = 3V/5V
–55 RANGE = 0 TO VREF

VDD
–60 VDD = 3V
SINGLE-ENDED MODE
D
R1 C2 –65
VIN–

THD (dB)
C1 D –70 VDD = 3V
DIFFERENTIAL MODE

04603-015
–75

Figure 18. Equivalent Analog Input Circuit, –80

Conversion Phase—Switches Open, Track Phase—Switches Closed VDD = 5V
–85 DIFFERENTIAL MODE
VDD = 5V
When no amplifier is used to drive the analog input, the source SINGLE-ENDED MODE
impedance should be limited to low values. The maximum –90

04603-018
0 100 200 300 400 500 600 700 800 900 1000
source impedance depends on the amount of THD that can be INPUT FREQUENCY (kHz)

tolerated. The THD increases as the source impedance increases Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages
and performance degrades. Figure 19 shows a graph of the
ANALOG INPUTS
THD vs. the analog input signal frequency for different source
impedances in single-ended mode, while Figure 20 shows the The AD7266 has a total of 12 analog inputs. Each on-board
THD vs. the analog input signal frequency for different source ADC has six analog inputs that can be configured as six single-
impedances in differential mode. ended channels, three pseudo differential channels, or three
–50
fully differential channels. These may be selected as described
FSAMPLE = 1.5MSPS
VDD = 3V RSOURCE = 300Ω
in the Analog Input Selection section.
–55 RANGE = 0V TO V
REF
Single-Ended Mode
–60
The AD7266 can have a total of 12 single-ended analog input
–65 channels. In applications where the signal source has high
RSOURCE = 0Ω
impedance, it is recommended to buffer the analog input
THD (dB)

–70
RSOURCE = 100Ω
before applying it to the ADC. The analog input range can be
–75
programmed to be either 0 to VREF or 0 to 2 × VREF.
RSOURCE = 47Ω

–80
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
–85 RSOURCE = 10Ω
signal to make it correctly formatted for the ADC. Figure 22
–90 shows a typical connection diagram when operating the ADC
04603-016

0 100 200 300 400 500 600

in single-ended mode.
INPUT FREQUENCY (kHz)
+2.5V
Figure 19. THD vs. Analog Input Frequency for Various
Source Impedances, Single-Ended Mode R
+1.25V 0V
R
–60 0V VIN
FSAMPLE = 1.5MSPS
VDD = 3V RSOURCE = 300Ω –1.25V 3R VA1 AD72661
RANGE = 0V TO VREF
–65 R
VB6 DCAP A/DCAP B
RSOURCE = 0Ω
–70 RSOURCE = 100Ω

0.47µF
THD (dB)

–75
04603-019

–80 RSOURCE = 47Ω 1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 22. Single-Ended Mode Connection Diagram

–85

RSOURCE = 10Ω
–90
04603-017

0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (kHz)

Figure 20. THD vs. Analog Input Frequency for

Various Source Impedances, Differential Mode
Rev. C | Page 14 of 28
 AD7266
3.5
Differential Mode TA = 25°C

The AD7266 can have a total of six differential analog 3.0

input pairs.

COMMON-MODE RANGE (V)

2.5
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s 2.0
common-mode rejection and improvements in distortion
performance. Figure 23 defines the fully differential analog 1.5

input of the AD7266.

1.0

VREF p-p VIN+

0.5

COMMON AD72661
MODE 0
VREF p-p VIN–

04603-021
VOLTAGE 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VREF (V)

04603-020 Figure 24. Input Common-Mode Range vs. VREF (0 to VREF Range, VDD = 5 V)
1ADDITIONAL PINS OMITTED FOR CLARITY.
5.0
TA = 25°C
Figure 23. Differential Input Definition 4.5

The amplitude of the differential signal is the difference 4.0

between the signals applied to the VIN+ and VIN− pins in each

COMMON-MODE RANGE (V)

3.5
differential pair (VIN+ − VIN−). VIN+ and VIN− should be
3.0
simultaneously driven by two signals each of amplitude VREF
2.5
(or 2 × VREF, depending on the range chosen) that are 180° out
of phase. The amplitude of the differential signal is, therefore 2.0

(assuming the 0 to VREF range is selected) −VREF to +VREF peak- 1.5

to-peak (2 × VREF), regardless of the common mode (CM). 1.0

The common mode is the average of the two signals 0.5

(VIN+ + VIN−)/2 0

04603-022
0 0.5 1.0 1.5 2.0 2.5
and is, therefore, the voltage on which the two inputs are VREF (V)

centered. Figure 25. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V)
This results in the span of each input being CM ± VREF/2. This Driving Differential Inputs
voltage has to be set up externally and its range varies with the
Differential operation requires that VIN+ and VIN− be
reference value, VREF. As the value of VREF increases, the
simultaneously driven with two equal signals that are 180° out
common-mode range decreases. When driving the inputs with
of phase. The common mode must be set up externally. The
an amplifier, the actual common-mode range is determined by
common-mode range is determined by VREF, the power supply,
the amplifier’s output voltage swing.
and the particular amplifier used to drive the analog inputs.
Figure 24 and Figure 25 show how the common-mode range Differential modes of operation with either an ac or dc input
typically varies with VREF for a 5 V power supply using the 0 to provide the best THD performance over a wide frequency
VREF range or 2 × VREF range, respectively. The common mode range. Because not all applications have a signal preconditioned
must be in this range to guarantee the functionality of the AD7266. for differential operation, there is often a need to perform
When a conversion takes place, the common mode is rejected, single-ended-to-differential conversion.
resulting in a virtually noise free signal of amplitude −VREF to
+VREF corresponding to the digital codes of 0 to 4096. If the
2 × VREF range is used, then the input signal amplitude extends
from −2 VREF to +2 VREF after conversion.

Rev. C | Page 15 of 28
AD7266
Using an Op Amp Pair Pseudo Differential Mode
An op amp pair can be used to directly couple a differential The AD7266 can have a total of six pseudo differential pairs. In
signal to one of the analog input pairs of the AD7266. The this mode, VIN+ is connected to the signal source that must have
circuit configurations illustrated in Figure 26 and Figure 27 an amplitude of VREF (or 2 × VREF, depending on the range
show how a dual op amp can be used to convert a single-ended chosen) to make use of the full dynamic range of the part. A dc
signal into a differential signal for both a bipolar and unipolar input is applied to the VIN− pin. The voltage applied to this
input signal, respectively. input provides an offset from ground or a pseudo ground for
The voltage applied to Point A sets up the common-mode the VIN+ input. The benefit of pseudo differential inputs is that
voltage. In both diagrams, it is connected in some way to the they separate the analog input signal ground from the ADC’s
reference, but any value in the common-mode range can be ground allowing dc common-mode voltages to be cancelled.
input here to set up the common mode. The AD8022 is a The typical voltage range for the VIN− pin, while in pseudo
suitable dual op amp that can be used in this configuration to differential mode, is shown in Figure 28 and Figure 29. Figure
provide differential drive to the AD7266. 30 shows a connection diagram for pseudo differential mode.
1.0
TA = 25°C
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives. 0.8

The driver circuits in Figure 26 and Figure 27 are optimized for

0.6
dc coupling applications requiring best distortion performance.
The circuit configuration shown in Figure 26 converts a 0.4

VIN– (V)
unipolar, single-ended signal into a differential signal.
0.2
The differential op amp driver circuit shown in Figure 27 is
0
configured to convert and level shift a single-ended, ground-
referenced (bipolar) signal to a differential signal centered at –0.2
the VREF level of the ADC.
3.75V –0.4

04603-043
2 × VREF p-p 220Ω
0 0.5 1.0 1.5 2.0 2.5 3.0
2.5V
440Ω V+ VREF (V)
VREF 1.25V
27Ω
GND
VIN+ AD72661 Figure 28. VIN−- Input Voltage Range vs. VREF in
V– Pseudo Differential Mode with VDD = 3 V
220Ω
3.75V 2.5
220Ω TA = 25°C
2.5V
V+
1.25V 2.0
27Ω
VIN– DCAP A/DCAP B
A
V–
10kΩ 1.5
0.47µF
VIN– (V)

1.0
04603-023

1ADDITIONAL PINS OMITTED FOR CLARITY. 0.5

Figure 26. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal

into a Differential Signal 0

2 × VREF p-p 220Ω 3.75V

2.5V –0.5
04603-044

440Ω V+
GND 1.25V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
27Ω
1
VIN+ AD7266 VREF (V)

V– Figure 29. VIN− Input Voltage Range vs. VREF in

220kΩ 220Ω Pseudo Differential Mode with VDD = 5 V
220Ω 3.75V
2.5V VREF
V+
1.25V p–p AD72661
27Ω VIN+
VIN– DCAP A/DCAP B
A
V–
10kΩ
0.47µF VIN–
20kΩ DC INPUT VREF
VOLTAGE
04603-024

0.47µF
1ADDITIONAL PINS OMITTED FOR CLARITY.
04603-025

Figure 27. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal

into a Differential Unipolar Signal 1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 30. Pseudo Differential Mode Connection Diagram

Rev. C | Page 16 of 28
 AD7266
ANALOG INPUT SELECTION The channels used for simultaneous conversions are selected
The analog inputs of the AD7266 can be configured as single- via the multiplexer address input pins, A0 to A2. The logic
states of these pins also need to be established prior to the
ended or true differential via the SGL/DIFF logic pin, as shown
acquisition time; however, they may change during the
in Figure 31. If this pin is tied to a logic low, the analog input
conversion time provided the mode is not changed. If the mode
channels to each on-chip ADC are set up as three true
is changed from fully differential to pseudo differential, for
differential pairs. If this pin is at logic high, the analog input
example, then the acquisition time would start again from this
channels to each on-chip ADC are set up as six single-ended
point. The selected input channels are decoded as shown in
analog inputs. The required logic level on this pin needs to be
Table 6.
established prior to the acquisition time and remain unchanged
during the conversion time until the track-and-hold has returned The analog input range of the AD7266 can be selected as 0 V to
to track. The track-and-hold returns to track on the 13th rising VREF or 0 V to 2 × VREF via the RANGE pin. This selection is
edge of SCLK after the CS falling edge (see Figure 41). If the made in a similar fashion to that of the SGL/DIFF pin by
level on this pin is changed, it will be recognized by the setting the logic state of the RANGE pin a time tacq prior to the
AD7266; therefore, it is necessary to keep the same logic level falling edge of CS. Subsequent to this, the logic level on this pin
during acquisition and conversion to avoid corrupting the can be altered after the third falling edge of SCLK. If this pin is
conversion in progress. tied to a logic low, the analog input range selected is 0 V to
VREF. If this pin is tied to a logic high, the analog input range
For example, in Figure 31 the SGL/DIFF pin is set at logic high
selected is 0 V to 2 × VREF.
for the duration of both the acquisition and conversion times
so the analog inputs are configured as single ended for that OUTPUT CODING
conversion (Sampling Point A). The logic level of the The AD7266 output coding is set to either twos complement or
SGL/DIFF changed to low after the track-and-hold returned to straight binary, depending on which analog input configuration
track and prior to the required acquisition time for the next is selected for a conversion. Table 5 shows which output coding
sampling instant at Point B; therefore, the analog inputs are scheme is used for each possible analog input configuration.
configured as differential for that conversion.
A B
Table 5. AD7266 Output Coding
tACQ Range Output Coding
CS SGL/DIFF
1 14 1 14 DIFF 0 V to VREF Twos complement
SCLK
DIFF 0 V to 2 × VREF Twos complement
04603-026

SGL/DIFF SGL 0 V to VREF Straight binary

SGL 0 V to 2 × VREF Twos complement
Figure 31. Selecting Differential or Single-Ended Configuration
PSEUDO DIFF 0 V to VREF Straight binary
PSEUDO DIFF 0 V to 2 × VREF Twos complement

Table 6. Analog Input Type and Channel Selection

ADC A ADC B
SGL/DIFF A2 A1 A0 VIN+ VIN− VIN+ VIN− Comment
1 0 0 0 VA1 AGND VB1 AGND Single ended
1 0 0 1 VA2 AGND VB2 AGND Single ended
1 0 1 0 VA3 AGND VB3 AGND Single ended
1 0 1 1 VA4 AGND VB4 AGND Single ended
1 1 0 0 VA5 AGND VB5 AGND Single ended
1 1 0 1 VA6 AGND VB6 AGND Single ended
0 0 0 0 VA1 VA2 VB1 VB2 Fully differential
0 0 0 1 VA1 VA2 VB1 VB2 Pseudo differential
0 0 1 0 VA3 VA4 VB3 VB4 Fully differential
0 0 1 1 VA3 VA4 VB3 VB4 Pseudo differential
0 1 0 0 VA5 VA6 VB5 VB6 Fully differential
0 1 0 1 VA5 VA6 VB5 VB6 Pseudo differential

Rev. C | Page 17 of 28
AD7266
TRANSFER FUNCTIONS DIGITAL INPUTS
The designed code transitions occur at successive integer LSB The digital inputs applied to the AD7266 are not limited by the
values (1 LSB, 2 LSB, and so on). In single-ended mode, the maximum ratings that limit the analog inputs. Instead, the
LSB size is VREF/4096 when the 0 V to VREF range is used, and digital inputs can be applied up to 7 V and are not restricted by
the LSB size is 2 × VREF/4096 when the 0 V to 2 × VREF range is the VDD + 0.3 V limit as are the analog inputs. See the Absolute
used. In differential mode, the LSB size is 2 × VREF/4096 when Maximum Ratings section for more information. Another
the 0 V to VREF range is used, and the LSB size is 4 × VREF/4096 advantage of the SCLK, RANGE, A0 to A2, and CS pins not
when the 0 V to 2 × VREF range is used. The ideal transfer being restricted by the VDD + 0.3 V limit is that power supply
characteristic for the AD7266 when straight binary coding is sequencing issues are avoided. If one of these digital inputs is
output is shown in Figure 32, and the ideal transfer applied before VDD, there is no risk of latch-up, as there would
characteristic for the AD7266 when twos complement coding is be on the analog inputs if a signal greater than 0.3 V were
output is shown in Figure 33 (this is shown with the 2 × VREF applied prior to VDD.
range).
VDRIVE
The AD7266 also has a VDRIVE feature to control the voltage at
111...111 which the serial interface operates. VDRIVE allows the ADC to
111...110 easily interface to both 3 V and 5 V processors. For example, if
the AD7266 was operated with a VDD of 5 V, the VDRIVE pin
111...000 could be powered from a 3 V supply, allowing a large dynamic
ADC CODE

1LSB = VREF/4096 range with low voltage digital processors. Therefore, the
011...111 AD7266 could be used with the 2 × VREF input range, with a VDD
of 5 V while still being able to interface to 3 V digital parts.
000...010
000...001
000...000
0V 1LSB VREF – 1LSB
ANALOG INPUT
04603-027

NOTE
1. VREF IS EITHER VREF OR 2 × VREF.

Figure 32. Straight Binary Transfer Characteristic

1LSB = 2  VREF/4096

011...111
011...110

000...001
ADC CODE

000...000
111...111

100...010
100...001
100...000
04603-028

–VREF + 1LSB VREF – 1LSB +VREF – 1 LSB

ANALOG INPUT

Figure 33. Twos Complement Transfer Characteristic with

VREF ± VREF Input Range

Rev. C | Page 18 of 28
 AD7266

MODES OF OPERATION
The mode of operation of the AD7266 is selected by controlling Once a data transfer is complete and DOUTA and DOUTB have
the (logic) state of the CS signal during a conversion. There are returned to three-state, another conversion can be initiated
three possible modes of operation: normal mode, partial after the quiet time, tQUIET, has elapsed by bringing CS low again
power-down mode, and full power-down mode. After a (assuming the required acquisition time is allowed).
conversion is initiated, the point at which CS is pulled high PARTIAL POWER-DOWN MODE
determines which power-down mode, if any, the device enters.
This mode is intended for use in applications where slower
Similarly, if already in a power-down mode, CS can control
throughput rates are required. Either the ADC is powered
whether the device returns to normal operation or remains in
down between each conversion, or a series of conversions may
power-down. These modes of operation are designed to
be performed at a high throughput rate, and the ADC is then
provide flexible power management options. These options can
powered down for a relatively long duration between these
be chosen to optimize the power dissipation/throughput rate
bursts of several conversions. When the AD7266 is in partial
ratio for differing application requirements.
power-down, all analog circuitry is powered down except for
NORMAL MODE the on-chip reference and reference buffer.
This mode is intended for applications needing fastest throughput To enter partial power-down mode, the conversion process
rates because the user does not have to worry about any power- must be interrupted by bringing CS high anywhere after the
up times with the AD7266 remaining fully powered at all times. second falling edge of SCLK and before the 10th falling edge of
Figure 34 shows the general diagram of the operation of the SCLK, as shown in Figure 35. Once CS is brought high in this
AD7266 in this mode. window of SCLKs, the part enters partial power-down, the
CS conversion that was initiated by the falling edge of CS is
1 10 14
terminated, and DOUTA and DOUTB go back into three-state. If
SCLK CS is brought high before the second SCLK falling edge, the
part remains in normal mode and does not power down. This
04603-029

DOUTA
LEADING ZEROS + CONVERSION RESULT
avoids accidental power-down due to glitches on the CS line.
DOUTB

Figure 34. Normal Mode Operation CS

The conversion is initiated on the falling edge of CS, as 1 2 10 14

SCLK
described in the Serial Interface section. To ensure that the part
remains fully powered up at all times, CS must remain low until

04603-030
DOUTA THREE-STATE
at least 10 SCLK falling edges have elapsed after the falling edge DOUTB

of CS. If CS is brought high any time after the 10th SCLK falling Figure 35. Entering Partial Power-Down Mode
edge but before the 14th SCLK falling edge, the part remains
powered up, but the conversion is terminated and DOUTA and To exit this mode of operation and power up the AD7266
DOUTB go back into three-state. Fourteen serial clock cycles are again, a dummy conversion is performed. On the falling edge of
required to complete the conversion and access the conversion CS, the device begins to power up and continues to power up as
result. The DOUT line does not return to three-state after 14 long as CS is held low until after the falling edge of the 10th
SCLK cycles have elapsed, but instead does so when CS is SCLK. The device is fully powered up after approximately 1 μs
brought high again. If CS is left low for another 2 SCLK cycles has elapsed, and valid data results from the next conversion, as
(for example, if only a 16 SCLK burst is available), two trailing shown in Figure 36. If CS is brought high before the second
zeros are clocked out after the data. If CS is left low for a further falling edge of SCLK, the AD7266 again goes into partial
14 (or16) SCLK cycles, the result from the other ADC on board power-down. This avoids accidental power-up due to glitches
is also accessed on the same DOUT line, as shown in Figure 42 on the CS line. Although the device may begin to power up on
(see the Serial Interface section). the falling edge of CS, it powers down again on the rising edge
of CS. If the AD7266 is already in partial power-down mode
Once 32 SCLK cycles have elapsed, the DOUT line returns to
three-state on the 32nd SCLK falling edge. If CS is brought high and CS is brought high between the second and 10th falling
prior to this, the DOUT line returns to three-state at that point. edges of SCLK, the device enters full power-down mode.
Therefore, CS may idle low after 32 SCLK cycles until it is
brought high again sometime prior to the next conversion
(effectively idling CS low), if so desired, because the bus still
returns to three-state upon completion of the dual result read.

Rev. C | Page 19 of 28
AD7266
FULL POWER-DOWN MODE Note that it is not necessary to complete the 14 SCLKs once CS
This mode is intended for use in applications where throughput is brought high to enter a power-down mode.
rates slower than those in the partial power-down mode are To exit full power-down and power up the AD7266, a dummy
required, as power-up from a full power-down takes substan- conversion is performed, as when powering up from partial
tially longer than that from partial power-down. This mode is power-down. On the falling edge of CS, the device begins to
more suited to applications where a series of conversions power up and continues to power up, as long as CS is held low
performed at a relatively high throughput rate are followed by a until after the falling edge of the 10th SCLK. The required
long period of inactivity and thus power-down. When the power-up time must elapse before a conversion can be initiated,
AD7266 is in full power-down, all analog circuitry is powered as shown in Figure 38. See the Power-Up Times section for the
down. Full power-down is entered in a similar way as partial power-up times associated with the AD7266.
power-down, except the timing sequence shown in Figure 35
must be executed twice. The conversion process must be
interrupted in a similar fashion by bringing CS high anywhere
after the second falling edge of SCLK and before the 10th falling
edge of SCLK. The device enters partial power-down at this
point. To reach full power-down, the next conversion cycle
must be interrupted in the same way, as shown in Figure 37.
Once CS is brought high in this window of SCLKs, the part
completely powers down.

THE PART IS FULLY

THE PART BEGINS POWERED UP; SEE
TO POWER UP. POWER-UP TIMES
tPOWER-UP1 SECTION.

CS

1 10 14 1 14
SCLK

04603-031
DOUTA
INVALID DATA VALID DATA
DOUTB

Figure 36. Exiting Partial Power-Down Mode

THE PART ENTERS THE PART BEGINS THE PART ENTERS

PARTIAL POWER DOWN. TO POWER UP. FULL POWER DOWN.

CS

1 2 10 14 1 2 10 14
SCLK
04603-032

DOUTA THREE-STATE THREE-STATE

DOUTB INVALID DATA INVALID DATA

Figure 37. Entering Full Power-Down Mode

Rev. C | Page 20 of 28
 AD7266
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
THE PART BEGINS
TO POWER UP. tPOWER-UP2
CS

1 10 14 1 14
SCLK

04603-033
DOUTA
INVALID DATA VALID DATA
DOUTB

Figure 38. Exiting Full Power-Down Mode

POWER-UP TIMES options can be used to make significant power savings.

As described in detail, the AD7266 has two power-down However, the AD7266 quiescent current is low enough that
modes, partial power-down and full power-down. This section even without using the power-down options, there is a
deals with the power-up time required when coming out of noticeable variation in power consumption with sampling rate.
either of these modes. It should be noted that the power-up This is true whether a fixed SCLK value is used or if it is scaled
times, as explained in this section, apply with the recommended with the sampling rate. Figure 39 and Figure 40 show plots of
capacitors in place on the DCAPA and DCAPB pins. power vs. the throughput rate when operating in normal mode
for a fixed maximum SCLK frequency and an SCLK frequency
To power up from full power-down, approximately 1.5 ms that scales with the sampling rate with VDD = 3 V and VDD = 5
should be allowed from the falling edge of CS, shown as V, respectively. In all cases, the internal reference was used.
tPOWER-UP2 in Figure 38. Powering up from partial power-down 10.0
TA = 25°C
requires much less time. The power-up time from partial
9.5
power-down is typically 1 μs; however, if using the internal
9.0
reference, then the AD7266 must be in partial power-down for
at least 67 μs in order for this power-up time to apply. 8.5
VARIABLE SCLK
8.0
POWER (mW)

When power supplies are first applied to the AD7266, the ADC
may power up in either of the power-down modes or normal 7.5

mode. Because of this, it is best to allow a dummy cycle to 7.0

24MHz SCLK
elapse to ensure the part is fully powered up before attempting 6.5
a valid conversion. Likewise, if it is intended to keep the part in 6.0
the partial power-down mode immediately after the supplies
5.5
are applied, then two dummy cycles must be initiated. The first
5.0
dummy cycle must hold CS low until after the 10th SCLK falling

04603-045
0 200 400 600 800 1000 1200 1400
edge (see Figure 34); in the second cycle, CS must be brought THROUGHPUT (kSPS)

high before the 10th SCLK edge but after the second SCLK Figure 39. Power vs. Throughput in Normal Mode with VDD = 3 V
falling edge (see Figure 35). Alternatively, if it is intended to 30
TA = 25°C
place the part in full power-down mode when the supplies are 28
applied, then three dummy cycles must be initiated. The first 26
dummy cycle must hold CS low until after the 10th SCLK falling
24
edge (see Figure 34); the second and third dummy cycles place VARIABLE SCLK
22
POWER (mW)

the part in full power-down (see Figure 37).

20
Once supplies are applied to the AD7266, enough time must be 32MHz SCLK
18
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final 16

values. 14

12
POWER vs. THROUGHPUT RATE
10
04603-046

The power consumption of the AD7266 varies with the 0 200 400 600 800 1000 1200 1400 1600 1800 2000
throughput rate. When using very slow throughput rates and as THROUGHPUT (kSPS)

fast an SCLK frequency as possible, the various power-down Figure 40. Power vs. Throughput in Normal Mode with VDD = 5 V

Rev. C | Page 21 of 28
AD7266

SERIAL INTERFACE
Figure 41 shows the detailed timing diagram for serial inter- A minimum of 14 serial clock cycles are required to perform
facing to the AD7266. The serial clock provides the conversion the conversion process and to access data from one conversion
clock and controls the transfer of information from the on either data line of the AD7266. CS going low provides the
AD7266 during conversion. leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
The CS signal initiates the data transfer and conversion process. edges, beginning with a second leading zero. Thus, the first
The falling edge of CS puts the track-and-hold into hold mode, falling clock edge on the serial clock has the leading zero
at which point the analog input is sampled and the bus is taken provided and also clocks out the second leading zero. The 12-
out of three-state. The conversion is also initiated at this point bit result then follows with the final bit in the data transfer valid
and requires a minimum of 14 SCLKs to complete. Once 13 on the 14th falling edge, having being clocked out on the
SCLK falling edges have elapsed, the track-and-hold goes back previous (13th) falling edge. In applications with a slower SCLK,
into track on the next SCLK rising edge, as shown in Figure 41 it may be possible to read in data on each SCLK rising edge
at Point B. If a 16 SCLK transfer is used, then two trailing zeros depending on the SCLK frequency. The first rising edge of
appear after the final LSB. On the rising edge of CS, the SCLK after the CS falling edge would have the second leading
conversion is terminated and DOUTA and DOUTB go back into zero provided, and the 13th rising SCLK edge would have DB0
three-state. If CS is not brought high but is instead held low for a provided.
further 14 (or 16) SCLK cycles on DOUTA, the data from
Note that with fast SCLK values, and thus short SCLK periods,
Conversion B is output on DOUTA (followed by two trailing
in order to allow adequately for t2, an SCLK rising edge may
zeros).
occur before the first SCLK falling edge. This rising edge of
Likewise, if CS is held low for a further 14 (or 16) SCLK cycles SCLK may be ignored for the purposes of the timing
on DOUTB, the data from Conversion A is output on DOUTB. This descriptions in this section. If a falling edge of SCLK is coincident
is illustrated in Figure 42 where the case for DOUTA is shown. In with the falling edge of CS, then this falling edge of SCLK is not
this case, the DOUT line in use goes back into three-state on the acknowledged by the AD7266, and the next falling edge of
32nd SCLK falling edge or the rising edge of CS, whichever SCLK will be the first registered after the falling edge of CS.
occurs first.

CS
t9
t2 t6 B
SCLK 1 2 3 4 5 13

t5 t8 tQUIET
t7
t3 t4
DOUTA
0 0 DB11 DB10 DB9 DB8 DB2 DB1 DB0
DOUTB THREE-
04603-034
THREE-STATE
STATE
2 LEADING ZEROS

Figure 41. Serial Interface Timing Diagram

CS

t2 t6
SCLK 1 2 3 4 5 14 15 16 17 32
t5 t10
t3 t4 t7
DOUTA 0 ZERO DB11A DB10A DB9A ZERO ZERO ZERO ZERO DB11B ZERO ZERO
THREE- THREE-
04603-035

STATE 2 LEADING 2 TRAILING ZEROS 2 TRAILING ZEROS STATE

ZEROS 2 LEADING ZEROS

Figure 42. Reading Data from Both ADCs on One DOUT Line with 32 SCLKs

Rev. C | Page 22 of 28
 AD7266

MICROPROCESSOR INTERFACING
The serial interface on the AD7266 allows the part to be directly The connection diagram is shown in Figure 43. The ADSP-
connected to a range of many different microprocessors. This 218x has the TFS0 and RFS0 of the SPORT0 and the RFS1 of
section explains how to interface the AD7266 with some of the SPORT1 tied together. TFS0 is set as an output, and both RFS0
more common microcontroller and DSP serial interface and RFS1 are set as inputs. The DSP operates in alternate
protocols. framing mode, and the SPORT control register is set up as
described. The frame synchronization signal generated on the
AD7266 TO ADSP-218x
TFS is tied to
The ADSP-218x family of DSPs interface directly to the CS, and as with all signal processing applications, equidistant
AD7266 without any glue logic required. The VDRIVE pin of the sampling is necessary. However, in this example, the timer
AD7266 takes the same supply voltage as that of the ADSP-218x. interrupt is used to control the sampling rate of the ADC and,
This allows the ADC to operate at a higher supply voltage than its under certain conditions, equidistant sampling may not be
serial interface and therefore, the ADSP-218x, if necessary. This achieved.
example shows both DOUTA and DOUTB of the AD7266
connected to both serial ports of the ADSP-218x. The SPORT0 AD72661 ADSP-218x1
SCLK SCLK0
and SPORT1 control registers should be set up as shown in
Table 7 and Table 8. SCLK1

CS TFS0
Table 7. SPORT0 Control Register Setup RFS0
Setting Description RFS1
TFSW = RFSW = 1 Alternate framing DOUTA DR0
INVRFS = INVTFS = 1 Active low frame signal DOUTB DR1
DTYPE = 00 Right justify data VDRIVE
SLEN = 1111 16-bit data-word (or may be set to
1101 for 14-bit data-word)
ISCLK = 1 Internal serial clock
VDD

04603-036
TFSR = RFSR = 1 Frame every word
1ADDITIONAL PINS OMITTED FOR CLARITY.
IRFS = 0
Figure 43. Interfacing the AD7266 to the ADSP-218x
ITFS = 1
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
Table 8. SPORT1 Control Register Setup
received, a value is transmitted with TFS/DT (ADC control
Setting Description
word). The TFS is used to control the RFS, and hence, the
TFSW = RFSW = 1 Alternate framing
reading of data. The frequency of the serial clock is set in the
INVRFS = INVTFS = 1 Active low frame signal
SCLKDIV register. When the instruction to transmit with TFS
DTYPE = 00 Right justify data
is given (AX0 = TX0), the state of the SCLK is checked. The
SLEN = 1111 16-bit data-word (or may be set to
1101 for 14-bit data-word) DSP waits until the SCLK has gone high, low, and high again
ISCLK = 0 External serial clock before transmission starts. If the timer and SCLK values are
TFSR = RFSR = 1 Frame every word
chosen such that the instruction to transmit occurs on or near
IRFS = 0
the rising edge of SCLK, then the data may be transmitted or it
ITFS = 1
may wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
To implement the power-down modes, SLEN should be set to 16 MHz. If the SCLKDIV register is loaded with the value 3,
1001 to issue an 8-bit SCLK burst. then an SCLK of 2 MHz is obtained, and eight master clock
periods will elapse for every one SCLK period. If the timer
registers are loaded with the value 803, then 100.5 SCLKs will
occur between interrupts and, subsequently, between transmit
instructions. This situation yields sampling that is not
equidistant as the transmit instruction is occurring on an SCLK
edge. If the number of SCLKs between interrupts is a whole
integer figure of N, then equidistant sampling will be
implemented by the DSP.

Rev. C | Page 23 of 28
AD7266
AD7266 TO ADSP-BF53x AD7266 TO TMS320C541
The ADSP-BF53x family of DSPs interface directly to the The serial interface on the TMS320C541 uses a continuous
AD7266 without any glue logic required. The availability of serial clock and frame synchronization signals to synchronize
secondary receive registers on the serial ports of the Blackfin® the data transfer operations with peripheral devices like the
DSPs means only one serial port is necessary to read from both AD7266. The CS input allows easy interfacing between the
DOUT pins simultaneously. Figure 44 shows both DOUTA and TMS320C541 and the AD7266 without any glue logic required.
DOUTB of the AD7266 connected to Serial Port 0 of the The serial ports of the TMS320C541 are set up to operate in
ADSP-BF53x. The SPORT0 Receive Configuration 1 register burst mode with internal CLKX0 (TX serial clock on Serial
and SPORT0 Receive Configuration 2 register should be set up Port 0) and FSX0 (TX frame sync from Serial Port 0). The serial
as outlined in Table 9 and Table 10. port control registers (SPC) must have the following setup.
AD72661 SERIAL
ADSP-BF53x1
Table 11. Serial Port Control Register Set Up
DEVICE A SPORT0
(PRIMARY) SPC FO FSM MCM TXM
DOUTA DR0PRI
SPC0 0 1 1 1
SCLK RCLK0
SPC1 0 1 0 0
CS RFS0

DOUTB DR0SEC
SERIAL The format bit, FO, may be set to 1 to set the word length to
VDRIVE DEVICE B
(SECONDARY)
8 bits to implement the power-down modes on the AD7266.
The connection diagram is shown in Figure 45. It is imperative
VDD
that for signal processing applications, the frame synchroniza-
04603-037

1ADDITIONAL
tion signal from the TMS320C541 provides equidistant
PINS OMITTED FOR CLARITY.
sampling. The VDRIVE pin of the AD7266 takes the same supply
Figure 44. Interfacing the AD7266 to the ADSP-BF53x voltage as that of the TMS320C541. This allows the ADC to
Table 9. The SPORT0 Receive Configuration 1 Register operate at a higher voltage than its serial interface and
(SPORT0_RCR1) therefore, the TMS320C541, if necessary.
Setting Description AD72661 TMS320C5411
RCKFE = 1 Sample data with falling edge of RSCLK SCLK CLKX0

LRFS = 1 Active low frame signal CLKR0

RFSR = 1 Frame every word CLKX1

IRFS = 1 Internal RFS used CLKR1
RLSBIT = 0 Receive MSB first DOUTA DR0
RDTYPE = 00 Zero fill DOUTB DR1
IRCLK = 1 Internal receive clock CS FSX0
RSPEN = 1 Receive enabled FSR0
SLEN = 1111 16-bit data-word (or may be set to 1101
VDRIVE FSR1
for 14-bit data-word)
TFSR = RFSR = 1
VDD
04603-038

1ADDITIONAL PINS OMITTED FOR CLARITY.

Table 10. The SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2) Figure 45. Interfacing the AD7266 to the TMS320C541
Setting Description
RXSE = 1 Secondary side enabled
SLEN = 1111 16-bit data-word ( or may be set to 1101
for 14-bit data-word)

To implement the power-down modes, SLEN should be set to

1001 to issue an 8-bit SCLK burst. A Blackfin driver for the
AD7266 is available to download at www.analog.com.

Rev. C | Page 24 of 28
 AD7266
AD7266 TO DSP563xx In the example shown in Figure 46, the serial clock is taken
The connection diagram in Figure 46 shows how the AD7266 from the ESSI0 so the SCK0 pin must be set as an output,
can be connected to the ESSI (synchronous serial interface) of SCKD = 1, while the SCK1 pin is set as an input, SCKD = 0.
the DSP563xx family of DSPs from Motorola. There are two The frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1,
on-board ESSIs, and each is operated in synchronous mode while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an
(Bit SYN = 1 in CRB register) with internally generated word input. The VDRIVE pin of the AD7266 takes the same supply
length frame sync for both TX and RX (Bit FSL1 = 0 and voltage as that of the DSP563xx. This allows the ADC to
Bit FSL0 = 0 in CRB). operate at a higher voltage than its serial interface and
therefore, the DSP563xx, if necessary.
Normal operation of the ESSI is selected by making MOD = 0
in the CRB. Set the word length to 16 by setting Bit WL1 = 1 AD72661 DSP563xx1
SCLK SCK0
and Bit WL0 = 0 in CRA.
SCK1
To implement the power-down modes on the AD7266, the
DOUTA SRD0
word length can be changed to 8 bits by setting Bit WL1 = 0
DOUTB SRD1
and Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set
CS SC02
to 1 so the frame sync is negative. It is imperative for signal
VDRIVE SC12
processing applications that the frame synchronization signal
from the DSP563xx provides equidistant sampling.
VDD

04603-039
1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 46. Interfacing the AD7266 to the DSP563xx

Rev. C | Page 25 of 28
AD7266

APPLICATION HINTS
GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP
The analog and digital supplies to the AD7266 are independent The lands on the chip scale package (CP-32-3) are rectangular.
and separately pinned out to minimize coupling between the The PCB pad for these should be 0.1 mm longer than the
analog and digital sections of the device. The printed circuit package land length, and 0.05 mm wider than the package land
board (PCB) that houses the AD7266 should be designed so width, thereby having a portion of the pad exposed. To ensure
that the analog and digital sections are separated and confined that the solder joint size is maximized, the land should be
to certain areas of the board. This design facilitates the use of centered on the pad.
ground planes that can be easily separated. The bottom of the chip scale package has a thermal pad. The
To provide optimum shielding for ground planes, a minimum thermal pad on the PCB should be at least as large as the
etch technique is generally best. All three AGND pins of the exposed pad. On the PCB, there should be a clearance of at least
AD7266 should be sunk in the AGND plane. Digital and analog 0.25 mm between the thermal pad and the inner edges of the
ground planes should be joined in only one place. If the AD7266 pad pattern to ensure that shorting is avoided.
is in a system where multiple devices require an AGND to To improve thermal performance of the package, use thermal
DGND connection, the connection should still be made at one vias on the PCB incorporating them in the thermal pad at
point only, a star ground point that should be established as 1.2 mm pitch grid. The via diameter should be between 0.3 mm
close as possible to the ground pins on the AD7266. and 0.33 mm, and the via barrel should be plated with 1 oz.
Avoid running digital lines under the device as this couples copper to plug the via. The user should connect the PCB
noise onto the die. However, the analog ground plane should be thermal pad to AGND.
allowed to run under the AD7266 to avoid noise coupling. The EVALUATING THE AD7266 PERFORMANCE
power supply lines to the AD7266 should use as large a trace as
The recommended layout for the AD7266 is outlined in the
possible to provide low impedance paths and reduce the effects
evaluation board documentation. The evaluation board
of glitches on the power supply line.
package includes a fully assembled and tested evaluation board,
To avoid radiating noise to other sections of the board, fast documentation, and software for controlling the board from
switching signals, such as clocks, should be shielded with digital the PC via the evaluation board controller. The evaluation
ground, and clock signals should never run near the analog board controller can be used in conjunction with the AD7266
inputs. Avoid crossover of digital and analog signals. To reduce evaluation board, as well as many other Analog Devices, Inc.
the effects of feedthrough within the board, traces on opposite evaluation boards ending in the CB designator, to
sides of the board should run at right angles to each other. A demonstrate/evaluate the ac and dc performance of the
microstrip technique is the best method but is not always AD7266.
possible with a double-sided board. In this technique, the
The software allows the user to perform ac (fast Fourier
component side of the board is dedicated to ground planes,
transform) and dc (histogram of codes) tests on the AD7266.
while signals are placed on the solder side.
The software and documentation are on a CD shipped with the
Good decoupling is also important. All analog supplies should evaluation board.
be decoupled with 10 μF tantalum capacitors in parallel with
0.1 μF capacitors to GND. To achieve the best results from
these decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 μF capacitors should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types or surface-mount types. These low ESR
and ESI capacitors provide a low impedance path to ground at
high frequencies to handle transient currents due to internal
logic switching.

Rev. C | Page 26 of 28
 AD7266

OUTLINE DIMENSIONS DETAIL A

(JEDEC 95)
5.10 0.30
5.00 SQ 0.25
PIN 1
INDICATOR 4.90 0.18
AREA
25 32 P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
24 1

0.50
BSC
3.25
EXPOSED 3.10 SQ
PAD
2.95

17 8

0.50 16 9
0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
0.30
0.80 FOR PROPER CONNECTION OF
0.75 SIDE VIEW THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70
0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE 0.20 REF

09-12-2018-A
PKG-003898

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD

Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
0.75 1.20
MAX 9.00 BSC SQ
0.60
0.45
32 25
1 24

PIN 1

7.00
TOP VIEW BSC SQ
0° MIN (PINS DOWN)
1.05 0.20
1.00 0.09
0.95 7°
3.5° 8 17
0.15 0° 9 16
SEATING
0.05 0.08 MAX
PLANE COPLANARITY VIEW A 0.80 0.45
BSC
LEAD PITCH 0.37
VIEW A 0.30
ROTATED 90° CCW
020607-A

COMPLIANT TO JEDEC STANDARDS MS-026-AB A

Figure 48. 32-Lead Thin Quad Flat Package [TQFP]

(SU-32-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description Package Option
AD7266BCPZ –40°C to +125°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-7
AD7266BCPZ-REEL7 –40°C to +125°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-7
AD7266BCPZ-REEL –40°C to +125°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-7
AD7266BSUZ –40°C to +125°C 32-Lead Thin Quad Flat Package (TQFP) SU-32-2
AD7266BSUZ-REEL7 –40°C to +125°C 32-Lead Thin Quad Flat Package (TQFP) SU-32-2
AD7266BSUZ-REEL –40°C to +125°C 32-Lead Thin Quad Flat Package (TQFP) SU-32-2
EVAL-AD7266EDZ Evaluation Board
EVAL-CED1Z Control Board
1
Z = RoHS Compliant Part.
2
The EVAL-AD7266CB can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes.
3
The EVAL-CED1Z controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in ED.

Rev. C | Page 27 of 28
AD7266

NOTES

©2005–2020 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04603-11/20(C)

Rev. C | Page 28 of 28