Plug & Trust Secure Element: Rev. 1.2 - 15 December 2020 Product Data Sheet 577312
Plug & Trust Secure Element: Rev. 1.2 - 15 December 2020 Product Data Sheet 577312
Plug & Trust Secure Element: Rev. 1.2 - 15 December 2020 Product Data Sheet 577312
1 Introduction
The SE051 is a ready-to-use IoT secure element solution. It provides a root of trust at the
IC level and it gives an IoT system state-of-the-art, edge-to-cloud security capability right
out of the box.
SE051 is updatable on applet level for feature updates or security maintenance
purposes.
SE051 allows for securely storing and provisioning credentials and performing
cryptographic operations for security critical communication and control functions. SE051
is versatile in IoT security use cases such as secure connection to public/private clouds,
device-to-device authentication or protection of sensor data.
SE051 has an independent Common Criteria EAL 6+ security certification up to OS level
and supports both RSA & ECC asymmetric cryptographic algorithms with high key length
and future proof ECC curves. The latest security measures protect the IC even against
sophisticated non-invasive and invasive attack scenarios.
The SE051 is a turnkey solution that comes with Java Card operating system and
an updatable applet optimized for IoT security use cases pre-installed. This is
complemented by a comprehensive product support package, enabling fast time to
market & easy design-in with Plug & Trust middleware for host applications, easy to
use development kits, reference designs, and extensive documentation for product
evaluation.
The SE051 is a product platform that comes in several pin-to-pin compatible product
variants, see [4].
Additional information on the integration can be found in several application notes on
www.nxp.com. Also see [3].
• Smart Home
• Smart Cities
• Smart Supply Chains
aaa-037479
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2 2
• Standard physical interface I C slave (High-speed mode, 3.4 Mbit/s), I C master (Fast
mode, 400 kbit/s). Both can be active at the same time
• Dedicated ISO14443-A passive contactless wireless interface for IoT use cases
simplifying configuration set-up, maintenance in the field and late stage configuration
• Secured user flash memory ranging from 45 kB full featured up to 101 kB for secure
data or key storage
• Support for SCP03 protocol (bus encryption and encrypted credential injection) to
securely bind the host with the secure element
• Support for applet level secure messaging channels to allow end-to-end encrypted
communication in multi-tenant ecosystems
2
• Support for Automatic detection of the I C T=1 protocol implementation based on the
initial message prologue. Supported protocols:
2
– NXP SE05x T=1 Over I C Specification. See [1].
– APDU Transport over SPI/I2C v1.0 | GPC_SPE_172. See [6].
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SE051 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
SE051 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
3 Functional description
API
EDGELOCK SE051
loT APPLET
HARDWARE
aaa-034211
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• ECC Key
• RSA Key
• HMAC Key
• Binary File
• User ID
• Counter
• Hash-Extend register
The Symmetric Key object can securely store symmetric keys of AES 128, 192 and 256
bit, 2K3DES and 3K3DES. The following specific operations are available on symmetric
key objects:
• Encrypt
• Decrypt
• Derive
• CMAC
• Secure Import
The ECC Key object has the ability to securely store ECC keys of the following curves
and key sizes:
• ECC NIST curve: NIST P-192, NIST P-224, NIST P-256, NIST P-384, NIST P-521
• ECC Brainpool curve: 160 bit, 192 bit, 224 bit, 256 bit, 320 bit, 384 bit, 512 bit
• Curve25519 (Montgomery) and Bi-rationally Equivalent Twisted Edwards Curve
• Curve448 (Goldilocks)
• ECC Koblitz curves: secp160k1, secp192k1, secp224k1, secp256k1
• ECC Barreto-Naehrig 256 bit curve
The following operations are available on ECC key objects (not all operations are
applicable to all curves):
• ECDSA/EdDSA Sign
• ECDSA/EdDSA Verify
• ECDH Generate Shared Secret/ECDHE
• ECDAA Sign
• Generate Key
• Secure Import
The RSA Key object has the ability to securely store RSA Keys up to 4096 bit. The
following specific operations are available on RSA key objects:
• RSA Sign
• RSA Verify
• RSA Encrypt
• RSA Decrypt
• RSA Generate Keys
• Secure Import
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An HMAC key object allows to securely store an HMAC key. The following operations are
supported on HMAC Key objects to compute an HMAC:
• Init
• Update
• Finalize
TLSCalculatePreMasterSecret
Binary file objects are byte arrays of a generic type. As in a standard file system, the
values can be accessed using read/write operations.
Counter objects are special kinds of binary file objects with specific functionality
interpreting the content of the file.
The supported operations for counters are:
• Set
• Get
• Increment
A hash-extend register secure object stores a hash over all data provided to that secure
object. It therefore contains the complete history of values provided to that register since
last reboot or since creation and can be used for attestation purposes.
User ID secure objects can be used to create sessions based on the User ID in cases
where multi-tenant support without cryptographic credential usage is required.
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SE051 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
4 Communication interfaces
2
4.1 I C Interfaces
2 2
The SE051 has one I C interface supporting slave and one I C interface supporting
master mode.
2
The I C slave interface is the main communication interface of the device and is used by
the host controller to send arbitrary APDUs to the device. It supports clock frequencies
2
up to 3.4 MHz when operated in High-Speed Mode (HS). The I C interface is using the
2
Smartcard T=1 over I C protocol.
The default slave address of the SE051 is configured to 0x48.
slave address
1 0 0 1 0 0 0 R/W
aaa-037450
Figure 3. Slave address
2
The I C master interface is supposed to be used with slave devices that need to be
securely written and read. This interface features a maximum SCL clock rate of 400 kHz.
2 2
I C Master can only be used when the I C slave interface is active.
2
4.1.1 Supported I C frequencies
2 2
The SE051 I C slave interface supports the I C high-speed mode with a maximum SCL
clock of up to 3.4 MHz when clock stretching is enabled.
In case clock stretching is disabled the maximum supported SCL clock frequency is
1.0 MHz.
2
The SE051 I C master interface supports maximum 400 kHz SCL clock frequency.
2
4.1.2 Default I C Communication Parameters
2
The default I C interface parameters of the SE051 devices are chosen with the highest
compatibility in mind:
2
• The used I C protocol is detected automatically on the first received frame amongst the
two possible protocols:
2
– NXP SE05x T=1 Over I C Specification. See [1].
– APDU Transport over SPI/I2C v1.0 | GPC_SPE_172. See [5].
• Clock Stretching is disabled, which allows SCL frequencies up to 1 MHz
• Automatically entering into the Power saving mode is disabled by default. Power
down can be explicitly requested by the host via an "End of APDU session
request" (according to [1]) respectively "RELEASE request" from GP T=1oI2C [5].
2
A In order to change the I C settings of the device the PERSO applet can be used.
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5 Power-saving modes
The device provides two power-saving operation modes. The Power-down mode (with
state retention) and the Deep Power-down mode (no state retention). These modes are
activated via pad ENA (Deep Power-down mode) or by the SW (Power-down mode).
1 ISO7816 is not enabled in generic SE051 configurations (see [3], AN12973) but available on customer
request.
2 In case ISO7816 is enabled a reset signal on RST_N exits the Power-down mode. After wake-up from
Power-down mode via RST_N the device is in idle mode (see Table 12)
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6 Ordering information
Table 3. Ordering information
12NC Type number SE051 Variant Orderable part number OEF
935414457472 SE051C2HQ1/Z01XD SE051C2 SE051C2HQ1/Z01XDZ A564
935414458472 SE051A2HQ1/Z01XE SE051A2 SE051A2HQ1/Z01XEZ A565
935409596472 SE051P2HQ1/Z011A SE051P2 SE051P2HQ1/Z011AZ A4A6
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7 Pinning information
7.1 Pinning
17 ISO 14443 LA
18 VCC
19 VSS
20 n.c.
index area
n.c. 4 12 VIN
aaa-031924
l2C_SDA
n.c.
n.c.
n.c.
Note: Terminal 1 index area is marked on the bottom with a notch on the center pad and
on the top with a printed dot.
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8 Package
SE051 is offered in HX2QFN20 package. The dimensions are 3 mm x 3 mm x 0,32 mm
with a 0,4 mm pitch.
Please refer to the package data sheet [2], SOT1969-1.
9 Marking
Table 5. Marking codes
Type number Marking code
Sx051... Line A: S51
Line B: **** (**** = 4-digit Batch code)
Line C: nDyww
D: RHF-2006 indicator
n: Assembly Center
Y: Year
WW: Week
10 Packing information
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12 Limiting values
Table 7. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VIN, Vcc supply voltage -0.3 +6 V
[1]
[1] Maximum supported supply voltage is 6 V. The SE051 is characterized for the specified operating supply voltage range of 1.62 V to 3.6 V. In case of
supply voltages above 3.6 V, Deep Power-down mode current <5 µA is not guaranteed.
[2] MIL Standard 883-D method 3015; human body model; C = 100 pF, R = 1.5 kΩ; Tamb = -40 °C to +105 °C.
[3] JESD22-C101, JEDEC Standard Field induced charge device model test method.
[4] Depending on appropriate thermal resistance of the package.
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+0.3
H Field strength Maximum field strength 1.5 7.5 A/m
at ambient temperature
[3]
<= 85 °C
H Field strength Maximum field strength 1.5 3.5 A/m
at ambient temperature
85...105 °C
[3]
[4]
Tamb Operating ambient temperature -40 +105 °C
[1] Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA is not guaranteed.
[2] IO1, CLK, RST has VCC as reference, SDA, SCL, IO2 and ENA has VIN as reference
[3] The field strength is valid for an Class 1 antennas.
[4] All product properties and values specified within this data sheet are only valid within the operating ambient temperature range.
1.62 V 3.6 V
aaa-015200_
Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-
down mode current <5 µA is not guaranteed.
Figure 5. Characteristic supply voltage operating range
14 Characteristics
[1] Thermal test board meets JEDEC specification for this package (JESD51-9)
[2] Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal
performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an
application-specific environment
[3] Junction-to-Case thermal resistance determined using an isothermal cold plate. Case is defined as the bottom of the packages (exposed pad)
14.2 DC characteristics
Measurement conventions
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Testing measurements are performed at the contact pads of the device under test. All
voltages are defined with respect to the ground contact pad VSS. All currents flowing into
the device are considered positive.
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Table 10. Electrical DC characteristics of Input/Output: IO1/IO2. Conditions: VCC = 1.62 V to 3.6 V (see ; VSS = 0 V;
Tamb = -40 °C to + 105 °C, unless otherwise specified...continued
In Table 10 VCC means for IO1 voltage on VCC pin, for IO2 voltage on VIN pin
Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA is
not guaranteed.
Symbol Parameter Conditions Min Typ Max Unit
-0.3 V ≤ VI < 0 V;+30 °C -1000 μA
≤ Tamb ≤
+105 °C
Test conditions: VI = -0.3
V;
VCC= VCC(max)Tamb =
+105 °C
IILIHQ Leakage input current at VCC < VI ≤ VCC + 0.3 V; 100 μA
input voltage beyond VCC -40 °C ≤
(only in "quasi-bidirectional" Tamb≤ +105 °C
mode) Test conditions: VI = VCC
+
0.3 V;VCC = VCC(max);
Tamb = +105 °C
IILILQ Leakage input current at input -0.3 V ≤ VI < 0 V; -40 °C -120 μA
voltage below VSS (only in ≤ Tamb ≤
"quasi-bidirectional" +30 °C
mode) Test conditions: VI = -0.3
V;
VCC = VCC(max)Tamb=
+30 °C
-0.3 V ≤ VI < 0 V;+30 °C -1000 μA
≤ Tamb ≤
+105 °C
Test conditions: VI = -0.3
V;
VCC = VCC(max)Tamb=
+105 °C
[2]
VOH HIGH level output voltage IOH = -20 μA; 0.7 VCC V
VOL LOW level output voltage IOL = 1.0 mA 0.3 V
IOL = 0.5 mA 0.15 VCC
[1] IO1/IO2 source a transition current when being externally driven from HIGH to LOW. This transition current (ITL) reaches its maximum value when the
input voltage VI is approximately 0.5 VCC. Current IIL is tested at input voltage VI= 0.3 V.
[2] External pull-up resistor 20 kΩ to VCC assumed. The worst case test condition for parameter VOH is present at minimum VCC.
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II VI
IIL1maxu IIH1maxu
VCC
-0.3 V 0
VIL1max VIH1min
IILI1maxI IIHI1maxI
aaa-029327
Vl
ll lILIHmax
lImin lIHmin
II
VI
IILIH1max
IIL1max II1max IIH1max
-0.3 V
VCC
IIL1min II1min
IlLlL1max aaa-007191
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II
VI
IlLIH2max
II2min IIH2min
VCC +0.3 V
2
14.2.2 I C Interface
2
Table 11. Electrical DC characteristics of I C pads SDA, SCL. Conditions: Vcc, VIN = 1.62 V to 3.6 V; VSS = 0 V; Tamb =
-40 °C to + 105 °C, unless otherwise specified*
Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA is
not guaranteed.
SSCL, SDA pads are in open-drain mode.
Symbol Parameter Conditions Min Typ Max Unit
VIH HIGH level input voltage 0.7 VIN VIN + 0.3 V
VIL LOW level input voltage -0.3 0.25 VIN V
VHYS Input hysteresis voltage - 0.081 V V
VOL(OD) Low level output voltage IOL = 3.0 mA 0 0.4 V
(open-drain mode)
IOL(OD) Low level output current VOL = 0.6 V 0.6 mA
(open-drain mode)
IWPU weak pull-up current VIO = 0 V -265 -180 -70 µA
IILIH Leakage input current high VSDA = 3.6 V, VSCL = 3.6 0.27 15 µA
level V
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Table 12. Electrical characteristics of IC supply voltage VCC; VSS = 0 V; Tamb = -40 °C to +105 C...continued
Symbol Parameter Conditions Min Typ Max Unit
during asymmetric crypto - 14.4 16.5 mA
operation
IDD (PD- supply current Power-down mode VCCmin ≤ VCC ≤ VCCmax; Clock to 430 480 μA
ISO7816) (ISO7816 clock-stop) input CLK stopped, Tamb= 25 °C
IDDD (DPD) supply current Deep Power-down VCCmin ≤ VIN ≤ VCCmax; Tamb= 3 5 μA
mode 25 °C
2
IDD (PD-I2C) supply current I C Power-down mode VCCmin ≤ VCC ≤ VCCmax; Clock 450 500 μA
2
(I C wake-up source) to input SCL stopped, Tamb=
25 °C SDA, SCL pads in pull-up
Typical value with VCC= 1.8 V
14.3 AC characteristics
Table 13. Non-volatile memory timing characteristics
Conditions: VCC = 1.62 V to 3.6 V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified.
[1]
Symbol Parameter Conditions Min Typ Max Unit
[2]
tEEP FLASH erase + program time 2.3 ms
tEEE FLASH erase time 0.9 ms
tEEW FLASH program time 1.4 ms
tEER FLASH data retention time Tamb = +55 °C 25 years
6
NEEC FLASH endurance (maximum 20 × 10 100 × cycles
6
number of programming cycles 10
applied to the whole memory
block performed by NXP static
and dynamic wear leveling
algorithm)
[1] Typical values are only referenced for information. They are subject to change without notice.
[2] Given value specifies physical access times of FLASH memory only.
2 2 [1]
Table 14. Electrical AC characteristics of I C_SDA, I C_SCL, and RST_N ; VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS =
0 V; Tamb = -40 °C to +105 °C°C
SCL, SDA pads in open-drain mode.
Symbol Parameter Conditions Min Typ Max Unit
2 2
Input/Output: I C_SDA, I C_SCL in open-drain mode
[2]
trIO I/O Input rise time Input/reception mode 1 μs
[2]
tfIO I/O Input fall time Input/reception mode 1 μs
[2]
tfOIO I/O Output fall time Output/transmission mode; CL 0.3 μs
= 30 pF
2
fCLK External clock frequency in I C tCLKW, Tamb and VCC in their - 3.4 MHz
applications specified limits
2 [3]
tPD Power down duration time (I C CPU clock = 48 MHz 67 μs
wake-up)
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2 2 [1]
Table 14. Electrical AC characteristics of I C_SDA, I C_SCL, and RST_N ; VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS =
0 V; Tamb = -40 °C to +105 °C°C...continued
SCL, SDA pads in open-drain mode.
Symbol Parameter Conditions Min Typ Max Unit
[4]
tWKPD Wake-up from power down CPU clock = 48 MHz 97 μs
2
duration time (I C wake-up)
CPIN Pin capacitances RST_N, Test frequency = 1 MHz; Tamb - 10.5 pF
2 2
I C_SDA, /I C_SCL = 25 °C
[5]
tENalt ENA low time and Vout, Vcc 2 μs
low time for entering deep
power down mode
Ron Resistance of power switch Tamb=105 °C, Iload=25 mA, 1.1 Ohm
Vin=1.62 V
Iout maximum current driving Tamb=105 °C 25 mA
capability of pin Vout
Inputs: RST_N (active only if ISO7816 UART interface is enabled)
tRW Reset pulse width (RST_N low) 40 400 μs
without entering Power-down
mode
tRDSLP Reset pulse width (RST_N low) 500 μs
to enter Power-down mode
tWKP Wake-up time from Power- fCLKmin < fCLK < fCLKmax - 8 10 μs
down mode
tWKPIO Pad LOW time for wake-up level triggered ext.int. - 8 10 μs
from Power-down mode
edge triggered ext.int. - 8 10 μs
tWKPRST RST_N LOW time for wake-up 40 - μs
from Power-down mode
CPIN Pin capacitances RST_N, Test frequency = 1 MHz; Tamb - 10.5 pF
2 2
I C_SDA, /I C_SCL = 25 °C
[1] All appropriately marked values are typical values and only referenced for information. They are subject to change without notice.
[2] tr is defined as rise time between 30 % and 70 % of the signal amplitude.
tf is defined as fall time between 70 % and 30 % of the signal amplitude.
2
[3] Wakeup from power down: if clock stretching disabled and I C_SCL=400 kHz; the wakeup time will not be sufficient under the rare condition where host
sends the first command during the time where SE is just entering power down; in this case the SE will send an R block to request retransmission from the
host
2
[4] Wakeup from power down: if clock stretching disabled and I C_SCL=1 MHz; the wakeup time will not be sufficient to receive the first host command; the
SE will send an R block to request retransmission from the host
[5] Low glitches below 0.4 V on pin ENA and Vin, Vout, Vcc larger than 30 ns cause Power-On-Reset, respectively entering deep power-down mode.
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Vhigh
70 % level
CLK (et al) 0.5 VDD
30 % level
Vlow
tCLKW
tfCLK trCLK
1/fCLK tfRST trRST
tfIO trIO
aaa-037451
1) 2 2
During AC testing the inputs RST_N, I C_SDA, I C_SCL are driven at 0 V to +0.3 V for a LOW
input level and at VCC -0.3 V to VCC for a HIGH input level. Clock period and signal pulse (duty
cycle) timing is measured at 50 % of VCC.
2)
tr is defined as rise time between 30 % and 70 % of the signal amplitude. tf is defined as fall
time between 70 % and 30 % of the signal amplitude.
2 2
Figure 10. External clock drive and AC test timing reference points of I C_SDA, I C_SCL,
1) 2)
and RST_N (see and ) in open-drain mode
Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)
Conditions: VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified. Typical
values are only referenced for information. They are subject to change without notice.
Symbol Parameter Conditions Min Typ Max Unit
Input/Output: IO1/IO2
[1]
trIO I/O Input rise time Input/reception mode 1 μs
[2]
[3]
0.25 x μs
[2]
tIOWx_min
[1]
tfIO I/O Input fall time Input/reception mode 1 μs
[2]
[3]
0.25 x μs
[2]
tIOWx_min
[2]
trOIO I/O Output rise time Output/transmission mode; CL 0.1 μs
= 30 pF
[2]
tfOIO I/O Output fall time Output/transmission mode; CL 0.1 μs
= 30 pF
Inputs: CLK and RST_N
[4]
fCLK External clock frequency tCLKW, tamb and VCC in their 0.85 11.5 MHz
in ISO/IEC 7816 UART specified limits
applications
tCLKW Clock pulse width i.r.t. clock 40 60 %
period (positive pulse duty
cycle of CLK)
[5]
trCLK CLK input rise time [6]
[2]
tfCLK CLK input fall time [6]
[6]
[2]
trRST RST_N input rise time 400 μs
[2]
tfRST RST_N input fall time 400 μs
[7]
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[1] At minimum IO1 input signal HIGH or LOW level voltage pulse width of 3.2 μs. This timing specification applies to ISO7816 configurations down to a
minimum etu duration of 16 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x96, (Fi/Di)=(512/32)), for example.
[2] tr is defined as rise time between 10 % and 90 % of the signal amplitude.
[3] At minimum IO1 input signal HIGH or LOW level voltage pulse width of less than 3.2 μs. This timing specification applies to ISO7816 configurations
beyond the conditions listed in note [2], down to a minimum etu duration of 8 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x97, (Fi/
Di)=(512/64)), for example. An 8 CLKs/etu @ fclk = 5 MHz configuration results in tIOWx_min = 1.6 μs, and in a time of 400 ns for trIO_max and tfIO_
max, matching the (Fi/Di)=(512/64) speed enhancement requirements of ETSI TS 102 221.
[4] ISO/IEC 7816 I/O applications have to supply a clock signal to input CLK in the frequency range of 1 MHz to 10 MHz nominal. A ± 15 % tolerance range
yields the allowed limits of 0.85 MHz and 11.5 MHz.
[5] During AC testing the inputs CLK, RST_N, and IO1 are driven at 0 V to +0.3 V for a LOW input level and at VCC − 0.3 V to VCC for a HIGH input level.
Clock period and signal pulse (duty cycle) timing is measured at 50 % of VCC, see Figure 18.
[6] The maximum CLK rise and fall time is 10 % of the CLK period 1/fCLK - with the following exception: In the CLK frequency range of 1 MHz to 5 MHz the
maximum allowed CLK rise and fall time is 50 ns, if 10 % of the CLK period is shorter than 50 ns.
[7] The ETSI TS102 221/GSM 11.1x specifications specify a maximum reset signal (RST_N) rise time and fall time of 400,000 μs, respectively.
Table 16. Electrical AC characteristics of LA, LB; Conditions: Tamb = -40 °C to 105 °C, unless otherwise
specified
Conditions: Tamb = -25 °C to +85 °C, unless otherwise specified.
[1]
Symbol Parameter Conditions Typ Max Unit
Input/Output: LA, LB
[2]
CLALB Pin capacitance LA, LB
Bare die (SO28 empty package
ground-off)
[3] [4]
Configured for antenna input with VLA,LB = 2.1 V (rms) 54.3 pF
[4]
56 pF capacitance VLA,LB = 0.3 V (rms) 50.1
Test frequency = 13.56 MHz;
Tamb= 25 °C
[2] [3] [4]
RLALB Configured for antenna input with VLA,LB = 2.1 V (rms) 0.913 kΩ
[5]
56 pF capacitance. Test frequency
= 13.56 MHz;
Tamb= 25 °C
fLALB Operating frequency LA, LB level triggered ext.int. 13.56 MHz
[1] Typical values (± 10 %) are only referenced for information. They are subject to change without notice.
[2] The CLALB and RLALB values stated here assume a parallel RC equivalent circuit for the chip.
[3] The value stated here was measured at estimated start of chip operation and is comparable to the values stated in other SmartMX3 family member data
sheets.
[4] Measured with sine wave at LA, LB.
[5] Parameter is valid in contactless ISO14443 compliant operation valid only.
2
14.4 I C Bus Timings
2
Parameters defined in this chapter replace the parameter definitions of I C bus, for
specification see [4].
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SDA
50 % 50 %
SCL
50 % 50 %
tHDf;DAT50 tHDr;DAT50
aaa-036486
2
Figure 11. I C Bus Timings
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2
Table 17. I C Bus Timing Specification
Symbol Parameter Condition Min Max Unit
[1]
tHDf;DAT50 data hold time Fast mode 8 ns
50% SCL - 50% SDA level
[2]
tHDr;DAT50 data hold time Fast mode 24 ns
50% SCL - 50% SDA level
[1]
tHDf;DAT50 data hold time Hs mode 8 ns
50% SCL - 50% SDA level
[2]
tHDr;DAT50 data hold time Hs mode 9 ns
50% SCL - 50% SDA level
[1] tHDf;DAT50, as defined in Figure 11, replaces parameter tHD;DAT defined in [4]
[2] tHDr;DAT50, as defined in Figure 11, replaces parameter tHD;DAT defined in [4]
14.5 EMC/EMI
EMC and EMI resistance according to IEC 61967-4.
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15 Abbreviations
Table 18. Abbreviations
Acronym Description
AES Advanced Encryption Standard
APDU Application Protocol Data Unit
CL Contactless
CLK External clock signal input contact pad
CC Common Criteria
CMAC Cipher-based MAC
CRC Cyclic Redundancy Check
CRI Cryptography Research Incorporated
DES Digital Encryption Standard
DPA Differential Power Analysis
DSS Digital Signature Standard
EAL Evaluation Assurance Level
ECC Elliptic Curve Cryptography
EMC Electromagnetic compatibility
EMI Electro Magnetic Immunity
FM Fast-Mode
FM+ Fast-Mode+
GP Global Platform
GPIO General-purpose input/output
HS High-Speed-Mode
HKDF HMAC-based Extract-and-Expand Key Derivation Function
HMAC Keyed-Hash Message Authentication Code
HW Hardware
IC Integrated Circuit
2
I C Inter-Integrated Circuit
I/O Input/Output
IoT Internet of Things
JCOP Java Card Open Platform
LA ISO 14443 Antenna Pad
LB ISO 14443 Antenna Pad
NFC Near Field Communication
MAC Message Authentication Code
MCU Microcontroller unit
MPU Microprocessor
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Table 18. Abbreviations...continued
Acronym Description
MW Middleware
OS Operating System
NIST National Institute for Standards and Technology
PCB Printed Circuit Board
PKI Public Key Infrastructure
PRF Pseudo Random Function
RAM Random Access Memory
RSA Rivest-Shamir-Adleman
RST Reset
SAM Secure Access Module
SCL Serial clock
SDA Serial data
SPA Simple Power Analysis
SFI Single Fault Injection
SHA Secure Hash Algorithm
SW Software
TLS Transport Layer Security
VCC Supply Voltage Input
VIN Voltage Input
VOUT Voltage Output
VSS Ground
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16 References
2
[1] NXP SE05x T=1 Over I C Specification User Manual, Document Number 11225.
Available on NXP website
[2] SOT1969-1; HX2QFN20; Reel packing and package data sheet. Available on NXP
website.
[3] SE051 IoT Applet APDU Specification, document number AN 12543. Available on
NXP website.
[4] SE051 configurations Application Note, document number AN12973. Available on
NXP website.
[5] APDU Transport over SPI/I2C v1.0 | GPC_SPE_172. Available here.
[6] How to use EdgeLock SE051 PERSO applet, SE051 Application Note AN13015.
Available on NXP website.
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17 Revision history
Table 19. Revision history
Document ID Release date Data sheet status Change notice Supersedes
577312 20-12-15 Product data sheet 577311
Modifications • updated Table 2
• updated legal disclaimer and references
• Figure 2
577311 20-11-17 Product data sheet 577310
Modifications corrected Table 2
577310 20-10-28 Objective data sheet -
Modifications Initial version
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18 Legal information
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devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
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No offer to sell or license — Nothing in this document may be interpreted open and/or proprietary technologies supported by NXP products for use
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Tables
Tab. 1. SE051 commercial name format ....................... 2 Tab. 12. Electrical characteristics of IC supply
Tab. 2. SE051 configuration .......................................... 5 voltage VCC; VSS = 0 V; Tamb = -40 °C to
Tab. 3. Ordering information ........................................14 +105 C ........................................................... 22
Tab. 4. Pin description HX2QFN20 ............................. 15 Tab. 13. Non-volatile memory timing characteristics ..... 23
Tab. 5. Marking codes .................................................16 Tab. 14. Electrical AC characteristics of I2C_SDA,
Tab. 6. Reel packing options .......................................17 I2C_SCL, and RST_N; VCC = 1.8 V ±
Tab. 7. Limiting values ................................................ 17 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb =
Tab. 8. Recommended operating conditions ............... 17 -40 °C to +105 °C°C ....................................... 23
Tab. 9. Thermal characteristics ................................... 18 Tab. 15. Electrical AC characteristics of IO1, IO2,
Tab. 10. Electrical DC characteristics of Input/ CLK and RST_N (ISO7816 interface) ............. 25
Output: IO1/IO2. Conditions: VCC = 1.62 V Tab. 16. Electrical AC characteristics of LA, LB;
to 3.6 V (see ; VSS = 0 V; Tamb = -40 °C to Conditions: Tamb = -40 °C to 105 °C,
+ 105 °C, unless otherwise specified .............. 19 unless otherwise specified .............................. 26
Tab. 11. Electrical DC characteristics of I2C pads Tab. 17. I2C Bus Timing Specification .......................... 28
SDA, SCL. Conditions: Vcc, VIN = 1.62 V Tab. 18. Abbreviations ...................................................29
to 3.6 V; VSS = 0 V; Tamb = -40 °C to + Tab. 19. Revision history ...............................................32
105 °C, unless otherwise specified* ................ 22
Figures
Fig. 1. SE051 solution block diagram ...........................2 Fig. 7. Input characteristic of IO1/IO2 ........................ 21
Fig. 2. SE051 functional diagram - example Open Fig. 8. Input characteristic of CLK when the IC is
SSL ....................................................................7 not in reset ...................................................... 21
Fig. 3. Slave address ................................................. 12 Fig. 9. Input characteristic of CLK during IC reset ...... 22
Fig. 4. Pin configuration for HX2QFN20 Fig. 10. External clock drive and AC test timing
(SOT1969-1) ....................................................15 reference points of I2C_SDA, I2C_SCL,
Fig. 5. Characteristic supply voltage operating and RST_N (see 1) and 2)) in open-drain
range ............................................................... 18 mode ............................................................... 25
Fig. 6. Input characteristic of RST_N ......................... 21 Fig. 11. I2C Bus Timings ..............................................27
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Contents
1 Introduction ......................................................... 1 14.1 Thermal Characteristics ...................................18
1.1 SE051 use cases .............................................. 1 14.2 DC characteristics ............................................18
1.2 SE051 target applications ..................................1 14.2.1 General and General Purpose I/O interface .....19
1.3 SE051 naming convention .................................2 14.2.2 I2C Interface .................................................... 22
2 Features and benefits .........................................3 14.2.3 Power consumption ......................................... 22
2.1 Key benefits .......................................................3 14.3 AC characteristics ............................................23
2.2 Key features ...................................................... 3 14.4 I2C Bus Timings .............................................. 26
2.3 Features in detail ...............................................5 14.5 EMC/EMI ..........................................................28
3 Functional description ........................................7 15 Abbreviations .................................................... 29
3.1 Functional diagram ............................................ 7 16 References ......................................................... 31
3.2 IoT Applet Functionality ..................................... 7 17 Revision history ................................................ 32
3.2.1 Supported secure object types .......................... 7 18 Legal information .............................................. 33
3.2.1.1 Symmetric Key .................................................. 8
3.2.1.2 ECC Key ............................................................8
3.2.1.3 RSA Key ............................................................ 8
3.2.1.4 HMAC Key object .............................................. 9
3.2.1.5 HKDF operation .................................................9
3.2.1.6 Binary file objects .............................................. 9
3.2.1.7 Counter Objects .................................................9
3.2.1.8 Hash-Extend register ......................................... 9
3.2.1.9 User ID secure object ........................................9
3.2.2 Access control ................................................... 9
3.2.3 Locking the Device Configuration .................... 10
3.2.4 Sessions and multi-threading .......................... 10
3.2.5 Attestation and trust provisioning .....................10
3.2.6 Application support .......................................... 10
3.2.7 Random numbers ............................................ 10
3.2.8 Credential Storage & Memory ......................... 10
3.3 PERSO applet ................................................. 11
3.4 SEMS Lite ........................................................11
3.5 Applet Updatability ...........................................11
3.6 Ease of use configuration ................................11
3.7 Startup behaviour ............................................ 11
4 Communication interfaces ............................... 12
4.1 I2C Interfaces .................................................. 12
4.1.1 Supported I2C frequencies .............................. 12
4.1.2 Default I2C Communication Parameters ......... 12
4.2 ISO7816 and ISO14443 Interface ................... 13
5 Power-saving modes ........................................ 13
5.1 Power-down mode ...........................................13
5.2 Deep Power-down mode ................................. 13
6 Ordering information ........................................ 14
7 Pinning information .......................................... 15
7.1 Pinning ............................................................. 15
7.1.1 Pinning HX2QFN20 ......................................... 15
8 Package ..............................................................16
9 Marking ...............................................................16
10 Packing information ..........................................16
10.1 Reel packing ....................................................16
11 Electrical and timing characteristics ...............17
12 Limiting values .................................................. 17
13 Recommended operating conditions .............. 17
14 Characteristics .................................................. 18
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