MSP 44x0G Multistandard Sound Processor Family: Micronas

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PRELIMINARY DATA SHEET
MICRONAS MSP 44x0G

Multistandard
Sound Processor Family
MICRONAS
Edition May 16, 2001
6251-533-1PD
MSP 44x0G PRELIMINARY DATA SHEET
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Contents
Page Section Title
6 1. Introduction
7 1.1. Features of the MSP 44x0G Family and Differences to MSPD
8 1.2. MSP 44x0G Version List
8 1.3. MSP 44x0G Versions and their Application Fields
10 2. Functional Description
11 2.1. Architecture of the MSP 44x0G Family
11 2.2. Sound IF Processing
11 2.2.1. Analog Sound IF Input
11 2.2.2. Demodulator: Standards and Features
12 2.2.3. Preprocessing of Demodulator Signals
12 2.2.4. Automatic Sound Select
12 2.2.5. Manual Mode
12 2.3. Preprocessing for SCART and I2S Input Signals
14 2.4. Source Selection and Output Channel Matrix
14 2.5. Audio Baseband Processing
14 2.5.1. Automatic Volume Correction (AVC)
14 2.5.2. Loudspeaker and Headphone Outputs
14 2.5.3. Subwoofer Output
14 2.5.4. Quasi-Peak Detector
14 2.5.5. Micronas Dynamic Bass (MDB)
15 2.5.5.1. Dynamic Amplification
15 2.5.5.2. Adding Harmonics
15 2.5.5.3. MDB Parameters
15 2.6. SCART Signal Routing
15 2.6.1. SCART DSP In and SCART Out Select
15 2.6.2. Stand-by Mode
16 2.7. I2S Bus Interfaces
16 2.7.1. Two-Channel I2S-Input
16 2.7.2. Multichannel I2S-Input
16 2.7.2.1. Using I2S_DA_IN3
16 2.7.2.2. Using I2S_DA_IN1/2/3
16 2.7.3. Two or Eight-Channel I2S-Output
17 2.8. ADR Bus Interface
17 2.9. Digital Control I/O Pins and Status Change Indication
17 2.10. Clock PLL Oscillator and Crystal Specifications
18 3. Control Interface
18 3.1. I2C Bus Interface
18 3.1.1. Internal Hardware Error Handling
19 3.1.2. Description of CONTROL Register
19 3.1.3. Protocol Description
20 3.1.4. Proposals for General MSP 44x0G I2C Telegrams
20 3.1.4.1. Symbols
20 3.1.4.2. Write Telegrams
20 3.1.4.3. Read Telegrams
20 3.1.4.4. Examples
2 Micronas
PRELIMINARY DATA SHEET MSP 44x0G
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Contents, continued
Page Section Title
20 3.2. Start-Up Sequence: Power-Up and I2C-Controlling

20 3.3. MSP 44x0G Programming Interface
20 3.3.1. User Registers Overview
24 3.3.2. Description of User Registers
25 3.3.2.1. STANDARD SELECT Register
25 3.3.2.2. Refresh of STANDARD SELECT Register
25 3.3.2.3. STANDARD RESULT Register
27 3.3.2.4. Write Registers on I2C Subaddress 10hex
29 3.3.2.5. Read Registers on I2C Subaddress 11hex
30 3.3.2.6. Write Registers on I2C Subaddress 12hex
43 3.3.2.7. Read Registers on I2C Subaddress 13hex
44 3.4. Programming Tips
44 3.5. Examples of Minimum Initialization Codes
44 3.5.1. B/G-FM (A2 or NICAM)
44 3.5.2. BTSC-Stereo
44 3.5.3. BTSC-SAP with SAP at Loudspeaker Channel
45 3.5.4. FM-Stereo Radio
45 3.5.5. Automatic Standard Detection
45 3.5.6. SCART1 Input to Loudspeaker in Stereo Sound
45 3.5.7. Software Flow for Interrupt driven STATUS Check
47 4. Specifications
47 4.1. Outline Dimensions
48 4.2. Pin Connections and Short Descriptions
51 4.3. Pin Descriptions
54 4.4. Pin Configurations
56 4.5. Pin Circuits
58 4.6. Electrical Characteristics
58 4.6.1. Absolute Maximum Ratings
59 4.6.2. Recommended Operating Conditions (TA = 0 to 70 °C)
59 4.6.2.1. General Recommended Operating Conditions
59 4.6.2.2. Analog Input and Output Recommendations
60 4.6.2.3. Recommendations for Analog Sound IF Input Signal
61 4.6.2.4. Crystal Recommendations
62 4.6.3. Characteristics
62 4.6.3.1. General Characteristics
63 4.6.3.2. Digital Inputs, Digital Outputs
64 4.6.3.3. Reset Input and Power-Up
65 4.6.3.4. I2C-Bus Characteristics
66 4.6.3.5. I2S-Bus Characteristics
69 4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
70 4.6.3.7. Sound IF Inputs
70 4.6.3.8. Power Supply Rejection
71 4.6.3.9. Analog Performance
74 4.6.3.10. Sound Standard Dependent Characteristics
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Contents, continued
Page Section Title
78 5. Appendix A: Overview of TV-Sound Standards

78 5.1. NICAM 728
79 5.2. A2-Systems
80 5.3. BTSC-Sound System
80 5.4. Japanese FM Stereo System (EIA-J)
81 5.5. FM Satellite Sound
81 5.6. FM-Stereo Radio
82 6. Appendix B: Manual/Compatibility Mode

82 6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode
83 6.2. DSP Write and Read Registers for Manual/Compatibility Mode
84 6.3. Manual/Compatibility Mode: Description of Demodulator Write Registers
84 6.3.1. Automatic Switching between NICAM and Analog Sound
84 6.3.1.1. Function in Automatic Sound Select Mode
84 6.3.1.2. Function in Manual Mode
86 6.3.2. A2 Threshold
86 6.3.3. Carrier-Mute Threshold
87 6.3.4. Register AD_CV
88 6.3.5. Register MODE_REG
90 6.3.6. FIR-Parameter, Registers FIR1 and FIR2
90 6.3.7. DCO-Registers
92 6.4. Manual/Compatibility Mode: Description of Demodulator Read Registers
92 6.4.1. NICAM Mode Control/Additional Data Bits Register
92 6.4.2. Additional Data Bits Register
92 6.4.3. CIB Bits Register
93 6.4.4. NICAM Error Rate Register
93 6.4.5. PLL_CAPS Readback Register
93 6.4.6. AGC_GAIN Readback Register
93 6.4.7. Automatic Search Function for FM-Carrier Detection in Satellite Mode
94 6.5. Manual/Compatibility Mode: Description of DSP Write Registers
94 6.5.1. Additional Channel Matrix Modes
94 6.5.2. Volume Modes of SCART1/2 Outputs
94 6.5.3. FM Fixed Deemphasis
94 6.5.4. FM Adaptive Deemphasis
95 6.5.5. NICAM Deemphasis
95 6.5.6. Identification Mode for A2 Stereo Systems
95 6.5.7. FM DC Notch
95 6.6. Manual/Compatibility Mode: Description of DSP Read Registers
95 6.6.1. Stereo Detection Register for A2 Stereo Systems
95 6.6.2. DC Level Register
96 6.7. Demodulator Source Channels in Manual Mode
96 6.7.1. Terrestric Sound Standards
96 6.7.2. SAT Sound Standards
4 Micronas
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Contents, continued
Page Section Title
98 7. Appendix D: Application Information

98 7.1. Exclusions of Audio Baseband Features
98 7.2. Phase Relationship of Analog Outputs
98 7.3. Compatibility Restrictions to MSP 34x0D
99 7.4. Application Circuit
100 8. Appendix E: MSP 44x0G Version History
100 9. Data Sheet History
License Notice:
“Dolby Pro Logic” and “Dolby Digital” are trademarks of Dolby Laboratories.
Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intel-
lectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies plan-
ning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.
Micronas 5
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Multistandard Sound Processor Family EIA-J. The MSP 44x0G has optimum stereo perfor-
mance without any adjustments.
1. Introduction The MSP 44x0G has built-in automatic functions: The

IC is able to detect the actual sound standard automat-
The MSP 44x0G family of single-chip Multistandard ically (Automatic Standard Detection). Furthermore,
Sound Processors covers the sound processing of all pilot levels and identification signals can be evaluated
analog TV-Standards worldwide, as well as the NICAM internally with subsequent switching between mono/
digital sound standards. The full TV sound processing, stereo/bilingual; no I2C interaction is necessary (Auto-
starting with analog sound IF signal-in, down to pro- matic Sound Selection).
cessed analog AF-out, is performed on a single chip.
Fig. 1–1 shows a simplified functional block diagram of The MSP 44x0G can handle very high FM deviations
the MSP 44x0G. even in conjunction with NICAM processing. This is
especially important for the introduction of NICAM in
This new generation of TV sound processing ICs now China.
includes versions for processing the multichannel tele-
vision sound (MTS) signal conforming to the standard All MSP 44xxG versions are pin and software compati-
recommended by the Broadcast Television Systems ble to the MSP 34xxG. The MSP 44x0G has all func-
Committee (BTSC). The DBX noise reduction, or alter- tions of the MSP 34x0G with additional multichannel
natively, Micronas Noise Reduction (MNR) is per- digital inputs and outputs. Its sample rate of 48 kHz
formed alignment free. makes this device ideal for applications in digital TV
systems. In general, outline dimensions, electrical
Other processed standards are the Japanese FM-FM characteristics and application diagrams are identical
multiplex standard (EIA-J) and the FM Stereo Radio to the MSP 34x0G.
standard.
The ICs are manufactured in submicron CMOS tech-
Current ICs have to perform adjustment procedures in nology. The MSP 44x0G is available in the following
order to achieve good stereo separation for BTSC and packages: PQFP80, PLQFP64, and PSDIP64.
Sound IF1 Loud- Loud-

De- Pre- speaker speaker
ADC DAC
modulator processing Sound
Sound IF2 Processing Subwoofer
Headphone/
Surround
Source Select
DAC Headphone
I2S1 Sound
Processing
I2S2 Prescale
I2S3 I2S
SCART1
DAC
SCART2 SCART
DSP SCART1
SCART3 Input ADC Prescale SCART
Select DAC Output
SCART4 Select
MONO
SCART2
Fig. 1–1: Block diagram of the MSP 44x0G
6 Micronas
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1.1. Features of the MSP 44x0G Family and Differences to MSPD
Feature (New features not available for MSPD are shaded gray.) 4410 4420 4440 4450
48 kHz sampling rate X X X X
20 kHz audio band width X X X X
Standard Selection with single I2C transmission X X X X
Automatic Standard Detection of terrestrial TV standards/Automatic Carrier Mute function X X X X
Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS X X X X
Two selectable sound IF (SIF) inputs X X X X
Automatic Carrier Mute function X X X X
Interrupt output programmable (indicating status change) X X X X
Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness X X X X
Loudspeaker channel with MDB (Micronas Dynamic Bass) X X X X
AVC: Automatic Volume Correction X X X X
Subwoofer output with programmable low-pass and complementary high-pass filter X X X X
5-band graphic equalizer for loudspeaker channel X X X X
Spatial effect for loudspeaker channel X X X X
Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs X X X X
Complete SCART in/out switching matrix X X X X
Three I2S inputs; one I2S output X X X X
3rd digital input (I2S3) with multichannel capability X X X X
Digital output with multichannel capability X X X X
All analog Mono sound carriers including AM-SECAM L X X X X
All analog FM-Stereo A2 and satellite standards X X
Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM X X
Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) X X
ASTRA Digital Radio (ADR) together with DRP 3510A X X
All NICAM standards X X
Demodulation of the BTSC multiplex signal and the SAP channel X X X
Alignment free digital DBX noise reduction for BTSC Stereo and SAP X X
Alignment free digital Micronas Noise Reduction (MNR) for BTSC Stereo and SAP X
BTSC and EIA-J stereo separation significantly better than spec. X X X
SAP and stereo detection for BTSC system X X X
Korean FM-Stereo A2 standard X X X X
Alignment-free Japanese standard EIA-J X X X
Demodulation of the FM-Radio multiplex signal X X X
Micronas 7
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1.2. MSP 44x0G Version List
Table 1–1: MSP 44x0G Version List
Version Status Description
MSP 4410G not confirmed NICAM and FM Stereo (A2) Version
MSP 4420G not confirmed NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR),
and Japanese EIA-J System)
MSP 4440G not confirmed NTSC Version (A2 Korea, BTSC with DBX Noise Reduction,
and Japanese EIA-J System)
MSP 4450G available Global Version (all sound standards)
1.3. MSP 44x0G Versions and their Application Fields
Table 1–2 provides an overview of TV sound stan-

dards that can be processed by the MSP 44x0G fam-
ily. In addition, the MSP 44x0G is able to handle the
FM-Radio standard. With the MSP 44x0G, a complete
multimedia receiver covering all TV sound standards
together with terrestrial/cable and satellite radio sound
can be built; even ASTRA Digital Radio can be pro-
cessed (with a DRP 3510A coprocessor).
Table 1–2: TV Stereo Sound Standards covered by the MSP 44x0G IC Family (details see Appendix A)
MSP Version TV- Position of Sound Sound Color Broadcast e.g. in:
System Carrier /MHz Modulation System
5.5/5.7421875 FM-Stereo (A2) PAL Germany

B/G
5.5/5.85 FM-Mono/NICAM PAL Scandinavia, Spain
L 6.5/5.85 AM-Mono/NICAM SECAM-L France
I 6.0/6.552 FM-Mono/NICAM PAL UK, Hong Kong
6.5/6.2578125 FM-Stereo (A2, D/K1) SECAM-East Slovak. Rep.

4410
6.5/6.7421875 FM-Stereo (A2, D/K2) PAL currently no broadcast

D/K
6.5/5.7421875 FM-Stereo (A2, D/K3) SECAM-East Poland
4450
6.5/5.85 FM-Mono/NICAM (D/K, NICAM) PAL China, Hungary
6.5 FM-Mono
7.02/7.2 FM-Stereo Europe Sat.
Satellite 7.38/7.56 PAL
ASTRA Digital Radio (ADR) with ASTRA
etc. DRP 3510A
4.5/4.724212 FM-Stereo (A2) NTSC Korea

4420, 4440
M/N 4.5 FM-FM (EIA-J) NTSC Japan
4.5 BTSC-Stereo + SAP NTSC, PAL USA, Argentina
FM-Radio 10.7 FM-Stereo Radio USA, Europe
8 Micronas
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S/PDI1
S/PDIF In 1/2 S/PDIF Out
Deemphasis
AC-3, MPEG L2, PCM or other Format PCM PCM-Format (Lt/Rt or L/R or Lo/Ro)
S/PDI2 or Loop-through (e.g. DTS)
SPDO
L
2
Post Processing
Input R
MPEG SOD3
Delay Lines
Buffer Ls
SOD2
Multipl.
Rs
SOD1
C/
SOD
SID* Sub Dolby Digital / Pro Logic Configuratio
AC-3 SOI
SII* Lt Example 1:
Rt
SOC
SIC* - internal L, C, R
I2S-In: Slave - internal woofer for low freq. of L, (C)
Noise - ext. Surround speakers SL, SR
SID
Gen. - ext. Subwoofer for SUB channel.
SII
SIC
Example 2:
- internal Left and Right used as C
- internal woofer for low freq. of C
Amp./ - ext. L, R
18.432 MHz
Osc.
PLL Synth. MAS 3528E - ext. Surround speakers SL, SR
Dolby Digital Decoder - ext. Subwoofer for SUB channel.
CLKO MPEG-L2 Decoder

Configuration Examples
I2S-Mode:Multichannel Mode auf D0 Dolby Digital /

(6 - 8 Channels, fs=32, 44.1 or 48 kHz, normal
Pro Logic
I2S_Inputs 16,18,....32 Bit)
1 2
1 2 3 Speaker
I2S_1_L Bass
I2S_WS3 D/A --- Cint Lext
I2S_1_R Treble
I2S_CL3 analog --- SUBext SUBext
I2S_2_L Balance
Volume --- (Cint) Rext
I2S_2_R Volume
Bass Headphone
AUDIO_ D/A
2-8 Ch. Input I2S_3_Lt Treble --- SL SL
CL_OUT analog
(LT, RT,L, R Balance --- SR SR
I2S_3_Rt Volume
SL, SR,C, SUB) Volume
18.432 SCART1
MHz L --- Lt Lt
Volume D/A
6 Channel --- Rt Rt
R
Loop-through
or SL L, R L, R
I2S_Out_L/R
Dolby C, SUB C, SUB
SR ---
Pro Logic SL, SR SL, SR
Decoder C Lt, Rt Lt, Rt
I2S_WS SUB
Dolby I2S_CL DPL 4519G
Digital Pro Logic Decoder
Upgrade
Module
Dolby Digital: (Lt, Rt, L, R, SL, SR, C, SUB)

Basic Pro Logic: (Lt, Rt, L, R, C, SubW)
TV-
Sound I2S_Inputs
System
1 2 3
I2S_WS3 I2S_1_L Sound- Speaker
D/A L Lint Cint
I2S_CL3 I2S_1_R Process.
analog Subw Subwint Subwint
Balance
Volume R Rint Cint
Volume
I2S_WS I2S_2_L
I2S_CL I2S_2_R
Bass Headphone
D/A
Treble L Lt Lt
I2S_3_Lt analog
Balance R Rt Rt
I2S_3_Rt Volume
18.432 Volume
2-8 I2S_3_L
MHz SCART1
Channel I2S_3_R L Lt Lt
Serial I2S_3_SL Volume D/A
R Rt Rt
Input I2S_3_SR
I2S_3_C
I2S_3_SUB SCART2
L Lt Lt
Volume D/A
R Rt Rt
SIF-IN Demod I2S_Out_L/R

L, R L, R L, R
SCART1_In .
.
2 .
A/D
SCART4_In MSP 4450G
Multistandard Sound Processor
Fig. 1–2: Typical MSP 44x0G application
Micronas 9
10
2. Functional Description
MSP 44x0G
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Automatic
ANA_IN1+ Standard Selection Sound Select
AGC A Deemphasis: FM/AM Loud- Bass/
FM/AM 0 Loud- Comple- D DACM_L
50/75 µs speaker
DEMODULATOR
DBX/MNR Channel AVC
Treble
or Σ ness mentary Spatial Balance
Highpass Effects
Volume
D (incl. Carrier Mute) Matrix
Panda1 Prescale Stereo or A/B 1 Equalize
(0Ehex) (29hex)
DACM_R
(08hex) (02hex) (04hex) 0.5 (2Dhex) (05hex) (01hex)
ANA_IN2+ Decoded (03hex)
Standards: NICAM Stereo or A 3 Level A
Lowpass MDB
− NICAM Deemphasis
Beeper
Adjust DACM_SUB
− A2 J17
(2Dhex) (2Chex) (00hex)
Stereo or B 4
− AM Prescale (14hex)
− BTSC (10hex)
− EIA-J
− SAT Standard I2C 10R
− FM-Radio and Sound Read
ADR-Bus
Interface Detection Register
Volume D
I2S1 Headphone DACA_L
Σ
Bass/ Loudness
2
I S Channel Balance
I2S_DA_IN1 5 Treble
Interface Matrix A
Prescale
DACA_R
Source Select
(09hex) (31/32hex) (33hex) (30hex) (06hex)
(16hex)
I2S2
I2S
I2S_DA_IN2 I2S I2S
6 Channel I2S_DA_OUT
Interface Interface
Prescale Matrix
(12hex) (0Bhex)
2 7
I S3
I2S_DA_IN3 I2S 8
Quasi-Peak I2C
Interface 9 Quasi-Peak
Channel Read
Prescale Detector
10 Matrix Register (19hex)
(11hex) (1Ahex)
(0Chex)
A SCART
SCART DSP Input Select
2 Volume D
SCART1
D Prescale Channel SCART1_L/R
(0Dhex)
Matrix A
(0Ahex) (07hex)
Volume SC1_OUT_L
SCART2 D
Channel SCART2_L/R
Matrix A
SC1_OUT_R
SCART Output Select

(13hex) (41hex) (40hex)
PRELIMINARY DATA SHEET

SC1_IN_L
SC1_IN_R
SC2_IN_L
SC2_OUT_L
SC2_IN_R
SC3_IN_L
SC2_OUT_R
SC3_IN_R
SC4_IN_L
SC4_IN_R
MONO_IN
Micronas
(13hex)
Fig. 2–1: Signal flow block diagram of the MSP 44x0G (input and output names correspond to pin names)
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2.1. Architecture of the MSP 44x0G Family BTSC-Mono + SAP: Detection and FM demodulation
of the aural carrier resulting in the MTS/MPX signal.
Fig. 2–1 on page 10 shows a simplified block diagram Detection and evaluation of the pilot carrier, detection
of the IC. The block diagram contains all features of and FM demodulation of the SAP subcarrier. Process-
the MSP 4450G. Other members of the MSP 44x0G ing of DBX noise reduction or Micronas Noise Reduc-
family do not have the complete set of features: The tion (MNR).
demodulator handles only a subset of the standards
presented in the demodulator block; NICAM process- Japan Stereo: Detection and FM demodulation of the
ing is only possible in the MSP 4410G and aural carrier resulting in the MPX signal. Demodulation
MSP 4450G. and evaluation of the identification signal and FM
demodulation of the (L−R)-carrier.
2.2. Sound IF Processing FM-Satellite Sound: Demodulation of one or two FM

carriers. Processing of high-deviation mono or narrow
2.2.1. Analog Sound IF Input bandwidth mono, stereo, or bilingual satellite sound
according to the ASTRA specification.
The input pins ANA_IN1+, ANA_IN2+, and ANA_IN−
offer the possibility to connect two different sound IF FM-Stereo-Radio: Detection and FM demodulation of
(SIF) sources to the MSP 44x0G. The analog-to-digital the aural carrier resulting in the MPX signal. Detection
conversion of the preselected sound IF signal is done and evaluation of the pilot carrier and AM demodula-
by an A/D-converter. An analog automatic gain circuit tion of the (L−R)-carrier.
(AGC) allows a wide range of input levels. The high-
pass filters formed by the coupling capacitors at pins The demodulator blocks of all MSP 44x0G versions
ANA_IN1+ and ANA_IN2+ (see Section 7.4. “Applica- have identical user interfaces. Even completely differ-
tion Circuit” on page 99) are sufficient in most cases to ent systems like the BTSC and NICAM systems are
suppress video components. Some combinations of controlled the same way. Standards are selected by
SAW filters and sound IF mixer ICs, however, show means of MSP Standard Codes. Automatic processes
large picture components on their outputs. In this case, handle standard detection and identification without
further filtering is recommended. controller interaction. The key features of the
MSP 44x0G demodulator blocks are:
2.2.2. Demodulator: Standards and Features Standard Selection: The controlling of the demodula-
tor is minimized: All parameters, such as tuning fre-
The MSP 44x0G is able to demodulate all TV-sound quencies or filter bandwidth, are adjusted automati-
standards worldwide including the digital NICAM sys- cally by transmitting one single value to the
tem. Depending on the MSP 44x0G version, the fol- STANDARD SELECT register. For all standards, spe-
lowing demodulation modes can be performed: cific MSP standard codes are defined.
A2 Systems: Detection and demodulation of two sep- Automatic Standard Detection: If the TV sound stan-
arate FM carriers (FM1 and FM2), demodulation and dard is unknown, the MSP 44x0G can automatically
evaluation of the identification signal of carrier FM2. detect the actual standard, switch to that standard, and
respond the actual MSP standard code.
NICAM Systems: Demodulation and decoding of the
NICAM carrier, detection and demodulation of the ana- Automatic Carrier Mute: To prevent noise effects or
log (FM or AM) carrier. For D/K-NICAM, the FM carrier FM identification problems in the absence of an FM
may have a maximum deviation of 384 kHz. carrier, the MSP 44x0G offers a configurable carrier
mute feature, which is activated automatically if the TV
Very high deviation FM-Mono: Detection and robust sound standard is selected by means of the STAN-
demodulation of one FM carrier with a maximum devi- DARD SELECT register. If no FM carrier is detected at
ation of 540 kHz. one of the two MSP demodulator channels, the corre-
sponding demodulator output is muted. This is indi-
BTSC-Stereo: Detection and FM demodulation of the cated in the STATUS register.
aural carrier resulting in the MTS/MPX signal. Detec-
tion and evaluation of the pilot carrier, AM demodula-
tion of the (L−R)-carrier and detection of the SAP sub-
carrier. Processing of DBX noise reduction or
Micronas Noise Reduction (MNR).
Micronas 11
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2.2.3. Preprocessing of Demodulator Signals – “Stereo or A” channel: Analog or digital mono

sound, stereo if available. In case of bilingual broad-
The NICAM signals must be processed by a deempha- cast, it contains language A (on left and right).
sis filter and adjusted in level. The analog demodu-
– “Stereo or B” channel: Analog or digital mono
lated signals must be processed by a deemphasis fil-
sound, stereo if available. In case of bilingual broad-
ter, adjusted in level, and dematrixed. The correct
cast, it contains language B (on left and right).
deemphasis filters are already selected by setting the
standard in the STANDARD SELECT register. The
Fig. 2–2 and Table 2–2 show the source channel
level adjustment has to be done by means of the FM/
assignment of the demodulated signals in case of
AM and NICAM prescale registers. The necessary
Automatic Sound Select mode for all sound standards.
dematrix function depends on the selected sound stan-
dard and the actual broadcasted sound mode (mono,
Note: The analog primary input channel contains the
stereo, or bilingual). It can be manually set by the FM
signal of the mono FM/AM carrier or the L+R signal of
Matrix Mode register or automatically by the Automatic
the MPX carrier. The secondary input channel con-
Sound Selection.
tains the signal of the 2nd FM carrier, the L-R signal of
the MPX carrier, or the SAP signal.
2.2.4. Automatic Sound Select
In the Automatic Sound Select mode, the dematrix primary

FM/AM 0
LS Ch.
channel FM/AM Matrix
function is automatically selected based on the identifi-
cation information in the STATUS register. No I2C
Source Select
secondary Prescale
channel Stereo or A/B 1
Automatic Output-Ch.
interaction is necessary when the broadcasted sound Sound matrices
mode changes (e.g. from mono to stereo). NICAM A NICAM
Select must be set
Stereo or A 3 once to
stereo.
The demodulator supports the identification check by NICAM B Prescale Stereo or B 4
switching between mono-compatible standards (stan-
dards that have the same FM-Mono carrier) automati-
cally and non-audible. If B/G-FM or B/G-NICAM is Fig. 2–2: Source channel assignment of demodulated
selected, the MSP will switch between these stan- signals in Automatic Sound Select Mode
dards. The same action is performed for the stan-
dards: D/K1-FM, D/K2-FM, D/K3-FM and D/K-NICAM.
Switching is only done in the absence of any stereo or 2.2.5. Manual Mode
bilingual identification. If identification is found, the
MSP keeps the detected standard. Fig. 2–3 shows the source channel assignment of
demodulated signals in case of manual mode. If man-
In case of high bit-error rates, the MSP 44x0G auto- ual mode is required, more information can be found in
matically falls back from digital NICAM sound to ana- Section 6.7. “Demodulator Source Channels in Manual
log FM or AM mono. Mode” on page 96.
Table 2–1 summarizes all actions that take place when

Automatic Sound Select is switched on.
primary
LS Ch.
channel FM/AM Matrix
To provide more flexibility, the Automatic Sound Select FM-Matrix FM/AM 0
Source Select
secondary
block prepares four different source channels of channel
Prescale
Output-Ch.
demodulated sound (Fig. 2–2). By choosing one of the matrices
must be set
four demodulator channels, the preferred sound mode NICAM A NICAM
according to
NICAM the standard.
can be selected for each of the output channels (loud- (Stereo or A/B)
1
speaker, headphone, etc.). This is done by means of NICAM B Prescale
the Source Select registers.
The following source channels of demodulated sound Fig. 2–3: Source channel assignment of demodulated
are defined: signals in Manual Mode
– “FM/AM” channel: Analog mono sound, stereo if

available. In case of NICAM, analog mono only 2.3. Preprocessing for SCART and
(FM or AM mono). I2S Input Signals
– “Stereo or A/B” channel: Analog or digital mono
sound, stereo if available. In case of bilingual broad- The SCART and I2S inputs need only be adjusted in
cast, it contains both languages A (left) and B level by means of the SCART and I2S prescale regis-
(right). ters.
12 Micronas
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Table 2–1: Performed actions of the Automatic Sound Selection
Selected TV Sound Standard Performed Actions
B/G-FM, D/K-FM, M-Korea, Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four
and M-Japan demodulator source channels according to Table 2–2.
B/G-NICAM, L-NICAM, I-NICAM, Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four
D/K-NICAM demodulator source channels according to Table 2–2.
In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches
back to NICAM if possible. A hysteresis prevents periodical switching.
B/G-FM, B/G-NICAM Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and non-
audible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-mono sound
or
carrier.
D/K1-FM, D/K2-FM, D/K3-FM, Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the
and D/K-NICAM absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP
keeps the corresponding standard.
BTSC-STEREO, FM Radio Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator
source channels according to Table 2–2. Detection of the SAP carrier.
M-BTSC-SAP In the absence of SAP, the MSP switches to BTSC-stereo if available. If SAP is detected, the MSP
switches automatically to SAP (see Table 2–2).
Table 2–2: Sound modes for the demodulator source channels with Automatic Sound Select
Source Channels in Automatic Sound Select Mode
Broadcasted Selected Broadcasted FM/AM Stereo or A/B Stereo or A Stereo or B

Sound MSP Standard Sound Mode (source select: 0) (source select: 1) (source select: 3) (source select: 4)
Standard Code3)
M-Korea 02 MONO Mono Mono Mono Mono

B/G-FM 03, 081)
D/K-FM 04, 05, 07, 0B1) STEREO Stereo Stereo Stereo Stereo
M-Japan 30
BILINGUAL: Left = A A B
Languages A and B Right = B Right = B
B/G-NICAM 08, 032) NICAM not available or analog Mono analog Mono analog Mono analog Mono
L-NICAM 09 error rate too high
I-NICAM 0A
D/K-NICAM 0B, 042), 052) MONO analog Mono NICAM Mono NICAM Mono NICAM Mono
D/K-NICAM 0C, 0D
(with high STEREO analog Mono NICAM Stereo NICAM Stereo NICAM Stereo
deviation FM)
BILINGUAL: analog Mono Left = NICAM A NICAM A NICAM B
Languages A and B Right = NICAM B
20, 21 MONO Mono Mono Mono Mono
STEREO Stereo Stereo Stereo Stereo
20 MONO + SAP Mono Mono Mono Mono
BTSC STEREO + SAP Stereo Stereo Stereo Stereo
21 MONO + SAP Left = Mono Left = Mono Mono SAP

Right = SAP Right = SAP
STEREO + SAP Left = Mono Left = Mono Mono SAP

FM Radio 40 MONO Mono Mono Mono Mono
STEREO Stereo Stereo Stereo Stereo

1)
The Automatic Sound Select process will automatically switch to the mono compatible analog standard.
2) The Automatic Sound Select process will automatically switch to the mono compatible digital standard.
3)
The MSP Standard Codes are defined in (see Table 3–7 on page 24).
Micronas 13
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2.4. Source Selection and Output Channel Matrix 2.5.2. Loudspeaker and Headphone Outputs
The Source Selector makes it possible to distribute all The following baseband features are implemented in
source signals (one of the demodulator source chan- the loudspeaker and headphone output channels:
nels, SCART, or I2S input) to the desired output chan- bass/treble, loudness, balance, and volume. A square
nels (loudspeaker, headphone, etc.). All input and out- wave beeper can be added to the loudspeaker and
put signals can be processed simultaneously. Each headphone channel. The loudspeaker channel addi-
source channel is identified by a unique source tionally performs: equalizer (not simultaneously with
address. bass/treble), spatial effects, and a subwoofer cross-
over filter.
For each output channel, the sound mode can be set
to sound A, sound B, stereo, or mono by means of the
output channel matrix. 2.5.3. Subwoofer Output
If Automatic Sound Select is on, the output channel The subwoofer signal is created by combining the left
matrix can stay fixed to stereo (transparent) for and right channels directly behind the loudness block
demodulated signals. using the formula (L+R)/2. Due to the division by 2, the
D/A converter will not be overloaded, even with full
scale input signals. The subwoofer signal is filtered by
2.5. Audio Baseband Processing a third-order low-pass with programmable corner fre-
quency followed by a level adjustment. At the loud-
2.5.1. Automatic Volume Correction (AVC) speaker channels, a complementary high-pass filter
can be switched on. Subwoofer and loudspeaker out-
Different sound sources (e.g. terrestrial channels, SAT put use the same volume (Loudspeaker Volume Reg-
channels, or SCART) fairly often do not have the same ister).
volume level. Advertisements during movies usually
have a higher volume level than the movie itself. This
results in annoying volume changes. The Automatic 2.5.4. Quasi-Peak Detector
Volume Correction (AVC) solves this problem by
equalizing the volume level. The quasi-peak readout register can be used to read
out the quasi-peak level of any input source. The fea-
To prevent clipping, the AVC’s gain decreases quickly ture is based on following filter time constants:
in dynamic boost conditions. To suppress oscillation
effects, the gain increases rather slowly for low level attack time: 1.3 ms
inputs. The decay time is programmable by means of decay time: 37 ms
the AVC register (see page 34).
For input signals ranging from −24 dBr to 0 dBr, the 2.5.5. Micronas Dynamic Bass (MDB)
AVC maintains a fixed output level of −18 dBr. Fig. 2–4
shows the AVC output level versus its input level. For The Micronas Dynamic Bass system (MDB) extends
prescale and volume registers set to 0 dB, a level of the frequency range of loudspeakers or headphones.
0 dBr corresponds to full scale input/output. This is
After the adaption of MDB to the loudspeakers and the
– SCART input/output 0 dBr = 2.0 Vrms
cabinet, further customizing of MDB allows individual
– Loudspeaker and Aux output 0 dBr = 1.4 Vrms fine tuning of the sound.
The MDB is placed in the subwoofer path. For applica-

output level tions without a subwoofer, the enhanced bass signal
[dBr] can be added back onto the Left/Right channels (see
Fig. 2–1 on page 10). Micronas Dynamic Bass com-
bines two effects: Dynamic Amplification and Adding
−18
Harmonics.
−24
input level
−30 −24 −18 −12 −6 0 [dBr]
Fig. 2–4: Simplified AVC characteristics
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2.5.5.1. Dynamic Amplification 2.6. SCART Signal Routing
Low frequency signals can be boosted while the output 2.6.1. SCART DSP In and SCART Out Select
signal amplitude is measured. If the amplitude comes
close to a definable limit, the gain is reduced automati- The SCART DSP Input Select and SCART Output
cally in dynamic Volume mode. Therefore, the system Select blocks include full matrix switching facilities. To
adapts to the signal amplitude which is really present design a TV set with four pairs of SCART-inputs and
at the output of the MSP device. Clipping effects are two pairs of SCART-outputs, no external switching
avoided. hardware is required. The switches are controlled by
the ACB user register (see page 42).
Amplitude
(db)
2.6.2. Stand-by Mode

MDB_LIMIT
If the MSP 44x0G is switched off by first pulling
Signal Level
STANDBYQ low and then (after >1 µs delay) switching
off DVSUP and AVSUP, but keeping AHVSUP
(‘Stand-by’-mode), the SCART switches maintain
their position and function. This allows the copying
Frequency
from SCART-input to SCART-output in the TV set’s
MDB_HP MDB_LP SUBW_FREQ stand-by mode.
Fig. 2–5: Dynamic Amplification In case of power on or starting from stand-by (switch-
ing on the DVSUP and AVSUP, RESETQ going high
2 ms later), all internal registers except the ACB regis-
2.5.5.2. Adding Harmonics ter (see page 42) are reset to the default configuration
(see Table 3–5 on page 21). The reset position of the
MDB exploits the psychoacoustic phenomenon of the ACB register becomes active after the first I2C trans-
‘missing fundamental’. Adding harmonics of the fre- mission into the Baseband Processing part. By trans-
quency components below the cutoff frequency gives mitting the ACB register first, the reset state can be
the impression of actually hearing the low frequency redefined.
fundamental. In other words: The listener has the
impression that a loudspeaker system seems to repro-
duce frequencies although physically not possible.
Amplitude (db)
Frequency
MDB_HP
Fig. 2–6: Adding Harmonics
2.5.5.3. MDB Parameters
Several parameters allow tuning the characteristics of

MDB according to the TV loudspeaker, the cabinet,
and personal preferences (see Table 3–11). For more
detailed information on how to set up MDB, please
refer to the corresponding application note on the
Micronas homepage.
Micronas 15
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2.7. I2S Bus Interfaces – I2S_CL3: I2S serial clock

– I2S_WS3:
The MSP 44x0G has three I2S bus input data lines and
I2S word strobe signal, defines frame start
one I2S bus output data line. They are all operated in
48 kHz mode.
In multichannel input mode, the number of channels
must be even and less or equal eight. If CL and WS
Together with I2S_WS/CL or I2S_WS3/CL3, the data
are active (master mode) only, eight-channel mode is
lines form two I2S bus interfaces with various opera-
available. Channel Select matrix I2S3-1/2 to I2S3-7/8
tional modes.
are used as input ports.
Both interfaces work in synchronous master or slave
I2S_DA_IN1, I2S_DA_IN2, I2S_CL, and I2S_WS are
mode. They accept a variety of formats with different
available simultaneously for two-channel input.
sample width, bit-orientation, and wordstrobe timing.
All I2S options are set by means of the MODUS and
the I2S_CONFIG register.
2.7.2.2. Using I2S_DA_IN1/2/3
The different operational modes are described in the
All I2S input lines (I2S_DA_IN1, I2S_DA_IN2, and
following sections.
I2S_DA_IN3 in PQFP80 package) can be used in par-
allel in two-channel mode to transmit six channels
simultaneously. The interface consist of the pins:
2.7.1. Two-Channel I2S-Input
– I2S_DA_IN1, I2S_DA_IN2, I2S_DA_IN3:
The two I2S bus input lines 1 and 2 are capable of I2S serial data input, 16, 18...32 bits per sample
receiving two channel I2S signals. The interface con-
sist of the pins: – I2S_CL3: I2S serial clock
– I2S_WS3:
– I2S_DA_IN1, I2S_DA_IN2/3
I2S word strobe signal, defines left and right sample
(I2S_DA_IN2 in PQFP80 package):
I2S serial data input, 16, 18...32 bits per sample
Channel Select matrix I2S3-1/2 to I2S3-5/6 are used
– I2S_CL: as input ports. I2S1 and I2S2 inputs are not available
I2S serial clock in this mode.
– I2S_WS
I2S word strobe signal, defines left and right sample.
2.7.3. Two or Eight-Channel I2S-Output
If the MSP 44x0G serves as master on this I2S inter-
Bit[0:1] of the I2S CONFIG register (see page 28)
face (active), the clock and word strobe lines are
switches the output to two-channel or eight-channel
driven by the MSP 44x0G. Depending on the I2S out-
multichannel output mode. The bit resolution per chan-
put definition (section 2.7.3.), the interface is switched
nel is 16 or 32-bit in master mode. The first two chan-
to a different wordlength. If the I2S output is set to 2*16
nels can be selected on the source select matrix.
bit, it works with 2*16bit MSB bound. In case of 2*32 or
Channel 2 is repeated six times (e.g.
8*32 bits, the first 18 bits after each WS Slope are
L,R,R,R,R,R,R,R). The multichannel output mode is
used.
used to connect with interfaces not working in two-
channel mode. Both master and slave mode are possi-
In slave mode, I2S_CL and I2S_WS are input to the
ble as long as the wordstrobe has only one positive
MSP 44x0G (tristate) and the MSP 44x0G clock is
edge per frame in slave mode. The interface consist of
synchronized to 384 times the I2S_WS rate (48 kHz).
the pins:
NICAM operation is not possible in slave mode. An I2S – I2S_DA_OUT:
timing diagram is shown in Fig. 4–24 on page 67. I2S serial data otuput, 16 or 32 bits per sample
– I2S_CL: I2S serial clock
2.7.2. Multichannel I2S-Input – I2S_WS:
I2S word strobe signal defines left and right sample
2.7.2.1. Using I2S_DA_IN3
Note: The I2S_DA_IN1 and I2S_DA_IN2 input buffers
The MSP 44x0G is capable of receiving signals with are filled with the first 18 bits after each WS Slope.
up to eight audio channels. The corresponding I2S bus
interface consist of the pins: An I2S timing diagram is shown in Fig. 4–25 on
page 68.
– I2S_DA_IN2/3 (I2S_DA_IN3 in PQFP80 package):
I2S serial data input, 16, 18...32 bits per sample
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2.8. ADR Bus Interface 2.9. Digital Control I/O Pins and
Status Change Indication
For the ASTRA Digital Radio System (ADR), the
MSP 4410G, and MSP 4450G performs preprocessing The static level of the digital input/output pins
such as carrier selection and filtering. Via the 3-line D_CTR_I/O_0/1 is switchable between HIGH and
ADR-bus, the resulting signals are transferred to the LOW via the I2C-bus by means of the ACB register
DRP 3510A coprocessor, where the source decoding (see page 42). This enables the controlling of external
is performed. To be prepared for an upgrade to ADR hardware switches or other devices via I2C-bus.
with an additional DRP board, the following lines of
MSP 44x0G should be provided on a feature connec- The digital input/output pins can be set to high imped-
tor: ance by means of the MODUS register (see page 27).
In this mode, the pins can be used as input. The cur-
– AUD_CL_OUT
rent state can be read out of the STATUS register (see
– I2S_DA_IN1 or I2S_DA_IN2 page 29).
– I2S_DA_OUT
Optionally, the pin D_CTR_I/O_1 can be used as an
– I2S_WS interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes poll-
– I2S_CL ing unnecessary, I2C bus interactions are reduced to a
– ADR_CL, ADR_WS, ADR_DA minimum (see “STATUS Register” on page 29 and
“MODUS Register” on page 27).
For more details, please refer to the DRP 3510A data
sheet.
2.10. Clock PLL Oscillator and
Crystal Specifications
The MSP 44x0G derives all internal system clocks

from the 18.432 MHz oscillator. In NICAM or in I2S-
Slave mode, the clock is phase-locked to the corre-
sponding source. Therefore, it is not possible to use
NICAM and I2S-Slave mode at the same time.
For proper performance, the MSP clock oscillator

requires a 18.432 MHz crystal. Note that for the
phase-locked modes (NICAM, I2S-Slave), crystals with
tighter tolerance are required.
Micronas 17
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3. Control Interface response time is about 0.3 ms. If the MSP cannot
accept another byte of data (e.g. while servicing an
3.1. I2C Bus Interface internal interrupt), it holds the clock line I2C_CL low to
force the transmitter into a wait state. The I2C Bus
The MSP 44x0G is controlled via the I2C bus slave Master must read back the clock line to detect when
interface. the MSP is ready to receive the next I2C transmission.
The positions within a transmission where this may
The IC is selected by transmitting one of the happen are indicated by ’Wait’ in Section 3.1.3. The
MSP 44x0G device addresses. In order to allow up to maximum wait period of the MSP during normal opera-
three MSP ICs to be connected to a single bus, an tion mode is less than 1 ms.
address select pin (ADR_SEL) has been implemented.
With ADR_SEL pulled to high, low, or left open, the
MSP 44x0G responds to different device addresses. A 3.1.1. Internal Hardware Error Handling
device address pair is defined as a write address and a
read address (see Table 3–1). In case of any hardware problems (e.g. interruption of
the power supply of the MSP), the MSP’s wait period is
Writing is done by sending the write device address, extended to 1.8 ms. After this time period elapses, the
followed by the subaddress byte, two address bytes, MSP releases data and clock lines.
and two data bytes.
Reading is done by sending the write device address, Indication and solving the Error Status:
followed by the subaddress byte and two address
bytes. Without sending a stop condition, reading of the To indicate the error status, the remaining acknowl-
addressed data is completed by sending the device edge bits of the actual I2C-protocol will be left high.
read address and reading two bytes of data. Additionally, bit[14] of CONTROL is set to one. The
MSP can then be reset via the I2C bus by transmitting
Refer to Section 3.1.3. for the I2C bus protocol and to the RESET condition to CONTROL.
Section 3.4. “Programming Tips” on page 44 for pro-
posals of MSP 44x0G I2C telegrams. See Table 3–2
for a list of available subaddresses. Indication of Reset:
Besides the possibility of hardware reset, the MSP can Any reset, even caused by an unstable reset line etc.,
also be reset by means of the RESET bit in the CON- is indicated in bit[15] of CONTROL.
TROL register by the controller via I2C bus.
A general timing diagram of the I2C bus is shown in
Due to the architecture of the MSP 44x0G, the IC can- Fig. 4–23 on page 65.
not react immediately to an I2C request. The typical
Table 3–1: I2C Bus device addresses
ADR_SEL Low High Left Open

(connected to DVSS) (connected to DVSUP)
Mode Write Read Write Read Write Read
MSP device address 80hex 81hex 84hex 85hex 88hex 89hex
Table 3–2: I2C Bus subaddresses
Name Binary Value Hex Value Mode Function
CONTROL 0000 0000 00 Read/Write Write: Software reset of MSP (see Table 3–3)
Read: Hardware error status of MSP
WR_DEM 0001 0000 10 Write write address demodulator
RD_DEM 0001 0001 11 Write read address demodulator
WR_DSP 0001 0010 12 Write write address DSP
RD_DSP 0001 0011 13 Write read address DSP
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3.1.2. Description of CONTROL Register
Table 3–3: CONTROL as a write register
Name Subaddress Bit[15] (MSB) Bits[14:0]
CONTROL 00hex 1 : RESET 0

0 : normal
Table 3–4: CONTROL as a read register
Name Subaddress Bit[15] (MSB) Bit[14] Bits[13:0]
CONTROL 00hex RESET status after last reading of Internal hardware status: not of interest
CONTROL: 0 : no error occured
1 : internal error occured
0 : no reset occured
1 : reset occured
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be
read once to be reset.
3.1.3. Protocol Description
Write to DSP or Demodulator
S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte ACK data-byte ACK P
device high low high low
address
Read from DSP or Demodulator
S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK S read Wait ACK data-byte- ACK data-byte NAK P
device high low device high low
address address
Write to Control Register
S write Wait ACK sub-addr ACK data-byte ACK data-byte ACK P

device high low
address
Read from Control Register
S write Wait ACK 00hex ACK S read Wait ACK data-byte- ACK data-byte NAK P
device device high low
address address
Note: S = I2C-Bus Start Condition from master

P= I2C-Bus Stop Condition from master
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray)
NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’
or from MSP indicating internal error state
Wait = I2C-Clock line is held low, while the MSP is processing the I2C command.
This waiting time is max. 1 ms
Micronas 19
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1
I2C_DA
0
S P
I2C_CL
Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.1.4. Proposals for General MSP 44x0G 3.2. Start-Up Sequence:

I2C Telegrams Power-Up and I2C-Controlling
3.1.4.1. Symbols After POWER-ON or RESET (see Fig. 4–22), the IC is

in an inactive state. All registers are in the Reset posi-
daw write device address (80hex, 84hex or 88hex) tion (see Table 3–5 and Table 3–6), the analog out-
dar read device address (81hex, 85hex or 89hex) puts are muted. The controller has to initialize all regis-
< Start Condition ters for which a non-default setting is necessary.
> Stop Condition
aa Address Byte
dd Data Byte 3.3. MSP 44x0G Programming Interface
3.3.1. User Registers Overview

3.1.4.2. Write Telegrams
The MSP 44x0G is controlled by means of user regis-
<daw 00 d0 00> write to CONTROL register ters. The complete list of all user registers are given in
<daw 10 aa aa dd dd> write data into demodulator Table 3–5 and Table 3–6. The registers are partitioned
<daw 12 aa aa dd dd> write data into DSP into the Demodulator section (Subaddress 10hex for
writing, 11hex for reading) and the Baseband Process-
ing sections (Subaddress 12hex for writing, 13hex for
3.1.4.3. Read Telegrams reading).
<daw 00 <dar dd dd> read data from Write and read registers are 16 bit wide, whereby the
CONTROL register MSB is denoted bit[15]. Transmissions via I2C bus
<daw 11 aa aa <dar dd dd> read data from demodulator have to take place in 16-bit words (two byte transfers, with
<daw 13 aa aa <dar dd dd> read data from DSP the most significant byte transferred first). All write regis-
ters, except the demodulator write registers are readable.
3.1.4.4. Examples Unused parts of the 16-bit write registers must be zero.
Addresses not given in this table must not be
<80 00 80 00> RESET MSP statically accessed.
<80 00 00 00> Clear RESET
<80 10 00 20 00 03> Set demodulator to stand. 03hex For reasons of software compatibility to the
<80 11 02 00 <81 dd dd> Read STATUS MSP 34xxD, a Manual/Compatibility Mode is available.
<80 12 00 08 01 20> Set loudspeaker channel More read and write registers together with a detailed
source to NICAM and description can be found in “Appendix B: Manual/Com-
Matrix to STEREO patibility Mode” on page 82.
More examples of typical application protocols are

listed in Section 3.4. “Programming Tips” on page 44.
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Table 3–5: List of MSP 44x0G write registers
Write Register Address Bits Description and Adjustable Range Reset See
(hex) Page
I2C Subaddress = 10hex ; Registers are not readable
STANDARD SELECT 00 20 [15:0] Initial Programming of the Demodulator 00 00 25
MODUS 00 30 [15:0] Demodulator, Automatic and I2S options 00 00 27
I2S CONFIGURATION 00 40 [15:0] Configuration of I2S options 00 00 28

2 2
I C Subaddress = 12hex ; Registers are all readable by using I C Subaddress = 13hex
Volume loudspeaker channel 00 00 [15:8] [+12 dB ... −114 dB, MUTE] MUTE 33
Volume / Mode loudspeaker channel [7:0] 1/8 dB Steps, 00hex

Reduce Volume / Tone Control / Compromise/
Dynamic
Balance loudspeaker channel [L/R] 00 01 [15:8] [0...100 / 100% and 100 / 0...100%] in 0.8 % steps 100%/100% 34
[−127...0 / 0 and 0 / −127...0 dB] in 1 dB steps
Balance mode loudspeaker [7:0] [Linear / logarithmic mode] linear mode
Bass loudspeaker channel 00 02 [15:8] [+20 dB ... −12 dB] 0 dB 35
Treble loudspeaker channel 00 03 [15:8] [+15 dB ... −12 dB] 0 dB 36
Loudness loudspeaker channel 00 04 [15:8] [0 dB ... +17 dB] 0 dB 37
Loudness filter characteristic [7:0] [NORMAL, SUPER_BASS] NORMAL
Spatial effect strength loudspeaker ch. 00 05 [15:8] [−100%...OFF...+100%] OFF 38
Spatial effect mode/customize [7:0] [SBE, SBE+PSE] SBE+PSE
Volume headphone channel 00 06 [15:8] [+12 dB ... −114 dB, MUTE] MUTE 33
Volume / Mode headphone channel [7:0] 1/8 dB Steps, Reduce Volume / Tone Control 00hex
Volume SCART1 output channel 00 07 [15:8] [+12 dB ... −114 dB, MUTE] MUTE 41
2 2 2
Loudspeaker source select 00 08 [15:8] [FM/AM, NICAM, SCART, I S1, I S2, I S3] FM/AM 32
Loudspeaker channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32
Headphone source select 00 09 [15:8] [FM/AM, NICAM, SCART, I2S1, I2S2, I2S3] FM/AM 32
Headphone channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32
SCART1 source select 00 0A [15:8] [FM/AM, NICAM, SCART, I2S1, I2S2, I2S3] FM/AM 32
SCART1 channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32

2 2 2 2
I S source select 00 0B [15:8] [FM/AM, NICAM, SCART, I S1, I S2, I S3] FM/AM 32
I2S channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32
Quasi-peak detector source select 00 0C [15:8] [FM/AM, NICAM, SCART, I2S1, I2S2, I2S3] FM/AM 32
Quasi-peak detector matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32
Prescale SCART input 00 0D [15:8] [00hex ... 7Fhex] 00hex 31
Prescale FM/AM 00 0E [15:8] [00hex ... 7Fhex] 00hex 30
FM matrix [7:0] [NO_MAT, GSTEREO, KSTEREO] NO_MAT 31
Prescale NICAM 00 10 [15:8] [00hex ... 7Fhex] (MSP 4410G, MSP 4450G only) 00hex 31
2
Prescale I S3 00 11 [15:8] [00hex ... 7Fhex] 10hex 31
Prescale I2S2 00 12 [15:8] [00hex ... 7Fhex] 10hex 31
ACB : SCART Switches a. D_CTR_I/O 00 13 [15:0] Bits [15..0] 00hex 42
Beeper 00 14 [15:0] [00hex ... 7Fhex]/[00hex ... 7Fhex] 00/00hex 42
Micronas 21
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Table 3–5: List of MSP 44x0G write registers, continued
Write Register Address Bits Description and Adjustable Range Reset See
(hex) Page
Prescale I2S1 00 16 [15:8] [00hex ... 7Fhex] 10hex 31
Mode tone control 00 20 [15:8] [BASS/TREBLE, EQUALIZER] BASS/TREB 35
Equalizer loudspeaker ch. band 1 00 21 [15:8] [+12 dB ... −12 dB] 0 dB 36
Automatic Volume Correction 00 29 [15:8] [off, on, decay time] off 34
Subwoofer level adjust 00 2C [15:8] [+12 dB ... −30 dB, mute] 0 dB 39
Subwoofer source switch [7:0] [INTERNAL; EXTERNAL] 0 dB
Subwoofer corner frequency 00 2D [15:8] [50 Hz ... 400 Hz] 00hex 39
Subwoofer complementary high-pass [7:0] [off, on, MDB to Main] off
Balance headphone channel [L/R] 00 30 [15:8] [0...100 / 100% and 100 / 0...100%] in 0,8 % steps 100 %/100 % 34
[−127...0 / 0 and 0 / −127...0 dB] in 1 dB steps
Balance mode headphone [7:0] [Linear mode / logarithmic mode] linear mode
Bass headphone channel 00 31 [15:8] [+20 dB ... −12 dB] 0 dB 35
Treble headphone channel 00 32 [15:8] [+15 dB ... −12 dB] 0 dB 36
Loudness headphone channel 00 33 [15:8] [0 dB ... +17 dB] 0 dB 37
Loudness filter characteristic [7:0] [NORMAL, SUPER_BASS] NORMAL
Volume SCART2 output channel 00 40 [15:8] [+12 dB ... −114 dB, MUTE] 00hex 41
2 2 2
SCART2 source select 00 41 [15:8] [FM, NICAM, SCART, I S1, I S2, I S3] FM 32
SCART2 channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 32
MDB Effect Strength 00 68 [15:8] [0 dB ... 127 dB, off] off 39
MDB Amplitude Limit 00 69 [15:8] [0 dBFS... –32 dBFS] 0 dBFS 40
MDB Harmonic Content 00 6A [15:8] [0% ... 100%] 0% 40
MDB Low Pass Corner Frequency 00 6B [15:8] [50 Hz ... 300 Hz] 0 Hz 40
MDB High Pass Corner Frequency 00 6C [15:8] [20 Hz ... 300 Hz] 0 Hz 40
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Table 3–6: List of MSP 44x0G read registers
Read Register Address Bits Description and Adjustable Range See

(hex) Page
I2C Subaddress = 11hex ; Registers are not writable
STANDARD RESULT 00 7E [15:0] Result of Automatic Standard Detection (see Table 3–8 on page 26) 29
STATUS 02 00 [15:0] Monitoring of internal settings e.g. Stereo, Mono, Mute etc. . 29
I2C Subaddress = 13hex ; Registers are not writable
Quasi peak readout left 00 19 [15:0] [00hex ... 7FFFhex]16 bit two’s complement 43
Quasi peak readout right 00 1A [15:0] [00hex ... 7FFFhex]16 bit two’s complement 43
MSP hardware version code 00 1E [15:8] [00hex ... FFhex] 43
MSP familiy code [7:4] [00hex ... FFhex]
MSP major revision code [3:0] [00hex ... FFhex]
MSP product code 00 1F [15:8] [00hex ... FFhex] 43
MSP ROM version code [7:0] [00hex ... FFhex]
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3.3.2. Description of User Registers
Table 3–7: Standard codes for STANDARD SELECT Register
MSP Standard Code TV Sound Standard Sound Carrier MSP 44x0G Version
(Data in hex) Frequencies in MHz
Automatic Standard Detection
00 01 Start Automatic Standard Detection and all

sets detected standards
Standard Selection
00 02 M-Dual FM-Stereo 4.5/4.724212 3400, -10, -20, -40, -50
00 03 B/G -Dual FM-Stereo1) 5.5/5.7421875 3400, -10, -50
00 04 D/K1-Dual FM-Stereo2) 6.5/6.2578125
00 05 D/K2-Dual FM-Stereo2) 6.5/6.7421875

3)
00 06 D/K -FM-Mono with HDEV3 , not detectable by Automatic 6.5
Standard Detection,
HDEV33) SAT-Mono (i.e. Eutelsat, s. Table 6–18)
00 07 D/K3-Dual FM-Stereo 6.5/5.7421875

1)
00 08 B/G -NICAM-FM 5.5/5.85 3410, -50
00 09 L -NICAM-AM 6.5/5.85
00 0A I -NICAM-FM 6.0/6.552
00 0B D/K -NICAM-FM2) 6.5/5.85
00 0C D/K -NICAM-FM with HDEV24), not detectable by Automatic 6.5/5.85

Standard Detection, for China
00 0D D/K -NICAM-FM with HDEV33), not detectable by Automatic 6.5/5.85

Standard Detection, for China
00 20 BTSC-Stereo 4.5 3420, -40, -50
00 21 BTSC-Mono + SAP
00 30 M-EIA-J Japan Stereo 4.5
00 40 FM-Stereo Radio with 75 µs Deemphasis 10.7
00 50 SAT-Mono (s. Table 6–18) 6.5 3400, -10, -50
00 51 SAT-Stereo (s. Table 6–18) 7.02/7.20
00 60 SAT ADR (Astra Digital Radio) 6.12

1) In case of Automatic Sound Select, the B/G-codes 3hex and 8hex are equivalent.
2) In case of Automatic Sound Select, the D/K-codes 4hex, 5hex, 7hex and Bhex are equivalent.
3) HDEV3: Max. FM deviation must not exceed 540 kHz
4)
HDEV2: Max. FM deviation must not exceed 360 kHz
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3.3.2.1. STANDARD SELECT Register 3.3.2.2. Refresh of STANDARD SELECT Register
The TV sound standard of the MSP 44x0G demodula- A general refresh of the STANDARD SELECT register
tor is determined by the STANDARD SELECT register. is not allowed. However, the following method
There are two ways to use the STANDARD SELECT enables watching the MSP 44x0G “alive” status and
register: detection of accidental resets (only versions B6 and
later):
– Setting up the demodulator for a TV sound standard
by sending the corresponding standard code with a – After Power-on, bit[15] of CONTROL will be set; it
single I2C bus transmission. must be read once to enable the reset-detection
feature.
– Starting the Automatic Standard Detection for ter-
restrial TV standards. This is the most comfortable – Reading of the CONTROL register and checking
way to set up the demodulator. Within 0.5 s, the the reset indicator bit[15] .
detection and setup of the actual TV sound standard
– If bit[15] is “0”, any refresh of the STANDARD
is performed. The detected standard can be read
SELECT register is not allowed.
out of the STANDARD RESULT register by the con-
trol processor. This feature is recommended for the – If bit[15] is “1”, indicating a reset, a refresh of the
primary setup of a TV set. Outputs should be muted STANDARD SELECT register and all other MSPG
during Automatic Standard Detection. registers is required.
The Standard Codes are listed in Table 3–7.

3.3.2.3. STANDARD RESULT Register
Selecting a TV sound standard via the STANDARD
SELECT register initializes the demodulator. This If Automatic Standard Detection is selected in the
includes: AGC-settings and carrier mute, tuning fre- STANDARD SELECT register, status and result of the
quencies, FIR-filter settings, demodulation mode (FM, Automatic Standard Detection process can be read out
AM, NICAM), deemphasis and identification mode. of the STANDARD RESULT register. The possible
results are based on the mentioned Standard Code
TV stereo sound standards that are unavailable for a and are listed in Table 3–8.
specific MSP version are processed in analog mono
sound of the standard. In that case, stereo or bilingual In cases where no sound standard has been detected
processing will not be possible. (no standard present, too much noise, strong interfer-
ers, etc.) the STANDARD RESULT register contains
For a complete setup of the TV sound processing from 00 00hex. In that case, the controller has to start further
analog IF input to the source selection, the transmis- actions (for example set the standard according to a
sions as shown in Section 3.5. are necessary. preference list or by manual input).
For reasons of software compatibility to the As long as the STANDARD RESULT register contains
MSP 34xxD, a Manual/Compatibility mode is available. a value greater than 07 FFhex, the Automatic Standard
A detailed description of this mode can be found on Detection is still active. During this period, the MODUS
page 82. and STANDARD SELECT register must not be written.
The STATUS register will be updated when the Auto-
matic Standard Detection has finished.
If a present sound standard is unavailable for a spe-

cific MSP-version, it detects and switches to the ana-
log mono sound of this standard.
Example:
The MSPs 4420G and 4440G will detect a B/G-NICAM
signal as standard 3 and will switch to the analog FM-
Mono sound.
Micronas 25
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Table 3–8: Results of the Automatic Standard Detection
Broadcasted Sound STANDARD RESULT Register

Standard Read 007Ehex
Automatic Standard 0000hex

Detection could not
find a sound standard
B/G-FM 0003hex
B/G-NICAM 0008hex
I 000Ahex
FM-Radio 0040hex
M-Korea 0002hex (if MODUS[14,13]=00)

M-Japan
M-BTSC 0020hex (if MODUS[14,13]=01)
0030hex (if MODUS[14,13]=10)
L-AM 0009hex (if MODUS[12]=0)

D/K1
D/K2 0004hex (if MODUS[12]=1)
D/K3
L-NICAM 0009hex (if MODUS[12]=0)

D/K-NICAM
000Bhex (if MODUS[12]=1)
Automatic Standard >07FFhex

Detection still active
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3.3.2.4. Write Registers on I2C Subaddress 10hex
Table 3–9: Write registers on I2C subaddress 10hex
Register Function Name

Address
00 20hex STANDARD SELECTION Register STANDARD_SEL

Defines TV-Sound or FM-Radio Standard
bit[15:0] 00 01hex start Automatic Standard Detection
00 02hex MSP Standard Codes (see Table 3–7)
...
00 60hex
00 30hex MODUS Register MODUS

Preference in Automatic Standard Detection:
bit[15] 0 undefined, must be 0
bit[14:13] detected 4.5 MHz carrier is interpreted as:1)
0 standard M (Korea)
1 standard M (BTSC)
2 standard M (Japan)
3 chroma carrier (M/N standards are ignored)
bit[12] detected 6.5 MHz carrier is interpreted as:1)
0 standard L (SECAM)
1 standard D/K1, D/K2, D/K3, or D/K NICAM
General MSP 44x0G Options
bit[11:9] 0 undefined, must be 0
bit[8] 0/1 ANA_IN1+/ANA_IN2+; select analog sound IF input pin
bit[7] 0/1 active/tristate state of audio clock output pin
AUD_CL_OUT
bit[6] I2S word strobe alignment
0 WS changes at data word boundary
1 WS changes one clock cycle in advance
bit[5] 0/1 master/slave mode of I2S interface (must be set to 0
(= Master) in case of NICAM mode)
bit[4] 0/1 active/tristate state of I2S output pins:
I2S_CL, I2S_WS, I2S_DA_OUT
bit[3] state of digital output pins D_CTR_I/O_0 and _1
0 active: D_CTR_I/O_0 and _1 are output pins
(can be set by means of the ACB register.
see also: MODUS[1])
1 tristate: D_CTR_I/O_0 and _1 are input pins
(level can be read out of STATUS[4,3])
bit[2] 0 undefined, must be 0
bit[1] 0/1 disable/enable STATUS change indication by means of
the digital I/O pin D_CTR_I/O_1
Necessary condition: MODUS[3] = 0 (active)
bit[0] 0/1 off/on: Automatic Sound Select
1)
Valid at the next start of Automatic Standard Detection.
Micronas 27
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Table 3–9: Write registers on I2C subaddress 10hex, continued

Address
00 40hex I2S CONFIGURATION Register I2S_CONFIG

bit[15:12] 0 not used, must be set to “0”
I2S31)
bit[11] I2S3 data alignment (must be 0 if bit[2] = 1) I2S3_ALIGN
0/1 left/right aligned
bit[10] I2S3 word strobe polarity (must be 0 if bit[2] = 1) I2S3_WS_POL
1 0 = right, 1 = left
0 1 = right, 0 = left
bit[9] I2S3 word strobe alignment I2S3_WS_MODE
0 WS changes at data word boundary
1 WS changes one clock cycle in advance
bit[8] I2S3 Sample Mode I2S3_MSAMP
0/1 Two/Multi sample
bit[7:4] I2S3 Word length of each Data packet = (n−2)/2, n = 16...32 bit I2S3_MBIT
bit[3]=0, bit[8]=1 (multi-sample input mode)
0111 16 bit
1000 18 bit
...
1111 32 bit
bit[3]=0, bit[8]=0 (two-sample input mode)
xxxx 16...32 bit, 18-bit valid
bit[3]=1, bit[8]=1 (multi-sample output mode)
1111 32 bit
bit[3]=1, bit[8]=0 (two-sample output mode)
0111 16 bit
1111 32 bit
bit[3] I2S3 CL/WS Mode I2S3_MODE
1 I2S3 CL/WS active
0 I2S3 CL/WS tristate
I2S1/2/3
I2S_TIMING
bit[2] I2S1/2/3 Timing
1 I2S3 timing for all I2S inputs (1/2/3)
0 default mode
I2S Out
bit[1:0] 00 2 * 16 Bit (1.536 MHz Clk)
01 2 * 32 Bit (3.072 MHz Clk)
1x 8 * 32 Bit (12.288 MHz Clk)
1)
I2S_CL3 frequency depends on bit[8] and bits[7:4] as follows:
[8] = 0, [7:4] = 0111 f = fs*(2*16)
[8] = 0, [7:4] = 1xxx f = fs*(2*32)
[8] = 1, [7:4] = xxxx f = fs*(8*32)
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3.3.2.5. Read Registers on I2C Subaddress 11hex
Table 3–10: Read registers on I2C subaddress 11hex

Address
00 7Ehex STANDARD RESULT Register STANDARD_RES

Readback of the detected TV sound or FM-Radio Standard
bit[15:0] 00 00hex Automatic Standard Detection could not find
a sound standard
00 02hex MSP Standard Codes (see Table 3–8 on page 26)
...
00 40hex
>07 FFhex Automatic Standard Detection still active
02 00hex STATUS Register STATUS

Contains all user relevant internal information about the status of the MSP
bit[15:10] undefined
bit[8] 0/1 “1” indicates bilingual sound mode or SAP present
(internally evaluated from received analog or digital
identification signals)
bit[7] 0/1 “1” indicates independent mono sound (only for
NICAM)
bit[6] 0/1 mono/stereo indication
(internally evaluated from received analog or digital
identification signals)
bit[5,9] 00 analog sound standard (FM or AM) active
01 this pattern will not occur
10 digital sound (NICAM) available
11 bad reception condition of digital sound (NICAM) due
to:
a. high error rate
b. unimplemented sound code
c. data transmission only
bit[4] 0/1 low/high level of digital I/O pin D_CTR_I/O_1
bit[3] 0/1 low/high level of digital I/O pin D_CTR_I/O_0
bit[2] 0 detected secondary carrier (2nd A2 or SAP sub-carrier)
1 no secondary carrier detected
bit[1] 0 detected primary carrier (Mono or MPX carrier)
1 no primary carrier detected
bit[0] undefined
If STATUS change indication is activated by means of MODUS[1]: Each
change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high
level. Reading the STATUS register resets D_CTR_I/O_1.
Micronas 29
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3.3.2.6. Write Registers on I2C Subaddress 12hex
Table 3–11: Write registers on I2C subaddress 12hex

Address
PREPROCESSING
00 0Ehex FM/AM Prescale PRE_FM

bit[15:8] 00hex Defines the input prescale gain for the demodulated
... FM or AM signal
7Fhex
00hex off (RESET condition)
For all FM modes except satellite FM and AM-mode, the combinations of pres-
cale value and FM deviation listed below lead to internal full scale.
FM mode
bit[15:8] 7Fhex 28 kHz FM deviation
48hex 50 kHz FM deviation
13hex 180 kHz FM deviation (limit)
FM high deviation mode (HDEV2, MSP Standard Code = Chex)
bit[15:8] 30hex 150 kHz FM deviation
14hex 360 kHz FM deviation (limit)
FM very high deviation mode (HDEV3, MSP Standard Code = 6 and Dhex)
bit[15:8] 20hex 450 kHz FM deviation
1Ahex 540 kHz FM deviation (limit)
Satellite FM with adaptive deemphasis
bit[15:8] 10hex recommendation
AM mode (MSP Standard Code = 9)
bit[15:8] 7Chex recommendation for SIF input levels from
0.1 Vpp to 0.8 Vpp
(Due to the AGC being switched on, the AM-output level

remains stable and independent of the actual SIF-level in
the mentioned input range)
30 Micronas
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Address
(continued) FM Matrix Modes FM_MATRIX

Defines the dematrix function for the demodulated FM signal
00 0Ehex
bit[7:0] 00hex no matrix (used for bilingual and unmatrixed stereo sound)
01hex German stereo (Standard B/G)
02hex Korean stereo (also used for BTSC, EIA-J and FM Radio)
03hex sound A mono (left and right channel contain the mono
sound of the FM/AM mono carrier)
04hex sound B mono
In case of Automatic Sound Select = on, the FM Matrix Mode is set automati-
cally. Writing to the FM/AM prescale register (00 0Ehex high part) is still allowed.
In order not to disturb the automatic process, the low part of any I2C transmis-
sion to this register is ignored. Therefore, any FM-Matrix readback values may
differ from data written previously.
In case of Automatic Sound Select = off, the FM Matrix Mode must be set as
shown in Table 6–17 of Appendix B.
To enable a Forced Mono Mode set A2 THRESHOLD as described in
Section 6.3.2.on page 86
00 10hex NICAM Prescale PRE_NICAM

Defines the input prescale value for the digital NICAM signal
bit[15:8] 00hex ... 7Fhex prescale gain
examples:
00hex off
20hex 0 dB gain
5Ahex 9 dB gain (recommendation)
7Fhex +12 dB gain (maximum gain)
00 16hex I2S1 Prescale PRE_I2S1

Defines the input prescale value for digital I2S input signals
examples:
00hex off
10hex 0 dB gain (recommendation)
7Fhex +18 dB gain (maximum gain)
00 0Dhex SCART Input Prescale PRE_SCART

Defines the input prescale value for the analog SCART input signal
examples:
00hex off
19hex 0 dB gain (2 VRMS input leads to digital full scale)
7Fhex +14 dB gain (400 mVRMS input leads to digital full scale)
Micronas 31
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Address
SOURCE SELECT AND OUTPUT CHANNEL MATRIX
Source for:
00 08hex Loudspeaker Output
00 09hex Headphone Output
00 0Ahex SCART1 DA Output
00 41hex SCART2 DA Output
00 0Bhex I2S Output
00 0Chex Quasi-Peak Detector
bit[15:8] 00hex “FM/AM”: demodulated FM or AM mono signal

01hex “Stereo or A/B”: demodulator Stereo or A/B signal
(in manual mode, this source is identical to the NICAM
source in the MSP 3410D)
03hex “Stereo or A”: demodulator Stereo Sound or
Language A (only defined for Automatic Sound Select)
04hex “Stereo or B”: demodulator Stereo Sound or
Language B (only defined for Automatic Sound Select)
02hex SCART input
05hex I2S1 input
06hex I2S2 input
07hex I2S3 input channels 1 and 2 (e.g. Lt, Rt)1)
08hex I2S3 input channels 3 and 4 (e.g. L, R)1)
09hex I2S3 input channels 5 and 6 (e.g. SL, SR)1)
0Ahex I2S3 input channels 7 and 8 (e.g. C, SUB)1)
For demodulator sources, seeTable 2–2.
Matrix Mode for:

00 08hex Loudspeaker Output MAT_MAIN
00 09hex Headphone Output MAT_AUX
00 0Ahex SCART1 DA Output MAT_SCART1
00 41hex SCART2 DA Output MAT_SCART2
00 0Bhex I2S Output MAT_I2S
00 0Chex Quasi-Peak Detector MAT_QPEAK
bit[7:0] 00hex Sound A Mono (or Left Mono)

10hex Sound B Mono (or Right Mono)
20hex Stereo (transparent mode)
30hex Mono (sum of left and right inputs divided by 2)
special modes are available (see Section 6.5.1. on page 94)
In Automatic Sound Select mode, the demodulator source channels are set
according to Table 2–2. Therefore, the matrix modes of the corresponding out-
put channels should be set to “Stereo” (transparent).
1)
Exemplary channel assignment in a Micronas digital multichannel sound system with MAS 3528E and
DPL 4519G.
32 Micronas
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Address
LOUDSPEAKER AND HEADPHONE PROCESSING
00 00hex Volume Loudspeaker VOL_MAIN

00 06hex Volume Headphone VOL_AUX
bit[15:8] volume table with 1 dB step size
7Fhex +12 dB (maximum volume)
7Ehex +11 dB
...
74hex +1 dB
73hex 0 dB
72hex −1 dB
...
02hex −113 dB
01hex −114 dB
00hex Mute (reset condition)
FFhex Fast Mute (needs about 75 ms until the signal is
completely ramped down)
bit[7:5] higher resolution volume table
0 +0 dB
1 +0.125 dB increase in addition to the volume table
...
bit[4] 0 must be set to 0
bit[3:0] clipping mode
0 reduce volume
1 reduce tone control
2 compromise
3 dynamic
With large scale input signals, positive volume settings may lead to signal clip-
ping.
The MSP 44x0G loudspeaker and headphone volume function is divided into a
digital and an analog section. With Fast Mute, volume is reduced to mute posi-
tion by digital volume only. Analog volume is not changed. This reduces any
audible DC plops. To turn volume on again, the volume step that has been used
before Fast Mute was activated must be transmitted.
If the clipping mode is set to “reduce volume”, the following rule is used: To pre-
vent severe clipping effects with bass, treble, or equalizer boosts, the internal
volume is automatically limited to a level where, in combination with either bass,
treble, or equalizer setting, the amplification does not exceed 12 dB.
If the clipping mode is “reduce tone control”, the bass or treble value is
reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain
of those bands is reduced, where amplification together with volume exceeds
12 dB.
If the clipping mode is “compromise”, the bass or treble value and volume are
reduced half and half if amplification exceeds 12 dB. If the equalizer is switched
on, the gain of those bands is reduced half and half, where amplification
together with volume exceeds 12 dB.
If the clipping mode is “dynamic”, volume is reduced automatically if the signal
amplitudes would exceed −2 dBFS within the IC. For operation of MDB, dyna-
mic mode must be switched on.
Micronas 33
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Address
00 29hex Automatic Volume Correction (AVC) Loudspeaker Channel AVC

bit[15:12] 00hex AVC off (and reset internal variables)
08hex AVC on
bit[11:8] 08hex 8 sec decay time
04hex 4 sec decay time
02hex 2 sec decay time
01hex 20 ms decay time (should be used for approx. 100 ms
after channel change)
Note: AVC should not be used in any Dolby Prologic mode (with DPL 35xx),
except in PANORAMA or 3D-PANORAMA mode, when only the loudspeaker
output is active.
00 01hex Balance Loudspeaker Channel BAL_MAIN

00 30hex Balance Headphone Channel BAL_AUX
bit[15:8] Linear Mode
7Fhex Left muted, Right 100%
7Ehex Left 0.8%, Right 100%
...
01hex Left 99.2%, Right 100%
00hex Left 100%, Right 100%
FFhex Left 100%, Right 99.2%
...
82hex Left 100%, Right 0.8%
81hex Left 100%, Right muted
bit[15:8] Logarithmic Mode
7Fhex Left −127 dB, Right 0 dB
7Ehex Left −126 dB, Right 0 dB
...
01hex Left −1 dB, Right 0 dB
00hex Left 0 dB, Right 0 dB
FFhex Left 0 dB, Right −1 dB
...
81hex Left 0 dB, Right −127 dB
80hex Left 0 dB, Right −128 dB
bit[7:0] Balance Mode
00hex linear
01hex logarithmic
Positive balance settings reduce the left channel without affecting the right
channel; negative settings reduce the right channel leaving the left channel
unaffected.
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Address
00 20hex Tone Control Mode Loudspeaker Channel TONE_MODE

bit[15:8] 00hex bass and treble is active
FFhex equalizer is active
Defines whether Bass/Treble or Equalizer is activated for the loudspeaker chan-
nel. Bass and Equalizer cannot work simultaneously. If Equalizer is used, Bass,
and Treble coefficients must be set to zero and vice versa.
00 02hex Bass Loudspeaker Channel BASS_MAIN

00 31hex Bass Headphone Channel BASS_AUX
bit[15:8] extended range
7Fhex +20 dB
78hex +18 dB
70hex +16 dB
68hex +14 dB
normal range
60hex +12 dB
58hex +11 dB
...
08hex +1 dB
00hex 0 dB
F8hex −1 dB
...
A8hex −11 dB
A0hex −12 dB
Higher resolution is possible: an LSB step in the normal range results in a gain
step of about 1/8 dB, in the extended range about 1/4 dB.
With positive bass settings, internal clipping may occur even with overall volume
less than 0 dB. This will lead to a clipped output signal. Therefore, it is not rec-
ommended to set bass to a value that, in conjunction with volume, would result
in an overall positive gain.
Micronas 35
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Address
00 03hex Treble Loudspeaker Channel TREB_MAIN

00 32hex Treble Headphone Channel TREB_AUX
bit[15:8] 78hex +15 dB
70hex +14 dB
...
08hex +1 dB
00hex 0 dB
F8hex −1 dB
...
A8hex −11 dB
A0hex −12 dB
Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB.
With positive treble settings, internal clipping may occur even with overall vol-
ume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not
recommended to set treble to a value that, in conjunction with volume, would
result in an overall positive gain.
00 21hex Equalizer Loudspeaker Channel Band 1 (below 120 Hz) EQUAL_BAND1

00 22hex Equalizer Loudspeaker Channel Band 2 (center: 500 Hz) EQUAL_BAND2
00 23hex Equalizer Loudspeaker Channel Band 3 (center: 1.5 kHz) EQUAL_BAND3
00 24hex Equalizer Loudspeaker Channel Band 4 (center: 5 kHz) EQUAL_BAND4
00 25hex Equalizer Loudspeaker Channel Band 5 (above: 10 kHz) EQUAL_BAND5
bit[15:8] 60hex +12 dB
58hex +11 dB
...
08hex +1 dB
00hex 0 dB
F8hex −1 dB
...
A8hex −11 dB
A0hex −12 dB
Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB.
With positive equalizer settings, internal clipping may occur even with overall
volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is
not recommended to set equalizer bands to a value that, in conjunction with vol-
ume, would result in an overall positive gain.
36 Micronas
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Address
00 04hex Loudness Loudspeaker Channel LOUD_MAIN

00 33hex Loudness Headphone Channel LOUD_AUX
bit[15:8] Loudness Gain
44hex +17 dB
40hex +16 dB
...
04hex +1 dB
03hex +0.75 dB
02hex +0.5 dB
01hex +0.25 dB
00hex 0 dB
bit[7:0] Loudness Mode
00hex normal (constant volume at 1 kHz)
04hex Super Bass (constant volume at 2 kHz)
Higher resolution of Loudness Gain is possible: An LSB step results in a gain
step of about 1/4 dB.
Loudness increases the volume of low- and high-frequency signals, while keep-
ing the amplitude of the reference frequency constant. The intended loudness
has to be set according to the actual volume setting. Because loudness intro-
duces gain, it is not recommended to set loudness to a value that, in conjunction
with volume, would result in an overall positive gain.
The corner frequency for bass amplification can be set to two different values. In
Super Bass mode, the corner frequency is shifted up. The point of constant vol-
ume is shifted from 1 kHz to 2 kHz.
Micronas 37
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Address
00 05hex Spatial Effects Loudspeaker Channel SPAT_MAIN

bit[15:8] Effect Strength
7Fhex Enlargement 100%
3Fhex Enlargement 50%
...
01hex Enlargement 0.78%
00hex Effect off
FFhex reduction 0.78%
...
C0hex reduction 50%
80hex reduction 100%
bit[7:4] Spatial Effect Mode
0hex Stereo Basewidth Enlargement (SBE) and
Pseudo Stereo Effect (PSE). (Mode A)
2hex Stereo Basewidth Enlargement (SBE) only. (Mode B)
bit[3:0] Spatial Effect High-Pass Gain
0hex max. high-pass gain
2hex 2/3 high-pass gain
4hex 1/3 high-pass gain
6hex min. high-pass gain
8hex automatic
There are several spatial effect modes available:
In mode A (low byte = 00hex), the spatial effect depends on the source mode. If
the incoming signal is mono, Pseudo Stereo Effect is active; for stereo signals,
Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The
strength of the effect is controllable by the upper byte. A negative value reduces
the stereo image. A strong spatial effect is recommended for small TV sets
where loudspeaker spacing is rather close. For large screen TV sets, a more
moderate spatial effect is recommended.
In mode B, only Stereo Basewidth Enlargement is effective. For mono input sig-
nals, the Pseudo Stereo Effect has to be switched on.
It is worth mentioning, that all spatial effects affect amplitude and phase
response. With the lower 4 bits, the frequency response can be customized. A
value of 0hex yields a flat response for center signals (L = R), but a high-pass
function for L or R only signals. A value of 6hex has a flat response for L or R
only signals, but a low-pass function for center signals. By using 8hex, the fre-
quency response is automatically adapted to the sound material by choosing an
optimal high-pass gain.
38 Micronas
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Address
SUBWOOFER OUTPUT CHANNEL
00 2Chex Subwoofer Level Adjustment

bit[15:8] Subwoofer Level Adjustment SUBW_LEVEL
0Chex +12 dB
...
01hex +1 dB
00hex 0 dB
FFhex −1 dB
...
E3hex −29 dB
E2hex −30 dB
...
80hex Mute
bit[7:0] Subwoofer Source Switch SUBW_SRC

00hex The output pin DACM_SUB is driven by the internally
computed subwoofer signal (Lowpass signal of (L+R)/2).
01hex The output pin DACM_SUB is driven by the I2S3 input
channel 8 (which is the right channel of source select
address 10. In a Micronas digital multichannel sound envi-
ronment, this is the subwoofer signal).
00 2Dhex Subwoofer Corner Frequency SUBW_FREQ

bit[15:8] 5...40dec corner frequency in 10 Hz steps
(range: 50...400 Hz)
If MDB is active, SUBW_FREQ must be set to a value higher than the MDB Lowpass
Frequency (MDB_LP). Choosing the corner frequency of the subwoofer closer to
MDB_LP results in a narrower MDB frequency range. Recommended value:
1.5×MDB_LP
Subwoofer Complementary High-Pass Filter SUBW_HP
bit[7:0] 00hex loudspeaker channel unfiltered

01hex a complementary high-pass is processed in the loud-
speaker output channel
02hex MDB added onto main channel
MDB CONTROL REGISTERS
00 68hex MDB Effect Strength MDB_STR

bit[15:8] 00hex MDB OFF (default)
7Fhex maximum MDB
bit[7:0] 00hex must be zero
The MDB effect strength can be adjusted in 1dB steps. A value of 44hex will yield
a medium MDB effect.
Micronas 39
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Address
00 69hex MDB Amplitude Limit MDB_LIM

bit[15:8] 00hex 0 dBFS (default limitation)
FFhex −1 dBFS
...
E0hex −32 dBFS
The MDB Amplitude Limit defines the maximum allowed amplitude at the output
of the MDB relative to 0 dbFS. If the amplitude exceeds MDB_LIM, the gain of
the MDB is automatically reduced. Note that the Volume Clipping Mode must be
set to “dynamic” (see page 33).
00 6Ahex MDB Harmonic Content MDB_HMC

bit[15:8] 00hex no harmonics are added (default)
3Fhex 50% fundamentals + 50% harmonics
7Fhex 100% harmonics
MDB creates harmonics of the frequencies below the MDB highpass frequency
(MDB_HP). The variable MDB_HMC describes the ratio of the harmonics
towards the original signal.
00 6Bhex MDB Low Pass Corner Frequency MDB_LP

bit[15:8] 5dec 50 Hz
6dec 60 Hz
...
30dec 300 Hz
The MDB lowpass corner frequency (range 50...300 Hz) defines the upper cor-
ner frequency of the MDB bandpass filter. Recommended values are the same
as for the MDB highpass corner frequency (MDB_HP).
00 6Chex MDB High Pass Corner Frequency MDB_HP

bit[15:8] 2dec 20 Hz
3dec 30 Hz
...
30dec 300 Hz
The MDB highpass corner frequency defines the lower corner frequency of the
MDB bandpass filter. The highpass filter avoids loading the loudspeakers with
low frequency components that are below the speakers’ cut off frequency. Rec-
ommended values for subwoofer systems are around 5 (=50 Hz), for regular TV
sets around 10 (=100 Hz).
40 Micronas
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Address
SCART OUTPUT CHANNEL
00 07hex Volume SCART1 Output Channel VOL_SCART1

00 40hex Volume SCART2 Output Channel VOL_SCART2
bit[15:8] volume table with 1 dB step size
7Fhex +12 dB (maximum volume)
7Ehex +11 dB
...
74hex +1 dB
73hex 0 dB
72hex −1 dB
...
02hex −113 dB
01hex −114 dB
00hex Mute (reset condition)
bit[7:5] higher resolution volume table
0 +0 dB
...
bit[4:0] 01hex this must be 01hex
Micronas 41
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Address
SCART SWITCHES AND DIGITAL I/O PINS
00 13hex ACB Register ACB_REG

Defines the level of the digital output pins and the position of the SCART
switches
bit[15] 0/1 low/high of digital output pin D_CTR_I/O_1
(MODUS[3]=0)
bit[14] 0/1 low/high of digital output pin D_CTR_I/O_0
(MODUS[3]=0)
bit[13:5] SCART DSP Input Select
xxxx00xx0 SCART1 to DSP input (RESET position)
xxxx01xx0 MONO to DSP input (Set Sound A Mono in the channel
matrix mode for the corresponding output channels)
xxxx10xx0 SCART2 to DSP input
xxxx11xx1 mute DSP input
bit[13:5] SCART1 Output Select
xx00xxx0x SCART3 input to SCART1 output (RESET position)
xx01xxx0x SCART2 input to SCART1 output
xx10xxx0x MONO input to SCART1 output
xx11xxx0x SCART1 DA to SCART1 output
xx00xxx1x SCART2 DA to SCART1 output
xx11xxx1x mute SCART1 output
bit[13:5] SCART2 Output Select
00xxxx0xx SCART1 DA to SCART2 output (RESET position)
01xxxx0xx SCART1 input to SCART2 output
10xxxx0xx MONO input to SCART2 output
00xxxx1xx SCART2 DA to SCART2 output
11xxxx0xx mute SCART2 output
bit[4:0] must be zero
The RESET position becomes active at the time of the first write transmission
on the control bus to the audio processing part. By writing to the ACB register
first, the RESET state can be redefined.
BEEPER
00 14hex Beeper Volume and Frequency BEEPER

bit[15:8] Beeper Volume
00hex off
7Fhex maximum volume
bit[7:0] Beeper Frequency
01hex 16 Hz (lowest)
40hex 1 kHz
FFhex 4 kHz
42 Micronas
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3.3.2.7. Read Registers on I2C Subaddress 13hex
Table 3–12: Read registers on I2C subaddress 13hex

Address
QUASI-PEAK DETECTOR READOUT
00 19hex Quasi-Peak Detector Readout Left QPEAK_L

00 1Ahex Quasi-Peak Detector Readout Right QPEAK_R
bit[15:0] 0hex... 7FFFhex values are 16 bit two’s complement (only positive)
MSP 44x0G VERSION READOUT REGISTERS
00 1Ehex MSP Hardware Version Code MSP_HARD

bit[15:8] 02hex MSP 44x0G - B8
A change in the hardware version code defines hardware optimizations that
may have influence on the chip’s behavior. The readout of this register is iden-
tical to the hardware version code in the chip’s imprint.
MSP Family Code MSP_FAMILY

MSP Major Revision Code MSP_REVISION

00 1Fhex MSP Product Code MSP_PRODUCT

bit[15:8] 0Ahex MSP 4410G - B8
14hex MSP 4420G - B8
By means of the MSP-Product Code, the control processor is able to decide
which TV sound standards have to be considered.
MSP ROM Version Code MSP_ROM

A change in the ROM version code defines internal software optimizations,
that may have influence on the chip’s behavior, e.g. new features may have
been included. While a software change is intended to create no compatibility
problems, customers that want to use the new functions can identify new
MSP 44x0G versions according to this number.
To avoid compatibility problems with MSP 3410B and MSP 34x0D, an offset of
40hex is added to the ROM version code of the chip’s imprint.
Micronas 43
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3.4. Programming Tips 3.5. Examples of Minimum Initialization Codes
This section describes the preferred method for initial- Initialization of the MSP 44x0G according to these list-
izing the MSP 44x0G. The initialization is grouped into ings reproduces sound of the selected standard on the
four sections: loudspeaker output. All numbers are hexadecimal. The
examples have the following structure:
– SCART Signal Path (analog signal path)
1. Perform an I2C controlled reset of the IC.
– Demodulator
2. Write MODUS register
– SCART and I2S Inputs
(with Automatic Sound Select).
– Output Channels
3. Set Source Selection for loudspeaker channel
(with matrix set to STEREO).
See Fig. 2–1 on page 10 for a complete signal flow.
4. Set Prescale
(FM and/or NICAM and dummy FM matrix).
SCART Signal Path
5. Write STANDARD SELECT register.
1. Select analog input for the SCART baseband pro-
6. Set Volume loudspeaker channel to 0 dB.
cessing (SCART DSP Input Select) by means of the
ACB register.
2. Select the source for each analog SCART output 3.5.1. B/G-FM (A2 or NICAM)
(SCART Output Select) by means of the ACB regis- <80 00 80 00> // Softreset
ter. <80 00 00 00>
<80 10 00 30 20 03> // MODUS-Register: Automatic = on
<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St
Demodulator
<80 12 00 0E 24 03> // FM/AM-Prescale = 24hex,
FM-Matrix = MONO/SOUNDA
For a complete setup of the TV sound processing from
analog IF input to the source selection, the following <80 12 00 10 5A 00> // NICAM-Prescale = 5Ahex
steps must be performed: <80 10 00 20 00 03> // Standard Select: A2 B/G or NICAM B/G
or
1. Set MODUS register to the preferred mode and <80 10 00 20 00 08>
Sound IF input. <80 12 00 00 73 00> // Loudspeaker Volume 0 dB
2. Choose preferred prescale (FM and NICAM) values.

3. Write STANDARD SELECT register. 3.5.2. BTSC-Stereo
<80 00 80 00> // Softreset
4. If Automatic Sound Select is not active:
Choose FM matrix repeatedly according to the <80 00 00 00>
sound mode indicated in the STATUS register. <80 10 00 30 20 03> // MODUS-Register: Automatic = on
SCART and I2S Inputs FM-Matrix = Sound A Mono
<80 10 00 20 00 20> // Standard Select: BTSC-STEREO
1. Select preferred prescale for SCART.
<80 12 00 00 73 00> // Loudspeaker Volume 0 dB
2. Select preferred prescale for I2S inputs
(set to 0 dB after RESET).
3.5.3. BTSC-SAP with SAP at Loudspeaker Channel
<80 00 80 00> // Softreset
Output Channels <80 00 00 00>
1. Select the source channel and matrix for each out- <80 10 00 30 20 03> // MODUS-Register: Automatic = on
put channel. <80 12 00 08 04 20> // Source Sel. = (St or B) & Ch. Matr. = St
2. Set audio baseband processing. <80 12 00 0E 24 03> // FM/AM-Prescale = 24hex,

FM-Matrix = Sound A Mono
3. Select volume for each output channel. <80 10 00 20 00 21> // Standard Select: BTSC-SAP
44 Micronas
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3.5.4. FM-Stereo Radio

<80 00 80 00> // Softreset
<80 00 00 00>
<80 10 00 20 00 40> // Standard Select: FM-STEREO-RADIO
3.5.5. Automatic Standard Detection
A detailed software flow diagram is shown in Fig. 3–1

on page 46.
<80 00 80 00> // Softreset
<80 00 00 00>
<80 12 00 10 5A 00> // NICAM-Prescale = 5Ahex
<80 10 00 20 00 01> // Standard Select:
Automatic Standard Detection
// Wait till STANDARD RESULT contains a value ≤ 07FF
// IF STANDARD RESULT contains 0000
// do some error handling
// ELSE
3.5.6. SCART1 Input to Loudspeaker in Stereo

Sound
<80 00 80 00> // reset
<80 00 00 00>
<80 12 00 08 02 20> // source loudspeaker = scart, stereo
<80 12 00 0d 19 00> // prescale scart
<80 12 00 00 73 00> // volume main = 0dB
3.5.7. Software Flow for Interrupt driven STATUS

Check
A detailed software flow diagram is shown in Fig. 3–1

on page 46.
If the D_CTR_I/O_1 pin of the MSP 44x0G is con-

nected to an interrupt input pin of the controller, the fol-
lowing interrupt handler can be applied to be automati-
cally called with each status change of the
MSP 44x0G. The interrupt handler may adjust the TV
display according to the new status information.
Interrupt Handler:
<80 11 02 00 <81 dd dd> // Read STATUS
// adjust TV display with given status information
// Return from Interrupt
Micronas 45
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Write MODUS Register:

Example for the essential bits:
[0] = 1 Automatic Sound Select = on
[1] = 1 Enable interrupt if STATUS changes
[8] = 0 ANA_IN1+ is selected
Define Preference for Automatic Standard
Detection:
[12] = 0 If 6.5 MHz, set SECAM-L
[14:13] = 3 Ignore 4.5 MHz carrier
Write SOURCE SELECT Settings

Example:
set loudspeaker Source Select to "Stereo or A"
set headphone Source Select to "Stereo or B"
set SCART_Out Source Select to "Stereo or A/B"
set Channel Matrix mode for all outputs to "Stereo"
Write FM/AM-Prescale
Write NICAM-Prescale
Write 01 into
STANDARD SELECT Register
(Start Automatic Standard Detection)
set previous standard or

Result = 0
set standard manually according yes
?
picture information
no
expecting MSPG-interrupt
In case of MSPG-
Interrupt to Controller: Read STATUS
Adjust TV-Display
If Bilingual, adjust Source Select setting if required
Fig. 3–1: Software flow diagram for a minimum demodulator setup for a European Multistandard TV set applying the
Automatic Sound Select feature
46 Micronas
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4. Specifications
4.1. Outline Dimensions
23 x 0.8 = 18.4 ± 0.1

0.17 ± 0.04 0.8
64 41
65 40
15 x 0.8 = 12.0 ± 0.1

0.8
17.2 ± 0.15
0.37 ± 0.04
14 ± 0.1
80 25
1.3 ± 0.05
1 24
2.7 ± 0.1
23.2 ± 0.15 0.1 20 ± 0.1
3 ±0.2
SPGS705000-3(P80)/1E
Fig. 4–1:
80-Pin Plastic Quad Flat Pack
(PQFP80)
Weight approximately 1.61 g
Dimensions in mm
15 x 0.5 = 7.5 ± 0.1
0.145 ± 0.055 0.5
48 33
49 32
15 x 0.5 = 7.5 ± 0.1
0.5
10 ± 0.1
12 ± 0.2
0.22 ± 0.05
64 17
1.75
1 16
1.75 1.4 ± 0.05
12 ± 0.2 0.1 10 ± 0.1
1.5 ± 0.1
SPGS707000-1/1E
Fig. 4–2:
64-Pin Plastic Low-Profile Quad Flat Pack
(PLQFP64)
Dimensions in mm
Micronas 47
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SPGS703000-1(P64)/1E
64 33
1 32
19.3 ±0.1
3.8 ±0.1
57.7 ±0.1 18 ±0.05

0.8 ±0.2
0.28 ±0.06
3.2 ±0.2
1 ±0.05 20.3 ±0.5

1.778 0.48 ±0.06
31 x 1.778 = 55.1 ±0.1
Fig. 4–3:
64-Pin Plastic Shrink Dual-Inline Package
(PSDIP64)
Dimensions in mm
4.2. Pin Connections and Short Descriptions
NC = not connected; leave vacant

LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
DVSS: if not used, connect to DVSS
AHVSS: connect to AHVSS
Pin No. Pin Name Type Connection Short Description

PQFP PLQFP PSDIP (If not used)
80-pin 64-pin 64-pin
1 64 8 NC LV Not connected
2 1 9 I2C_CL IN/OUT X I2C clock
3 2 10 I2C_DA IN/OUT X I2C data
4 3 11 I2S_CL IN/OUT LV I2S clock
5 4 12 I2S_WS IN/OUT LV I2S word strobe
6 5 13 I2S_DA_OUT OUT LV I2S data output
7 6 14 I2S_DA_IN1 IN LV I2S1 data input
8 7 15 ADR_DA OUT LV ADR data output
9 8 16 ADR_WS OUT LV ADR word strobe
10 9 17 ADR_CL OUT LV ADR clock
11 − − DVSUP X Digital power supply 5 V
12 − − DVSUP X Digital power supply 5 V
48 Micronas
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13 10 18 DVSUP X Digital power supply 5 V
14 − − DVSS X Digital ground
15 − − DVSS X Digital ground
16 11 19 DVSS X Digital ground
− 12 20 I2S_DA_IN2/3 IN LV I2S2/3-data input
17 − − I2S_DA_IN2 IN LV PQFP80: pin 22 separate

I2S_DA_IN3
19 14 22 I2S_CL3 IN/OUT LV I2S3 clock
20 15 23 I2S_WS3 IN/OUT LV I2S3 word strobe
21 16 24 RESETQ IN X Power-on-reset
22 − − I2S_DA_IN3 IN LV I2S3-data input
23 − − NC LV Not connected
24 17 25 DACA_R OUT LV Headphone out, right
25 18 26 DACA_L OUT LV Headphone out, left
26 19 27 VREF2 X Reference ground 2
27 20 28 DACM_R OUT LV Loudspeaker out, right
28 21 29 DACM_L OUT LV Loudspeaker out, left
30 23 31 DACM_SUB OUT LV Subwoofer output
33 25 33 SC2_OUT_R OUT LV SCART output 2, right
34 26 34 SC2_OUT_L OUT LV SCART output 2, left
35 27 35 VREF1 X Reference ground 1
36 28 36 SC1_OUT_R OUT LV SCART output 1, right
37 29 37 SC1_OUT_L OUT LV SCART output 1, left
38 30 38 CAPL_A X Volume capacitor AUX
39 31 39 AHVSUP X Analog power supply 8 V
40 32 40 CAPL_M X Volume capacitor MAIN
Micronas 49
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43 − − AHVSS X Analog ground
44 33 41 AHVSS X Analog ground
45 34 42 AGNDC X Analog reference voltage
46 − − NC LV or AHVSS Not connected
47 35 43 SC4_IN_L IN LV SCART 4 input, left
48 36 44 SC4_IN_R IN LV SCART 4 input, right
49 37 45 ASG AHVSS Analog Shield Ground
59 46 54 VREFTOP X Reference voltage IF

A/D converter
60 47 55 MONO_IN IN LV Mono input
61 − − AVSS X Analog ground
62 48 56 AVSS X Analog ground
65 − − AVSUP X Analog power supply 5 V
66 49 57 AVSUP X Analog power supply 5 V
67 50 58 ANA_IN1+ IN LV IF input 1
68 51 59 ANA_IN− IN AVSS via IF common (can be left

56 pF / LV vacant only if IF input 1 is also
not in use)
69 52 60 ANA_IN2+ IN AVSS via IF input 2 (can be left vacant,

56 pF / LV only if IF input 1 is also not in
use)
70 53 61 TESTEN IN X Test pin
50 Micronas
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71 54 62 XTAL_IN IN X Crystal oscillator
72 55 63 XTAL_OUT OUT X Crystal oscillator
73 56 64 TP LV Test pin
74 57 1 AUD_CL_OUT OUT LV Audio clock output

(18.432 MHz)
77 60 4 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1
78 61 5 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0
79 62 6 ADR_SEL IN X I2C Bus address select
80 63 7 STANDBYQ IN X Stand-by (low-active)
4.3. Pin Descriptions ADR_WS – ADR Bus Word Strobe Output

(Fig. 4–19)
I2C_CL – I2C Clock Input/Output (Fig. 4–14) Word strobe output for the ADR bus.
Via this pin, the I2C-bus clock signal has to be sup-
plied. The signal can be pulled down by the MSP in ADR_CL – ADR Bus Clock Output (Fig. 4–19)
case of wait conditions. Clock line for the ADR bus.
I2C_DA – I2C Data Input/Output (Fig. 4–14) DVSUP* – Digital Supply Voltage
Via this pin, the I2C-bus data is written to or read from Power supply for the digital circuitry of the MSP. Must
the MSP. be connected to a +5 V power supply.
I2S_CL – I2S Clock Input/Output (Fig. 4–15) DVSS* – Digital Ground

Clock line for the I2S bus. In master mode, this line is Ground connection for the digital circuitry of the MSP.
driven by the MSP; in slave mode, an external I2S
clock has to be supplied. I2S_DA_IN2/3 – I2S Data Input (Fig. 4–11)
This pin is connected to the second data input of the
I2S_WS – I2S Word Strobe Input/Output (Fig. 4–15) synchronous I2S-bus interface (=I2S_DA_IN2) and in
Word strobe line for the I2S bus. In master mode, this parallel to the data input of the multichannel I2S-bus
line is driven by the MSP; in slave mode, an external interface (=I2S_DA_IN3). With source select, the
I2S word strobe has to be supplied. required input is chosen (not available for PQFP80
package).
I2S_DA_OUT – I2S Data Output (Fig. 4–19)
Output of digital serial sound data of the MSP on the I2S_DA_IN2 – I2S Data Input 2 (Fig. 4–11)
I2S bus. Second input of digital serial sound data to the MSP
via the I2S bus.
I2S_DA_IN1 – I2S Data Input 1 (Fig. 4–11)
First input of digital serial sound data to the MSP via I2S_CL3 – I2S Clock Input/Output (Fig. 4–15)
the I2S bus. Clock line for the asynchronous I2S bus. Since only a
slave mode is available an external I2S clock has to be
ADR_DA – ADR Bus Data Output (Fig. 4–19) supplied.
Output of digital serial data to the DRP 3510A via the
ADR bus.
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I2S_WS3 – I2S Word Strobe Input/Output (Fig. 4–15) CAPL_A – Volume Capacitor Headphone (Fig. 4–20)
Word strobe line for the asynchronous I2S bus. Since A 10-µF capacitor to AHVSUP must be connected to
only a slave mode is available an external I2S word this pin. It serves as a smoothing filter for headphone
strobe has to be supplied. volume changes in order to suppress audible plops.
The value of the capacitor can be lowered to 1-µF if
RESETQ – Reset Input (Fig. 4–7) faster response is required. The area encircled by the
In the steady state, high level is required. A low level trace lines should be minimized; keep traces as short
resets the MSP 44x0G. as possible. This input is sensitive for magnetic induc-
tion.
I2S_DA_IN3 – I2S Data Input 3 (Fig. 4–11)
Input of digital serial sound data to the MSP via the AHVSUP* – Analog Power Supply High Voltage
multichannel I2S bus (only available for PQFP80 pack- Power is supplied via this pin for the analog circuitry of
age). the MSP (except IF input). This pin must be connected
to the +8 V supply.
DACA_R/L – Headphone Outputs (Fig. 4–17)
Output of the headphone signal. A 1-nF capacitor to CAPL_M – Volume Capacitor Loudspeaker (Fig. 4–20)
AHVSS must be connected to these pins. The DC off- A 10-µF capacitor to AHVSUP must be connected to
set on these pins depends on the selected headphone this pin. It serves as a smoothing filter for loudspeaker
volume. volume changes in order to suppress audible plops.
The value of the capacitor can be lowered to 1 µF if
VREF2 – Reference Ground 2 faster response is required. The area encircled by the
Reference analog ground. This pin must be connected trace lines should be minimized; keep traces as short
separately to ground (AHVSS). VREF2 serves as a as possible. This input is sensitive for magnetic induc-
clean ground and should be used as the reference for tion.
analog connections to the loudspeaker and head-
phone outputs. AHVSS* – Ground for Analog Power Supply
High Voltage
DACM_R/L – Loudspeaker Outputs (Fig. 4–17) Ground connection for the analog circuitry of the MSP
Output of the loudspeaker signal. A 1-nF capacitor to (except IF input).
AHVSS must be connected to these pins. The DC off-
set on these pins depends on the selected loud- AGNDC – Internal Analog Reference Voltage
speaker volume. This pin serves as the internal ground connection for
the analog circuitry (except IF input). It must be con-
DACM_SUB – Subwoofer Output (Fig. 4–17) nected to the VREF pins with a 3.3-µF and a 100-nF
Output of the subwoofer signal. A 1-nF capacitor to capacitor in parallel. This pins shows a DC level of typ-
AHVSS must be connected to this pin. Due to the low ically 3.73 V.
frequency content of the subwoofer output, the value
of the capacitor may be increased for better suppres- SC4_IN_L/R – SCART4 Inputs (Fig. 4–10)
sion of high-frequency noise. The DC offset on this pin The analog input signal for SCART4 is fed to this pin.
depends on the selected loudspeaker volume. Analog input connection must be AC-coupled.
SC2_OUT_R/L – SCART2 Outputs (Fig. 4–18) ASG – Analog Shield Ground

Output of the SCART2 signal. Connections to these Analog ground (AHVSS) should be connected to this
pins must use a 100-Ω series resistor and are intended pin to reduce cross-coupling between SCART inputs.
to be AC-coupled.
SC3_IN_L/R – SCART3 Inputs (Fig. 4–10)
VREF1 – Reference Ground 1 The analog input signal for SCART3 is fed to this pin.
Reference analog ground. This pin must be connected Analog input connection must be AC-coupled.
separately to ground (AHVSS). VREF1 serves as a
clean ground and should be used as the reference for ASG – Analog Shield Ground
analog connections to the SCART outputs. Analog ground (AHVSS) should be connected to this
pin to reduce cross-coupling between SCART inputs.
SC1_OUT_R/L – SCART1 Outputs (Fig. 4–18)
Output of the SCART1 signal. Connections to these SC2_IN_L/R – SCART2 Inputs (Fig. 4–10)
pins must use a 100-Ω series resistor and are intended The analog input signal for SCART2 is fed to this pin.
to be AC-coupled. Analog input connection must be AC-coupled.
ASG – Analog Shield Ground

Analog ground (AHVSS) should be connected to this
pin to reduce cross-coupling between SCART inputs.
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SC1_IN_L/R – SCART1 Inputs (Fig. 4–10) AUD_CL_OUT – Audio Clock Output (Fig. 4–16)
The analog input signal for SCART1 is fed to this pin. This is the 18.432 MHz main clock output.
Analog input connection must be AC-coupled.
D_CTR_I/O_1/0 – Digital Control Input/Output Pins
VREFTOP – Reference Voltage IF A/D Converter (Fig. 4–15)
(Fig. 4–12) General purpose input/output pins. Pin D_CTR_I/O_1
Via this pin, the reference voltage for the IF A/D con- can be used as an interrupt request pin to the control-
verter is decoupled. It must be connected to AVSS ler.
pins with a 10-µF and a 100-nF capacitor in parallel.
Traces must be kept short. ADR_SEL – I2C Bus Address Select (Fig. 4–13)
By means of this pin, one of three device addresses
MONO_IN – Mono Input (Fig. 4–10) for the MSP can be selected. The pin can be con-
The analog mono input signal is fed to this pin. Analog nected to ground (I2C device addresses 80/81hex), to
input connection must be AC-coupled. +5 V supply (84/85hex), or left open (88/89hex).
AVSS* – Ground for Analog Power Supply Voltage STANDBYQ – Stand-by

Ground connection for the analog IF input circuitry of In normal operation, this pin must be high. If the
the MSP. MSP 44x0G is switched off by first pulling STANDBYQ
low and then (after >1µs delay) switching off DVSUP
AVSUP* – Analog Power Supply Voltage and AVSUP, but keeping AHVSUP (‘Standby’-mode),
Power is supplied via this pin for the analog IF input the SCART switches maintain their position and func-
circuitry of the MSP. This pin must be connected to the tion.
+5 V supply.
* Application Note:
ANA_IN1+ – IF Input 1 (Fig. 4–12) All ground pins should be connected to one low-resis-
The analog sound IF signal is supplied to this pin. tive ground plane. All supply pins should be connected
Inputs must be AC-coupled. This pin is designed as separately with short and low-resistive lines to the
symmetrical input: ANA_IN1+ is internally connected power supply. Decoupling capacitors from DVSUP to
to one input of a symmetrical op amp, ANA_IN- to the DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are
other. recommended as closely as possible to these pins.
Decoupling of DVSUP and DVSS is most important.
ANA_IN− – IF Common (Fig. 4–12) We recommend using more than one capacitor. By
This pins serves as a common reference for ANA_IN1/ choosing different values, the frequency range of
2+ inputs. active decoupling can be extended. In our application
boards we use: 220 pF, 470 pF, 1.5 nF, and 10 µF.
ANA_IN2+ – IF Input 2 (Fig. 4–12) The capacitor with the lowest value should be placed
The analog sound if signal is supplied to this pin. nearest to the DVSUP and DVSS pins.
Inputs must be AC-coupled. This pin is designed as
symmetrical input: ANA_IN2+ is internally connected The ASG pins should be connected as closely as pos-
to one input of a symmetrical op amp, ANA_IN− to the sible to the MSP ground. If they are lead with the
other. SCART-inputs as shielding lines, they should not be
connected to ground at the SCART connector.
TESTEN – Test Enable Pin (Fig. 4–8)
This pin enables factory test modes. For normal opera-
tion, it must be connected to ground.
XTAL_IN, XTAL_OUT – Crystal Input and Output Pins

(Fig. 4–16)
These pins are connected to an 18.432 MHz crystal
oscillator which is digitally tuned by integrated shunt
capacitances. An external clock can be fed into
XTAL_IN. The audio clock output signal
AUD_CL_OUT is derived from the oscillator. External
capacitors at each crystal pin to ground (AVSS) are
required. It should be verified by layout, that no supply
current for the digital circuitry is flowing through the
ground connection point.
TP – This pin enables factory test modes. For normal

operation, it must be left vacant.
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4.4. Pin Configurations
SC2_IN_L ASG
SC2_IN_R SC3_IN_R
ASG SC3_IN_L
SC1_IN_L ASG
SC1_IN_R SC4_IN_R
VREFTOP SC4_IN_L
NC NC
MONO_IN AGNDC
AVSS AHVSS
AVSS AHVSS
NC NC
NC NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AVSUP 65 40 CAPL_M
AVSUP 66 39 AHVSUP
ANA_IN1+ 67 38 CAPL_A
ANA_IN− 68 37 SC1_OUT_L
ANA_IN2+ 69 36 SC1_OUT_R
TESTEN 70 35 VREF1
XTAL_IN 71 34 SC2_OUT_L
XTAL_OUT 72 33 SC2_OUT_R
TP 73
MSP 44x0G 32 NC
AUD_CL_OUT 74 31 NC
NC 75 30 DACM_SUB
NC 76 29 NC
D_CTR_I/O_1 77 28 DACM_L
D_CTR_I/O_0 78 27 DACM_R
ADR_SEL 79 26 VREF2
STANDBYQ 80 25 DACA_L
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC DACA_R
I2C_CL NC
I2C_DA I2S_DA_IN3
I2S_CL RESETQ
I2S_WS I2S_WS3
I2S_DA_OUT I2S_CL3
I2S_DA_IN1 NC
ADR_DA I2S_DA_IN2
ADR_WS DVSS
ADR_CL DVSS
DVSUP DVSS
DVSUP DVSUP
Fig. 4–4: PQFP80 package
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SC2_IN_L ASG
SC2_IN_R SC3_IN_R
ASG SC3_IN_L
SC1_IN_L ASG
SC1_IN_R SC4_IN_R
VREFTOP SC4_IN_L
MONO_IN AGNDC
AVSS AHVSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AVSUP 49 32 CAPL_M
ANA_IN1+ 50 31 AHVSUP
ANA_IN− 51 30 CAPL_A
ANA_IN2+ 52 29 SC1_OUT_L
TESTEN 53 28 SC1_OUT_R
XTAL_IN 54 27 VREF1
XTAL_OUT 55 26 SC2_OUT_L
TP 56 25 SC2_OUT_R
AUD_CL_OUT 57
MSP 44x0G 24 NC
NC 58 23 DACM_SUB
NC 59 22 NC
D_CTR_I/O_1 60 21 DACM_L
C_CTR_I/O_0 61 20 DACM_R
ADR_SEL 62 19 VREF2
STANDBYQ 63 18 DACA_L
NC 64 17 DACA_R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I2C_CL RESETQ
I2C_DA I2S_WS3
I2S_CL I2S_CL3
I2S_WS NC
I2S_DA_OUT I2S_DA_IN2/3
I2S_DA_IN1 DVSS
ADR_DA DVSUP
ADR_WS ADR_CL
Fig. 4–5: PLQFP64 package
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4.5. Pin Circuits

AUD_CL_OUT 1 64 TP
NC 2 63 XTAL_OUT
NC 3 62 XTAL_IN
D_CTR_I/O_1 4 61 TESTEN
D_CTR_I/O_0 5 60 ANA_IN2+ >300 k
ADR_SEL 6 59 ANA_IN−
STANDBYQ 7 58 ANA_IN+
DVSS
NC 8 57 AVSUP
I2C_CL 9 56 AVSS Fig. 4–7: Input Pin: RESETQ
I2C_DA 10 55 MONO_IN
I2S_CL 11 54 VREFTOP
I2S_WS 12 53 SC1_IN_R
I2S_DA_OUT 13 52 SC1_IN_L AVSUP
MSP 44x0G
I2S_DA_IN1 14 51 ASG
ADR_DA 15 50 SC2_IN_R 200 k
ADR_WS 16 49 SC2_IN_L
ADR_CL 17 48 ASG
DVSUP 18 47 SC3_IN_R
DVSS 19 46 SC3_IN_L Fig. 4–8: Input Pin TESTEN
I2S_DA_IN2/3 20 45 ASG
NC 21 44 SC4_IN_R
I2S_CL3 22 43 SC4_IN_L
I2S_WS3 23 42 AGNDC
RESETQ 24 41 AHVSS
24 kΩ
DACA_R 25 40 CAPL_M
≈ 3.75 V
DACA_L 26 39 AHVSUP
VREF2 27 38 CAPL_A
DACM_R 28 37 SC1_OUT_L Fig. 4–9: Input Pin: MONO_IN
DACM_L 29 36 SC1_OUT_R
NC 30 35 VREF1
NC 31 34 SC2_OUT_L
NC 32 33 SC2_OUT_R
40 kΩ
≈ 3.75 V
Fig. 4–6: PSDIP64 package
Fig. 4–10: Input Pins: SC4-1_IN_L/R
Fig. 4–11: Input Pins:

I2S_DA_IN1..3, STANDBYQ
ANA_IN1+
ANA_IN2+
A
D
ANA_IN−
VREFTOP
Fig. 4–12: Input Pins:

VREFTOP, ANA_IN1+, ANA_IN-, ANA_IN2+
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DVSUP AHVSUP
23 kΩ
0...1.2 mA
23 kΩ 3.3 kΩ
GND
ADR_SEL
Fig. 4–17: Output Pins:
Fig. 4–13: Input Pin: ADR_SEL DACA_R/L, DACM_R/L, DACM_SUB
26 pF
N
120 kΩ
GND
Fig. 4–14: Input/Output Pins: I2C_CL, I2C_DA 300 Ω
≈ 3.75 V
DVSUP
P Fig. 4–18: Output Pins:
SC_2_OUT_R/L, SC_1_OUT_R/L
N
GND
DVSUP
Fig. 4–15: Input/Output Pins: P
I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0,
I2S_CL3, I2S_WS3
N
GND
Fig. 4–19: Output Pins:

P I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL
3−30 pF 500 kΩ
N
0...2 V
2.5 V
3−30 pF
Fig. 4–20: Capacitor Pins: CAPL_A, CAPL_M
Fig. 4–16: Input/Output Pins:

XTAL_IN, XTAL_OUT, AUD_CL_OUT
125 kΩ
≈ 3.75 V
Fig. 4–21: Pin: AGNDC
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4.6. Electrical Characteristics
4.6.1. Absolute Maximum Ratings
Symbol Parameter Pin Name Min. Max. Unit
TA Ambient Operating Temperature − 0 70 °C
TS Storage Temperature − −40 125 °C
VSUP1 First Supply Voltage AHVSUP −0.3 9.0 V
VSUP2 Second Supply Voltage DVSUP −0.3 6.0 V
VSUP3 Third Supply Voltage AVSUP −0.3 6.0 V
dVSUP23 Voltage between AVSUP AVSUP, −0.5 0.5 V

and DVSUP DVSUP
PTOT Power Dissipation AHVSUP,

PSDIP64 DVSUP, 1300 mW
PQFP80 AVSUP 1000 mW
PLQFP64 960 mW
VIdig Input Voltage, all Digital Inputs −0.3 VSUP2+0.3 V
IIdig Input Current, all Digital Pins − −20 +20 mA1)
VIana Input Voltage, all Analog Inputs SCn_IN_s,2) −0.3 VSUP1+0.3 V

MONO_IN
IIana Input Current, all Analog Inputs SCn_IN_s,2) −5 +5 mA1)

MONO_IN
IOana Output Current, all SCART Outputs SCn_OUT_s2) 3) 4)

, 3) 4)
,
IOana Output Current, all Analog Outputs DACp_s2) 3) 3)

except SCART Outputs
ICana Output Current, other pins CAPL_p,2) 3) 3)

connected to capacitors AGNDC
1)
positive value means current flowing into the circuit
2)
“n” means “1”, “2”, “3”, or “4”, “s” means “L” or “R”, “p” means “M” or “A”
3)
The analog outputs are short-circuit proof with respect to First Supply Voltage and ground.
4)
Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
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4.6.2. Recommended Operating Conditions (TA = 0 to 70 °C)
4.6.2.1. General Recommended Operating Conditions
Symbol Parameter Pin Name Min. Typ. Max. Unit
VSUP1 First Supply Voltage AHVSUP 7.6 8.0 8.7 V

(AHVSUP = 8 V)
First Supply Voltage 4.75 5.0 5.25 V

(AHVSUP = 5 V)
VSUP2 Second Supply Voltage DVSUP 4.75 5.0 5.25 V
VSUP3 Third Supply Voltage AVSUP 4.75 5.0 5.25 V
tSTBYQ1 STANDBYQ Setup Time before STANDBYQ, 1 µs

Turn-off of Second Supply Voltage DVSUP
4.6.2.2. Analog Input and Output Recommendations
CAGNDC AGNDC-Filter-Capacitor AGNDC −20% 3.3 µF
Ceramic Capacitor in Parallel −20% 100 nF
CinSC DC-Decoupling Capacitor in front of SCn_IN_s1) −20% 330 nF

SCART Inputs
VinSC SCART Input Level 2.0 VRMS
VinMONO Input Level, Mono Input MONO_IN 2.0 VRMS
RLSC SCART Load Resistance SCn_OUT_s1) 10 kΩ
CLSC SCART Load Capacitance 6.0 nF
CVMA Main/AUX Volume Capacitor CAPL_p1) 10 µF
CFMA Main/AUX Filter Capacitor DACp_s1) −10% 1 +10% nF

1)
“n” means “1”, “2”, “3", or “4", “s” means “L” or “R”, “p” means “M” or “A”
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4.6.2.3. Recommendations for Analog Sound IF Input Signal
CVREFTOP VREFTOP-Filter-Capacitor VREFTOP −20% 10 µF
Ceramic Capacitor in Parallel −20% 100 nF
FIF_FMTV Analog Input Frequency Range ANA_IN1+, 0 9 MHz

for TV Applications ANA_IN2+,
ANA_IN−
FIF_FMRADIO Analog Input Frequency for 10.7 MHz
FM-Radio Applications
VIF_FM Analog Input Range FM/NICAM 0.1 0.8 3 Vpp
VIF_AM Analog Input Range AM/NICAM 0.1 0.45 0.8 Vpp
RFMNI Ratio: NICAM Carrier/FM Carrier

(unmodulated carriers)
BG: −20 −7 0 dB
I: −23 −10 0 dB
RAMNI Ratio: NICAM Carrier/AM Carrier −25 −11 0 dB

(unmodulated carriers)
RFM Ratio: FM-Main/FM-Sub Satellite 7 dB
RFM1/FM2 Ratio: FM1/FM2 7 dB

German FM-System
RFC Ratio: Main FM Carrier/ 15 − − dB

Color Carrier
RFV Ratio: Main FM Carrier/ 15 − − dB

Luma Components
PRIF Passband Ripple − − ±2 dB
SUPHF Suppression of Spectrum 15 − dB

above 9.0 MHz (not for FM Radio)
FMMAX Maximum FM-Deviation (approx.)

normal mode ±180 kHz
HDEV2: high deviation mode ±360 kHz
HDEV3: very high deviation mode ±540 kHz
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4.6.2.4. Crystal Recommendations
General Crystal Recommendations
fP Crystal Parallel Resonance Fre- 18.432 MHz

quency at 12 pF Load Capacitance
RR Crystal Series Resistance 8 25 Ω
C0 Crystal Shunt (Parallel) Capacitance 6.2 7.0 pF
CL External Load Capacitance1) XTAL_IN, PSDIP approx. 1.5 pF

XTAL_OUT P(L)QFP approx. 3.3 pF
Crystal Recommendations for Master-Slave Applications (MSP-clock must perform synchronization to I2S clock)
fTOL Accuracy of Adjustment −20 +20 ppm
DTEM Frequency Variation −20 +20 ppm

versus Temperature
C1 Motional (Dynamic) Capacitance 19 24 fF
fCL Required Open Loop Clock AUD_CL_OUT 18.431 18.433 MHz

Frequency (Tamb = 25 °C)
Crystal Recommendations for FM/NICAM Applications (No MSP-clock synchronization to I2S clock possible)

versus Temperature
C1 Motional (Dynamic) Capacitance 15 fF

Crystal Recommendations for all analog FM/AM Applications (No MSP-clock synchron. to I2S/NICAM clock possible)

versus Temperature

Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF)
VXCA External Clock Amplitude XTAL_IN 0.7 Vpp

1)
External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-
quency of the internal PLL and to stabilize the frequency in closed-loop operation.
Due to different layouts, the accurate capacitor value should be determined with the customer PCB. The sug-
gested values (1.5...3.3 pF) are figures based on experience and should serve as “start value”.
To adjust the capacitor value, reset the MSP. After the reset no I2C telegrams should be transmitted. Measure the
frequency at AUD_CL_OUT-pin. Change the capacitor value until the free running frequency matches
18.432 MHz as closely as possible. The higher the capacity, the lower the resulting clock frequency.
Note: To minimize adjustment tolerances for all MSP-generations, it is strongly recommended to use the so-called
MSP-XTAL-REF ICs (available in all packages) for the capacitor adjustment.
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4.6.3. Characteristics
at TA = 0 to 70 °C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. values
at TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values,
TJ = Junction Temperature
MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel
4.6.3.1. General Characteristics
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Supply
ISUP1A First Supply Current (active) AHVSUP 17 25 mA Vol. Main and Aux = 0 dB
(AHVSUP = 8 V) 11 16 mA Vol. Main and Aux = -30dB
First Supply Current (active) 11 17 mA Vol. Main and Aux = 0 dB

(AHVSUP = 5 V) 8 11 mA Vol. Main and Aux = -30 dB
ISUP2A Second Supply Current (active) DVSUP 65 80 mA
ISUP3A Third Supply Current (active) AVSUP 30 38 mA
ISUP1S First Supply Current AHVSUP 5.6 7.7 mA STANDBYQ = low

(AHVSUP = 8 V)
First Supply Current 3.7 5.1 mA

(AHVSUP = 5 V)
Clock
fCLOCK Clock Input Frequency XTAL_IN 18.432 MHz
DCLOCK Clock High to Low Ratio 45 55 %
tJITTER Clock Jitter (Verification not 50 ps

provided in Production Test)
VxtalDC DC-Voltage Oscillator 2.5 V
tStartup Oscillator Startup Time at XTAL_IN, 0.4 2 ms

VDD Slew-rate of 1 V/1 µs XTAL_OUT
VACLKAC Audio Clock Output AC Voltage AUD_CL_OUT 1.2 1.8 Vpp load = 40 pF
VACLKDC Audio Clock Output DC Voltage 0.4 0.6 VSUP3 Imax = 0.2 mA
routHF_ACL HF Output Resistance 140 Ω
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4.6.3.2. Digital Inputs, Digital Outputs
Digital Input Levels
VDIGIL Digital Input Low Voltage STANDBYQ 0.2 VSUP2

D_CTR_I/O_0/1
VDIGIH Digital Input High Voltage 0.5 VSUP2
ZDIGI Input Impedance 5 pF
IDLEAK Digital Input Leakage Current −1 1 µA 0 V < UINPUT< DVSUP

D_CTR_I/O_0/1: tri-state
VDIGIL Digital Input Low Voltage ADR_SEL 0.2 VSUP2
VDIGIH Digital Input High Voltage 0.8 VSUP2
IADRSEL Input Current Address Select Pin −500 −220 µA UADR_SEL= DVSS
220 500 µA UADR_SEL= DVSUP
Digital Output Levels
VDCTROL Digital Output Low Voltage D_CTR_I/O_0 0.4 V IDDCTR = 1 mA

D_CTR_I/O_1
VDCTROH Digital Output High Voltage VSUP2 V IDDCTR = −1 mA
−0.3
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4.6.3.3. Reset Input and Power-Up
RESETQ Input Levels
VRHL Reset High-Low Transition Voltage RESETQ 0.3 0.4 VSUP2
VRLH Reset Low-High Transition Voltage 0.45 0.55 VSUP2
ZRES Input Capacitance 5 pF
IRES Input High Current 20 µA URESETQ = DVSUP
DVSUP
AVSUP
4.5 V
t/ms
RESETQ Note: The reset should

not reach high level
Low-to-High before the oscillator has
Threshold started. This requires a
0.45× DVSUP reset delay of >2 ms
0.3...0.4× DVSUP High-to-Low
Threshold 0.45 x DVSUP means
2.25 Volt with
DVSUP = 5.0 V
t/ms
Reset Delay
>2 ms
Internal
Reset High
Low
t/ms
Fig. 4–22: Power-up sequence
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4.6.3.4. I2C-Bus Characteristics
2
VI2CIL I C-Bus Input Low Voltage I2C_CL, 0.3 VSUP2
I2C_DA
VI2CIH I2C-Bus Input High Voltage 0.6 VSUP2
tI2C1 I2C Start Condition Setup Time 120 ns
tI2C2 I2C Stop Condition Setup Time 120 ns
tI2C5 I2C-Data Setup Time 55 ns

before Rising Edge of Clock
tI2C6 I2C-Data Hold Time 55 ns

after Falling Edge of Clock
tI2C3 I2C-Clock Low Pulse Time I2C_CL 500 ns
tI2C4 I2C-Clock High Pulse Time 500 ns
fI2C I2C-BUS Frequency 1.0 MHz
VI2COL I2C-Data Output Low Voltage I2C_CL, 0.4 V II2COL = 3 mA

I2C_DA
II2COH I2C-Data Output 1.0 µA VI2COH = 5 V
High Leakage Current
tI2COL1 I2C-Data Output Hold Time 15 ns

after Falling Edge of Clock
tI2COL2 I2C-Data Output Setup Time 100 ns fI2C = 1 MHz

before Rising Edge of Clock
1/FI2C
TI2C4 TI2C3
I2C_CL
TI2C1 TI2C5 TI2C6 TI2C2
I2C_DA as input
TI2COL2 TI2COL1
I2C_DA as output
Fig. 4–23: I2C bus timing diagram
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4.6.3.5. I2S-Bus Characteristics
VI2SIL Input Low Voltage I2S_CL 0.2 VSUP2

I2S_WS
VI2SIH Input High Voltage I2S_CL3 0.5 VSUP2
I2S_WS3
ZI2SI Input Impedance I2S_DA_IN1..3 5 pF
ILEAKI2S Input Leakage Current −1 1 µA 0 V < UINPUT< DVSUP
VI2SOL I2S Output Low Voltage I2S_CL 0.4 V II2SOL = 1 mA

I2S_WS
VI2SOH I2S Output High Voltage I2S_DA_OUT VSUP2 V II2SOH = −1 mA
− 0.3
fI2SOWS I2S-Word Strobe Output Frequency I2S_WS 48.0 kHz
fI2SOCL I2S-Clock Output Frequency I2S_CL 1.536 3.072 12.288 MHz

2
RI2S10/I2S20 I S-Clock Output High/Low-Ratio 0.9 1.0 1.1
2
I S Interface 1/2
ts_I2S I2S Input Setup Time I2S_DA_IN1/2 12 ns for details see Fig. 4–24
before Rising Edge of Clock I2S_CL “I2S bus timing diagram
(synchronous interface 1/
2)”
th_I2S I2S Input Hold Time 40 ns

after Rising Edge of Clock
td_I2S I2S Output Delay Time I2S_CL 28 ns CL=30 pF

after Falling Edge of Clock I2S_WS
I2S_DA_OUT
fI2SWS I2S-Word Strobe Input Frequency I2S_WS 48.0 kHz deviation = ±300 ppm
fI2SCL I2S-Clock Input Frequency I2S_CL 1.536 3.072 12.288 MHz deviation = ±300 ppm
2
RI2SCL I S-Clock Input Ratio 0.9 1.1
I2S Interface 3
ts_I2S3 I2S3 Input Setup Time I2S_CL3 4 ns for details see Fig. 4–25
before Rising Edge of Clock I2S_WS3 “I2S timing diagram (inter-
I2S_DA_IN3 face 3)”
th_I2S3 I2S3 Input Hold Time 40 ns
after Rising Edge of Clock
fI2S3WS I2S3-Word Strobe Input Frequency I2S_WS3 48 kHz
fI2S3CL I2S3-Clock Input Frequency I2S_CL3 1.536 12.288 MHz
RI2S3CL I2S3-Clock Input Ratio 0.9 1.1
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1/FI2SWS
I2S_WS
MODUS[6] = 0
MODUS[6] = 1 Detail C
I2S_CL
Detail A
I2S_DA_IN*) R LSB L MSB L LSB R MSB R LSB L LSB
16/32 bit left channel 16/32 bit right channel
Detail B
I2S_DA_OUT R LSB L MSB L LSB R MSB R LSB L LSB
16/32 bit left channel 16/32 bit right channel
Data: MSB first, I2S synchronous master
1/FI2SWS
I2S_WS
MODUS[6] = 0
MODUS[6] = 1 Detail C
I2S_CL
Detail A
I2S_DA_IN*) R LSB L MSB L LSB R MSB R LSB L LSB
16,18...32 bit left channel 16, 18...32 bit right channel
16, 18...32 bit left channel

Detail B
I2S_DA_OUT R LSB L MSB L LSB R MSB R LSB L LSB
16, 18...32 bit right channel
Data: MSB first, I2S synchronous slave
Note:
1)I2S_DA_IN can be
− I2S_DA_IN1,
− I2S_DA_IN2, or
Detail C 1/FI2SCL Detail A,B − I2S_DA_IN2/3
I2S_CL I2S_CL
Ts_I2S Th_I2S
Ts_I2S
I2S_DA_IN1)
I2S_WS as INPUT
Td_I2S
Td_I2S
I2S_WS as OUTPUT I2S_DA_OUT
Fig. 4–24: I2S bus timing diagram (synchronous interface 1/2)
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I2S_CL3
1/FI2S3WS
Left sample (I2S_CONFIG[10] = 0) Right sample (I2S_CONFIG[10] = 0)

I2S_WS3
2
Left sample (I S_CONFIG[10] = 1) Right sample (I2S_CONFIG[10] = 1)
I2S_DA_IN3 Left aligned (I2S_CONFIG[9] = 0)

16,18...32 Bit data & clocks allowed
MSB MSB
I2S_DA_IN3 Left aligned (I2S_CONFIG[9] = 1)

16,18...32 Bit data & clocks allowed
MSB MSB
I2S_DA_IN3 Right aligned (I2S_CONFIG[11] = 1, I2S_CONFIG[9] = 0)

LSB 16 Bit data & 16...32 clocks allowed LSB
1/FI2S3CL
I2S_CL3
Ts_I2S3 Th_I2S3
I2S_DA_IN3
Ts_I2S3
I2S_WS3
Fig. 4–25: I2S timing diagram (interface 3)
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4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
Analog Ground
VAGNDC0 AGNDC Open Circuit Voltage AGNDC 3.77 V Rload ≥ 10 MΩ

(AHVSUP =8 V)
AGNDC Open Circuit Voltage 2.51 V

(AHVSUP = 5 V)
RoutAGN AGNDC Output Resistance 70 125 180 kΩ 3 V ≤ VAGNDC ≤ 4 V

(AHVSUP = 8 V)
AGNDC Output Resistance 47 83 120 kΩ

(AHVSUP = 5 V)
Analog Input Resistance
RinSC SCART Input Resistance SCn_IN_s1) 25 40 58 kΩ fsignal = 1 kHz, I = 0.05 mA

from TA = 0 to 70 °C
RinMONO MONO Input Resistance MONO_IN 15 24 35 kΩ fsignal = 1 kHz, I = 0.1 mA

from TA = 0 to 70 °C
Audio Analog-to-Digital-Converter
VAICL Analog Input Clipping Level for SCn_IN_s,1) 2.00 2.25 VRMS fsignal = 1 kHz
Analog-to-Digital- MONO_IN
Conversion
(AHVSUP = 8 V)
Analog Input Clipping Level for 1.13 1.51 VRMS

Analog-to-Digital-
Conversion
(AHVSUP = 5 V)
SCART Outputs
RoutSC SCART Output Resistance SCn_OUT_s1) fsignal = 1 kHz, I = 0.1 mA

200 330 460 Ω Tj = 27 °C
200 500 Ω TA = 0 to 70 °C
dVOUTSC Deviation of DC-Level at SCART −70 +70 mV

Output from AGNDC Voltage
ASCtoSC Gain from Analog Input SCn_IN_s,1) −1.0 +0.5 dB fsignal = 1 kHz
to SCART Output MONO_IN
→
frSCtoSC Frequency Response from Analog SCn_OUT_s1) −0.5 +0.5 dB with resp. to 1 kHz
Input to SCART Output Bandwidth: 0 to 20000 Hz
VoutSC Signal Level at SCART Output SCn_OUT_s1) 1.8 1.9 2.0 VRMS fsignal = 1 kHz
(AHVSUP = 8 V) Volume 0 dB
Full Scale input from I2S
Signal Level at SCART Output 1.17 1.27 1.37 VRMS
(AHVSUP = 5V)
1)
“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”
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Main and AUX Outputs
RoutMA Main/AUX Output Resistance DACp_s1) fsignal = 1 kHz, I = 0.1 mA

2.1 3.3 4.6 kΩ Tj = 27 °C
2.1 5.0 kΩ TA = 0 to 70 °C
VoutDCMA DC-Level at Main/AUX-Output 1.80 2.04 2.28 V Volume 0 dB

(AHVSUP = 8 V) 61 mV Volume −30 dB
DC-Level at Main/AUX-Output 1.12 1.36 1.60 V Volume 0 dB

(AHVSUP = 5 V) 40 mV Volume −30 dB
VoutMA Signal Level at Main/AUX-Output 1.23 1.37 1.51 VRMS fsignal = 1 kHz
(AHVSUP = 8 V) Volume 0 dB
Full scale input from I2S
Signal Level at Main/AUX-Output 0.76 0.90 1.04 VRMS
(AHVSUP = 5 V)
1)
“s” means “L” or “R”; “p” means “M” or “A”
4.6.3.7. Sound IF Inputs
RIFIN Input Impedance ANA_IN1+, 1.5 2 2.5 kΩ Gain AGC = 20 dB

ANA_IN2+, 6.8 9.1 11.4 kΩ Gain AGC = 3 dB
ANA_IN−
DCVREFTOP DC Voltage at VREFTOP VREFTOP 2.45 2.65 2.75 V
DCANA_IN DC Voltage on IF Inputs ANA_IN1+, 1.3 1.5 1.7 V

ANA_IN2+,
ANA_IN−
XTALKIF Crosstalk Attenuation ANA_IN1+, 40 dB fsignal = 1 MHz

ANA_IN2+, Input Level = −2 dBr
BWIF 3 dB Bandwidth ANA_IN− 10 MHz
AGC AGC Step Width 0.85 dB
4.6.3.8. Power Supply Rejection
PSRR: Rejection of Noise on AHVSUP at 1 kHz
PSRR AGNDC AGNDC 80 dB

2
From Analog Input to I S Output MONO_IN, 70 dB
SCn_IN_s1)
From Analog Input to MONO_IN, 70 dB

SCART Output SCn_IN_s1)
SCn_OUT_s1)
From I2S Input to SCART Output SCn_OUT_s1) 60 dB

2 1)
From I S Input to MAIN or AUX DACp_s 80 dB
Output
1) “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”
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4.6.3.9. Analog Performance
Specifications for AHVSUP = 8 V
SNR Signal-to-Noise Ratio
from Analog Input to I2S Output MONO_IN, 85 88 dB Input Level = −20 dB with
SCn_IN_s1) resp. to VAICL, fsig = 1 kHz,
unweighted
20 Hz...20 kHz
from Analog Input to MONO_IN, 93 96 dB Input Level = −20 dB,

SCART Output SCn_IN_s1) fsig = 1 kHz,
→ unweighted
SCn_OUT_s1) 20 Hz...20 kHz
from I2S Input to SCART Output SCn_OUT_s1) 85 88 dB Input Level = −20 dB,
fsig = 1 kHz,
unweighted
20 Hz...20 kHz
from I2S Input to Main/AUX-Output DACp_s1) Input Level = −20 dB,

for Analog Volume at 0 dB 85 88 dB fsig = 1 kHz,
for Analog Volume at −30 dB 78 83 dB unweighted
20 Hz...20 kHz
THD Total Harmonic Distortion
from Analog Input to I2S Output MONO_IN, 0.01 0.03 % Input Level = −3 dBr with
unweighted
20 Hz...20 kHz
from Analog Input to MONO_IN, 0.01 0.03 % Input Level = −3 dBr,

SCART Output SCn_IN_s fsig = 1 kHz,
→ unweighted
from I2S Input to SCART Output SCn_OUT_s1) 0.01 0.03 % Input Level = −3 dBr,
fsig = 1 kHz,
unweighted
20 Hz...20 kHz
from I2S Input to Main or AUX Out- DACp_s1) 0.01 0.03 % Input Level = −3 dBr,
put fsig = 1 kHz,
unweighted
20 Hz...20 kHz
1)
“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”
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Specifications for AHVSUP = 5 V
SNR Signal-to-Noise Ratio
from Analog Input to I2S Output MONO_IN, 82 85 dB Input Level = −20 dB with
unweighted
20 Hz...20 kHz
from Analog Input to MONO_IN, 90 93 dB Input Level = −20 dB,

SCART Output SCn_IN_s1) fsig = 1 kHz,
→ unweighted
from I2S Input to SCART Output SCn_OUT_s1) 82 85 dB Input Level = −20 dB,
fsig = 1 kHz,
unweighted
20 Hz...20 kHz
from I2S Input to Main/AUX-Output DACp_s1) Input Level = −20 dB,

for Analog Volume at 0 dB 82 85 dB fsig = 1 kHz,
for Analog Volume at −30 dB 75 80 dB unweighted
20 Hz...20 kHz
THD Total Harmonic Distortion
from Analog Input to I2S Output MONO_IN, 0.03 0.1 % Input Level = −3 dBr with
unweighted
20 Hz...20 kHz
from Analog Input to MONO_IN, 0.1 % Input Level = −3 dBr,

SCART Output SCn_IN_s fsig = 1 kHz,
→ unweighted
from I2S Input to SCART Output SCn_OUT_s1) 0.1 % Input Level = −3 dBr,
fsig = 1 kHz,
unweighted
20 Hz...20 kHz
from I2S Input to Main or AUX Out- DACp_s1) 0.1 % Input Level = −3 dBr,
put fsig = 1 kHz,
unweighted
20 Hz...20 kHz
1) “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”
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CROSSTALK Specifications for AHVSUP = 8 V and 5 V
XTALK Crosstalk Attenuation Input Level = −3 dB,

− PSDIP64 fsig = 1 kHz, unused analog
inputs connected to ground
by Z < 1 kΩ
between left and right channel within unweighted

SCART Input/Output pair (L→R, R→L) 20 Hz...20 kHz
SCn_IN → SCn_OUT1) PSDIP64 80 dB
SC1_IN or SC2_IN → I2S Output PSDIP64 80 dB
SC3_IN → I2S Output PSDIP64 80 dB
I2S Input → SCn_OUT1) PSDIP64 80 dB
between left and right channel within unweighted

Main or AUX Output pair 20 Hz...20 kHz
I2S Input → DACp1) PSDIP64 75 dB
between SCART Input/Output pairs (unweighted

20 Hz...20 kHz
D = disturbing program
same signal source on left
O = observed program
and right disturbing chan-
D: MONO/SCn_IN → SCn_OUT PSDIP64 100 dB nel, effect on each
O: MONO/SCn_IN → SCn_OUT1) observed output channel
D: MONO/SCn_IN → SCn_OUT or unsel. PSDIP64 95 dB
O: MONO/SCn_IN → I2S Output
D: MONO/SCn_IN → SCn_OUT PSDIP64 100 dB
O: I2S Input → SCn_OUT1)
D: MONO/SCn_IN → unselected PSDIP64 100 dB
O: I2S Input → SC1_OUT1)
Crosstalk between Main and AUX Output pairs (unweighted

20 Hz...20 kHz)
I S Input → DACp
2 1)
PSDIP64 90 dB same signal source on left
nel, effect on each
observed output channel
XTALK Crosstalk from Main or AUX Output to SCART Output (unweighted

and vice versa 20 Hz...20 kHz)
same signal source on left
D = disturbing program
nel, effect on each
O = observed program
observed output channel
D: MONO/SCn_IN/DSP → SCn_OUT PSDIP64 80 dB SCART output load resis-
O: I2S Input → DACp1) tance 10 kΩ
D: MONO/SCn_IN/DSP → SCn_OUT PSDIP64 85 dB SCART output load resis-
O: I2S Input → DACp1) tance 30 kΩ
D: I2S Input → DACp PSDIP64 95 dB
O: MONO/SCn_IN → SCn_OUT1)
D: I2S Input → DACM PSDIP64 95 dB
O: I2S Input → SCn_OUT1)
1)
“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”
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4.6.3.10. Sound Standard Dependent Characteristics
NICAM Characteristics (MSP Standard Code = 8)
dVNICAMOUT Tolerance of Output Voltage DACp_s −1.5 +1.5 dB 2.12 kHz, Modulator input
of NICAM Baseband Signal SCn_OUT_s1 level = 0 dBref
S/NNICAM S/N of NICAM Baseband Signal 72 dB NICAM: −6 dB, 1 kHz, RMS

unweighted
0 to 15 kHz, Vol = 9 dB
NIC_Presc = 7Fhex
Output level 1 VRMS at
DACp_s
THDNICAM Total Harmonic Distortion + Noise 0.1 % 2.12 kHz, Modulator input
of NICAM Baseband Signal level = 0 dBref
BERNICAM NICAM: Bit Error Rate 1 10−7 FM+NICAM, norm conditions
fRNICAM NICAM Frequency Response , −1.0 +1.0 dB Modulator input

20...15000 Hz level = −12 dB dBref; RMS
XTALKNICAM NICAM Crosstalk Attenuation (Dual) 80 dB
SEPNICAM NICAM Channel Separation (Stereo) 80 dB
FM Characteristics (MSP Standard Code = 3)
dVFMOUT Tolerance of Output Voltage DACp_s, −1.5 +1.5 dB 1 FM-carrier, 50 µs, 1 kHz,
of FM Demodulated Signal SCn_OUT_s1 40 kHz deviation; RMS
S/NFM S/N of FM Demodulated Signal 73 dB 1 FM-carrier 5.5 MHz, 50 µs,

1 kHz, 40 kHz deviation;
THDFM Total Harmonic Distortion + Noise 0.1 % RMS, unweighted
of FM Demodulated Signal 0 to 15 kHz (for S/N);
full input range, FM-Pres-
cale = 46hex, Vol = 0 dB
→ Output Level 1 VRMS at
DACp_s
fRFM FM Frequency Responses, −1.0 +1.0 dB 1 FM-carrier 5.5 MHz,

20...15000 Hz 50 µs, Modulator input
level = −14.6 dBref; RMS
XTALKFM FM Crosstalk Attenuation (Dual) 80 dB 2 FM-carriers 5.5/5.74 MHz,

50 µs, 1 kHz, 40 kHz devia-
tion; Bandpass 1 kHz
SEPFM FM Channel Separation (Stereo) 50 dB 2 FM-carriers 5.5/5.74 MHz,

50 µs, 1 kHz, 40 kHz devia-
tion; RMS
AM Characteristics (MSP Standard Code = 9)
S/NAM(1) S/N of AM Demodulated Signal DACp_s, 55 dB SIF level: 0.1−0.8 Vpp

measurement condition: RMS/Flat SCn_OUT_s1 AM-carrier 54% at 6.5 MHz
Vol = 0 dB, FM/AM
S/NAM(2) S/N of AM Demodulated Signal 45 dB prescaler set for
measurement condition: QP/CCIR output = 0.5 VRMS at
Loudspeaker out;
THDAM Total Harmonic Distortion + Noise 0.6 % Standard Code = 09hex
of AM Demodulated Signal no video/chroma
components
fRAM AM Frequency Response −2.5 +1.0 dB
50...12000 Hz
1) “n” means “1” or “2”; “s” means “L” or “R”; “p” means “M” or “A”
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BTSC Characteristics (MSP Standard Code = 20hex, 21hex)
S/NBTSC S/N of BTSC Stereo Signal DACp_s, 68 dB 1 kHz L or R or SAP, 100%

SCn_OUT_s1) modulation, 75 µs deempha-
S/N of BTSC-SAP Signal 57 dB
sis, RMS unweighted 0 to 15
kHz
THDBTSC THD+N of BTSC Stereo Signal 0.1 % 1 kHz L or R or SAP, 100%

75 µs EIM2), DBX NR or
THD+N of BTSC SAP Signal 0.5 %
MNR, RMS unweighted
0 to 15 kHz
fRDBX Frequency Response of BTSC Ste- −1.0 1.0 dB L or R or SAP,

reo, 50 Hz...12 kHz 1%...66% EIM2), DBX NR
Frequency Response of BTSC- −1.0 1.0 dB
SAP, 50 Hz...9 kHz
fRMNR Frequency Response of BTSC Ste- −2.0 2.0 dB L or R 5%...66% EIM2), MNR
reo, 50 Hz...12 kHz
Frequency Response of BTSC- −2.0 2.0 dB SAP, white noise, 10% Modu-
SAP, 50 Hz...9 kHz lation, MNR
XTALKBTSC Stereo → SAP 76 dB 1 kHz L or R or SAP, 100%

modulation, 75 µs deempha-
SAP → Stereo 80 dB
sis, Bandpass 1 kHz
SEPDBX Stereo Separation DBX NR L or R 1%...66% EIM2), DBX

50 Hz...10 kHz 35 dB NR
50 Hz...12 kHz 30 dB
SEPMNR Stereo Separation MNR 30 dB L = 300 Hz, R = 3.1 kHz

14% Modulation, MNR
FMpil Pilot deviation threshold ANA_IN1+, 4.5 MHz carrier modulated

ANA_IN2+ with fh = 15.734 kHz
Stereo off → on 3.2 3.5 kHz
SIF level = 100 mVpp
Stereo on → off 1.2 1.5 kHz indication: STATUS Bit[6]
fPilot Pilot Frequency Range 15.563 15.843 kHz standard BTSC stereo signal,
sound carrier only
1)“n” means “1” or “2”; “s” means “L” or “R”; “p” means “M” or “A”
2)EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,
when the DBX encoding process is replaced by a 75-µs preemphasis network.
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BTSC Characteristics (MSP Standard Code = 20hex, 21hex)

with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components)
S/NBTSC S/N of BTSC Stereo Signal DACp_s, 64 dB 1 kHz L or R or SAP, 100%

SCn_OUT_s1 modulation, 75 µs deempha-
S/N of BTSC-SAP Signal 55 dB
sis, RMS unweighted 0 to 15
kHz
THDBTSC THD+N of BTSC Stereo Signal 0.15 % 1 kHz L or R or SAP, 100%

75 µs EIM2), DBX NR or
THD+N of BTSC SAP Signal 0.8 %
MNR, RMS unweighted
0 to 15 kHz
fRDBX Frequency Response of BTSC Ste- −1.0 1.0 dB L or R or SAP,

reo, 50 Hz...12 kHz 1%...66% EIM2), DBX NR
Frequency Response of BTSC- −1.0 1.0 dB
SAP, 50 Hz...9 kHz
fRMNR Frequency Response of BTSC Ste- −2.0 2.0 dB L or R 5%...66% EIM2), MNR
reo, 50 Hz...12 kHz
Frequency Response of BTSC- −2.0 2.0 dB SAP, white noise, 10% Modu-
SAP, 50 Hz...9 kHz lation, MNR
XTALKBTSC Stereo → SAP 75 dB 1 kHz L or R or SAP, 100%

modulation, 75 µs deempha-
SAP → Stereo 75 dB
sis, Bandpass 1 kHz
SEPDBX Stereo Separation DBX NR L or R 1%...66% EIM2), DBX

50 Hz...10 kHz 35 dB NR
50 Hz...12 kHz 30 dB
SEPMNR Stereo Separation MNR 30 dB L = 300 Hz, R = 3.1 kHz

14% Modulation, MNR
1)“n” means “1” or “2”; “s” means “L” or “R”; “p” means “M” or “A”
2)EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,
when the DBX encoding process is replaced by a 75-µs preemphasis network.
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EIA-J Characteristics (MSP Standard Code = 30hex)
S/NEIAJ S/N of EIA-J Stereo Signal DACp_s, 60 dB 1 kHz L or R,

SCn_OUT_s1) 100% modulation,
S/N of EIA-J Sub-Channel 60 dB
75 µs deemphasis,
RMS unweighted
THDEIAJ THD+N of EIA-J Stereo Signal 0.2 % 0 to 15 kHz
THD+N of EIA-J Sub-Channel 0.3 %
fREIAJ Frequency Response of EIA-J −0.5 1.0 dB 100% modulation,

Stereo, 50 Hz...12 kHz 75 µs deemphasis
Frequency Response of EIA-J −1.0 1.0 dB
Sub-Channel, 50 Hz...12 kHz
XTALKEIAJ Main → SUB 66 dB 1 kHz L or R, 100%

modulation, 75 µs
Sub → MAIN 80 dB
deemphasis,
Bandpass 1 kHz
SEPEIAJ Stereo Separation EIA-J Stereo Signal, L or R

50 Hz...5 kHz 35 dB 100% modulation
50 Hz...10 kHz 28 dB
FM-Radio Characteristics (MSP Standard Code = 40hex)
S/NUKW S/N of FM-Radio Stereo Signal DACp_s, 68 dB 1 kHz L or R, 100% modula-

SCn_OUT_s1) tion, 75 µs deemphasis, RMS
THDUKW THD+N of FM-Radio Stereo Signal 0.1 % unweighted
0 to 15 kHz
fRUKW Frequency Response of L or R, 1%...100% modula-

FM-Radio Stereo tion, 75 µs deemphasis
50 Hz...15 kHz −1.0 +0.5 dB
SEPUKW Stereo Separation 50 Hz...15 kHz 45 dB
fPilot Pilot Frequency Range ANA_IN1+ 18.844 19.125 kHz standard FM radio
ANA_IN2+ stereo signal
1) “n” means “1” or “2”; “s” means “L” or “R”; “p” means “M” or “A”
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5. Appendix A: Overview of TV-Sound Standards
5.1. NICAM 728
Table 5–1: Summary of NICAM 728 sound modulation parameters
Specification I B/G L D/K
Carrier frequency of 6.552 MHz 5.85 MHz 5.85 MHz 5.85 MHz
digital sound
Transmission rate 728 kbit/s
Type of modulation Differentially encoded quadrature phase shift keying (DQPSK)
Spectrum shaping by means of Roll-off filters

Roll-off factor
1.0 0.4 0.4 0.4
Carrier frequency of 6.0 MHz 5.5 MHz 6.5 MHz AM mono 6.5 MHz
analog sound component FM mono FM mono FM mono
terrestrial cable
Power ratio between 10 dB 13 dB 10 dB 16 dB 13 dB

vision carrier and
analog sound carrier
Power ratio between 10 dB 7 dB 17 dB 11 dB China/ Poland

analog and modulated Hungary
digital sound carrier
12 dB 7 dB
Table 5–2: Summary of NICAM 728 sound coding characteristics
Characteristics Values
Audio sampling frequency 32 kHz
Number of channels 2
Initial resolution 14 bit/sample
Companding characteristics near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks
Coding for compressed samples 2’s complement
Preemphasis CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz)
Audio overload level +12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)
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5.2. A2-Systems
Table 5–3: Key parameters for A2 Systems of Standards B/G, D/K, and M
Characteristics Sound Carrier FM1 Sound Carrier FM2
TV-Sound Standard B/G D/K M B/G D/K M
Carrier frequency in MHz 5.5 6.5 4.5 5.7421875 6.2578125 4.724212

6.7421875
5.7421875
Vision/sound power difference 13 dB 20 dB
Sound bandwidth 40 Hz to 15 kHz
Preemphasis 50 µs 75 µs 50 µs 75 µs
Frequency deviation (nom/max) ±27/±50 kHz ±17/±25 kHz ±27/±50 kHz ±15/±25 kHz
Transmission Modes
Mono transmission mono mono
Stereo transmission (L+R)/2 (L+R)/2 R (L−R)/2
Dual sound transmission language A language B
Identification of Transmission Mode
Pilot carrier frequency 54.6875 kHz 55.0699 kHz
Max. deviation portion ±2.5 kHz
Type of modulation / modulation depth AM / 50%
Modulation frequency mono: unmodulated

stereo: 117.5 Hz 149.9 Hz
dual: 274.1 Hz 276.0 Hz
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5.3. BTSC-Sound System
Table 5–4: Key parameters for BTSC-Sound Systems
Aural BTSC-MPX-Components
Carrier
(L+R) Pilot (L−R) SAP Prof. Ch.
Carrier frequency 4.5 MHz Baseband fh 2 fh 5 fh 6.5 fh

(fhNTSC = 15.734 kHz)
(fhPAL = 15.625 kHz)
Sound bandwidth in kHz 0.05 - 15 0.05 - 15 0.05 - 12 0.05 - 3.4
Preemphasis 75 µs DBX DBX 150 µs
Max. deviation to Aural Carrier 73 kHz 25 kHz1) 5 kHz 50 kHz1) 15 kHz 3 kHz
(total)
Max. Freq. Deviation of Subcarrier 10 kHz 3 kHz

Modulation Type AM FM FM
1)
Sum does not exceed 50 kHz due to interleaving effects
5.4. Japanese FM Stereo System (EIA-J)
Table 5–5: Key parameters for Japanese FM-Stereo Sound System EIA-J
Aural EIA-J-MPX-Components
Carrier
FM (L+R) (L−R) Identification
Carrier frequency (fh = 15.734 kHz) 4.5 MHz Baseband 2 fh 3.5 fh
Sound bandwidth 0.05 - 15 kHz 0.05 - 15 kHz −
Preemphasis 75 µs 75 µs none
Max. deviation portion to Aural Carrier 47 kHz 25 kHz 20 kHz 2 kHz
Max. Freq. Deviation of Subcarrier 10 kHz 60%

Modulation Type FM AM
Transmitter-sided delay 20 µs 0 µs 0 µs
Mono transmission L+R − unmodulated
Stereo transmission L+R L−R 982.5 Hz
Bilingual transmission Language A Language B 922.5 Hz
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5.5. FM Satellite Sound
Table 5–6: Key parameters for FM Satellite Sound
Carrier Frequency Maximum Sound Mode Bandwidth Deemphasis

FM Deviation
6.5 MHz 85 kHz Mono 15 kHz 50 µs
7.02/7.20 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive
5.6. FM-Stereo Radio
Table 5–7: Key parameters for FM-Stereo Radio Systems
Aural FM-Radio-MPX-Components
Carrier
(L+R) Pilot (L−R) RDS/ARI
Carrier frequency (fp = 19 kHz) 10.7 MHz Baseband fp 2 fp 3 fh
Sound bandwidth in kHz 0.05 - 15 0.05 - 15
Preemphasis:
− USA 75 µs 75 µs
− Europe 50 µs 50 µs
Max. deviation to Aural Carrier 75 kHz 90% 10% 90% 5%

(100%)
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6. Appendix B: Manual/Compatibility Mode
To adapt the modes of the STANDARD SELECT regis-

ter to individual requirements and for reasons of com-
patibility to the MSP 34x0D, the MSP 44x0G offers
an Manual/Compatibility Mode, which provides sophis-
ticated programming of the MSP 44x0G.
Using the STANDARD SELECT register generally pro-

vides a more economic way to program the
MSP 44x0G and will result in optimal behavior. There-
fore, it is not recommend to use the Manual/Com-
patibility mode. In those cases, where the
MSP 34x0D is to be substituted by the MSP 44x0G,
the tips given in Section 7.3. on page 98 have to be
obeyed by the controller software.
6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode
Table 6–1: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable!
Demodulator Address MSP- Description Reset Page

Write Registers (hex) Version Mode
AUTO_FM/AM 00 21 3410, 1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of 00 00 84

3450 Automatic Switching between NICAM and FM/AM in case of bad NICAM
reception
2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic
Switching between NICAM and FM/AM in case of bad NICAM reception
A2_Threshold 00 22 all A2 Stereo Identification Threshold 00 19hex 86
CM_Threshold 00 24 all Carrier-Mute Threshold 00 2Ahex 86
AD_CV 00 BB all SIF-input selection, configuration of AGC, and Carrier-Mute Function 00 00 87
MODE_REG 00 83 3410, Controlling of MSP-Demodulator and Interface options. As soon as this 00 00 88

3450 register is applied, the MSP 44x0G works in the MSP 34x0D compatibility
mode.
Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only
MSP 34x0D features are available; the use of MODUS and STATUS register
is not allowed.
The MSP 44x0G is reset to the normal mode by first programming the
MODUS register followed by transmitting a valid standard code to the
STANDARD SELECTION register.
FIR1 00 01 FIR1-filter coefficients channel 1 (6 ⋅ 8 bit) 00 00 90

FIR2 00 05 FIR2-filter coefficients channel 2 (6 ⋅ 8 bit), + 3 ⋅ 8 bit offset (total 72 bit)
DCO1_LO 00 93 Increment channel 1 Low Part 00 00 90

DCO1_HI 00 9B Increment channel 1 High Part
DCO2_LO 00 A3 Increment channel 2 Low Part
DCO2_HI 00 AB Increment channel 2 High Part
PLL_CAPS 00 1F Not of interest for the customer 00 56 93

Switchable PLL capacitors to tune open-loop frequency
Note: All registers except AUTO_FM/AM, A2_Threshold, and CM_Threshold are initialized during STANDARD SELECTION and are
automatically updated when Automatic Sound Select (MODUS[0]=1) is on.
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Table 6–2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable!
Demodulator Address MSP- Description Page

Read Registers (hex) Version
C_AD_BITS 00 23 3410, NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits 92
3450
ADD_BITS 00 38 NICAM: bit [10:3] of additional data bits 92
CIB_BITS 00 3E NICAM: CIB1 and CIB2 control bits 92
ERROR_RATE 00 57 NICAM error rate, updated with 182 ms 93
PLL_CAPS 02 1F Not for customer use 93
AGC_GAIN 02 1E Not for customer use 93
6.2. DSP Write and Read Registers for Manual/Compatibility Mode
Table 6–3: DSP-Write Registers; Subaddress: 12hex, all registers are readable as well
Write Register Address Bits Operational Modes and Adjustable Range Reset Page
(hex) Mode
Volume SCART1 channel: Ctrl. mode 00 07 [7:0] [Linear mode / logarithmic mode] 00hex 94
FM Fixed Deemphasis 00 0F [15:8] [50 µs, 75 µs, J17, OFF] 50 µs 94
FM Adaptive Deemphasis [7:0] [OFF, WP1] OFF 94
Identification Mode 00 15 [7:0] [B/G, M] B/G 95
FM DC Notch 00 17 [7:0] [ON, OFF] ON 95
Volume SCART2 channel: Ctrl. mode 00 40 [7:0] [Linear mode / logarithmic mode] 00hex 94
Table 6–4: DSP Read Registers; Subaddress: 13hex, all registers are not writable
Additional Read Registers Address Bits Output Range Page

(hex)
Stereo detection register for 00 18 [15:8] [80hex ... 7Fhex] 8 bit two’s complement 95
A2 Stereo Systems
DC level readout FM1/Ch2-L 00 1B [15:0] [8000hex ... 7FFFhex] 16 bit two’s complement 95
DC level readout FM2/Ch1-R 00 1C [15:0] [8000hex ... 7FFFhex] 16 bit two’s complement 95
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6.3. Manual/Compatibility Mode: 6.3.1.1. Function in Automatic Sound Select Mode

Description of Demodulator Write Registers
The Automatic Sound Select feature (MODUS[0]=1)
6.3.1. Automatic Switching between NICAM and includes the procedure mentioned above. By default, the
Analog Sound internal ERROR_RATE threshold is set to 700dec. i.e.:
– NICAM → analog Sound if ERROR_RATE > 700
In case of bad NICAM reception or loss of the
NICAM-carrier, the MSP 44x0G offers an Automatic – analog Sound → NICAM if ERROR_RATE < 700/2
Switching (fall back) to the analog sound (FM/AM-
mono), without the necessity for the controller of reading The ERROR_RATE value of 700 corresponds to a
and evaluating any parameters. If a proper NICAM sig- BER of approximately 5.46*10-3 /s.
nal returns, switching back to this source is performed
automatically as well. The feature evaluates the NICAM Individual configuration of the threshold can be done
ERROR_RATE and switches, if necessary, all output using Table 6–5. However, the internal setting used by
channels which are assigned to the NICAM-source, to the standard selection is recommended.
the analog source, and vice versa.
The optimum NICAM sound can be assigned to the
An appropriate hysteresis algorithm avoids oscillating MSP output channels by selecting one of the “Stereo
effects (see Fig. 6–1). STATUS[9] and C_AD_BITS[11] or A/B”, “Stereo or A”, or “Stereo or B” source chan-
(Address: 0023hex) provide information about the actual nels
NICAM-FM/AM-status.
6.3.1.2. Function in Manual Mode

Selected Sound
If the manual mode (MODUS[0]=0) is required, the
activation and configuration of the Automatic Switching
NICAM
feature has to be done as described in Table 6–6.
Note that the channel matrix of the corresponding out-
put-channels must be set according to the
analog NICAM-mode and need not to be changed in the FM/
sound ERROR_RATE
threshold/2 threshold AM-fallback case.
Fig. 6–1: Hysteresis for Automatic Switching Example:

Required threshold = 500: bits[10:1] = 00 1111 1010
Table 6–5: Coding of Automatic NICAM/Analog Sound Switching;

Automatic Sound Select is on (MODUS[0] = 1)
Mode Description AUTO_FM [11:0] ERROR_RATE- Source Select:

Addr. = 00 21hex Threshold/dec Input at NICAM Path1)
1 Automatic Switching with bit[11:0] = 0 700 NICAM or FM/AM,

Default internal threshold depending on
ERROR_RATE
2 Automatic Switching with bit[11] =0 set by customer;
external threshold bit[10:1] = 25...1000 recommended
(Customizing of Automatic = threshold/2 range: 50...2000
Sound Select) bit[0] =1
3 Forced Analog Mono bit[11] =1 always FM/AM

bit[10:1] = ignored
bit[0] =1
1)
The NICAM path may be assigned to “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels
(see Table 2–2 on page 13).
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Table 6–6: Coding of Automatic NICAM/Analog Sound Switching;

Automatic Sound Select is off (MODUS[0] = 0)
Mode Description AUTO_FM [11:0] ERROR_RATE- Source Select:

Addr. = 00 21hex Threshold/dec Input at NICAM Path
0 Forced NICAM bit[11] =0 none always NICAM; Mute in

reset (Automatic Switching disabled) bit[10:1] = 0 case of no NICAM available
status bit[0] =0
1 Automatic Switching with bit[11] =0 700 NICAM or FM/AM,

internal threshold bit[10:1] = 0 depending on
(Default, if Automatic Sound bit[0] =1 ERROR_RATE
Select is on)
2 Automatic Switching with bit[11] =0 set by customer;

external threshold bit[10:1] = 25...1000 recommended
(Customizing of Automatic = threshold/2 range: 50...2000
Sound Select) bit[0] =1
3 Forced Analog Mono bit[11] =1 none always FM/AM

(Automatic Switching disabled) bit[10:1] = 0
bit[0] =1
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6.3.2. A2 Threshold
The threshold between Stereo/Bilingual and Mono

Identification for the A2 Standard has been made pro-
grammable according to the user’s preferences. An
internal hysteresis ensures robustness and stability
.
Table 6–7: Write Register on I2C Subaddress 10hex : A2 Threshold

Address
THRESHOLDS
00 22hex (write) A2 THRESHOLD Register A2_THRESH

Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual
detection
bit[15:0] 07F0hex force Mono Identification
...
0190hex default setting after reset
...
00A0hex minimum Threshold for stable detection
recommended range : 00A0hex...03C0hex
6.3.3. Carrier-Mute Threshold
The Carrier-Mute threshold has been made program-

mable according to the user’s preferences. An internal
hysteresis ensures stable behavior.
Table 6–8: Write Register on I2C Subaddress 10hex : Carrier-Mute Threshold

Address
THRESHOLDS
00 24hex (write) Carrier-Mute THRESHOLD Register CM_THRESH

Defines threshold for the carrier mute feature
bit[15:0] 0000hex Carrier-Mute always ON (both channels muted)
...
002Ahex default setting after reset
...
07FFhex Carrier-Mute always OFF
(both channels forced on)
recommended range : 0014hex...0050hex
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6.3.4. Register AD_CV
The use of this register is no longer recommended.

Use it only in cases where compatibility to the
MSP 34x0D is required. Using the STANDARD
SELECTION register together with the MODUS regis-
ter provides a more economic way to program the
MSP 44x0G.
Table 6–9: AD_CV Register; reset status: all bits are “0”
AD_CV Automatic setting by

(00 BBhex) STANDARD SELECT Register
Bit Function Settings 2-8, 0A-60hex 9
[0] not used must be set to 0 0 0
[1:6] Reference level in case of Automatic Gain 101000 100011

Control = on (see Table 6–10). Constant
gain factor when Automatic Gain Control =
off (see Table 6–11).
[7] Determination of Automatic Gain or 0 = constant gain 1 1

Constant Gain 1 = automatic gain
[8] Selection of Sound IF source 0 = ANA_IN1+ X X

(identical to MODUS[8]) 1 = ANA_IN2+
[9] MSP-Carrier-Mute Feature 0 = off: no mute 1 0

1 = on: mute as de-
scribed in section 2.2.2.
[10:15] not used must be set to 0 0 0
X : not affected while choosing the TV sound standard by means of the STANDARD SELECT Register
Note: This register is initialized during STANDARD SELECTION and is automatically updated when Automatic
Sound Select (MODUS[0]=1) is on.
Table 6–10: Reference Values for Active AGC (AD_CV[7] = 1)
Application Input Signal Contains AD_CV [6:1] AD_CV [6:1] Range of Input Signal
Ref. Value in integer at pin ANA_IN1+
and ANA_IN2+
Terrestrial TV
− FM Standards 1 or 2 FM Carriers 101000 40 0.10 − 3 Vpp1)
− NICAM/FM 1 FM and 1 NICAM Carrier 101000 40 0.10 − 3 Vpp1)
− NICAM/AM 1 AM and 1 NICAM Carrier 100011 35 0.10 − 1.4 Vpp
(recommended: 0.10 − 0.8 Vpp)
− NICAM only 1 NICAM Carrier only 010100 20 0.05 − 1.0 Vpp
SAT 1 or more FM Carriers 100011 35 0.10 − 3 Vpp1)
ADR FM and ADR carriers see DRP 3510A data sheet

1)
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the
robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or
FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.
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Table 6–11: AD_CV parameters for Constant Input Gain (AD_CV[7]=0)
Step AD_CV [6:1] Gain Input Level at pin ANA_IN1+ and ANA_IN2+
Constant Gain
0 000000 3.00 dB maximum input level: 3 Vpp (FM) or 1 Vpp (NICAM)1)

1 000001 3.85 dB
2 000010 4.70 dB
3 000011 5.55 dB
4 000100 6.40 dB
5 000101 7.25 dB
6 000110 8.10 dB
7 000111 8.95 dB
8 001000 9.80 dB
9 001001 10.65 dB
10 001010 11.50 dB
11 001011 12.35 dB
12 001100 13.20 dB
13 001101 14.05 dB
14 001110 14.90 dB
15 001111 15.75 dB
16 010000 16.60 dB
17 010001 17.45 dB
18 010010 18.30 dB
19 010011 19.15 dB
20 010100 20.00 dB maximum input level: 0.14 Vpp
1)
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result. Due to the
robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or
FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.
6.3.5. Register MODE_REG
Note: The use of this register is no longer recom-

mended. It should be used only in cases where soft-
ware compatibility to the MSP 34x0D is required.
Using the STANDARD SELECTION register together
with the MODUS register provides a more economic
way to program the MSP 44x0G.
As soon as this register is applied, the MSP 44x0G

works in the MSP 34x0D Manual/Compatibility
Mode. In this mode, BTSC, EIA-J, and FM-Radio are
disabled. Only MSP 34x0D features are available; the
use of MODUS and STATUS register is not allowed.
The MSP 44x0G is reset to the normal mode by first
programming the MODUS register, followed by trans-
mitting a valid standard code to the STANDARD
SELECTION register.
The register ‘MODE_REG’ contains the control bits

determining the operation mode of the MSP 44x0G in
the MSP 34x0D Manual/Compatibility Mode; Table 6–
12 explains all bit positions.
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Table 6–12: Control word ‘MODE_REG’; reset status: all bits are “0”
MODE_REG 00 83hex Automatic setting by

STANDARD SELECT Register
Bit Function Comment Definition 2-5 8, A, B 9
[0] not used 0 : must be used 0 0 0
[1] DCTR_TRI Digital control out 0 : active X X X

0/1 tri-state 1 : tri-state
[2] I2S_TRI I2S outputs tri-state 0 : active X X X

(I2S_CL, I2S_WS, 1 : tri-state
I2S_DA_OUT)
[3] I2S Mode1) Master/Slave mode 0 : Master X X X

of the I2S bus 1 : Slave
[4] I2S_WS Mode WS due to the Sony or 0 : Sony X X X

Philips-Format 1 : Philips
[5] Audio_CL_OUT Switch 0 : on X X X

Audio_Clock_Output 1 : tri-state
to tri-state
[6] NICAM1) Mode of MSP-Ch1 0 : FM 0 1 1

1 : Nicam
[7] not used 0 : must be used 0 0 0
[8] FM AM Mode of MSP-Ch2 0 : FM 0 0 1

1 : AM
[9] HDEV High Deviation Mode 0 : normal 0 0 0

(channel matrix must be 1 : high deviation mode
sound A)
[11:10] not used 0 : must be used 0 0 0
[12] MSP-Ch1 Gain see also Table 6–14 0 : Gain = 6 dB 0 0 0

1 : Gain = 0 dB
[13] FIR1-Filter see also Table 6–14 0 : use FIR1 1 0 0

Coeff. Set 1 : use FIR2
[14] ADR Mode of MSP Ch1/ 0 : normal mode/tri-state 0 0 0

ADR-Interface 1 : ADR-mode/active
[15] AM-Gain Gain for AM 0 : 0 dB (default. of MSPB) 1 1 1

Demodulation 1 :12 dB (recommended)
1)
NICAM and I2S-Master mode are not allowed simultaneously X: not affected by
STANDARD SELECT register
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Table 6–13: Loading sequence for FIR-coefficients ally by the control processor via the control bus. Two
not necessarily different sets of coefficients are
FIR1 00 01hex (MSP-Ch1: NICAM/FM2)
required: one for MSP-Ch1 (NICAM or FM2) and one
for MSP-Ch2 (FM1 = FM-mono). In Table 6–14 several
No. Symbol Name Bits Value coefficient sets are proposed.
1 NICAM/FM2_Coeff. (5) 8 To load the FIR-filters, the following data values are to
be transferred 8 bits at a time embedded
2 NICAM/FM2_Coeff. (4) 8 LSB-bound in a 16-bit word.
3 NICAM/FM2_Coeff. (3) 8
see Table 6–14 The loading sequences must be obeyed. To change a
4 NICAM/FM2_Coeff. (2) 8 coefficient set, the complete block FIR1 or FIR2 must
be transmitted.
Note: For compatibility with MSP 3410B, IMREG1 and
IMREG2 have to be transmitted. The value for
FIR2 00 05hex (MSP-Ch2: FM1/AM) IMREG1 and IMREG2 is 004. Due to the partitioning to
8-bit units, the values 04hex, 40hex, and 00hex arise.
No. Symbol Name Bits Value
1 IMREG1 8 04hex 6.3.7. DCO-Registers

2 IMREG1/ IMREG2 8 40hex
3 IMREG2 8 00hex mended. It should be used only in cases where soft-
ware-compatibility to the MSP 34x0D is required.
4 FM/AM_Coef (5) 8 Using the STANDARD SELECTION register together
with the MODUS register provides a more economic
5 FM/AM_Coef (4) 8 way to program the MSP 44x0G.
6 FM/AM_Coef (3) 8
see Table 6–14 When selecting a TV-sound standard by means of the
7 FM/AM_Coef (2) 8 STANDARD SELECT register, all frequency tuning is
performed automatically.
8 FM/AM_Coef (1) 8
If manual setting of the tuning frequency is required, a
9 FM/AM_Coef (0) 8 set of 24-bit registers determining the mixing frequen-
cies of the quadrature mixers can be written manually
into the IC. In Table 6–15, some examples of DCO
registers are listed. It is necessary to divide them up
into low part and high part. The formula for the calcula-
6.3.6. FIR-Parameter, Registers FIR1 and FIR2 tion of the registers for any chosen IF frequency is as
follows:
mended. It should be used only in cases where soft- INCRdec = int(f/fs ⋅ 224)
ware compatibility to the MSP 34x0D is required.
Using the STANDARD SELECTION register together with: int = integer function
with the MODUS register provides a more economic f = IF frequency in MHz
way to program the MSP 44x0G. fS = sampling frequency (18.432 MHz)
Data-shaping and/or FM/AM bandwidth limitation is Conversion of INCR into hex-format and separation of
performed by a pair of linear phase Finite Impulse the 12-bit low and high parts lead to the required regis-
Response filters (FIR-filter). The filter coefficients are ter values (DCO1_HI or _LO for MSP-Ch1, DCO2_HI
programmable and are either configured automatically or LO for MSP-Ch2).
by the STANDARD SELECT register or written manu-
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Table 6–14: 8-bit FIR-coefficients (decimal integer) for MSP 34x0D; reset status: all coefficients are “0”
Coefficients for FIR1 00 01hex and FIR2 00 05hex
Terrestrial TV Standards FM - Satellite

FIR filter corresponds to a
band-pass with a band- B
width of B = 130 to 500 kHz
fc frequency
B/G-, D/K- I- L- B/G-, D/K-, 130 180 200 280 380 500 Auto-
NICAM-FM NICAM-FM NICAM-AM M-Dual FM kHz kHz kHz kHz kHz kHz search
Coef(i) FIR1 FIR2 FIR1 FIR2 FIR1 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2
0 −2 3 2 3 −2 −4 3 73 9 3 −8 −1 −1 −1
1 −8 18 4 18 −8 −12 18 53 18 18 −8 −9 −1 −1
2 −10 27 −6 27 −10 −9 27 64 28 27 4 −16 −8 −8
3 10 48 −4 48 10 23 48 119 47 48 36 5 2 2
4 50 66 40 66 50 79 66 101 55 66 78 65 59 59
5 86 72 94 72 86 126 72 127 64 72 107 123 126 126
Mode- 0 0 0 0 1 1 1 1 1 1 0
REG[12]
Mode- 0 0 0 1 1 1 1 1 1 1 0
REG[13]
For compatibility, except for the FIR2-AM and the Autosearch-sets, the FIR-filter programming as used for the MSP 3410B is also possible.
ADR coefficients are listed in the DRP data sheet.
Table 6–15: DCO registers for the MSP 44x0G; reset status: DCO_HI/LO = “0000”
DCO1_LO 00 93hex, DCO1_HI 00 9Bhex; DCO2_LO 00 A3hex, DCO2_HI 00 ABhex
Freq. MHz DCO_HI/hex DCO_LO/hex Freq. MHz DCO_HI/hex DCO_LO/hex
4.5 03E8 000
5.04 0460 0000 5.76 0500 0000

5.5 04C6 038E 5.85 0514 0000
5.58 04D8 0000 5.94 0528 0000
5.7421875 04FC 00AA
6.0 0535 0555 6.6 05BA 0AAA

6.2 0561 0C71 6.65 05C5 0C71
6.5 05A4 071C 6.8 05E7 01C7
6.552 05B0 0000
7.02 0618 0000 7.2 0640 0000
7.38 0668 0000 7.56 0690 0000
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6.4. Manual/Compatibility Mode: Table 6–16: NICAM operation modes as defined by

Description of Demodulator Read Registers the EBU NICAM 728 specification
Note: The use of these register is no longer recom- C4 C3 C2 C1 Operation Mode

mended. It should be used only in cases where soft-
ware compatibility to the MSP 34x0D is required. 0 0 0 0 Stereo sound (NICAMA/B),
Using the STANDARD SELECTION register together independent mono sound (FM1)
with the STATUS register provides a more economic
0 0 0 1 Two independent mono signals
way to program the MSP 44x0G and to retrieve infor- (NICAMA, FM1)
mation from the IC.
0 0 1 0 Three independent mono channels
All registers except C_AD_BITs are 8 bits wide. They (NICAMA, NICAMB, FM1)
can be read out of the RAM of the MSP 44x0G if the
0 0 1 1 Data transmission only; no audio
MSP 34x0D Manual/Compatibility Mode is required.
1 0 0 0 Stereo sound (NICAMA/B), FM1
All transmissions take place in 16-bit words. The valid carries same channel
8-bit data are the 8 LSBs of the received data word.
1 0 0 1 One mono signal (NICAMA). FM1
If the Automatic Sound Select feature is not used, the carries same channel as NICAMA
NICAM or FM-identification parameters must be read 1 0 1 0 Two independent mono channels
and evaluated by the controller in order to enable (NICAMA, NICAMB). FM1 carries
appropriate switching of the channel select matrix of same channel as NICAMA
the baseband processing part. The FM-identification
registers are described in section 6.6.1. To handle the 1 0 1 1 Data transmission only; no audio
NICAM-sound and to observe the NICAM-quality, at x 1 x x Unimplemented sound coding
least the registers C_AD_BITS and ERROR_RATE option (not yet defined by EBU
must be read and evaluated by the controller. Addi- NICAM 728 specification)
tional data bits and CIB bits, if supplied by the NICAM
transmitter, can be obtained by reading the registers AUTO_FM: monitor bit for the AUTO_FM Status:
0: NICAM source is NICAM
ADD_BITS and CIB_BITS.
1: NICAM source is FM
6.4.1. NICAM Mode Control/Additional Data Bits Note: It is no longer necessary to read out and evalu-
Register ate the C_AD_BITS. All evaluation is performed in the
MSP and indicated in the STATUS register.
NICAM operation mode control bits and A[2:0] of the
additional data bits.
6.4.2. Additional Data Bits Register
Format:
Contains the remaining 8 of the 11 additional data bits.
MSB C_AD_BITS 00 23hex LSB The additional data bits are not yet defined by the
11 ... 7 6 5 4 3 2 1 0
NICAM 728 system.
Auto ... A[2] A[1] A[0] C4 C3 C2 C1 S Format:

_FM
MSB ADD_BITS 00 38hex LSB
7 6 5 4 3 2 1 0
Important: “S” = Bit[0] indicates correct NICAM-syn-
A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3]
chronization (S = 1). If S = 0, the MSP 4410/4450G
has not yet synchronized correctly to frame and
sequence, or has lost synchronization. The remaining
read registers are therefore not valid. The MSP mutes
6.4.3. CIB Bits Register
the NICAM output automatically and tries to synchro-
nize again as long as MODE_REG[6] is set.
CIB bits 1 and 2 (see NICAM 728 specifications).
The operation mode is coded by C4-C1 as shown in
Format:
Table 6–16.
MSB CIB_BITS 00 3Ehex LSB
7 6 5 4 3 2 1 0
x x x x x x CIB1 CIB2
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6.4.4. NICAM Error Rate Register 6.4.7. Automatic Search Function for FM-Carrier
Detection in Satellite Mode
ERROR_RATE 00 57hex
The AM demodulation ability of the MSP 4410G and
Error free 0000hex MSP 4450G offers the possibility to calculate the “field
strength” of the momentarily selected FM carrier,
maximum error rate 07FFhex which can be read out by the controller. In SAT receiv-
ers, this feature can be used to make automatic FM
carrier search possible.
Average error rate of the NICAM reception in a time
interval of 182 ms, which should be close to 0. The ini- For this, the MSP has to be switched to AM-mode
tial and maximum value of ERROR_RATE is 2047. (MODE_REG[8]), FM-Prescale must be set to
This value is also active if the NICAM bit of 7Fhex = +127dec, and the FM DC notch (see section
MODE_REG is not set. Since the value is achieved by 6.5.7.) must be switched off. The sound-IF frequency
filtering, a certain transition time (approx. 0.5 sec) is range must now be “scanned” in the MSP-channel 2
unavoidable. Acceptable audio may have error rates by means of the programmable quadrature mixer with
up to a value of 700 int. Individual evaluation of this an appropriate incremental frequency (i.e. 10 kHz).
value by the controller and an appropriate threshold After each incrementation, a field strength value is
may define the fallback mode from NICAM to FM/ available at the quasi-peak detector output (quasi-
AM-Mono in case of poor NICAM reception. peak detector source must be set to FM), which must
be examined for relative maxima by the controller. This
The bit error rate per second (BER) can be calculated results in either continuing search or switching the
by means of the following formula: MSP back to FM demodulation mode.
BER = ERROR_RATE * 12.3*10−6 /s During the search process, the FIR2 must be loaded
with the coefficient set “AUTOSEARCH”, which
enables small bandwidth, resulting in appropriate field
6.4.5. PLL_CAPS Readback Register strength characteristics. The absolute field strength
value (can be read out of “quasi-peak detector output
It is possible to read out the actual setting of the FM1”) also gives information on whether a main FM
PLL_CAPS. In standard applications, this register is carrier or a subcarrier was detected; and as a practical
not of interest for the customer. consequence, the FM bandwidth (FIR1/2) and the
deemphasis (50 µs or adaptive) can be switched
PLL_CAPS 02 1Fhex L accordingly.
minimum frequency 1111 1111 FFhex Due to the fact that a constant demodulation frequency
offset of a few kHz leads to a DC level in the demodu-
nominal frequency 0101 0110 56hex lated signal, further fine tuning of the found carrier can
RESET
be achieved by evaluating the “DC Level Readout
maximum frequency 0000 0000 00hex FM1”. Therefore, the FM DC Notch must be switched
on, and the demodulator part must be switched back to
PLL_CAPS 02 1Fhex H FM-demodulation mode.
PLL open xxxx xxx0 For a detailed description of the automatic search
function, please refer to the corresponding MSP Win-
PLL closed xxxx xxx1
dows software.
6.4.6. AGC_GAIN Readback Register
It is possible to read out the actual setting of

AGC_GAIN in Automatic Gain Mode. In standard
applications, this register is not of interest for the cus-
tomer.
AGC_GAIN 02 1Ehex
max. amplification 0001 0100 14hex

(20 dB)
min. amplification 0000 0000 00hex

(3 dB)
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6.5. Manual/Compatibility Mode: 6.5.2. Volume Modes of SCART1/2 Outputs

Description of DSP Write Registers
Volume Mode SCART1 00 07hex [3:0]
6.5.1. Additional Channel Matrix Modes
Volume Mode SCART2 00 40hex [3:0]
Loudspeaker Matrix 00 08hex L
linear 0000 0hex
Headphone Matrix 00 09hex L RESET
logarithmic 0001 1hex

SCART1 Matrix 00 0Ahex L
SCART2 Matrix 00 41hex L

Linear Mode
I2S Matrix 00 0Bhex L
Volume SCART1 00 07hex H
Quasi-Peak 00 0Chex L
Detector Matrix Volume SCART2 00 40hex H
SUM/DIFF 0100 0000 40hex OFF 0000 0000 00hex

RESET
AB_XCHANGE 0101 0000 50hex
0 dB gain 0100 0000 40hex
PHASE_CHANGE_B 0110 0000 60hex (digital full scale (FS) to 2
VRMS output)
PHASE_CHANGE_A 0111 0000 70hex
+6 dB gain (−6 dBFS to 2 0111 1111 7Fhex
A_ONLY 1000 0000 80hex VRMS output)
B_ONLY 1001 0000 90hex

Note: SCART Volume linear mode will not be sup-
ported in the future (documented for compatibility rea-
sons only).
This table shows additional modes for the channel
matrix registers.
6.5.3. FM Fixed Deemphasis
The sum/difference mode can be used together with
the quasi-peak detector to determine the sound mate-
rial mode. If the difference signal on channel B (right) FM Deemphasis 00 0Fhex H
is near to zero, and the sum signal on channel A (left) 50 µs 0000 0000 00hex
is high, the incoming audio signal is mono. If there is a RESET
significant level on the difference signal, the incoming
audio is stereo. 75 µs 0000 0001 01hex
J17 not available
OFF 0011 1111 3Fhex
Note: This register is initialized during STANDARD

SELECTION and is automatically updated when Auto-
matic Sound Select (MODUS[0]=1) is on.
6.5.4. FM Adaptive Deemphasis
FM Adaptive 00 0Fhex L
Deemphasis WP1
OFF 0000 0000 00hex

RESET
WP1 0011 1111 3Fhex
Note: This register is initialized during STANDARD

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6.5.5. NICAM Deemphasis 6.6. Manual/Compatibility Mode:

Description of DSP Read Registers
A J17 Deemphasis is always applied to the NICAM
signal. It is not switchable. All readable registers are 16-bit wide. Transmissions
via I2C bus have to take place in 16-bit words. Some of
the defined 16-bit words are divided into low and high
6.5.6. Identification Mode for A2 Stereo Systems byte, thus holding two different control entities.
Identification Mode 00 15hex L

These registers are not writable.
Standard B/G 0000 0000 00hex

(German Stereo) RESET 6.6.1. Stereo Detection Register
for A2 Stereo Systems
Standard M 0000 0001 01hex
(Korean Stereo)
Stereo Detection 00 18hex H
Reset of Ident-Filter 0011 1111 3Fhex Register
Stereo Mode Reading

(two’s complement)
To shorten the response time of the identification algo-
rithm after a program change between two FM-Stereo MONO near zero
capable programs, the reset of the ident-filter can be
applied. STEREO positive value (ideal
reception: 7Fhex)
Sequence: BILINGUAL negative value (ideal
1. Program change reception: 80hex)
2. Reset ident-filter
Note: It is no longer necessary to read out and evalu-
3. Set identification mode back to standard B/G or M ate the A2 identification level. All evaluation is per-
4. Wait approx. 500 ms formed in the MSP and indicated in the STATUS regis-
ter.
5. Read stereo detection register
Note: This register is initialized during STANDARD 6.6.2. DC Level Register

DC Level Readout 00 1Bhex H+L
FM1 (MSP-Ch2)
6.5.7. FM DC Notch DC Level Readout 00 1Chex H+L
FM2 (MSP-Ch1)
The DC compensation filter (FM DC Notch) for FM
input can be switched off. This is used to speed up the DC Level [8000hex ... 7FFFhex]
automatic search function (see Section 6.4.7.). In nor- values are 16 bit two’s
complement
mal FM-mode, the FM DC Notch should be switched
on.
The DC level register measures the DC component of
FM DC Notch 00 17hex L the incoming FM signals (FM1 and FM2). This can be
used for seek functions in satellite receivers and for IF
ON 0000 0000 00hex FM frequencies fine tuning. A too low demodulation
Reset frequency (DCO) results in a positive DC-level and
vice versa. For further processing, the DC content of
OFF 0011 1111 3Fhex
the demodulated FM signals is suppressed. The time
constant τ, defining the transition time of the DC Level
Register, is approximately 28 ms.
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6.7. Demodulator Source Channels in Manual Mode
6.7.1. Terrestric Sound Standards
Table 6–17 shows the source channel assignment of

the demodulated signals in case of manual mode for
all terrestric sound standards. See Table 2–2 for the
assignment in the Automatic Sound Select mode. In
manual mode for terrestric sound standards, only two
demodulator sources are defined.
6.7.2. SAT Sound Standards
Table 6–18 shows the source channel assignment of

the demodulated signals for SAT sound standards.
Table 6–17: Manual Sound Select Mode for Terrestric Sound Standards
Source Channels of Sound Select Block
Broadcasted Selected MSP Broadcasted Sound FM Matrix FM/AM Stereo or A/B

Sound Standard Mode (use 0 for channel select) (use 1 for channel select)
Standard Code
B/G-FM 03 MONO Sound A Mono Mono Mono

D/K-FM 04, 05
M-Korea 02 STEREO German Stereo Stereo Stereo
M-Japan 30 Korean Stereo
BILINGUAL, No Matrix Left = A Left = A

Languages A and B Right = B Right = B
B/G-NICAM 08 NICAM not available Sound A Mono1) analog Mono no sound

L-NICAM 09 or NICAM error rate
with AUTO_FM:
I-NICAM 0A too high
analog Mono
D/K-NICAM 0B
D/K-NICAM 0C MONO Sound A Mono1) analog Mono NICAM Mono
(with high 0D
deviation FM) STEREO Sound A Mono1) analog Mono NICAM Stereo
BILINGUAL, Sound A Mono1) analog Mono Left = NICAM A

Languages A and B Right = NICAM B
MONO Sound A Mono Mono Mono
STEREO Korean Stereo Stereo Stereo

20
MONO + SAP Sound A Mono Mono Mono
STEREO + SAP Korean Stereo Stereo Stereo

BTSC
MONO
Sound A Mono Mono Mono
STEREO
21
MONO + SAP Left = Mono Left = Mono
No Matrix
STEREO + SAP
MONO Sound A Mono Mono Mono

FM-Radio 40
STEREO Korean Stereo Stereo Stereo
1)
Automatic refresh to Sound A Mono, do not write any other value to the register FM Matrix!
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Table 6–18: Manual Sound Select Modes for SAT-Standards
Source Channels of Sound Select Block

for SAT-Modes
Broadcasted Selected Broadcasted FM Matrix FM/AM Stereo or A/B Stereo or A

Sound MSP Standard Sound Mode (source select: 0) (source select: 1) (source select: 3)
Standard Code
6, 50hex MONO Sound A Mono Mono Mono Mono
51hex STEREO No Matrix Stereo Stereo Stereo

FM SAT
BILINGUAL No Matrix Left = A (FM1) Left = A (FM1) A (FM1)
Right = B (FM2) Right = B (FM2)
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7. Appendix D: Application Information 7.3. Compatibility Restrictions to MSP 34x0D
7.1. Exclusions of Audio Baseband Features The MSP 44x0G is fully hardware compatible to the
MSP 34x0D. However, to substitute a MSP 34x0D by
In general, all functions can be switched independently. the corresponding MSP 44x0G, the controller software
Two exceptions exist: has to be adapted slightly:
1. NICAM cannot be processed simultaneously with 1. The register FM-Matrix (00 0Ehex low part) must be
the FM2 channel. changed from “no matrix (00hex)” to “sound A mono
(03hex)” during mono transmission of all TV-sound
2. FM adaptive deemphasis cannot be processed
standards (see also Table 6–17).
simultaneously with FM-identification.
2. With the MSP 44x0G, the STANDARD SELECTION
initializes the FM-deemphasis, which is not the case
7.2. Phase Relationship of Analog Outputs for the MSP 34x0D. So, if STANDARD SELECTION
is applied, this I2C instruction can be omitted.
The analog output signals: Loudspeaker, headphone,
and SCART2 all have the same phases. The user
does not need to correct output phases when using
these analog outputs directly. The SCART1 output has
opposite phase.
Using the I2S-outputs for other DSPs or D/A convert-

ers, care must be taken to adjust for the correct phase.
If the attached coprocessor is one of the MSP family,
the following schematics help to determine the phase
relationship.
I2S_IN1/2/3 I2S_OUT
Loudspeaker
Headphone
SCART1-Ch.
Audio
Baseband
SCART1
Processing
SCART1
SCART2 SCART
DSP
SCART3 Input
Select SCART2-Ch.
SCART4 SCART2
MONO
MONO, SCART1...4 SCART

Output Select
Fig. 7–1: Phase diagram of the MSP 44x0G
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7.4. Application Circuit
SIF 2 IN
Tuner 2 if ANA_IN2+ not used
Signal GND C s. section 4.6.2.
10 100
SIF 1 IN µF - nF 8 V(5 V) 100 pF 56 pF
Tuner 1 + ANA_IN1/2+
18.432
3.3 100 MHz
µF nF + + Alternative circuit for
1 kΩ
56 pF 56 pF 56 pF + 10 µF 10 µF SIF-inputs for more
attenuation of video
components:
VREFTOP
CAPL_A
ANA_IN1+
ANA_IN2+
AGNDC
XTAL_IN
ANA_IN-
CAPL_M
XTAL_OUT
1 µF
DACM_L
MONO_IN
330 nF
1 nF 1 µF
DACM_R
LOUD
SC1_IN_L
SPEAKER
330 nF 1 nF 1 µF
SC1_IN_R DACM_SUB
330 nF
AHVSS ASG
1 nF
SC2_IN_L
330 nF
330 nF
SC2_IN_R 1 µF
AHVSS ASG DACA_L
330 nF
SC3_IN_L
1 µF HEAD
1 nF
SC3_IN_R DACA_R
PHONE
330 nF
AHVSS ASG
1 nF
SC4_IN_L
330 nF
330 nF
SC4_IN_R
MSP 44x0G 100 Ω 22 µF
5V SC1_OUT_L
+
5V
STANDBYQ 100 Ω 22 µF
DVSS SC1_OUT_R
+
ADR_SEL
100 Ω 22 µF
DVSS SC2_OUT_L +
I2C_DA
I2C_CL 100 Ω 22 µF
SC2_OUT_R +
ADR_WS
ADR_CL
ADR_DA D_CTR_I/O_0
I2S_WS D_CTR_I/O_1
I2S_CL
I2S_DA_IN1 AUD_CL_OUT
I2S_DA_IN2
I2S_DA_OUT TESTEN
I2S_DA_IN3
AHVSS
I2S_CL3
I2S_WS3
AHVSUP
RESETQ
DVSUP
AVSUP
AHVSS
VREF1
VREF2
DVSS
AVSS
220 470 470

pF pF pF
RESETQ 470 1.5 1.5
pF nF nF
(from Controller, see section 4.6.3.3.) 1.5 10 10
nF µF µF
10
µF
AHVSS
AHVSS
AHVSS
AVSS
5V 5V 8V
(5 V)
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8. Appendix E: MSP 44x0G Version History 9. Data Sheet History
1. Preliminary data sheet: “MSP 44x0G Multistandard

MSP 3450G-B8 Sound Processor Family”, May 16, 2001,
6251-533-1PD. First release of the preliminary data
First release for Multichannel application together with sheet.
DPL 4519G and MAS 3528E.
Micronas GmbH All information and data contained in this data sheet are without any
Hans-Bunte-Strasse 19 commitment, are not to be considered as an offer for conclusion of a
D-79108 Freiburg (Germany) contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
P.O. Box 840 and delivery are exclusively subject to our respective order confirmation
D-79008 Freiburg (Germany) form; the same applies to orders based on development samples deliv-
Tel. +49-761-517-0 ered. By this publication, Micronas GmbH does not assume responsibil-
Fax +49-761-517-2174 ity for patent infringements or other rights of third parties which may
E-mail: docservice@micronas.com result from its use.
Internet: www.micronas.com Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
Printed in Germany No part of this publication may be reproduced, photocopied, stored on a
Order No. 6251-533-1PD retrieval system, or transmitted without the express written consent of
Micronas GmbH.
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PRELIMINARY DATA SHEET

MICRONAS MSP 44x0G

Page Section Title

Page Section Title

20 3.2. Start-Up Sequence: Power-Up and I2C-Controlling

Page Section Title

78 5. Appendix A: Overview of TV-Sound Standards

82 6. Appendix B: Manual/Compatibility Mode

Page Section Title

98 7. Appendix D: Application Information

100 8. Appendix E: MSP 44x0G Version History

100 9. Data Sheet History

1. Introduction The MSP 44x0G has built-in automatic functions: The

Sound IF1 Loud- Loud-

Fig. 1–1: Block diagram of the MSP 44x0G

1.1. Features of the MSP 44x0G Family and Differences to MSPD

48 kHz sampling rate X X X X

20 kHz audio band width X X X X

Standard Selection with single I2C transmission X X X X

Automatic Standard Detection of terrestrial TV standards/Automatic Carrier Mute function X X X X

Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS X X X X

Two selectable sound IF (SIF) inputs X X X X

Automatic Carrier Mute function X X X X

Interrupt output programmable (indicating status change) X X X X

Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness X X X X

Loudspeaker channel with MDB (Micronas Dynamic Bass) X X X X

AVC: Automatic Volume Correction X X X X

Subwoofer output with programmable low-pass and complementary high-pass filter X X X X

5-band graphic equalizer for loudspeaker channel X X X X

Spatial effect for loudspeaker channel X X X X

Complete SCART in/out switching matrix X X X X

Three I2S inputs; one I2S output X X X X

3rd digital input (I2S3) with multichannel capability X X X X

Digital output with multichannel capability X X X X

All analog Mono sound carriers including AM-SECAM L X X X X

All analog FM-Stereo A2 and satellite standards X X

Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM X X

Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) X X

ASTRA Digital Radio (ADR) together with DRP 3510A X X

All NICAM standards X X

Demodulation of the BTSC multiplex signal and the SAP channel X X X

BTSC and EIA-J stereo separation significantly better than spec. X X X

SAP and stereo detection for BTSC system X X X

Korean FM-Stereo A2 standard X X X X

Alignment-free Japanese standard EIA-J X X X

Demodulation of the FM-Radio multiplex signal X X X

1.2. MSP 44x0G Version List

Table 1–1: MSP 44x0G Version List

Version Status Description

MSP 4410G not confirmed NICAM and FM Stereo (A2) Version

MSP 4450G available Global Version (all sound standards)

1.3. MSP 44x0G Versions and their Application Fields

Table 1–2 provides an overview of TV sound stan-

5.5/5.7421875 FM-Stereo (A2) PAL Germany

L 6.5/5.85 AM-Mono/NICAM SECAM-L France

I 6.0/6.552 FM-Mono/NICAM PAL UK, Hong Kong

6.5/6.2578125 FM-Stereo (A2, D/K1) SECAM-East Slovak. Rep.

6.5/6.7421875 FM-Stereo (A2, D/K2) PAL currently no broadcast