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Hex Non-Inverted Buffers With Open-Collector Outputs: IN74LS07

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TECHNICAL DATA

IN74LS07

Hex Non-Inverted Buffers with Open-


Collector Outputs

This device contains hex non inverted buffers with open-collector. It


performs the Boolean function Y=A in positive Logic.
• High Output Voltage (30 V)
• High Speed ( tPD = 12 ns typical)
• Low Power Dissipation (PD = 13 mW per Gate)

ORDERING INFORMATION
IN74LS07N Plastic
IN74LS07D SOIC
TA = 0° to 70° C for all
packages

LOGIC DIAGRAM

PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output
A Y
H H
L L

PIN 14 =VCC
PIN 7 = GND

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IN74LS07

MAXIMUM RATINGS*

Symbol Parameter Value Unit


VCC Supply Voltage 7.0 V
VIN Input Voltage 5.5 V
VOUT Output Voltage 30 V
Tstg Storage Temperature Range -65 to +150 °C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.

RECOMMENDED OPERATING CONDITIONS


Symbol Parameter Min Max Unit
VCC Supply Voltage 4.75 5.25 V
VIH High Level Input Voltage 2.0 V
VIL Low Level Input Voltage 0.8 V
VOH High Level Output Voltage 30 V
IOL Low Level Output Current 40 mA
TA Ambient Temperature Range 0 +70 °C

DC ELECTRICAL CHARACTERISTICS over full operating conditions


Guaranteed Limit
Symbol Parameter Test Conditions Min Max Unit
VIK Input Clamp Voltage VCC = min, IIN = -18 mA -1.5 V
IOH High Level Output Current VCC = min, VOH= max 250 µA
VOL Low Level Output Voltage VCC = min, IOL = 16 mA 0.4 V
VCC = min, IOL = 40 mA 0.7
IIH High Level Input Current VCC = max, VIN = 2.7 V 20 µA
VCC = max, VIN = 5.5 V 1 mA
IIL Low Level Input Current VCC = max, VIN = 0.4 V -0.2 mA
ICC Supply Current VCC = max Total with 14 mA
outputs high
Total with 45
outputs low

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IN74LS07

AC ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF,


RL = 110 Ω,tr = 15 ns, tf = 6.0 ns)
Symbol Parameter Min Max Unit
tPLH Propagation Delay, Input A to Output Y 10 ns
tPHL Propagation Delay, Input A to Output Y 30 ns

Figure 1. Switching Waveforms

NOTE A. CL includes probe and jig capacitance.

Figure 2. Test Circuit

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