A Dynamic Performance Study of an HVDC System using … 319

JPE 5-4-9

A Dynamic Performance Study of an HVDC System using

a Hybrid Simulator

Chan-Ki Kim†, Byeong-Mo Yang* Hahk-Sung Lee**

†
Korea Electric Power Research Institute(KEPRI), Power System Research Laboratory,
Munji Dong 106-16, Yuseong-Gu, Daejon 305-380, Korea
**
Hyosung Industrial

ABSTRACT

This paper deals with the development of a new type of simulator for the study of the dynamic performance of an
HVDC scheme. The new simulator uses a digital model of the power equipment and an analogue model of the existing
HVDC controller. This simulator is used to study the dynamic performance of the Cheju - Haenam HVDC system and to
verify the control characteristics of the HVDC system. The paper discusses the simulator development requirements and
criteria. The paper provides guidelines for the development of the simulator and presents the results of the simulation
studies.

Keywords: HVDC, Hybrid Simulator

1. Introduction advantage of the characteristics of the HVDC system, and

applying these appropriately, an HVDC system can
Fast acting power equipment like HVDC, SVC and enhance the operation and stability of the ac networks.
FACTS can be used to significantly improve the The CHEJU-HAENAN 300MW HVDC system was
performance of an AC network. However, to ensure that completed in Korea in 1998. The HVDC system transmits
such equipment is used to the maximum advantage of the relatively cheap electric power by submarine DC cables
ac network, an accurate simulator is required by planning from the Haenam substation on mainland Korea to the
engineers for system analysis and also for the training of Cheju substation on Cheju Island, a distance of 100km.
system operators. For example, if an HVDC system is The power transmitted on the 12-pulse bipolar HVDC
designed and operated with the sole objective of system is normally a maximum of 150 MW, which
transmitting power between ac networks, it may under corresponds to 60% of the total load demand on Cheju
some conditions be detrimental to the operation and Island. The control of the operation of the inverter at
stability of the ac network. However, by taking full Cheju is normally current control (main control), with
mean γ control used as the secondary control. DC
Manuscript received June 13, 2005; revised August 9, 2005 voltage control is used as the main control at the rectifier
†
Corresponding Author: ckkim@kepri.re.kr, KEPRI at Haenam, with current control as the secondary control.
Tel: +82-42-865-5871, Fax: +82-42-865-5844
*
Korea Electric Power Research Institute(KEPRI) For most other HVDC schemes in the world the main
**
Hyosung Industrial control for the rectifier is dc current control with the

Copyright (C) 2006 NuriMedia Co., Ltd.

 320 Journal of Power Electronics, Vol. 5, No. 4, October 2005

inverter in dc voltage control. The unusual arrangement of 2. The Simulator Approach

the controls for the Cheju-Haenam HVDC scheme was
developed to enable the scheme to operate as the sole The approach taken usually depends on the simulation
power supply to Cheju, without the use of tool used and how the model is going to be used.
telecommunication [7]. Reactive power compensation for
the Cheju side is provided by an ac harmonic filter and MODULATION SIGNAL AND
CONSTANT FREUQENCY
CONSTANT POWER LOOP CONTROL
shunt capacitor banks in steady state while synchronous VDCOL
TYPE OF
CONTROL

compensators provide dynamic reactive power CONSTANT CURRENT LOOP

FIRING CONTROL

compensation at the inverter terminal. LIMITS

C
At present the power consumption on Cheju is
increasing at 7% per year. To meet the increasing demand HARMONIC
INSTABILITY
TYPE OF
INTERACTION

the construction of an additional HVDC system is planned, LEVEL OF

CONTROL
RECOVERY &
as well as the addition of renewable energy of about OVERVOLTAGES

VALVE AND STABILITY

100MW to the Cheju AC network. FIRING
(=1ms)
The main objective of this paper is to describe the POLE MASTER
(10 to 500ms) (up to 10s)
approach taken to develop an accurate simulator of the
Fig. 1 Relation between simulation time and HVDC control
Cheju-Haenam HVDC system that can be used for level and interactions
detailed system analysis. The simulator will be used to
simulate several HVDC faults and to study the HVDC The actual HVDC controls for the existing HVDC
modification. The simulator objective is to capture the scheme are partly digital and partly analog (OpAmps,
system response for frequencies from DC to several kilo Transistors, Resistors and Capacitors).
Hertz. Since we depended on the exact instantaneous At the outset, it was decided that the controls are going
wave-shapes for our analysis, we needed to use an RTDS to be modeled exactly as in the actual system to represent
(Real Time Digital Simulator) with the most detailed its analog and digital behavior. The important factors in
representation of electrical components and the HVDC the simulator development are as follows:
valves.

RTDS

Control Phase Firing Firing Phase

MASTER PCCS Pole #1 Pole #1 PCCS MASTER
Desk Controller Control Control Controller

Phase Firing Firing Phase

PCCS Pole #2 Pole #2 PCCS
Controller Control Control Controller

Inverter Rectifier

. Filter
. .
. .
.
Filter
.
.
.

AC Network AC Network
(Inverter) (Rectifier)

Fig. 2 HVDC simulator configuration

Copyright (C) 2006 NuriMedia Co., Ltd.

 A Dynamic Performance Study of an HVDC System using … 321

• Real time or non-real time

Loop Controller Gain PLO Comparator

R2 R4
C1
Idc

Iref
R1

R1
―
+
R3
―
+
R5
― ―
• Simulation time
+

• Simulation scope(Overvoltage/Harmonic stability)

+

2[V]

K1 K2 K3 K4 • Software implementation or Hardware implementation

(a) • Accuracy
Among the above factors, the simulation scope and the
K1 K2 K3 K4
simulation time were determined by the relation between
(b)
simulation time and the HVDC control level as shown in
figure 1. In the HVDC control system, VBE (Valve Based
G1
Electronics) generates the pulse train by which the
G1 = K1 · K2 · K3 · K4 thyristors get gate signals. VBE does not have crucial
effects on the transient performance of the HVDC system;
(c)
hence, it is not represented in detail.
Where, K1 : Loop Control gain 1 =  − R2  The selection of hardware implementation or software
 R1 
implementation was determined from the viewpoint of
 R4 
K 2 : Loop Control gain 2 =  − , cost. Therefore, in this paper the AC network including
 R3 
1 generators, the HVDC valves, converter transformers and
K 3 : The gain of PLO =
(12 × fo (60 Hz ) × R5 × C1 ) ac harmonic filters were implemented using an RTDS
1 (Real Time Digital Simulator) and the HVDC controller
K 4 : Comparator level =
2[V ] was implemented using an actual system as shown in
figure 2. The implementation of the HVDC controller was
R2 C1
1
done in two ways. First, the performance of the HVDC
R1 system using the reduced control model as shown in figure
3 was analyzed mathematically. Using this method, we
R3 C2
2
R7 can estimate the system stability and the harmonic
R4 stability. Secondly, the signal waveform of the actual
3 ―
+
6 controller was measured by using an oscilloscope as
R5
4 shown in figure 4. The measured waveforms were
R6 compared with the waveform of the implemented
5
simulator controller.
(d) Where, 1. 3-phase voltage, 2. Firing pulse, 3. Alpha
s · T31
error, 4. Control reference, 5.Voltage controller error,
1 + s · T32 6.Current error, 7.Alpha max controller error, 8. Alpha
(e) response, 9. Gamma response

Where, *Input 1 :Vdc , 3: γ ord , 4:γ response

* Output 6: γ output
R7 R
Output = − ⋅ γ response + − 7 ⋅ γ ord
R5 R4
1
+ ( − A ⋅ R7 ) / ( R2 + ) ⋅Vdc
s ⋅ C1
T31 = ( A ⋅ R7 ) ⋅ C1 , T32 = R2 ⋅ C1
A = M p 9 ⋅ R35 / ( R33 ⋅ (−7.5 − M p 9) + M p 9 ⋅ R35 )
= Setting gain due to variable resistance
Fig. 3 Reduced model of an HVDC controller Fig. 4 Actual HVDC controller waveforms

Copyright (C) 2006 NuriMedia Co., Ltd.

 322 Journal of Power Electronics, Vol. 5, No. 4, October 2005

3. Control Characteristics power to the Cheju system when this mode is selected.
This control operation can be described as in equation. (2).
• Master control
The master control is the uppermost control in the Porder
I order = (2)
HVDC system, and it determines the filter switching mode, Vdc
the power transfer direction, and the control mode. This
control doesn't affect the transient performance of the Where Iorder is the current order from the power control,
HVDC system since the time constant of the master Porder is the DC power order, and Vdc is the DC voltage
control is only a few seconds. value.

• Pole Control • Current Control

Figure 5 shows the block diagram of the pole control. Current control generates the current order value, and is
Pole control receives the signal of the control mode and adopted as the main control on the Cheju side (Inverter).
power transfer direction from the master control, which Input of the current control depends on the HVDC
sends the corresponding control signal to the phase control. operation mode: For example, the current order is
Detailed descriptions of each part are as follows. generated from current control when the HVDC system is
in current control mode, and the output value of pole
• Frequency Control
control or frequency control becomes the input for current
The frequency of the Cheju power system is controlled
control.
by regulating the power delivered from the dc line when
• Voltage Control
the control mode is in frequency mode. It corresponds to
the governor free operation of the turbine-generator. This Voltage control acts as the main control on the Haenam
control is based on the speed-droop characteristic of the side (Rectifier), while it is used as an overvoltage limiter
HVDC system, and can be expressed like equation (1). on the Cheju side.
• Current Balancing

Forder ( Hz ) = Fdemand ( Hz ) −  Pdc( MW ) ∗ Slope(%) ∗
0 ⋅ 6  Hz  (1) Current balancing is the function to minimize the current
150  MW 
   on the neutral line when the HVDC system is in bi-pole
operation.
Where, Forder (Hz) is the frequency output value, Fdemand
• Blocking Control
(Hz) is the frequency order value, Pdc (MW) is the DC
Blocking control issues control signals such as Block D,
power, and slope (%droop) is the speed-droop
Bypass and forced retard signals when system failures
characteristic of the system.
occur.
• Auxiliary Loop Control - Pole Control
Frequency Current I order Loop control of the pole control blocks the HVDC
M a s t e r C o n tr o l

Control Control
system with the blocking control. In the loop control the
(+)
I_balance Alpha min.
Loop Control Gam. Disable Phase Control
α-min value is regulated to attain the fast restoration rate,
Current I_balance(-)
and the control prevents the failure from being propagated.
Balancing
Voltage V order
Contro1
Power
A. Phase Control
Control Bypass Figure 6 shows the block diagram of phase control in
Blacking Block D
Loop Control
Control Forced the HVDC system.
Retard

Fig. 5 Block diagram of the pole control HVDC simulator • AC Voltage Measurement
configuration This card generates a Y-Δ voltage signal with a 30
degree angle difference from the 3 phase signal of VT
• Power Control since measurements of the phase angle of the AC input
The HVDC line delivers a constant scheduled value of voltage are required for the phase control system.

Copyright (C) 2006 NuriMedia Co., Ltd.

 A Dynamic Performance Study of an HVDC System using … 323

Line
Winding
AC Voltage
Measurement
Viw A
Viw B
extinction angle using the closed loop.
Volts Viw C
Valve
Timing
α−pair signals 6
α,γ
pair • Alpha Balance
Voltages Osillator Pulses signals

α balance is similar to γ balance, and it is used at the

6
CG1
(VG Protection)
R/I
di 6 Phase γ−pair signals 6
Gamma
dt Limit Q1 CG6
Block D
2 Balancing
rectifier. Unbalance in the AC system changes the α
α & γ response
γ monitoring
Reset Suppression
Forced Reset
Reset
value, and it enlarges the second harmonic of the AC
Loop
Loop
Error
Signals
12
Start
system. The alpha balancing controls the gating time of
Control Loop Oscillator Ring
(Valve Control)
Signals
(From PCCS)
Control Counter
12
Stop
the 2 valves at each phase.
• Loop Control
α ADVANCE
Bypass
Bypass Fail

Alpha
Balancing
Block D
Bypass
Reselection
Intiated
Loop control in phase control generates an error signal
Block D by comparing the order value with the measured value.
I order
R/I
3rd
Harmonic
• Oscillator
Viw A Balancing

The oscillator generates gate pulses at an equal interval.

Viw B
Viw C

Fig. 6 Block diagram of the phase control

The pulse depends on the maximum value of the error
from the loop control. The Max./Min. selector or
Permission Logic is built using AND/OR logic. The
• Phase Limit
permission logic in Figure 8 is the Max/Min selector
The phase limit card has the forced firing circuit which
which determines the HVDC system mode. The oscillator
forces the firing angle to be between 2 and 182 degrees,
has the forced reset signal from the phase limit and the
and calculates the values of α and γ. The permission reset suppression signal, and both signals related with the
logic of the oscillator receives a signal from the phase permission logic ensure that the gate signals are in the
limit. range of 2 – 180 degrees.
• Gamma Balance • Ring Counter
The values of the three-phase voltage are unbalanced in The ring counter converts the pulse from the oscillator
the strict sense although they are generally assumed to be into the gating signal, and it has a Block D command and
balanced. Hence, the values of α and γ don’t coincide a bypass command.
in steady state. Instability of γ control is caused by γ
gain (sin α /sin γ ); a trend in which ∂ α / ∂ γ becomes 4. The System Performance
positive results in a repeated commutation failure. This
problem can be resolved by igniting 12 valves at the same Figure 6 shows the control characteristics of the HVDC

RTDS
· Valve
· DC Line
Digital Controller · C.Tr
Analog Card
· Master Control · Filter · Phase Controller
· PCCS · AC계통 · Protection
· Rack #2

Monitering
Control Desk · MPM
· Inverter · SER
· DTR

Fig. 7 HVDC simulator

Copyright (C) 2006 NuriMedia Co., Ltd.

 324 Journal of Power Electronics, Vol. 5, No. 4, October 2005

Forced
Decision Logic
V dc
p.u.
Reset
Reset
Suppression

In Error
-G +
(Loop 1)
R Y
-
A Y'
1.0 Y''
Ud (inv) Error
-G + B D
(Loop 2)
R
C
-
X''
Mean γ
(Loop 3)
-G + Pulse Reset X''
R -

X
α MAX Error
(Loop 4)
-G + Pulse W LVCL1
R -
Generator
Oscillator 0.4
Pulses
LVCL2
AC Volt Error E
(Loop 5)
-G +
0.2 D'
R - C'

LVCC
Ud (rect) Error
F I dc
-G +
(Loop 7)
R -
0 0.3 I ord 1.2 1.3 1.8 1.9 p.u.
Scheme Imax I max
0.04 0.1
Inv Rect
α MIN Error
(Loop 8)
-G +
R -
Fig. 9 Cheju-Haenam HVDC characteristics
Analogue Reset

Ramp -OV - -Vf

Genterator +
+

S/H Frequency
++
+
transient state. This selection is performed in the
Limit

Minimum Value Selector, and the smaller value is chosen

150ms
Vf

3rd Harmonic
Balance
γ balance
by comparing the control output of both controls.
α balance

Fig. 8 Oscillator 5. Hvdc System Analysis

Figure 6 shows the control characteristics of the HVDC B. The Need for Simulation
system between Cheju and Haenam. ABCC'EF represents Every simulation requires system modeling, and the
constant voltage control which is performed when the complexity of the model depends on the simulation
current is less than the rated current (1.0p.u). The control purpose. In this paper, the purpose of the simulation is
mode is changed to current mode when the voltage at the mainly the analysis of the transient performance of the
inverter drops or the current is over 1.3p.u. The line from
system, so 50μs is used for the sampling time. RTDS,
B to C has the same slope as the YY'Y" line in order to
which is used in this paper, is a popular program to
ensure one operating point when the voltage of the
analyze transient and dynamic characteristic in power
inverter drops. This slope is determined by the %
systems.
impedance of the transformer. The curve C'EF is known as
the VDCL (Voltage Dependant Current Limit), and it
C. Simulation Results
limits the current according to the voltage drop due to the
A simulation was performed for the condition where the
failure in the AC system. The curve Y"Y'YXW0
rated voltage of a pole is 180 kV and the rated current is
represents the characteristic of the inverter. The curve YX
416A. Saturation effects of transformers, harmonic
corresponds to current control, and the curve YY'Y" to
characteristics of AC systems, and current unbalance
average γ control. The curve XW0 is the VDCL, and the
between poles are not considered in this simulation.
slope is determined by the AC system condition. The simulation scenarios are to analyze the performance
The slope of the curve XW0 is different from the curve of the power modes in the HVDC systems. The AC
CEF in the convertor, and it helps keep the system stable network condition of this scenario is the same as below
when the SCR of an AC system is small. The selection of
• AC network total load: 300MW,
current control or voltage control is performed at the
• HVDC system power transfer: 150MW
Maximum Value Selector by comparing the output control
• Local AC generator: 75 ⅹ 2
values from both controls. In the inverter there is a current
control loop and an average γ control loop, and the • Synchronous Compensator (S.C): 55MVA ⅹ 2
former is used in steady state and the latter is used in • Frequency source of HVDC is from S.C

Copyright (C) 2006 NuriMedia Co., Ltd.

 A Dynamic Performance Study of an HVDC System using … 325

(a) Load Rejection (power mode) (a)

(b) 3-phase fault (power mode)

(c) Enlargement of (a)

Fig. 11 Remote fault of HVDC system (Commutation Failure)

(C) 3-phase fault (frequency mode)

Fig. 10 Power mode operation and frequency mode

operation of HVDC system Fig. 12 1-valve fault of HVDC system

Copyright (C) 2006 NuriMedia Co., Ltd.

 326 Journal of Power Electronics, Vol. 5, No. 4, October 2005

(a) Synchronous Compensator Shaft fed (c) Synchronous Compensator Shaft fed

(b) AC voltage Bus fed (d) AC voltage Bus fed

Fig. 13 HVDC operating characteristics according to a change in frequency source

The reason for this scenario is that the HVDC had black measurement point of the HVDC controller is the shaft of
start capability originally, so the frequency source of the synchronous compensator; (b) is on the AC network
HVDC comes from a synchronous compensator. But bus. Fig 11 shows the commutation failure due to a remote
because of the increasing demand for power, an additional fault. Figure 12 shows the HVDC system characteristics
generator was constructed on Cheju Island. Therefore, the according to a 1-valve fault of the HVDC system. Figures
interactions between the HVDC and the local generator 11 and 12 were compared with the actual fault cases and
were simulated. Figure 10 shows the power operation, a) used to estimate the simulator accuracy. Figure 13 shows
is the load rejection condition and b) is the condition of the comparison between the frequency sources that are on
the 3-phase fault. the AC bus and the Synchronous compensator shaft.
From figure 10, power mode generates the oscillation, Before the simulation, SSR (Sub-Synchronous
otherwise frequency mode controls the AC network Resonance) due to the synchronous compensator was
frequency and generator oscillation. Figure 11 shows the estimated. However, figure 13 show that the HVDC
system response of frequency mode, the frequency frequency controller can control the oscillation of the

Copyright (C) 2006 NuriMedia Co., Ltd.

 A Dynamic Performance Study of an HVDC System using … 327

synchronous compensator according to the changing of A1.Cable

AVR reference or governor reference. Additionally, the Length of cable 101Km
synchronous compensator stated in this paper can do the Cu area 800mm²
governor control because the synchronous compensator Resistance 0.0221 Ω/km @20°C
has a turbine to do a black-start. From fig.13, the
0.0247 Ω/km @20°C
waveforms show that changing the frequency
Inductance 0.1516mH/km @60Hz
measurement point doesn’t affect the transient
Capacitance 0.53 μF/km
performance of the HVDC system.
Range of cable 2.23 – 2.25 ohms
resistance
6. Conclusions
Total Inductance 15.31mH @60Hz
Total Capacitance 53.53 μF
This paper deals with the development of an HVDC
simulator with RTDS for the Cheju-Hanam HVDC system
A2. Electrode Line/Electrode
for transient analysis and operator training. Field record
Length of cable 15km(one side)
data were used to enhance the accuracy of the model. This
Resistance 0.06 Ohm/km
simulator is valuable for analyzing characteristics of the
The total neutral resistance 0.7 Ohms
HVDC system between Cheju and Haenam, and will be
used to study various cases which are related to the HVDC Total capacitance 0.21 μF
system. Total inductance
(Soil Resistor = 200 Ω.m) 26mH @60Hz
(Soil Resistor = 500 Ω.m) 27mH @60Hz
References

[1] CHEJU-HAENAM HVDC MANUAL, GEC Alstom, 1993. A3. Direct Voltage, Current and Power Rating
[2] J. D. Ainsworth, "Developments in the Phase Locked HVDC voltage range 180 to 189kV dc
Oscillator Control System for HVDC and Other Large Nominal power transfer 300MW
Converters,” GEC Report, 1970. DC current 840 A
[3] O.B. Nayak, A.M. Gole, et. al, "Dynamic Performance of
Static and Synchronous Compensators at HVDC Inverter
2.4 Alpha and Gamma Limits
Bus a very Weak AC System,” IEEE Transactions on Power
The minimum gamma angle 18°
Systems, Vol.9. No.3, pp.1350-1358, 1994.
[4] P. Kunder, Power system stability and control, The minimum alpha angle 2°
McGraw-Hill, 1996.
[5] High-Voltage Direct Current Handbook, EPRI
TR-104166S, 1994.
Chan-Ki Kim(M'1996) received his B.S.,
[6] P.C. SEN, "Thyristor DC Drive,” A Wiley- Inter science
M.S, Ph.D. degrees in Electrical Engineering
Publication, 1981.
from Chung-Ang University, Korea in 1991,
[7] H L Thanawala & R S Whitehouse – GEC ALSTHOM, G 1993, 1996 respectively. Currently he is P/L
O Kwon, S J Lee, Kepco, “Equipment and Control Features for HVDC at KEPRI that is the R & D center
of Haenam-Cheju HVDC Link in South Korea”, CIGRE SC of KEPCO, fellow/editor of KIEE and a
14 Session, Paris, 1994. member of IEEE. His research interests are power system
operation and control, HVDC and Power. He has published 150
papers in the electric field including KIEE and IEEE and
Appendix
submitted 20 patents and programs. He has received the
Technical Award from the Ministry of Science & Technology of
The Data of Cheju-Haenam HVDC
the Korean Government.

Copyright (C) 2006 NuriMedia Co., Ltd.

 328 Journal of Power Electronics, Vol. 5, No. 4, October 2005

Byeong-Mo Yang was born in Chun-Buk,

Korea, on June 09, 1969. He received his B.S.
and M.S. degrees in electrical engineering
from Yonsei University. Since 1997, he has
worked in KEPRI. He is experienced with
HVDC as well as power system grounds and
simulations. His current research interests are power system
simulation and HVDC.

Hahk Sung Lee was born in Korea in 1957.

He received his B.S. and M.S. degrees from
Seoul National University, Seoul, Korea in
1981 and 1983, respectively, and the Ph. D.
degree from the University of Southern
California in 1992. In 1992, he rejoined to
R&D Institute of Hyosung, where he is currently the head of the
Research & Development Center, as a senior vice president of
Hyosung Corporation. His main research interests include
FACTS application in large power grid and power automation
systems, especially substation automation systems.

Copyright (C) 2006 NuriMedia Co., Ltd.