BR-MLK 15 CFL-H Uma MB ps8802 x02 20180118 For DELL

5 4 3 2 1
COMPAL CONFIDENTIAL
MODEL NAME : DDP80 Vinafix.com
D D
PCB NO : LA-F711P
BOM P/N :
GPIO MAP: Dell GPIO map EC16 062416 Compal Only
Breckenridge MLK 15 UMA

Cof f ee Lake H
2018-01-11
C
REV : 0.5 (X02) C
@ : Nopop Component
EMI@ : EMI Component
@EMI@ : EMI Nopop Component
ESD@ : ESD Component
@ESD@ : ESD Nopop Component
RF@ : RF Component
B
@RF@ : RF Nopop Component B
XDP@ : XDP Component

CONN@ : Connector Component
MB PCB
Part Number Description
eSPI@ : eSPI interface
DA8001D0000 PCB 26H LA-F711P REV0 MB UMA 1
LPC@ : LPC interface
Layout Dell logo 15U@ : Lat i t ude c onf i
15P@ : Precision conf i g
A DS3@ : Deep sleep support A
NDS3@ : non Deep sleep support DELL CONFIDENTIAL/PROPRIETARY

Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
COPYRIGHT 2017 Issued Date 2016/01/01 Deciphered Date 2017/01/01
ALL RIGHT RESERVED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
REV: X02 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
PWB: GXXF6 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A
LA-F711P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 18, 2018 Sheet 1 of 63
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5 4 3 2 1
Breckenridge MLK 15 UMA non-TBT Block Diagram
Reverse Type
Vinafix.com Memory BUS (DDR4) DDR4-SO-DIMM X2

D eDP Lane x 2 BANK 0, 1, 2, 3 D
EDP CONN eDP 1866/2133/2400 MHz
P32 P.14/15
Intel
HDMI 1.4b HDMI DDI[1] COFFEE LAKE-H
DDIB
CONN P26 BGA CPU USB2.0[9]
LCD Touch
1440 Pins P32
DDI[2]
To Type C DDIC USB2.0[11]
Camera
P32 Trough eDP Cable
DDI[3] USB2.0[1] SLGC55544CVTR USB2.0[1]_PS
DDID USB POWER SHARE
PAGE 6~13 P42
USB3.0 Conn
USB3.0[1]
PS(Ext Port 1)
P42
DMI x4 Gen 3
USB2.0[2]
USB3.0 Conn
USB3.0[3] (Ext Port 2) P43
C
DP redriver USB USB2.0[3] C
CRT CONN VGA DP TO VGA PS8330 USB3.0 Conn

P27 RTD2166 P27
P25 USB3.0[4] (Ext Port 3) P43
Intel
CannonLake-H
BGA PCH
874 Pins
HD Audio I/F
PAGE 16~24
SATA[0]/PCIE[9..12] INT.Speaker
P.36
SATA[2]
HDA Codec Universal Jack
SPI
ALC3246 P.36 P.36
PCIE[6] PCIE[5] PCIE[17] PCIE[7] CNVi W25Q256

Dig. MIC Trough eDP Cable
eSPI
P.19
P.32
Card reader Intel Jacksonville 256MB
RTS5242 P34 WGI219LM P33 M.2,3042 Key B M.2, 2230 Key E
WWAN/LTE MX25L256
/HCA/SSD WLAN+BT/CNVi P.19
B P35 P35 M2 Key M B
256MB
USB2.0[8] USB2.0[14]
reserve for colay SSD Conn P.40
SD4.0 Transformer
P34 P33 TPM2.0 - NPCT75x
PCIE/USB3 Switch
PI3PCIE3212ZBEX P.39 SATA REPEATER SATA HDD
RJ45 P33 PI3EQX6741STZDEX Conn LID SWITCH
P41 P45
P41
USB3.0[2] PCIE[18] KB/TP CONN
SMSC KBC P.44
USH CONN
MEC5105 P39
Non-AR Type C
P.37 FAN CONN
DP1.2 4 lanes P.38 CPU&PCH XDP Port
P7
DDI[2]
TX/RX HS Redriver Switch
TUSB1046 USB3.0[5] USH board AUTOMATIC POWER
P28 SWITCH(APS) P21
Smart Card TDA8034HN

USB 3.0 + AM GPIO USB2.0[10] Free Fall sensor
USH TPM1.2 P41
Type C CONN. USB2.0 BCM58102
SMBUS
RFID/NFC SPI
CC PD Solut i on USB2.0[4] DC/DC Interface
A A
TPS65982DC P47
P31
Vbus P29-30 Fingerprint SPI POWER ON/OFF
CONN SW & LED P45
P39
5V VR DELL CONFIDENTIAL/PROPRIETARY
Title
Issued Date 2016/01/01 Deciphered Date 2017/01/01
Charger THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F711P
Date: Friday, January 26, 2018 Sheet 2 of 63
5 4 3 2 1
5 4 3 2 1
POWER STATES
USB3.0 SSIC PCIE SATA DESTINATION USB PORT# DESTINATION
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
S3# S4# S5# A# PLANE PLANE PLANE PLANE JUSB1-->Right
State USB3.0-1 JUSB1-->Right 1
2 JUSB2 ->Lef t
USB3.0-2 SSIC-1 JNGFF2-->M2 3042(LTE)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
Vinafix.com USB3.0-3 SSIC-2 JUSB2-->LEFT 3 JUSB3-->Rear
D S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF D
JUSB3-->REAR 4 Type C
USB3.0-4
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF JUSBC1-->TypeC 5 NA
USB3.0-5
NA 6 test point
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
USB3.0-6
7 NA
USB3.0-7 PCIE-1
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
8 JNGFF2-->M2 3042(WWAN)
USB3.0-8 PCIE-2
NA
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF 9 JEDP1-->Touch Screen
USB3.0-9 PCIE-3
10 JUSH1-->USH
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
USB3.0-10 PCIE-4
LOM 11 JEDP1-->Camera
PCIE-5
Card Reader 12 NA
PM TABLE PCIE-6
C PCIE-7 JNGFF1-->M.2 2230(WLAN) 13 NA

C
+5V_ALW
+3.3V_ALW PCIE-8 NA 14 JNGFF1--> M.2 2230(CNVi_BT)
+3.3V_ALW_DSW +3.3V_SUS +5V_RUN
+3.3V_ALW_PCH +1.2V_MEM +3.3V_RUN PCIE-9
power USH H BIO
plane +RTC_CELL +1.0V_VCCST +0.6V_DDR_VTT PCIE-10 M.2 Socket 3 (Key M)
+1.8V_PRIM +2.5V_MEM +1.2V_RUN M.2 2280 SSD
+1.0V_PRIM +VCC_CORE PCIE-11 SATA-0A (PCIex4 or SATA) VIDEO DESTINATION
+1.0V_PRIM_CORE +VCC_GT PCIE-12 SATA-1A eDP LCD
+5V_ALW2 +1.0VS_VCCIO
State PCIE-13 SATA-0B NA
+3.3V_ALW2 +VCC_SA DDI-B JHDMI1
+3.3V_RTC_LDO +1.8V_RUN PCIE-14 SATA-1B NA
+1.0V_MPHYGT DDI-C Type-C
PCIE-15 SATA-2 JSATA1-->HDD SATA
S0 ON ON ON
PCIE-16 SATA-3 NA
B B
S3 ON ON OFF PCIE-17 SATA-4 M.2 3042 (HCA or QCA LTE) SSD Cache DDI-D MB VGA
S5 S4/AC ON OFF OFF

PCIE-18 SATA-5 M.2 3042 (HCA or QCA LTE) SSD Cache
PCIE-19 NA
S5 S4/AC doesn't exist OFF OFF OFF
PCIE-20 NA
A A
DELL CONFIDENTIAL/PROPRIETARY
Title
Port Assignment
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A 0.5
5 4 3 2 1
5 4 3 2 1
@SIO_SLP_SUS#
CPU PWR
SIO_SLP_S4# TPS22961 @SIO_SLP_S4#
PCH PWR
+1.2V_MEM +VCC_SFR_OC
Vinafix.com
SY8210A
(PU200)
(UZ26) VCCSTG_EN GT3 PWR
Peripheral Device PWR
0.6V_DDR_VTT_ON RUN_ON
D TPS22961 SIO_SLP_S0# TYPE-C Power D
Barrel Type-C +0.6V_DDR_VTT (UZ19) +1.0V_VCCSTG
ADAPTER ADAPTER GPU PWR
SIO_SLP_S4#
TPS22961
(UZ21) +1.0V_VCCST
PCH_PRIM_EN
SY8286RAC @SIO_SLP_SUS#
+1.0V_PRIM
(PU301)
RUN_ON
CHARGER SY8057QDC
ISL9538 +PWR_SRC +5V_ALW +1.0VS_VCCIO
ALW ON
(PU401)
(PU901) SY8288C
(PU102)
+5V_ALW2
RUN_ON 3.3V_TS_EN
EM5209 LP2301
(UZ4) +5V_RUN (QV8) +5V_TSP
BATTERY AUD_PW R_EN

EM5209
(@UZ5) +5V_RUN_AUDIO
USB_PW R_SHR_EN#
SY8288B +3.3V_RTC_LDO SLGC55544C
(PU100) (UI3) +5V_USB_CHG_PWR
C C
ALW ON
USB_PW R_EN1#
+3.3V_ALW2 SY6288D
(UI1) +USB_EX2_PWR
USB_PW R_EN2#
+3.3V_ALW SY6288D
(UI2) +USB_EX3_PWR
PCH_PRIM_EN RUN_ON
RT8097ALGE @SIO_SLP_SUS# AOZ1336
+1.8V_PRIM (UZ8) +1.8V_RUN
(PU501)
NCP81215(PU1700) (PU1800)
(PU1801) AO6405 SIO_SLP_LAN#
NCP302045 (PU1900) (QV1) +3.3V_LAN
(PU2001) (PU2000) EM5209
(PU1901) (UZ2)
AUX_EN_W OW L
IMVP_VR_ON
IMVP_VR_ON
IMVP_VR_ON
@SIO_SLP_W LAN#
EN_INVPWR
+3.3V_WLAN
PCH_PRIM_EN
@SIO_SLP_SUS#
@PCH_ALW _ON +3.3V_ALW_PCH
EM5209
(UZ3)
3.3V_CAM_EN#
+VCC_SA +VCC_GT +VCC_CORE +BL_PWR_SRC RUN_ON LP2301A
+3.3V_RUN (QZ1) +3.3V_CAM
B B
3.3V_W WAN_EN
EM5209 AUD_PW R_EN
(UZ4) +3.3V_WWAN EM5209
(@UZ5) +3.3V_RUN_AUDIO
ENVDD_PCH
G524B1T11U
(UV24) +LCDVDD
TYPE-C
+5V_ALW
TPS65982DC
(UT5) +TBT_VBUS(5V~20V) TPS22967 CV2_ON
+PP_HV(5V~20V) (UZ18) +3.3V_CV2
USH/B
SIO_SLP_S4#
AP7361C
(PU503) +2.5V_MEM
for DDR4
+5V_ALW
AP2204 AP2112K
(UT8) (UT7) +3.3V_VDD_PIC
+5V_TBT_VBUS
A A
Title
Power Rails
5 4 3 2 1
5 4 3 2 1
1K 2.2K
SMBUS Address [0x9a]
1K
+3.3V_ALW_PCH 2.2K
+3.3V_RUN
AW44 MEM_SMBCLK 202
MEM_SMBDATA
DMN66D0LDW-7
BB43 200 DIMMA
DMN66D0LDW-7
PCH
Vinafix.com
499
202
D +3.3V_ALW_PCH 200 DIMMB D

499
AY44 SML0_SMBCLK 28
SML0_SMBDATA 31 LOM
BB39
AW45 AW42 53
51 XDP
1K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
1K
1
E11 D8 2.2K LNG2DMTR
4
+3.3V_TP
03 03 2.2K
02 C12 DAT_TP_SIO_I2C_CLK 9
02 E10 CLK_TP_SIO_I2C_DAT 8 TP
@2.2K 2.2K
+3.3V_ALW +3.3V_CV2
@2.2K 2.2K
01 B3 USH_EXPANDER_SMBCLK M9
C C
E5 USH_EXPANDER_SMBDAT USH
01 L9
2.2K USH/B
00 D7 2.2K
00 E7
2.2K +3.3V_ALW +3.3V_TBT_FLASH
KBC 2.2K
C3 UPD1_SMBCLK UPD1_SMBCLK_Q B5
04 DMN66D0LDW-7
B4 UPD1_SMBDAT PD &
UPD1_SMBDAT_Q A5
04 DMN66D0LDW-7 FW reflash
MEC 5105
F7
05
B6
05
06 A12
06 N10
B 2.2K B
+3.3V_ALW
2.2K
07 F7 GPU_SMCLK
07 B6 GPU_SMDAT
08 C5
08 C8
09 F6
09 E9 2.2K
Charger
+3.3V_ALW
2.2K
10
100 ohm 7
N2 PBAT_CHARGER_SMBCLK
100 ohm 6
BATTERY
A 10 M3 PBAT_CHARGER_SMBDAT CONN A
Title
SMbus Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.5
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
CFL-H
UC1C
E25 B25
D25 PEG_RXP_0 PEG_TXP_0 A25
PEG_RXN_0 PEG_TXN_0
E24 B24
F24 PEG_RXP_1 PEG_TXP_1 C24
PEG_RXN_1 PEG_TXN_1
E23 B23
PEG_RXN_2 PEG_TXN_2
E22 B22
PEG_RXN_3 PEG_TXN_3
E21 B21
PEG_RXN_4 PEG_TXN_4
E20 B20
PEG_RXN_5 PEG_TXN_5
E19 B19
PEG_RXN_6 PEG_TXN_6
E18 B18
C C
PEG_RXN_7 PEG_TXN_7
D17 A17
E17 PEG_RXP_8 PEG_TXP_8 B17
PEG_RXN_8 PEG_TXN_8
F16 C16
PEG_RXN_9 PEG_TXN_9
D15 A15
PEG_RXN_10 PEG_TXN_10
F14 C14
D13 A13
F12 C12
D11 A11
F10 C10
PEG_COMP G2
PEG_RCOMP
B B
DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0
<17> DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 <17>
E8 A8
<17> DMI_CRX_PTX_N0 DMI_RXN_0 DMI_TXN_0 DMI_CTX_PRX_N0 <17>
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
F6 B6 DMI_CTX_PRX_N1 <17>
<17> DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1
DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2
E5 A5
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
<17> DMI_CRX_PTX_P3 DMI_RXP_3 DMI_CTX_PRX_P3 <17>
DMI_CRX_PTX_N3 J9 3 OF 13 DMI_TXP_3 B4 DMI_CTX_PRX_N3
CFL-H_BGA1440
+1.0VS_VCCIO
1 2 PEG_COMP
RC2 24.9_0402_1%
Trace width=5 mils

,Spacing=15mil
Max length= 600 mils.
A A
Title
CFL-H (1/8)
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM +1.0V_PRIM_XDP
CFG11 CFG10
+3.3V_ALW_PCH 1 2
1
1
@ RC216 0_0603_1% SAFE mode boot
XDP@ RC133
1.5K_0402_5%
CPU XDP @
DMI_AC_coupled
@
1
RC441 RC440
1K_0402_5%
HALF-SWING 1 1K_0402_5% active 1
+1.0V_VCCSTG +1.0V_PRIM_XDP XDP@ DC coupled
XDP_PRSNT_PIN1 1
2
+1.0V_PRIM_XDP 2 CFG3
2
RC121 1K_0402_5% +1.0V_PRIM_XDP FULL-SWING 0 Not active 0
2
Vinafix.com AC coupling
1 2
SYS_PWROK_R
ESD@ CC334
ESD@ CC335
@ RC122 0_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1 1 JXDP1
0.1U_0402_25V6
1 1 1 1 2
CPU_XDP_PREQ# 3 GND0 GND1
@ CC33
@ CC28
@ CC29
4 CFG17 +1.0VS_VCCIO
D Place near JXDP1.47 CPU_XDP_PRDY# 5 OBSFN_A0 OBSFN_C0 6 CFG16 CFG12 CFG9 1
@ RC439
2
D
2 2 7 OBSFN_A1 OBSFN_C1 8 SVID NOT Present
1
1K_0402_5%
1
2 2 2 CFG0 9 GND2 GND3 10 CFG8
CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9 @
@ RC438
13 OBSDATA_A1 OBSDATA_C1 14 RC442
1 Present 1
CFG2 15 GND4 GND5 16 CFG10 1K_0402_5% PMSYNC2.0 1K_0402_5%
CFG3 17 OBSDATA_A2 OBSDATA_C2 18 CFG11
2
19 OBSDATA_A3 OBSDATA_C3 20 Not presnet 0
Place near JXDP1 XDP_OBS0_R 21 GND6 GND7 22 CFG19 LEGACY 0
+3.3V_ALW XDP_OBS1_R 23 OBSFN_B0 OBSFN_D0 24 CFG18
25 OBSFN_B1 OBSFN_D1 26
CFG4 27 GND8 GND9 28 CFG12
29 OBSDATA_B0 OBSDATA_D0
1
1.5K_0402_5%
XDP@ RC241
CFG5 30 CFG13 CFG8

31 OBSDATA_B1 OBSDATA_D1 32
33 GND10 GND11
1
CFG6 34 CFG14 CFG UNLOCK
CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15 @
<20,44> PCH_RSMRST#_AND 37 OBSDATA_B3 OBSDATA_D3 38 RC437
2
XDP@ RC124 1 2 1K_0402_5% H_VCCST_PWRGD_XDP 39 GND12 GND13 40 PCH_XDP_CLK_DP

1K_0402_5%
SIO_PWRBTN# T191 @ PAD~D SIO_PWRBTN# 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 PCH_XDP_CLK_DN PCH_XDP_CLK_DP <18> disable 1
<20,37> SIO_PWRBTN# PCH_XDP_CLK_DN <18>
FIVR_EN 43 HOOK1 ITPCLK#/HOOK5
2
@ RC217 1 2 0_0402_5% 44
FIVR_EN_R 45 VCC_OBS_AB VCC_OBS_CD CPU_XDP_HOOK6 2 ITP_PMODE_CPU
0.1U_0402_25V6
ESD@ CC269
CFG0 XDP@ RC126 1 2 1K_0402_5% 46 1 ITP_PMODE_CPU <20> enable 0

XDP@ RC128 1 2 1K_0402_5% SYS_PWROK_R 47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET# XDP@ RC144 0_0402_5%
1 Place near JXDP1.41 <19> PCH_SPI_D0
@ RC129 1 2 0_0402_5% 49 HOOK3 DBR#/HOOK7 50
<20,37> SYS_PWROK XDP_DBRESET# <17>
51 GND14 GND15 52 CPU_XDP_TDO
<14,15,20,41> DDR_XDP_WAN_SMBDAT
53 SDA TD0 54 CPU_XDP_TRST#
CPU_XDP_TRST# <22>
2 <14,15,20,41> DDR_XDP_WAN_SMBCLK 55 SCL TRST# 56 CPU_XDP_TDI CFG1
<20> PCH_JTAG_TCK CPU_XDP_TCLK 57 TCK1 TDI 58 CPU_XDP_TMS
59 TCK0 TMS PCHLESS MODE (CRB)
1
60 CPU_XDP_PRS 1 2 PCH_SPI_D2_XDP
GND16 Not link CIS GND17 PCH_SPI_D2_XDP <19> Reserved CFG lane (EDS)
XDP@ RC127 1K_0402_5% @
CPU_XDP_TDO H_VCCST_PWRGD_XDP CPU_XDP_TRST# SAMTE_BSH-030-01-L-D-A CONN@ RC436
1K_0402_5% NORMAL 1
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
2
+1.0V_PRIM_XDP
PCHLESS 0
1
1
CPU_XDP_HOOK6 1 2
C C
XDP@ RC115 2.2K_0402_5%
+1.0V_PRIM_XDP
2
2
CC306
CC307
CC308
+3.3V_ALW_PCH
CFG13 CFG0
1 2 CPU_XDP_PREQ# XDP_DBRESET# 1 2 Stall reset sequence after PCU
1
@ RC138 51_0402_5% RC137 3K_0402_5% SYNC & AYNC MODE PLL lock until de-asserted
+1.0V_VCCSTG @ @
+1.0VS_VCCIO RC443 RC321
ESD request,Place near JXDP1 side. 1K_0402_5% ASYNCHRONOUS 1K_0402_5% 1
CPU_XDP_TDO 1 2
1 No Stall
2
1 2 FIVR_EN_R RC135 51_0402_5%
RC132 150_0402_5% CPU_XDP_TRST# 1 2 SYNCHRONOUS 0 Stall 0
CPU_XDP_TMS 1 2 @ RC136 51_0402_5%
+1.0V_VCCSTG PCH_JTAG_TMS <20>
RC228 0_0402_5%
CPU_XDP_TDI CPU_XDP_TCLK 1 2
1 2
PCH_JTAG_TDI <20> RC139 51_0402_5%
1 2 PROCHOT# RC229 0_0402_5% CFG2
CPU_XDP_TDO 1 2
RC83 1K_0402_5% PCH_JTAG_TDO <20> CFL-H
1
RC230 0_0402_5%
+1.0V_VCCST
CPU_XDP_TCLK 1 2 UC1E PEG LANE REVERSAL
PCH_JTAGX <20> @
RC143 0_0402_5% RC181
H_THERMTRIP# CPU_XDP_PRDY# 1 2
1 2 PCH_XDP_PRDY# <22> PCH_CPU_BCLK_R_D XDP_DBRESET# 1K_0402_5% NORMAL 1
0.1U_0402_25V6
ESD@ CC32
RC80 1K_0402_5% RC314 0_0402_5% B31 BN25 CFG0 1
CPU_XDP_PREQ#1 <18> PCH_CPU_BCLK_R_D PCH_CPU_BCLK_R_D# BCLKP CFG_0
2
1 2 PCH_JTAGX 2 A32 BN27 CFG1
RC315 0_0402_5%
PCH_XDP_PREQ# <22> <18> PCH_CPU_BCLK_R_D# BCLKN CFG_1 BN26 CFG2 LANE
@ RC166 1K_0402_5% PCH_CPU_PCIBCLK_R_D CFG_2 0
1 2 VCCST_PWRGD <18> PCH_CPU_PCIBCLK_R_D
D35 BN28 CFG3 REVERSED
PCH_CPU_PCIBCLK_R_D# C36 PCI_BCLKP CFG_3 BR20 CFG4 2
RC71 1K_0402_5% <18> PCH_CPU_PCIBCLK_R_D# PCI_BCLKN CFG_4
1 2 H_CATERR# BM20 CFG5
CPU_24MHZ_R_D E31 CFG_5 BT20 CFG6
@ RC79 49.9_0402_1% <18> CPU_24MHZ_R_D CPU_24MHZ_R_D# CLK24P CFG_6
D31 BP20 CFG7 CFG4
<18> CPU_24MHZ_R_D# CLK24N CFG_7
+1.0V_VCCST BR23 CFG8
CFG_8 BR22 CFG9 eDP enable
1
CFG_9 BT23 CFG10
1 2 FIVR_EN
CFG_10 BT22 CFG11
@ RC218 150_0402_5% CFG_11 RC322 Disabled 1
BM19 CFG12 1K_0402_5%
CFG_12 BR19 CFG13
B 1 2 FIVR_EN CFG_13 B
BP19
2
CFG14
@ RC219 10K_0402_5% CPU_VIDALERT# CFG_14 Enabled 0
BH31 BT19 CFG15
VR_SVID_CLK BH32 VIDALERT# CFG_15
<55> VR_SVID_CLK VR_SVID_DATA VIDSCK
BH29 BN23 CFG17
PROCHOT# 1 2 H_PROCHOT#_R BR30 VIDSOUT CFG_17 BP23 CFG16
+1.0V_VCCST <37,49,55> PROCHOT# PROCHOT# CFG_16
RC84 499_0402_1% BP22 CFG19
DDR_VTT_CTRL BT13 CFG_19 BN22 CFG18
<14> DDR_VTT_CTRL DDR_VTT_CNTL CFG_18 CFG5
1
1
56.2_0402_1%
100_0402_5%
BR27 XDP_OBS0 @ RC239 1 2 0_0402_5% XDP_OBS0_R

PCI Express* Bifurcation
RC152
RC157
BPM#_0 BT27 XDP_OBS1 @ RC240 1 2 0_0402_5% XDP_OBS1_R

@ [6:5]
BPM#_1 RC323
BM31 1K_0402_5%
VCCST_PWRGD 1 2 VCCST_PWRGD_CPU H13 BPM#_2 BT30
<37,38> VCCST_PWRGD VCCST_PWRGD BPM#_3 1x8, 2x4 00
2
2
VR_SVID_DATA RC78 60.4_0402_1%
<55> VR_SVID_DATA H_PWRGD BT31
<20> H_PWRGD PLTRST_CPU# PROCPWRGD CPU_XDP_TDO
VR_SVID_ALERT# BP35 BT28 @
<16> PLTRST_CPU# H_PM_SYNC RESET# PROC_TDO CPU_XDP_TDI PAD~D T184 Reserved 01
<55> VR_SVID_ALERT# BM34 BL32 @
<16> H_PM_SYNC H_PM_DOWN H_PM_DOWN_R BP31 PM_SYNC PROC_TDI CPU_XDP_TMS PAD~D T185 CFG6
1 2 BP28
1
220_0402_5%
<16> H_PM_DOWN H_PECI PM_DOWN PROC_TMS CPU_XDP_TCLK PAD~D @ T180

BT34 BR28
1
RC168 20_0402_5%
RC153
<16,37> H_PECI H_THERMTRIP# H_THERMTRIP#_R J31 PECI PROC_TCK PAD~D @ T181 2x8 10
<14,15,16,38> H_THERMTRIP# 1 2 @
RC169 0_0402_5% THERMTRIP# BP30 CPU_XDP_TRST#
H_SKTOCC# PROC_TRST# CPU_XDP_PREQ# PAD~D @ T179 RC324
VR_SVID_DATA 1 2 BR33 BL30
SKL_CNL# SKTOCC# PROC_PREQ# CPU_XDP_PRDY# PAD~D @ T190 1K_0402_5% 1x16 11
2
RC319 1 2 0_0402_5% BN1 BP27

PROC_SELECT# PROC_PRDY# PAD~D @ T189
2
@ RC171 0_0402_5%
CPU_VIDALERT#
pop RC171 for CNL H_CATERR# BM30
depop RC171 for SKL & KBL (CFL CRB rev0.5) CATERR# BT25
AT13 CFG_RCOMP
just remind to check layout !! PAD~D @ T26 ZVM#
AW13
PAD~D @ T25 MSM#
1
AU13 RC114 CFG7
PAD~D @ T31 AY13 RSVD1 49.9_0402_1%
PAD~D @ T32 RSVD2
1
5 OF 13
PEG Training
@
2
RC325 (default) PEG Train
CFL-H_BGA1440 1K_0402_5%
A immediately following 1 A
RESET# de-assertion
2
H_PWRGD VCCST_PWRGD H_THERMTRIP#
PEG Wait for BIOS for
PROCHOT# training 0
RF Request
100P_0402_50V8J
ESD@
100P_0402_50V8J
ESD@
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
1
VR_SVID_CLK 1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
CC300
CC301
@RF@ CC325 33P_0402_50V8J

2
2
CC323
CC324
Issued Date Deciphered Date 2017/01/01 Title

2016/01/01
CFL-H (2/8)
Place close CPU side DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.5
ESD Request:place near CPU side MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F711P
5 4 3 2 1
5 4 3 2 1
<14> DDR_A_DQS#[0..7]
<14> DDR_A_DQS[0..7]
<15> DDR_B_DQS#[0..7]
<15> DDR_B_DQS[0..7]
Vinafix.com
D D
CFL-H
UC1A CFL-H
UC1B
DDR CHANNEL A DDR CHANNEL B
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4 DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
<14> DDR_A_D[0..15] DDR_A_D0 BR6 AG1 DDR_A_CLK0 <14> DDR_A_D[16..31] DDR_A_D16 BT11 AM9 DDR_B_CLK0
DDR_A_D1 BT6 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 AG2 DDR_A_CLK#0 DDR_A_CLK0 <14> DDR_A_D17 BR11 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 AN9 DDR_B_CLK#0 DDR_B_CLK0 <15>
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK1 DDR_A_CLK#0 <14> DDR_A_D18 BT9 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 DDR_B_CLK1 DDR_B_CLK#0 <15>
DDR_A_D3 BR3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 AK1 DDR_A_CLK#1 DDR_A_CLK1 <14> DDR_A_D19 BR8 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 AM8 DDR_B_CLK#1 DDR_B_CLK1 <15>
DDR_A_D4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR_A_CLK#1 <14> DDR_A_D20 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 DDR_B_CLK#1 <15>
BN5 AL3 BP11 AM11
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3 DDR_A_D21 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2 DDR_A_D22 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1 DDR_A_D23 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR_A_D24 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0 DDR_A_D25 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_B_CKE0
DDR_A_D10 BL2 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 AT2 DDR_A_CKE1 DDR_A_CKE0 <14> DDR_A_D26 BL8 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 AT10 DDR_B_CKE1 DDR_B_CKE0 <15>
DDR_A_D11 BM1 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT3 DDR_A_CKE1 <14> DDR_A_D27 BJ8 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 AT7 DDR_B_CKE1 <15>
DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5 DDR_A_D28 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR_A_D29 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0 DDR_A_D30 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_B_CS#0
DDR_A_D15 BK2 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 AE2 DDR_A_CS#1 DDR_A_CS#0 <14> DDR_A_D31 BJ7 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 AE7 DDR_B_CS#1 DDR_B_CS#0 <15>
<14> DDR_A_D[32..47] DDR_A_D32 BG4 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 AD2 DDR_A_CS#1 <14> <14> DDR_A_D[48..63] DDR_A_D48 BG11 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 AF10 DDR_B_CS#1 <15>
DDR_A_D33 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5 DDR_A_D49 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_A_D34 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR_A_D50 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_A_D35 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0 DDR_A_D51 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 DDR_B_ODT0
DDR_A_D36 BG2 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 AE4 DDR_A_ODT1 DDR_A_ODT0 <14> DDR_A_D52 BF11 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 AE8 DDR_B_ODT1 DDR_B_ODT0 <15>
DDR_A_D37 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 DDR_A_ODT1 <14> DDR_A_D53 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 DDR_B_ODT1 <15>
BG1 AE1 BF10 AE9
DDR_A_D38 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4 DDR_A_D54 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_A_D39 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR_A_D55 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
DDR_A_D40 DDR0_DQ_23/DDR0_DQ_39 DDR_A_BA0 DDR_A_D56 DDR1_DQ_23/DDR0_DQ_55 DDR_B_MA16 DDR_B_MA[0..16] <15>
BD2 AH5 BB11 AH10
DDR_A_D41 BD1 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 AH1 DDR_A_BA1 DDR_A_BA0 <14> DDR_A_D57 BC11 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 AH11 DDR_B_MA14
DDR_A_D42 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR_A_BG0 DDR_A_BA1 <14> DDR_A_D58 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 DDR_B_MA15
BC4 AU1 BB8 AF8
DDR_A_D43 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <14> DDR_A_D59 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15
BC5 BC8
DDR_A_D44 DDR0_DQ_27/DDR0_DQ_43 DDR_A_MA16 DDR_A_MA[0..16] <14> DDR_A_D60 DDR1_DQ_27/DDR0_DQ_59 DDR_B_BA0
BD5 AH4 BC10 AH8
DDR_A_D45 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA14 DDR_A_D61 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <15>
BD4 AG4 BB10 AH9
C DDR_A_D46 BC1 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 AD1 DDR_A_MA15 DDR_A_D62 BC7 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 AR9 DDR_B_BG0 DDR_B_BA1 <15> C
DDR_A_D47 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_D63 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <15>
BC2 BB7
<15> DDR_B_D[0..15] DDR_B_D0 DDR0_DQ_31/DDR0_DQ_47 DDR_A_MA0 <15> DDR_B_D[16..31] DDR_B_D16 DDR1_DQ_31/DDR0_DQ_63 DDR_B_MA0
AB1 AH3 AA11 AJ9
DDR_B_D1 AB2 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 AP4 DDR_A_MA1 DDR_B_D17 AA10 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 AK6 DDR_B_MA1
DDR_B_D2 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2 DDR_B_D18 AC11 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK5 DDR_B_MA2
DDR_B_D3 AA5 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 AP5 DDR_A_MA3 DDR_B_D19 AC10 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_5/DDR1_MA_2 AL5 DDR_B_MA3
DDR_B_D4 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4 DDR_B_D20 AA7 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 AL6 DDR_B_MA4
DDR_B_D5 AB4 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 AP1 DDR_A_MA5 DDR_B_D21 AA8 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 AM6 DDR_B_MA5
DDR_B_D6 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6 DDR_B_D22 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_B_D7 AA1 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 AN1 DDR_A_MA7 DDR_B_D23 AC7 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 AN10 DDR_B_MA7
DDR_B_D8 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8 DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_B_D9 V2 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 AT4 DDR_A_MA9 DDR_B_D24 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
DDR_B_D10 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10 DDR_B_D25 W7 DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 AR11 DDR_B_MA9
DDR_B_D11 U2 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 AN2 DDR_A_MA11 DDR_B_D26 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
DDR_B_D12 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12 DDR_B_D27 V11 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 AN11 DDR_B_MA11
DDR_B_D13 V4 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 AE3 DDR_A_MA13 DDR_B_D28 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
DDR_B_D14 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_A_BG1 DDR_B_D29 W10 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 AF9 DDR_B_MA13
DDR_B_D15 U4 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 AU3 DDR_A_ACT# DDR_A_BG1 <14> DDR_B_D30 V7 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 AR7 DDR_B_BG1
<15> DDR_B_D[32..47] DDR_B_D32 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR_A_ACT# <14> DDR_B_D31 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <15>
R2 V8 AT9
DDR_B_D33 DDR0_DQ_48/DDR1_DQ_32 DDR_A_PAR <15> DDR_B_D[48..63] DDR_B_D48 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <15>
P5 AG3 R11
DDR_B_D34 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_ALERT# DDR_A_PAR <14> DDR_B_D49 DDR1_DQ_48/DDR1_DQ_48 DDR_B_PAR
R4 AU5 P11 AJ7
DDR_B_D35 P4 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR_A_ALERT# <14> DDR_B_D50 P7 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR AR8 DDR_B_ALERT# DDR_B_PAR <15>
DDR_B_D36 DDR0_DQ_51/DDR1_DQ_35 DDR_B_D51 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR_B_ALERT# <15>
R5 DDR4(IL)/LP3-DDR4(NIL) R8
DDR_B_D37 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0 DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_B_D38 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#1 DDR_A_DQS#0 <14> DDR_B_D53 DDR1_DQ_52/DDR1_DQ_52 DDR_A_DQS#2
R1 BL3 P10 BN9
DDR_B_D39 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 DDR_A_DQS#4 DDR_A_DQS#1 <14> DDR_B_D54 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR_A_DQS#3 DDR_A_DQS#2 <14>
P1 BG3 R7 BL9
DDR_B_D40 M4 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 BD3 DDR_A_DQS#5 DDR_A_DQS#4 <14> DDR_B_D55 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 DDR_A_DQS#6 DDR_A_DQS#3 <14>
DDR_B_D41 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 DDR_B_DQS#0 DDR_A_DQS#5 <14> DDR_B_D56 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 DDR_A_DQS#7 DDR_A_DQS#6 <14>
M1 AA3 L11 BC9
DDR_B_D42 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 DDR_B_DQS#1 DDR_B_DQS#0 <15> DDR_B_D57 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 DDR_B_DQS#2 DDR_A_DQS#7 <14>
L4 U3 M11 AC9
DDR_B_D43 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 DDR_B_DQS#4 DDR_B_DQS#1 <15> DDR_B_D58 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 DDR_B_DQS#3 DDR_B_DQS#2 <15>
L2 P3 L7 W9
DDR_B_D44 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 DDR_B_DQS#5 DDR_B_DQS#4 <15> DDR_B_D59 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 DDR_B_DQS#6 DDR_B_DQS#3 <15>
M5 L3 M8 R9
DDR_B_D45 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR_B_DQS#5 <15> DDR_B_D60 L10 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 M9 DDR_B_DQS#7 DDR_B_DQS#6 <15>
DDR_B_D46 DDR0_DQ_61/DDR1_DQ_45 DDR_A_DQS0 DDR_B_D61 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7 DDR_B_DQS#7 <15>
L5 BP5 M10
DDR_B_D47 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS1 DDR_A_DQS0 <14> DDR_B_D62 DDR1_DQ_61/DDR1_DQ_61 DDR_A_DQS2
L1 BK3 M7 BP9
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 DDR_A_DQS4 DDR_A_DQS1 <14> DDR_B_D63 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR_A_DQS3 DDR_A_DQS2 <14>
BF3 L8 BJ9
B LP3/DDR4 DDR0_DQSP_2/DDR0_DQSP_4 BC3 DDR_A_DQS5 DDR_A_DQS4 <14> DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_A_DQS6 DDR_A_DQS3 <14> B
BA2 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_B_DQS0 DDR_A_DQS5 <14> AW11 LP3/DDR4 DDR1_DQSP_2/DDR0_DQSP_6 BB9 DDR_A_DQS7 DDR_A_DQS6 <14>
NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR_B_DQS1 DDR_B_DQS0 <15> NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 DDR_B_DQS2 DDR_A_DQS7 <14>
BA1 V3 AY11 AA9
NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 DDR_B_DQS4 DDR_B_DQS1 <15> NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 DDR_B_DQS3 DDR_B_DQS2 <15>
AY4 R3 AY8 V9
NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 DDR_B_DQS5 DDR_B_DQS4 <15> NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 DDR_B_DQS6 DDR_B_DQS3 <15>
AY5 M3 AW8 P9
BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5 DDR_B_DQS5 <15> AY10 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 L9 DDR_B_DQS7 DDR_B_DQS6 <15>
NC/DDR0_ECC_4 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7 DDR_B_DQS7 <15>
BA4 AY3 AW10
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3 AY7 NC/DDR1_ECC_5 AW9
AY2 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8
1 OF 13 AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9
NC/DDR0_ECC_7 NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8
CFL-H_BGA1440
RC5 1 2 121_0402_1% DDR_RCOMP0 G1 BN13

DDR_RCOMP1 DDR_RCOMP_0 DDR_VREF_CA +DDR_VREF_CA
RC6 1 2 75_0402_1% H1 BP13
DDR_RCOMP2 DDR_RCOMP_1 DDR0_VREF_DQ PAD~D @ T199
RC7 1 2 100_0402_1% J2 2 OF 13 BR13 +DDR_VREF_B_DQ
DDR_RCOMP_2 DDR1_VREF_DQ
CFL-H_BGA1440
Trace width=12-15 mils

,Spacing=20mil
Max length= 500 mils.
A A
Title
CFL-H (3/8)
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
CFL-H
UC1D
CPU_DP1_P0 K36 D29 EDP_TXP0

<26> CPU_DP1_P0 CPU_DP1_N0 K37 DDI1_TXP_0 EDP_TXP_0 E29 EDP_TXN0 EDP_TXP0 <32>
<26> CPU_DP1_N0 CPU_DP1_P1 J35 DDI1_TXN_0 EDP_TXN_0 F28 EDP_TXP1 EDP_TXN0 <32>
<26> CPU_DP1_P1 CPU_DP1_N1 J34 DDI1_TXP_1 EDP_TXP_1 E28 EDP_TXN1 EDP_TXP1 <32>
<26> CPU_DP1_N1 CPU_DP1_P2 H37 DDI1_TXN_1 EDP_TXN_1 A29 EDP_TXN1 <32>
<26> CPU_DP1_P2 CPU_DP1_N2 H36 DDI1_TXP_2 EDP_TXP_2 B29
HDMI <26> CPU_DP1_N2 CPU_DP1_P3 DDI1_TXN_2 EDP_TXN_2
J37 C28
<26> CPU_DP1_P3 CPU_DP1_N3 J38 DDI1_TXP_3 EDP_TXP_3 B28
<26> CPU_DP1_N3 DDI1_TXN_3 EDP_TXN_3
D27 C26 EDP_AUXP
DDI1_AUXP EDP_AUXP EDP_AUXN EDP_AUXP <32>
E27 B26
DDI1_AUXN EDP_AUXN EDP_AUXN <32>
CPU_DP2_P0 H34
<28> CPU_DP2_P0 CPU_DP2_N0 H33 DDI2_TXP_0
<28> CPU_DP2_N0 CPU_DP2_P1 F37 DDI2_TXN_0 A33
<28> CPU_DP2_P1 CPU_DP2_N1 DDI2_TXP_1 EDP_DISP_UTIL PAD~D @ T194
C G38 C
<28> CPU_DP2_N1 CPU_DP2_P2 F34 DDI2_TXN_1 +1.0VS_VCCIO
<28> CPU_DP2_P2 CPU_DP2_N2 F35 DDI2_TXP_2 D37 EDP_COMP
Type C <28> CPU_DP2_N2 CPU_DP2_P3 DDI2_TXN_2 DISP_RCOMP
E37
<28> CPU_DP2_P3 CPU_DP2_N3 E36 DDI2_TXP_3 EDP_COMP 1 2
<28> CPU_DP2_N3 DDI2_TXN_3 RC1 24.9_0402_1%
CPU_DP2_AUXP F26
<28,29> CPU_DP2_AUXP CPU_DP2_AUXN DDI2_AUXP
<28,29> CPU_DP2_AUXN E26
DDI2_AUXN
CPU_DP3_P0 C34
min Trace width=5 mils
<25> CPU_DP3_P0 CPU_DP3_N0 D34 DDI3_TXP_0 ,Spacing=20mil
<25> CPU_DP3_N0 CPU_DP3_P1 B36 DDI3_TXN_0 Max length= 600 mils.
<25> CPU_DP3_P1 CPU_DP3_N1 B34 DDI3_TXP_1
<25> CPU_DP3_N1 CPU_DP3_P2 F33 DDI3_TXN_1
<25> CPU_DP3_P2 CPU_DP3_N2 E33 DDI3_TXP_2
<25> CPU_DP3_N2 CPU_DP3_P3 C33 DDI3_TXN_2
VGA <25> CPU_DP3_P3 CPU_DP3_N3 DDI3_TXP_3
B33
<25> CPU_DP3_N3 DDI3_TXN_3 G27 AUD_AZACPU_SCLK
CPU_DP3_AUXP PROC_AUDIO_CLK AUD_AZACPU_SDO AUD_AZACPU_SCLK <20>
<25> CPU_DP3_AUXP A27 G25 AUD_AZACPU_SDO <20>
CPU_DP3_AUXN B27 DDI3_AUXP PROC_AUDIO_SDI G29 AUD_AZACPU_SDI
<25> CPU_DP3_AUXN DDI3_AUXN 4 ofPROC_AUDIO_SDO
13
CFL-H_BGA1440
AUD_AZACPU_SDI 1 2AUD_AZACPU_SDI_R
AUD_AZACPU_SDI_R <20>
RC66 20_0402_5%
B B
A A
Title
CFL-H (4/8)
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
CFL-H
UC1M
PAD~D @ T4 E2
IST_TRIG E3 RSVD_TP5
PAD~D @ T3 IST_TRIG
PAD~D @ T2 E1
D1 RSVD_TP4
PAD~D @ T1 RSVD_TP3
PAD~D @ T5 BR1 BK28
BT2 RSVD_TP1 RSVD11 BJ28 T29 @ PAD~D
PAD~D @ T6 RSVD_TP2 RSVD10 T30 @ PAD~D
PAD~D @ T7 BN35
RSVD15
PAD~D @ T9 J24
H24 RSVD28
PAD~D @ T10 RSVD27
PAD~D @ T11 BN33
BL34 RSVD14
PAD~D @ T8 RSVD13
PAD~D @ T14 N29
R14 RSVD30
PAD~D @ T13 RSVD31
PAD~D @ T15 AE29
C RSVD2 C
PAD~D @ T12 AA14
AP29 RSVD1
PAD~D @ T28 AP14 RSVD5
PAD~D @ T27 VSS_A36 RSVD4
A36
VSS_A36
VSS_A37 A37
VSS_A37
PCH_2_CPU_TRIGGER H23
<22> PCH_2_CPU_TRIGGER CPU_2_PCH_TRIGGER_R PROC_TRIGIN
J23
PROC_TRIGOUT
TP_SKL_F30 F30
PAD~D @ T285 RSVD24
TP_SKL_E30 E30
PAD~D @ T284 RSVD23
PAD~D @ T18
B30 BL31
RSVD7 RSVD12 T44 @ PAD~D
C30 AJ8
PAD~D @ T19 RSVD21 RSVD3 T41 @ PAD~D
G13
RSVD25 T42 @ PAD~D
PAD~D @ T21 G3
J3 RSVD26 C38
C1
RSVD20 BR2 T48 @ PAD~D
RSVD17 T47 @ PAD~D
BR35 BP1 T46 @ PAD~D
PAD~D @ T23 RSVD19 RSVD16
PAD~D @ T24
BR31 B38 T45 @ PAD~D
BH30 RSVD18 RSVD8 B2
13 OF 13
CFL-H_BGA1440
B B
CPU_2_PCH_TRIGGER 1 2 CPU_2_PCH_TRIGGER_R
<22> CPU_2_PCH_TRIGGER
RC177 30_0402_5%
VSS_A36 RC178 1 2 0_0402_5%

VSS_A37 RC179 1 2 0_0402_5%
A A
Title
CFL-H (5/8)
5 4 3 2 1
5 4 3 2 1
+VCC_GT +VCC_GT
CFL-H
+VCC_SA +1.2V_MEM
+VCCPLL_OC source PDDG page19, if don`t support DS3, contact to VDDQ directly
UC1K
AT14 BD35 CFL-H +1.2V_MEM +VCC_SFR_OC
Vinafix.com
AT31 VCCGT1 VCCGT80 BD36 UC1L
AT32 VCCGT2 VCCGT81 BE31 12A
AT33 VCCGT3 VCCGT82 BE32 J30 AA6 1 2
VCCGT4 VCCGT83 K29 VCCSA1 VDDQ1 AE12
AT34 BE33 VCCSA2 VDDQ2 @ RZ119 0_0402_5%
AT35 VCCGT5 VCCGT84 BE34 K30 AF5
D
VCCGT6 VCCGT85 K31 VCCSA3 VDDQ3 AF6 D
AT36 BE35 VCCSA4 VDDQ4
AT37 VCCGT7 VCCGT86 BE36 K32 AG5 UZ26
VCCGT8 VCCGT87 K33 VCCSA5 VDDQ5 AG9
AT38 BE37 VCCSA6 VDDQ6 1
VCCGT9 VCCGT88 K34 AJ12 1 2 2 VIN1
AU14 BE38 VCCSA7 VDDQ7 VIN2
AU29 VCCGT10 VCCGT89 BF13 K35 AL11 CZ102 1U_0402_6.3V6K
VCCGT11 VCCGT90 L31 VCCSA8 VDDQ8 AP6
AU30 BF14 VCCSA9 VDDQ9 7 6 1 2
VCCGT12 VCCGT91 L32 AP7 VIN thermal VOUT CZ103 0.1U_0201_10V6K
AU31 BF29 VCCSA10 VDDQ10
AU32 VCCGT13 VCCGT92 BF30 L35 AR12 3
VCCGT14 VCCGT93 L36 VCCSA11 VDDQ11 AR6 +5V_ALW VBIAS
AU35 BF31 VCCSA12 VDDQ12
AU36 VCCGT15 VCCGT94 BF32 L37 AT12 VCCSTG_EN 1 2 4 5
VCCGT16 VCCGT95 L38 VCCSA13 VDDQ13 AW6 ON GND
AU37 BF35 VCCSA14 VDDQ14 RZ120 0_0402_5%
AU38 VCCGT17 VCCGT96 BF36 M29 AY6
VCCGT18 VCCGT97 M30 VCCSA15 VDDQ15 J5 +3.3V_ALW
AV29 BF37 VCCSA16 VDDQ16 TPS22961DNYR_WSON8
AV30 VCCGT19 VCCGT98 BF38 M31 J6 @ CZ104
VCCGT20 VCCGT99 M32 VCCSA17 VDDQ17 K12
AV31 BG29 VCCSA18 VDDQ18 1 2
AV32 VCCGT21 VCCGT100 BG30 M33 K6
VCCGT22 VCCGT101 M34 VCCSA19 VDDQ19 L12
AV33 BG31 VCCSA20 VDDQ20 0.1U_0402_10V7K
5
AV34 VCCGT23 VCCGT102 BG32 M35 L6
VCCGT24 VCCGT103 M36 VCCSA21 VDDQ21 R6
AV35 BG33 1
P
VCCGT25 VCCGT104 VCCSA22 VDDQ22 T6 <20,46,52,53> PCH_PRIM_EN B
AV36 BG34 VDDQ23 4
VCCGT26 VCCGT105 W6 2 Y
AW14 BG35 VDDQ24 <11,20,21,37,51,52> SIO_SLP_S4# A
G
AW31 VCCGT27 VCCGT106 BG36 Y12 @ UZ34
VCCGT28 VCCGT107 +1.0VS_VCCIO AG12 VDDQ25
AW32 BH33 VCCIO1 TC7SH08FU_SSOP5
3
AW33 VCCGT29 VCCGT108 BH34 G15
VCCGT30 VCCGT109 G17 VCCIO2
AW34 BH35 VCCIO3
AW35 VCCGT31 VCCGT110 BH36 G19 BH13 +VCC_SFR_OC
VCCGT32 VCCGT111 G21 VCCIO4 VCCPLL_OC1 BJ13
AW36 BH37 VCCIO5 VCCPLL_OC2
AW37 VCCGT33 VCCGT112 BH38 H15 G11
VCCGT34 VCCGT113 H16 VCCIO6 VCCPLL_OC3
AW38 BJ16 VCCIO7
AY29 VCCGT35 VCCGT114 BJ17 H17 H30 +1.0V_VCCST
VCCGT36 VCCGT115 H19 VCCIO8 VCCST
AY30 BJ19 VCCIO9
AY31 VCCGT37 VCCGT116 BJ20 H20 H29
VCCIO10 VCCSTG2 +1.0V_VCCSTG
AY32 VCCGT38 VCCGT117 BJ21 H21
C
AY35
AY36
VCCGT39
VCCGT40
VCCGT41
VCCGT118
VCCGT119
VCCGT120
BJ23
BJ24
H26
H27
J15
VCCIO11
VCCIO12
VCCIO13
VCCSTG1
G30
H28
+VCC_FUSEPRG +1.0V_VCCSTG source +1.0V_VCCSTG +VCC_FUSEPRG
C
AY37 BJ26 VCCIO14 VCCPLL1 +1.0V_VCCSFR 2 1
AY38 VCCGT42 VCCGT121 BJ27 J16 J28
VCCGT43 VCCGT122 J17 VCCIO15 VCCPLL2 RC326 0_0402_5%
BA13 BJ37 VCCIO16
1
VCCGT44 VCCGT123 J19 +1.0V_PRIM
BA14 BJ38 VCCIO17
BA29 VCCGT45 VCCGT124 BK16 J20 M38 VCC_SA_SENSE <55> PJP2
VCCGT46 VCCGT125 J21 VCCIO18 VCCSA_SENSE M37 UZ19
BA30 BK17 VCCIO19 VSSSA_SENSE VSS_SA_SENSE <55> PAD-OPEN1x1m
BA31 VCCGT47 VCCGT126 BK19 J26 1
VCCGT48 VCCGT127 J27 VCCIO20 H14 2 VIN1
BA32 BK20 VCCIO21 VCCIO_SENSE VCC_IO_SENSE <54> VIN2
BA33 VCCGT49 VCCGT128 BK21 J14 VSS_IO_SENSE <54>
2
VCCGT50 VCCGT129 12 OF 13 VSSIO_SENSE +5V_ALW 7 6 +1.0V_VCCSTG_C 1 2
BA34 BK23 VIN thermal VOUT
BA35 VCCGT51 VCCGT130 BK24 CZ106 0.1U_0402_10V7K
BA36 VCCGT52 VCCGT131 BK26 CFL-H_BGA1440 3
VBIAS
1U_0402_6.3V6K
BB13 VCCGT53 VCCGT132 BK27 1
BB14 VCCGT54 VCCGT133 BL15 4 5
ON GND
CZ105
BB31 VCCGT55 VCCGT134 BL16
VCCGT57 VCCGT136 2 TPS22961DNYR_WSON8
BB33 BL23
BB34 VCCGT58 VCCGT137 BL24 +1.8V_PRIM_PCH +1.8V_PRIM +3.3V_RUN 4.4mohm/6A
TR=12.5us@Vin=1.05V
VCCGT61 VCCGT140 +3.3V_ALW
BB37 BL27
0.1U_0402_25V6
2
VCCGT62 VCCGT141
2
1
BB38 BL28
BC29 VCCGT63 VCCGT142 BL36 RZ543 RZ542
VCCGT64 VCCGT143
CZ544
BC30 BL37 10K_0402_5% 10K_0402_5%
2
BC31 VCCGT65 VCCGT144 BM15
5
VCCGT66 VCCGT145 @
BC32 BM16
1
C10_PWR_GATE#_R
1
VCCGT67 VCCGT146 UZ61 1
P
BC35 BM17 IN1 VCCSTG_EN
BC36 VCCGT68 VCCGT147 BM36 1 5 4
VCCGT69 VCCGT148 NC VCC 2 O
BC37 BM37 <37,38,46,52,54> RUN_ON IN2
G
BC38 VCCGT70 VCCGT149 BN15 2
VCCGT71 VCCGT150 <16,54> CPU_C10_GATE# A C10_PWR_GATE# UZ35
BD13 BN16 4 1 2
3
VCCGT72 VCCGT151 3 Y RH620 0_0402_5% SN74AHC1G08DCKR_SC70-5
BD14 BN17 GND
BD29 VCCGT73 VCCGT152 BN36
BD30 VCCGT74 VCCGT153 BN37 74AUP1G07GW_TSSOP5 1 2
BD31 VCCGT75 VCCGT154 BN38 @ RZ320 0_0402_5%
B VCCGT76 VCCGT155 1 2 B
BD32 BP15 <20,21,39,54> SIO_SLP_S0#
VCCGT77 VCCGT156 @ RH619 0_0402_5%
BD33 BP16
BD34 VCCGT78 VCCGT157 BP17
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
BR15 VCCGT160 VCCGT165 BT16
VCCGT163 VCCGT168
+VCC_SFR_OC
11 OFVSSGT_SENSE
13
VCCGT_SENSE
AH37
AH38 VSS_GT_SENSE
VCC_GT_SENSE
<55>
<55>
+1.0V_PRIM +1.0V_VCCST source
CFL-H_BGA1440 UZ21
1
2.2P_0402_50V8C
1 +1.0V_VCCST +1.0V_VCCSFR
2 VIN1
+1.0V_VCCSTG +1.0V_VCCST
RF@ CC322
VIN2 PJP1
2 +5V_ALW 7 6 +1.0V_VCCST_C 2 1 1 2
VIN thermal VOUT RC304 0_0402_5%
1 2
3
@ RZ151 0_0402_5% VBIAS PAD-OPEN1x1m
1
1U_0402_6.3V6K
4 5 1
ON GND
CZ100
0.1U_0402_10V7K
CZ101
RF Request 2 TPS22961DNYR_WSON8
2
4.4mohm/6A
TR=12.5us@Vin=1.05V
<11,20,21,37,51,52> SIO_SLP_S4#
A A
Title
CFL-H (6/8)
5 4 3 2 1
5 4 3 2 1
+1.2V_MEM
Vinafix.com
+1.0V_VCCSTG
PLACE CAP BACKSIDE
+1.0V_VCCSFR +1.0V_VCCST +VCC_SFR_OC +VCC_CORE +VCC_CORE
D D
+VCC_CORE +VCC_CORE CFL-H

CFL-H
10U_0603_6.3V6M~D
UC1J UC1I
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 2 2 2 2 2 2 AA13 AH13
@ CC195
AA31 VCC1 VCC64 AH14
K14 W35
CC185
CC186
CC192
CC191
CC210
CC209
VCC1 VCC64 AA32 VCC2 VCC65 AH29
L13 W36 VCC3 VCC66
2 1 1 1 1 1 1 L14 VCC2 VCC65 W37 AA33 AH30
VCC3 VCC66 AA34 VCC4 VCC67 AH31
N13 W38 VCC5 VCC68
N14 VCC4 VCC67 Y29 AA35 AH32
VCC5 VCC68 AA36 VCC6 VCC69 AJ14
N30 Y30 VCC7 VCC70
N31 VCC6 VCC69 Y31 AA37 AJ29
VCC7 VCC70 AA38 VCC8 VCC71 AJ30
N32 Y32 VCC9 VCC72
N35 VCC8 VCC71 Y33 AB29 AJ31
VCC9 VCC72 AB30 VCC10 VCC73 AJ32
close to UC1.Y12 N36 Y34 VCC11 VCC74
N37 VCC10 VCC73 Y35 AB31 AJ33
PLACE CAP BACKSIDE or BOARD EDGE VCC11 VCC74 AB32 VCC12 VCC75 AJ34
+1.0VS_VCCIO N38 Y36 VCC13 VCC76
+1.0V_VCCSFR P13 VCC12 VCC75 AB35 AJ35
VCC13 AB36 VCC14 VCC77 AJ36
PLACE CAP BACKSIDE P14 VCC15 VCC78
P29 VCC14 AB37 AK31
VCC15 AB38 VCC16 VCC79 AK32
P30 VCC17 VCC80
For SKL-H 4+2 P31 VCC16 AC13 AK33
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VCC17 AC14 VCC18 VCC81 AK34
22U_0603_6.3V6M
Remove VCCOPC/VCCEOPIO/
@ CC272
2 P32 VCC19 VCC82
1 VCC18 AC29 AK35
1
P33
CC189
CC188
CC187
VCC20 VCC83
VCCOPC_1P8 Cap VCC19 AC30 AK36
CC333
P34 VCC21 VCC84
P35 VCC20 AC31 AK37
1 VCC21 AC32 VCC22 VCC85 AK38
2
2
P36 VCC23 VCC86
R13 VCC22 AC33 AL13
VCC23 AC34 VCC24 VCC87 AL29
R31 VCC25 VCC88
R32 VCC24 AC35 AL30
VCC25 AC36 VCC26 VCC89 AL31
R33 VCC27 VCC90
R34 VCC26 AD13 AL32
VCC27 AD14 VCC28 VCC91 AL35
PDG rev1.0 R35
R36 VCC28 AD31 VCC29 VCC92 AL36
VCC29 AD32 VCC30 VCC93 AL37
R37 VCC31 VCC94
C R38 VCC30 AD33 AL38 C
VCC31 AD34 VCC32 VCC95 AM13
+1.0V_VCCST T29 VCC33 VCC96
T30 VCC32 AD35 AM14
T31 VCC35 VCC98
T32 VCC34 AD37 AM30
T35 VCC37 VCC100
T36 VCC36 AE13 AM32
VCC37 AE14 VCC38 VCC101 AM33
T37
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 VCC38 AE30 VCC39 VCC102 AM34

T38 VCC40 VCC103
U29 VCC39 AE31 AM35
CC193
CC194
VCC40 AE32 VCC41 VCC104 AM36

U30 VCC42 VCC105
U31 VCC41 AE35 AN13
1 1 VCC43 VCC106
U32 VCC42 AE36 AN14
VCC43 AE37 VCC44 VCC107 AN31
U33 VCC45 VCC108
U34 VCC44 AE38 AN32
VCC45 AF29 VCC46 VCC109 AN33
U35 VCC47 VCC110
VCC46 AF30 AN34
Remove to Power (+VCC_SA cap) U36
V13 VCC47 AF31 VCC48
VCC49
VCC111
VCC112
AN35
V14 VCC48 AF32 AN36
VCC49 AF33 VCC50 VCC113 AN37
V31 VCC51 VCC114
V32 VCC50 AF34 AN38
VCC51 AF35 VCC52 VCC115 AP13
V33 VCC53 VCC116
V34 VCC52 AF36 AP30
+1.2V_MEM VCC53 AF37 VCC54 VCC117 AP31
PLACE CAP BACKSIDE V35 VCC55 VCC118
+1.2V_MEM DECOUPLING V36 VCC54
VCC55
AF38
AG14 VCC56 VCC119
AP32
AP35
V37 VCC57 VCC120 +VCC_CORE
V38 VCC56 AG31 AP36
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
VCC57 AG32 VCC58 VCC121 AP37

W13 VCC59 VCC122
1 1 1 1 1 1 1 1 1 1 W14 VCC58 AG33 AP38
VCC60 VCC123
1
100_0402_1%
W29 VCC59 AG34 K13
CC161
CC170
CC164
CC168
CC163
CC166
CC171
CC165
CC172
CC167
VCC61 VCC124
RC140
W30 VCC60 AG35
VCC61 AG36 VCC62
2 2 2 2 2 2 2 2 2 2 W31 VCC63
W32 VCC62 10 OF 13
VCC63
2
CFL-H_BGA1440 VCC_SENSE
AG37
B VCC_SENSE VSS_SENSE VCC_SENSE <55> B
9 OF 13 AG38
VSS_SENSE VSS_SENSE <55>
CFL-H_BGA1440
1
100_0402_1%
RC141
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
CC81
CC82
CC83
CC84
2
VSS_SENSE 1 2 VCC_SENSE
@ RC221 49.9_0402_1%
A A
Title
CFL-H (7/8)
5 4 3 2 1
5 4 3 2 1
CFL-H CFL-H
CFL-H
UC1F UC1G UC1H
A10 AK4 AW5 BJ15 BN4 F15
A12 VSS_1 VSS_82 AL10 VSS_163 VSS_244 BN7 VSS_325 VSS_409 F17
VSS_2 VSS_83 AY12 BJ18 VSS_326 VSS_410
A16 AL12 AY33 VSS_164 VSS_245 BJ22 BP12 F19
VSS_3 VSS_84 VSS_327 VSS_411
A18
A20
A22
VSS_4
VSS_5
VSS_85
VSS_86 Vinafix.com
AL14
AL33
AL34
AY34
B9
BA10
VSS_165
VSS_166
VSS_167
VSS_246
VSS_247
VSS_248
BJ25
BJ29
BJ30
BP14
BP18
BP21
VSS_328
VSS_329
VSS_412
VSS_413
F2
F21
F23
A24 VSS_6 VSS_87 AL4 VSS_168 VSS_249 BP24 VSS_330 VSS_414 F25
D VSS_7 VSS_88 BA11 BJ31 VSS_331 VSS_415 D
A26 AL7 BA12 VSS_169 VSS_250 BJ32 BP25 F27
A28 VSS_8 VSS_89 AL8 VSS_170 VSS_251 BP26 VSS_332 VSS_416 F29
VSS_9 VSS_90 BA37 BJ33 VSS_333 VSS_417
A30 AL9 BA38 VSS_171 VSS_252 BJ34 BP29 F3
A6 VSS_10 VSS_91 AM1 VSS_172 VSS_253 BP33 VSS_334 VSS_418 F31
VSS_11 VSS_92 BA6 BJ35 VSS_335 VSS_419
A9 AM12 BA7 VSS_173 VSS_254 BJ36 BP34 F36
AA12 VSS_12 VSS_93 AM2 VSS_174 VSS_255 BP7 VSS_336 VSS_420 F4
VSS_13 VSS_94 BA8 BK13 VSS_337 VSS_421
AA29 AM3 BA9 VSS_175 VSS_256 BK14 BR12 F5
AA30 VSS_14 VSS_95 AM37 VSS_176 VSS_257 BR14 VSS_338 VSS_422 F8
VSS_15 VSS_96 BB1 BK15 VSS_339 VSS_423
AB33 AM38 BB12 VSS_177 VSS_258 BK18 BR18 F9
AB34 VSS_16 VSS_97 AM4 VSS_178 VSS_259 BR21 VSS_340 VSS_424 G10
AB6 AM5 BB29 VSS_179 VSS_260 BK25 BR24 G12
AC1 VSS_18 VSS_99 AN12 VSS_180 VSS_261 BR25 VSS_342 VSS_426 G14
AC12 AN29 BB30 VSS_181 VSS_262 BK6 BR26 G16
VSS_21 VSS_102 BB4 BL13 VSS_345 VSS_429
AC3 AN5 BB5 VSS_183 VSS_264 BL14 BR34 G20
VSS_23 VSS_104 BB6 BL18 VSS_347 VSS_431
AC38 AP10 BC12 VSS_185 VSS_266 BL19 BR7 G23
AC4 VSS_24 VSS_105 AP11 VSS_186 VSS_267 BT12 VSS_348 VSS_432 G24
VSS_25 VSS_106 BC13 BL20 VSS_349 VSS_433
AC5 AP12 BC14 VSS_187 VSS_268 BL21 BT14 G26
AC6 VSS_26 VSS_107 AP33 VSS_188 VSS_269 BT18 VSS_350 VSS_434 G28
AD10 AP34 BC34 VSS_189 VSS_270 BL29 BT21 G4
AD11 VSS_28 VSS_109 AP8 VSS_190 VSS_271 BT24 VSS_352 VSS_436 G5
AD12 AP9 BD10 VSS_191 VSS_272 BL35 BT26 G6
AD29 VSS_30 VSS_111 AR1 VSS_192 VSS_273 BT29 VSS_354 VSS_438 G8
VSS_31 VSS_112 BD11 BL38 VSS_355 VSS_439
AD30 AR13 BD12 VSS_193 VSS_274 BL6 BT32 G9
AD6 VSS_32 VSS_113 AR14 VSS_194 VSS_275 BT5 VSS_356 VSS_440 H11
VSS_33 VSS_114 BD37 BM11 VSS_357 VSS_441
AD8 AR2 BD6 VSS_195 VSS_276 BM12 C11 H12
AD9 VSS_34 VSS_115 AR29 VSS_196 VSS_277 C13 VSS_358 VSS_442 H18
AE33 AR3 BD8 VSS_197 VSS_278 BM14 C15 H22
C
AE34 VSS_36 VSS_117 AR30 VSS_198 VSS_279 C17 VSS_360 VSS_444 H25 C
AE6 AR31 BE1 VSS_199 VSS_280 BM2 C19 H32
AF1 VSS_38 VSS_119 AR32 VSS_200 VSS_281 C21 VSS_362 VSS_446 H35
VSS_39 VSS_120 BE2 BM21 VSS_363 VSS_447
AF12 AR33 BE29 VSS_201 VSS_282 BM22 C23 J10
AF13 VSS_40 VSS_121 AR34 VSS_202 VSS_283 C25 VSS_364 VSS_448 J18
AG10 AR4 BF12 VSS_207 VSS_288 BM28 C5 J36
AG11 VSS_46 VSS_127 AR5 VSS_208 VSS_289 C8 VSS_370 VSS_454 J4
VSS_47 VSS_128 BF33 BM29 VSS_371 VSS_455
AG13 AT29 BF34 VSS_209 VSS_290 BM3 C9 J7
AG29 VSS_48 VSS_129 AT30 VSS_210 VSS_291 D10 VSS_372 VSS_456 K1
VSS_49 VSS_130 BF6 BM33 VSS_373 VSS_457
AG30 AT6 BG12 VSS_211 VSS_292 BM35 D12 K10
AG6 VSS_50 VSS_131 AU10 VSS_212 VSS_293 D14 VSS_374 VSS_458 K11
VSS_51 VSS_132 BG13 BM38 VSS_375 VSS_459
AG7 AU11 BG14 VSS_213 VSS_294 BM5 D16 K2
AG8 VSS_52 VSS_133 AU12 VSS_214 VSS_295 D18 VSS_376 VSS_460 K3
AH12 AU33 BG38 VSS_215 VSS_296 BM7 D20 K38
AH33 VSS_54 VSS_135 AU34 VSS_216 VSS_297 D22 VSS_378 VSS_462 K4
AH34 AU6 BH1 VSS_217 VSS_298 BM9 D24 K5
VSS_57 VSS_138 BH10 BN12 VSS_381 VSS_465
AH36 AU8 BH11 VSS_219 VSS_300 BN14 D28 K8
AJ1 AV37 BH14 VSS_221 VSS_302 BN19 D30 L29
AJ13 VSS_60 VSS_141 AV38 VSS_222 VSS_303 D33 VSS_384 VSS_468 L30
AJ2 AW1 BH3 VSS_223 VSS_304 BN20 D6 L33
AJ3 VSS_62 VSS_143 AW12 VSS_224 VSS_305 D9 VSS_386 VSS_470 L34
AJ37 AW2 BH5 VSS_225 VSS_306 BN24 E34 M12
AJ38 VSS_64 VSS_145 AW29 VSS_226 VSS_307 E35 VSS_388 VSS_472 M13
B VSS_65 VSS_146 BH6 BN29 VSS_389 VSS_473 B
AJ4 AW3 BH7 VSS_227 VSS_308 BN30 E38 N10
AJ5 VSS_66 VSS_147 AW30 VSS_228 VSS_309 E4 VSS_390 VSS_474 N11
AJ6 AW4 BH9 VSS_229 VSS_310 BN34 E9 N12
W4 VSS_68 VSS_149 U6 VSS_230 VSS_311 N3 VSS_392 VSS_476 N2
VSS_69 VSS_150 T2 P38 VSS_393 VSS_477
W5 V12 T3 VSS_231 VSS_312 P6 N33 BT8
Y10 VSS_70 VSS_151 V29 VSS_232 VSS_313 N34 VSS_394 VSS_478 BR9
VSS_71 VSS_152 T33 R12 VSS_395 VSS_479
Y11 V30 T34 VSS_233 VSS_314 R29 N4
Y13 VSS_72 VSS_153 A14 VSS_234 VSS_315 N5 VSS_396 A3
VSS_73 VSS_154 T4 AY14 VSS_397 VSS_A3
Y14 AD7 T5 VSS_235 VSS_316 BD38 N6 A34
Y37 VSS_74 VSS_155 V6 VSS_236 VSS_317 N7 VSS_398 VSS_A34 A4
VSS_75 VSS_156 T7 R30 VSS_399 VSS_A4
Y38 W1 T8 VSS_237 VSS_318 T1 N8 B3
Y7 VSS_76 VSS_157 W12 VSS_238 VSS_319 N9 VSS_400 VSS_B3 B37
VSS_77 VSS_158 T9 T10 VSS_401 VSS_B37
Y8 W2 U37 VSS_239 VSS_320 T11 P12 BR38
Y9 VSS_78 VSS_159 W3 VSS_240 VSS_321 P37 VSS_402 VSS_BR38 BT3
VSS_79 VSS_160 U38 T12 VSS_403 VSS_BT3
AK29 W33 BJ12 VSS_241 VSS_322 T13 M14 BT35
AK30 VSS_80
6 OF VSS_161
13 W34 VSS_2427 OF VSS_323 M6 VSS_404 VSS_BT35 BT36
VSS_81 VSS_162 BJ14 13 T14 VSS_405 VSS_BT36
VSS_243 VSS_324 N1 BT4
CFL-H_BGA1440 F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 VSS_4078 OF 13VSS_C2
F13 D38
VSS_408 VSS_D38
CFL-H_BGA1440
A A
Title
CFL-H (8/8)
5 4 3 2 1
5 4 3 2 1
<8> DDR_A_DQS#[0..7]
<8> DDR_A_DQS[0..7]
<8> DDR_A_D[0..15]
<8> DDR_A_D[16..31]
<8> DDR_A_D[32..47] +1.2V_MEM +1.2V_MEM
<8> DDR_A_D[48..63]
JDIMM1
<8> DDR_A_MA[0..16]
1 2
DDR_A_D5 3 VSS1 VSS2 4 DDR_A_D4
5 DQ5 DQ4 6
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9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
Layout Note: 15 DQS0_t VSS7 16 DDR_A_D6
DDR_A_D2 VSS8 DQ6
D
Place near JDIMM1 17
19 DQ7 VSS9
18
20 DDR_A_D7
D
DDR_A_D3 21 VSS10 DQ2 22

23 DQ3 VSS11 24 DDR_A_D12
DDR_A_D9 25 VSS12 DQ12 26
27 DQ13 VSS13 28 DDR_A_D13
DDR_A_D8 29 VSS14 DQ8 30 +1.2V_MEM
+1.2V_MEM 31 DQ9 VSS15 32 DDR_A_DQS#1
33 VSS16 DQS1_c 34 DDR_A_DQS1
35 DM1_n/DBI_n DQS1_t 36
1
DQ15 DQ14
330U_D3_2.5VY_R6M
39 40
DDR_A_D10 VSS19 VSS20 DDR_A_D11
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
41 42 RD11
43 DQ10 DQ11 44 470_0402_1%
1 1 DDR_A_D33 VSS21 VSS22 DDR_A_D32
330U_2V_M
1 1 1 1 1 1 1 1 @ @ 45 46
2
DQ21 DQ20
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD17
CD63
+ + 47 48
51 DQ17 DQ16 52 1 2 DDR4_DRAMRST#_PCH
2 2 2 2 2 2 2 2 2 2 DDR_A_DQS#4 VSS25 VSS26 <15> DDR_DRAMRST# DDR4_DRAMRST#_PCH <20>
53 54 RD12 0_0402_5%
DDR_A_DQS4 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_A_D38
DDR_A_D34 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D39
+2.5V_MEM DDR_A_D35 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D44
DDR_A_D41 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_A_D45
DDR_A_D40 71 VSS34 DQ24 72
DQ25 VSS35
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
73 74 DDR_A_DQS#5
1 1 1 1 1 1 1 1 1 1 1 1 VSS36 DQS3_c DDR_A_DQS5
75 76
DM3_n/DBI3_n DQS3_t
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
CD18
CD19
CD20
CD21
77 78
2 2 2 2 2 2 2 2 2 2 2 2 81 DQ30 DQ31 82
85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
C DQS8_c DM8_n/DBI_n/NC C
97 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
103 CB2/NC VSS49 104 JDIMM1_EVENT# 1 2
VSS50 CB7/NC H_THERMTRIP# <7,15,16,38>
105 106 @ RD14 1K_0402_5%
107 CB3/NC VSS51 108 DDR_DRAMRST#
Layout Note: DDR_A_CKE0 109 VSS52 RESET_n 110 DDR_A_CKE1
1
<8> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <8>
Place near DDR_A_BG1
111
113 VDD1 VDD2
112
114 DDR_A_ACT# @ CD29
JDIMM1.258 <8>
<8>
DDR_A_BG1
DDR_A_BG0
DDR_A_BG0 115 BG1 ACT_n 116 DDR_A_ALERT# DDR_A_ACT#
DDR_A_ALERT#
<8>
<8> 0.1U_0402_10V6K
117 BG0 ALERT_n 118 2
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
DDR_A_MA6 127 A8 A5 128 DDR_A_MA4
129 A6 A4 130
+0.6V_DDR_VTT +DDR_VREF_A_CA DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
DDR_A_MA1 133 A3 A2 134 JDIMM1_EVENT#
135 A1 EVENT_n/NF 136
DDR_A_CLK0 137 VDD9 VDD10 138 DDR_A_CLK1 +1.2V_MEM
<8> DDR_A_CLK0 DDR_A_CLK#0 CK0_t CK1_t/NF DDR_A_CLK#1 DDR_A_CLK1 <8>
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
139 140
<8> DDR_A_CLK#0 CK0_c CK1_c/NF DDR_A_CLK#1 <8>
0.1U_0402_10V6K
1 1 1 141 142
1
DDR_A_PAR VDD11 VDD12 DDR_A_MA0
CD22
CD23
CD24
2.2U_0402_6.3V6M
1K_0402_1%
1 1 143 144
<8> DDR_A_PAR DDR_A_BA1 PARITY A0 DDR_A_MA10
@ CD26
145 146
<8> DDR_A_BA1 BA1 A10/AP
CD25
RD15
147 148
2 2 2 DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
2 2 <8> DDR_A_CS#0 DDR_A_MA14 CS0_n BA0 DDR_A_MA16 DDR_A_BA0 <8> +DDR_VREF_A_CA +DDR_VREF_CA
151 152
2
153 WE_n/A14 RAS_n/A16 154
DDR_A_ODT0 155 VDD15 VDD16 156 DDR_A_MA15
<8> DDR_A_ODT0 DDR_A_CS#1 ODT0 CAS_n/A15 DDR_A_MA13
157 158 1 2
<8> DDR_A_CS#1 CS1_n A13 +DDR_VREF_A_CA
159 160 RD17 2_0402_1%
DDR_A_ODT1 VDD17 VDD18 @ T50
0.022U_0402_16V7K
161 162
<8> DDR_A_ODT1 ODT1 C0/CS2_n/NC PAD~D +DDR_VREF_A_CA
163 164
1
VDD19 VREFCA DIMM1_SA2
1K_0402_1%
165 166 1
T51 @ PAD~D C1, CS3_n,NC SA2
CD31
167 168
DDR_A_D17 VSS53 VSS54 DDR_A_D16
RD16
169 170
171 DQ37 DQ36 172
DDR_A_D21 173 VSS55 VSS56 174 DDR_A_D20 2
2
DQ33 DQ32
24.9_0402_1%
175 176
1
DDR_A_DQS#2 177 VSS57 VSS58 178
DDR_A_DQS2 DQS4_c DM4_n/DBI4_n
RD18
B 179 180 B
181 DQS4_t VSS59 182 DDR_A_D23
DDR_A_D22 183 VSS60 DQ39 184
185 DQ38 VSS61 186 DDR_A_D18
2
DDR_A_D19 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D30
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN DDR_A_D25
DDR_A_D26
191
193
195
VSS64
DQ44
VSS66
DQ45
VSS65
DQ41
192
194
196
DDR_A_D24
1
197 DQ40 VSS67 198 DDR_A_DQS#3

@ RD4 @ RD6 @ RD8 RD10 199 VSS68 DQS5_c 200 DDR_A_DQS3
0_0402_5% 0_0402_5% 0_0402_5% 0_0603_5% 201 DM5_n/DBI5_n DQS5_t 202
205 DQ46 DQ47 206
2
+3.3V_RUN_DIMM1 DDR_A_D29 207 VSS71 VSS72 208 DDR_A_D27

DIMM1_SA0 209 DQ42 DQ43 210
DIMM1_SA1 DDR_A_D49 VSS73 VSS74 DDR_A_D48 +3.3V_RUN
2.2U_0402_6.3V6M
0.1U_0201_10V6K
1 1 211 212
DIMM1_SA2 213 DQ52 DQ53 214
SA0 SA1 SA2 DDR_A_D50 VSS75 VSS76 DDR_A_D54
CD27
CD28
215 216
1
217 DQ49 DQ48 218

* DIMM1 0 0 0
1
2 2 DDR_A_DQS#6 VSS77 VSS78
330K_0402_5%
RD5 RD7 RD9 219 220
DDR_A_DQS6 DQS6_c DM6_n/DBI6_n
RD19
0_0402_5% 0_0402_5% 0_0402_5% 221 222
DIMM2 1 0 0 223 DQS6_t VSS79 224 DDR_A_D53
DDR_A_D55 225 VSS80 DQ54 226
DIMM3 0 1 0
2
227 DQ55 VSS81 228 DDR_A_D52 +1.2V_MEM
2
DDR_A_D51 229 VSS82 DQ50 230
DIMM4 1 1 0 231 DQ51 VSS83 232 DDR_A_D62 UD1
DDR_A_D60 233 VSS84 DQ60 234 1 5 1 2
235 DQ61 VSS85 236 DDR_A_D57 NC VCC @ CD32 0.1U_0402_25V6
DDR_A_D59 237 VSS86 DQ57 238 2
DQ56 VSS87 DDR_A_DQS#7 <7> DDR_VTT_CTRL A 0.6V_DDR_VTT_ON
239 240 4
VSS88 DQS7_c DDR_A_DQS7 Y 0.6V_DDR_VTT_ON <51>
241 242 3
243 DM7_n/DBI7_n DQS7_t 244 GND
DDR_A_D61 245 VSS89 VSS90 246 DDR_A_D56 74AUP1G07SE-7_SOT353
Byte[0] DQ[7:0] DQS/DQS#[0] DDR_A_D58

247
249
251
DQ62
VSS91
DQ58
DQ63
VSS92
DQ59
248
250
252
DDR_A_D63
Byte[1] DQ[15:8] DQS/DQS#[1] <7,15,20,41> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM1

253
255
257
VSS93
SCL
VDDSPD
VSS94
SDA
SA0
254
256
258
DIMM1_SA0 DDR_XDP_WAN_SMBDAT <7,15,20,41>
A
Byte[2] DQ[23:16] DQS/DQS#[2]
+2.5V_MEM
259
261
VPP1
VPP2
GND1
VTT
SA1
GND2
260
262
DIMM1_SA1 +0.6V_DDR_VTT
* Byte[3] DQ[31:24] DQS/DQS#[3]

Byte[4] DQ[39:32] DQS/DQS#[4] LCN_DAN05-Q0406-0103
CONN@
* Byte[5] DQ[47:40] DQS/DQS#[5]

Byte[6] DQ[55:48] DQS/DQS#[6] DELL CONFIDENTIAL/PROPRIETARY
Byte[7] DQ[63:56] DQS/DQS#[7] Security Classification Compal Secret Data
Title
DDR4-SODIMM SLOT1
5 4 3 2 1
5 4 3 2 1
<8> DDR_B_DQS#[0..7]
<8> DDR_B_DQS[0..7]
<8> DDR_B_D[0..15]
<8> DDR_B_D[16..31] +1.2V_MEM +1.2V_MEM
<8> DDR_B_D[32..47]
JDIMM2
<8> DDR_B_D[48..63]
<8> DDR_B_MA[0..16]
1 2
DDR_B_D0 3 VSS1 VSS2 4 DDR_B_D1
5 DQ5 DQ4 6
9 DQ1 DQ0 10
DDR_B_DQS#0 11 VSS5 VSS6 12
Vinafix.com
DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D2
Layout Note: DDR_B_D3 17 VSS8 DQ6 18
DQ7 VSS9 DDR_B_D6
Place near JDIMM2 DDR_B_D7
19
21 VSS10 DQ2
20
22
D 23 DQ3 VSS11 24 DDR_B_D8 D
DDR_B_D12 25 VSS12 DQ12 26
27 DQ13 VSS13 28 DDR_B_D13
DDR_B_D9 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_B_DQS#1
33 VSS16 DQS1_c 34 DDR_B_DQS1
+1.2V_MEM 35 DM1_n/DBI_n DQS1_t 36
39 DQ15 DQ14 40
DQ10 DQ11
330U_D3_2.5VY_R6M
43 44
DDR_B_D38 VSS21 VSS22 DDR_B_D36
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
45 46
47 DQ21 DQ20 48
1 1 DDR_B_D32 VSS23 VSS24 DDR_B_D34
330U_2V_M
1 1 1 1 1 1 1 1 @ @ 49 50
DQ17 DQ16
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD49
CD64
+ + 51 52
DDR_B_DQS4 55 DQS2_c DM2_n/DBI2_n 56
2 2 2 2 2 2 2 2 2 2 57 DQS2_t VSS27 58 DDR_B_D33
DDR_B_D35 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_B_D39
DDR_B_D37 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_B_D45
+2.5V_MEM DDR_B_D40 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D41
DDR_B_D44 71 VSS34 DQ24 72
DQ25 VSS35
73 74 DDR_B_DQS#5
VSS36 DQS3_c DDR_B_DQS5
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
75 76
77 DM3_n/DBI3_n DQS3_t 78
1 1 1 1 1 1 1 1 1 1 1 1 DDR_B_D46 VSS37 VSS38 DDR_B_D43
79 80
DQ30 DQ31
CD41
CD42
CD43
CD44
CD45
CD46
CD47
CD48
CD50
CD51
CD52
CD53
81 82
2 2 2 2 2 2 2 2 2 2 2 2 85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
C CB2/NC VSS49 C
103 104
105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108 DDR_DRAMRST# JDIMM2_EVENT# 1 2
DDR_B_CKE0 VSS52 RESET_n DDR_B_CKE1 DDR_DRAMRST# <14> H_THERMTRIP# <7,14,16,38>
109 110 @ RD27 1K_0402_5%
<8> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <8>
111 112
Layout Note: DDR_B_BG1 113 VDD1 VDD2 114 DDR_B_ACT#
1
<8> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <8>
Place near <8> DDR_B_BG0
115
117 BG0 ALERT_n
116
118 DDR_B_ALERT# <8>
@ CD61
JDIMM2.258 DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11
0.1U_0402_10V6K
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7 2
123 A9 A7 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
+0.6V_DDR_VTT DDR_B_MA1 133 A3 A2 134 JDIMM2_EVENT#
+DDR_VREF_B_CA 135 A1 EVENT_n/NF 136
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1
<8> DDR_B_CLK0 DDR_B_CLK#0 CK0_t CK1_t/NF DDR_B_CLK#1 DDR_B_CLK1 <8>
139 140
<8> DDR_B_CLK#0 CK0_c CK1_c/NF DDR_B_CLK#1 <8>
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
141 142
DDR_B_PAR 143 VDD11 VDD12 144 DDR_B_MA0
1 1 1 <8> DDR_B_PAR DDR_B_BA1 PARITY A0 DDR_B_MA10 +1.2V_MEM
CD54
CD55
CD56
0.1U_0402_10V6K
2.2U_0402_6.3V6M
145 146
<8> DDR_B_BA1 BA1 A10/AP
@ CD58
1 1 147 148
DDR_B_CS#0 VDD13 VDD14 DDR_B_BA0
CD57
149 150 DDR_B_BA0 <8>

<8> DDR_B_CS#0
1
2 2 2 DDR_B_MA14 CS0_n BA0 DDR_B_MA16
1K_0402_1%
151 152
153 WE_n/A14 RAS_n/A16 154
2 2 DDR_B_ODT0 VDD15 VDD16 DDR_B_MA15
RD28
155 156
<8> DDR_B_ODT0 DDR_B_CS#1 ODT0 CAS_n/A15 DDR_B_MA13 +DDR_VREF_B_CA +DDR_VREF_B_DQ
<8> DDR_B_CS#1
157 158
159 CS1_n A13 160 +DDR_VREF_B_CA
@ T52
2
DDR_B_ODT1 161 VDD17 VDD18 162
<8> DDR_B_ODT1 ODT1 C0/CS2_n/NC PAD~D +DDR_VREF_B_CA
163 164 1 2
165 VDD19 VREFCA 166 DIMM2_SA2 RD30 2_0402_1%
T53 @ PAD~D C1, CS3_n,NC SA2
0.022U_0402_16V7K
167 168
1
DDR_B_D22 VSS53 VSS54 DDR_B_D19
1K_0402_1%
169 170
171 DQ37 DQ36 172
DDR_B_D23 VSS55 VSS56 DDR_B_D18 1
RD29
CD62
173 174
175 DQ33 DQ32 176
2
DDR_B_DQS2 179 DQS4_c DM4_n/DBI4_n 180 2
DDR_B_D17 VSS60 DQ39
24.9_0402_1%
183 184
1
185 DQ38 VSS61 186 DDR_B_D20
B B
DDR_B_D16 VSS62 DQ35
RD31
187 188
189 DQ34 VSS63 190 DDR_B_D28
DDR_B_D24 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_B_D29
2
DDR_B_D25 195 VSS66 DQ41 196
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN 197
199
201
DQ40
VSS68
DM5_n/DBI5_n
VSS67
DQS5_c
DQS5_t
198
200
202
DDR_B_DQS#3
DDR_B_DQS3
1

@ RD20 RD22 @ RD24 RD26 205 DQ46 DQ47 206
0_0402_5% 0_0402_5% 0_0402_5% 0_0603_5% DDR_B_D27 207 VSS71 VSS72 208 DDR_B_D30
209 DQ42 DQ43 210
2
+3.3V_RUN_DIMM2 213 DQ52 DQ53 214

DIMM2_SA0 DDR_B_D54 215 VSS75 VSS76 216 DDR_B_D48
DIMM2_SA1 DQ49 DQ48
2.2U_0402_6.3V6M
0.1U_0201_10V6K
1 1 217 218
DIMM2_SA2 DDR_B_DQS#6 219 VSS77 VSS78 220
SA0 SA1 SA2 DDR_B_DQS6 DQS6_c DM6_n/DBI6_n
CD59
CD60
221 222
1

DIMM1 0 0 0 RD21 @ RD23 RD25 2 2 DDR_B_D53 225 VSS80 DQ54 226
0_0402_5% 0_0402_5% 0_0402_5% 227 DQ55 VSS81 228 DDR_B_D50
DIMM2 1 0 0 DDR_B_D49 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_B_D61
* DIMM3 0 1 0
2
DDR_B_D62 233 VSS84 DQ60 234

235 DQ61 VSS85 236 DDR_B_D57
DIMM4 1 1 0 DDR_B_D59 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_B_DQS#7
241 VSS88 DQS7_c 242 DDR_B_DQS7
243 DM7_n/DBI7_n DQS7_t 244
247 DQ62 DQ63 248
251 DQ58 DQ59 252
Byte[0] DQ[7:0] DQS/DQS#[0] <7,14,20,41> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM2

253
255
257
VSS93
SCL
VDDSPD
VSS94
SDA
SA0
254
256
258
DIMM2_SA0 DDR_XDP_WAN_SMBDAT <7,14,20,41>

+2.5V_MEM
259
261
VPP1
VPP2
GND1
VTT
SA1
GND2
260
262
DIMM2_SA1 +0.6V_DDR_VTT
A
A
* Byte[3] DQ[31:24] DQS/DQS#[3] LCN_DAN05-Q0406-0103

CONN@

* Byte[5] DQ[47:40] DQS/DQS#[5]
Byte[6] DQ[55:48] DQS/DQS#[6] DELL CONFIDENTIAL/PROPRIETARY
Byte[7] DQ[63:56] DQS/DQS#[7] Security Classification Compal Secret Data
Title
DDR4-SODIMM SLOT2
5 4 3 2 1
5 4 3 2 1
+1.8V_PRIM +1.8V_PRIM
2
@ RH607
100K_0402_5% RH604
4.7K_0402_5%
1
CNV_COEX1 CNV_BRI_PTX_DRX
CNP-H
UH1M
1
VCCSPI hard strap
1
CAM_MIC_CBL_DET# CLK_CNV_PRX_DTX_N
Vinafix.com
AW13 BD4
<32> CAM_MIC_CBL_DET# GPP_G0/SD_CMD CNV_WR_CLKN CLK_CNV_PRX_DTX_P CLK_CNV_PRX_DTX_N <35> RH608 Xtal Frequency select @ RH603
BE9 BE3
GPP_G1/SD_DATA0 CNV_WR_CLKP CLK_CNV_PRX_DTX_P <35> 100K_0402_5% 10K_0402_5%
BF8 HIG H 1.8V
BF9 GPP_G2/SD_DATA1 BB3 CNV_PRX_DTX_N0
CNV_PRX_DTX_N0 <35> HIG H 24MHz
CONTACTLESS_DET# GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_P0
2
BG8 BB4
2
<39> CONTACTLESS_DET# HOST_SD_WP# GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_N1 CNV_PRX_DTX_P0 <35>
D BE8 BA3 D
<34> HOST_SD_WP# AUD_PWR_EN GPP_G5/SD_CD# CNV_WR_D1N CNV_PRX_DTX_P1 CNV_PRX_DTX_N1 <35> LOW 3.3V
<36> AUD_PWR_EN BD8 BA2 LOW 38.4/19.2MHz
GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 <35> (default)
AV13
GPP_G7/SD_WP BC5 CLK_CNV_PTX_DRX_N
CNV_WT_CLKN CLK_CNV_PTX_DRX_P CLK_CNV_PTX_DRX_N <35> CNP EDS rev0.7
AP3 BB6
GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP CLK_CNV_PTX_DRX_P <35> An external pull-up is required on this strap
AP2 since 38.4 MHz XTAL is not supported on the PCH.
AN4 GPP_I12/M2_SKT2_CFG1 BE6 CNV_PTX_DRX_N0
GPP_I13/M2_SKT2_CFG2 CNV_WT_D0N CNV_PTX_DRX_P0 CNV_PTX_DRX_N0 <35>
AM7 BD7
GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P CNV_PTX_DRX_N1 CNV_PTX_DRX_P0 <35>
BG6 +1.8V_PRIM
CNV_COEX3 CNV_WT_D1N CNV_PTX_DRX_P1 CNV_PTX_DRX_N1 <35>
<35> CNV_COEX3 AV6 BF6
GPP_J1 GPP_J0/CNV_PA_BLANKING CNV_WT_D1P CNV_WT_RCOMP CNV_PTX_DRX_P1 <35>
1 2 AY3 BA1 2 1
<11,54> CPU_C10_GATE# GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
RH616 0_0402_5% AR13 RH612 150_0402_1%
2
AV7 GPP_J11/A4WP_PRESENT B12 PCIECOMP# 2 1
AW3 GPP_J10 PCIE_RCOMPN A13 PCIECOMP RH192 100_0402_1% RH605
AT10 GPP_J_2 PCIE_RCOMPP BE5 SD_RCOMP_1P8 2 1 20K_0402_5%
+1.8V_PRIM CNV_BRI_PTX_DRX AV4 GPP_J_3 SD_1P8_RCOMP SD_RCOMP_3P3 RH611 2
BE4 1 200_0402_1%
<35> CNV_BRI_PTX_DRX CNV_BRI_PRX_DTX AY2 GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP BD1 200_0402_1%
1
<35> CNV_BRI_PRX_DTX RH610
1 2 CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX BA4 GPP_J5/CNV_BRI_RSP/UART0B_RXDGPPJ_RCOMP_1P81 BE1 GPPJ_RCOMP 2 1 CNV_RGI_PTX_DRX
<35> CNV_RGI_PTX_DRX CNV_RGI_PRX_DTX AV3 GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82
RH614 20K_0402_5% BE2 RH609 200_0402_1%
CNV_RGI_PRX_DTX <35> CNV_RGI_PRX_DTX CNV_COEX2 GPP_J7/CNV_RGI_RSP/UART0B_CTS#GPPJ_RCOMP_1P83
1 2 <35> CNV_COEX2 AW2
1
RH613 20K_0402_5% CNV_COEX1 AU9 GPP_J8/CNV_MFUART2_RXD Y35
<35> CNV_COEX1 T34 @ PAD~D M.2 CNV Mode Select
GPP_J9/CNV_MFUART2_TXD RSVD2 Y36
T33 @ PAD~D @ RH606
RSVD3
Integrated CNVi 100K_0402_5%
BC1 HIG H
CFL PDG rev0.5 13 OF 13 RSVD1 AL35 T36 @ PAD~D disable
2
To avoid floating input at the I/O pin it is recommended TP T35 @ PAD~D
to add a weak pull up resistor to the SOC pin with a recommended value of 20K ohm. CNP-H_BGA874 Rev1.0 Integrated CNVi
LOW
enable
CNP-H
C C
UH1C
PCH_CL_CLK1 AR2 G36 PCIE_PRX_DTX_N9
<35> PCH_CL_CLK1 PCH_CL_DATA1 CL_CLK PCIE9_RXN PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 <40>
AT5 F36
<35> PCH_CL_DATA1 PCH_CL_RST1# CL_DATA PCIE9_RXP PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 <40>
AU4 C34
<35> PCH_CL_RST1# CL_RST# PCIE9_TXN PCIE_PTX_DRX_P9 PCIE_PTX_DRX_N9 <40>
D34
P48 PCIE9_TXP PCIE_PTX_DRX_P9 <40>
V47 GPP_K8
GPP_K9 PCIE_PRX_DTX_N10 M.2 Socket 3 (Key M)
V48 K37
GPP_K10 PCIE10_RXN PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 <40>
W47 J37
GPP_K11 PCIE10_RXP PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <40>
C35
L47 PCIE10_TXN B35 PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 <40>
L46 GPP_K0 PCIE10_TXP PCIE_PTX_DRX_P10 <40>
U48 GPP_K1 F44 SATA_PRX_DTX_N2
GPP_K2 PCIE15_RXN/SATA2_RXN SATA_PRX_DTX_P2 SATA_PRX_DTX_N2 <41>
U47 E45
GPP_K3 PCIE15_RXP/SATA2_RXP SATA_PTX_DRX_N2 SATA_PRX_DTX_P2 <41>
N48 B40 SATA HDD
N47 GPP_K4 PCIE_15_SATA_2_TXN C40 SATA_PTX_DRX_P2 SATA_PTX_DRX_N2 <41>
P47 GPP_K5 PCIE15_TXP/SATA2_TXP SATA_PTX_DRX_P2 <41>
+3.3V_RUN R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40
PCIE_PTX_DRX_P11 C36 PCIE16_RXP/SATA3_RXP B41
<40> PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
1 2 CAM_MIC_CBL_DET# <40> PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
M.2 Socket 3 (Key M) F39
RH319 10K_0402_5% <40> PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 PCIE11_RXP/SATA0A_RXP PCIE_PRX_DTX_N17
M2280_PCIE_SATA# G38 K43
1 2 <40> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN PCIE_PRX_DTX_P17 PCIE_PRX_DTX_N17 <35>
K44
RH318 10K_0402_5% BIOS_REC PCIE17_RXP/SATA4_RXP PCIE_PTX_DRX_N17 PCIE_PRX_DTX_P17 <35>
HOST_SD_WP# AR42 A42 M.2 3042 HCA or QCA LTE SSD Cache
1 2 AR48 GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN B42 PCIE_PTX_DRX_P17 PCIE_PTX_DRX_N17 <35>
RH214 100K_0402_5% AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP PCIE_PTX_DRX_P17 <35>
1 2 HDD_DET# GPP_F13/SATA_SDATAOUT0 PCIE_PRX_DTX_N18
AU46 P41
RH324 10K_0402_5% GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN PCIE_PRX_DTX_P18 PCIE_PRX_DTX_N18 <35>
BIOS_REC R40
1 2 PCIE18_RXP/SATA5_RXP PCIE_PTX_DRX_N18 PCIE_PRX_DTX_P18 <35>
C39 C42 M.2 3042 HCA or QCA LTE SSD Cache
RH76 10K_0402_5% PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN PCIE_PTX_DRX_P18 PCIE_PTX_DRX_N18 <35>
D39 D42
D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCIE_PTX_DRX_P18 <35>
1 2 m3042_PCIE#_SATA PCIE14_RXN/SATA1B_RXN
C47 AK48 SATALED#
RH344 10K_0402_5% PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED# SATALED# <35,40,45>
CONTACTLESS_DET# B38 AH41 SATAGP0

1 2 C38 PCIE13_TXN/SATA0B_TXNGPP_E0/SATAXPCIE0/SATAGP0 AJ43 M2280_PCIE_SATA#
RH90 10K_0402_5% PCIE13_TXP/SATA0B_TXPGPP_E1/SATAXPCIE1/SATAGP1 HDD_DET# M2280_PCIE_SATA# <40>
AUD_PWR_EN C45 AK47
1 2 PCIE13_RXN/SATA0B_RXNGPP_E2/SATAXPCIE2/SATAGP2 HDD_DET# <41>
C46 AN47 SATAGP3
RH345 10K_0402_5% PCIE13_RXP/SATA0B_RXP
GPP_F0/SATAXPCIE3/SATAGP_3 AM46 m3042_PCIE#_SATA
1 2 SATALED# PCIE_PTX_DRX_P12 GPP_F1/SATAXPCIE4/SATAGP4 m3042_PCIE#_SATA <37>
E37 AM43 SATAGP5
RH380 10K_0402_5% <40> PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 PCIE12_TXP/SATA1A_TXPGPP_F2/SATAXPCIE5/SATAGP5
1 2 D38 AM47 SATAGP6
SATAGP0 <40> PCIE_PTX_DRX_N12 PCIE_PRX_DTX_P12 PCIE12_TXN/SATA1A_TXNGPP_F3/SATAXPCIE6/SATAGP6 Reserve
B M.2 Socket 3 (Key M) J41 AM48 SATAGP7 B
@ RH316 10K_0402_5% <40> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 PCIE12_RXP/SATA_1A_RXP
GPP_F4/SATAXPCIE7/SATAGP7 Reserve
<40> PCIE_PRX_DTX_N12 H42
PCIE12_RXN/SATA1A_RXN AU48 BIA_PWM_PCH
B44 GPP_F21/EDP_BKLTCTL AV46 PANEL_BKEN_PCH BIA_PWM_PCH <32>
A44 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN AV44 ENVDD_PCH PANEL_BKEN_PCH <32>
R37 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN ENVDD_PCH <32>
1 2 M2280_PCIE_SATA# PCIE20_RXP/SATA7_RXP PCH_THERMTRIP#
R35 AD3 RH75 1 2 620_0402_5%
@RH317 10K_0402_5% D43 PCIE20_RXN/SATA7_RXN THRMTRIP# AF2 PCH_PECI RH73 1 2 13_0402_5% H_PECI H_THERMTRIP# <7,14,15,38>
1 2 SATAGP3 H_PM_SYNC_R H_PECI <7,37>
C44 PCIE19_TXP/SATA6_TXP PECI AF3 RH156 1 2 30_0402_5% H_PM_SYNC
RH323 10K_0402_5% PCIE19_TXN/SATA6_TXN PM_SYNC PLTRST_CPU# H_PM_SYNC <7>
1 2 N42 AG5
SATAGP0 PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# H_PM_DOWN PLTRST_CPU# <7>
M44 AE2
RH377 10K_0402_5% PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOWN <7>
1 2 SATAGP5
CNP-H_BGA874 Rev1.0
RH325 10K_0402_5%
1 2 SATAGP6
@ RH326 10K_0402_5%
1 2 SATAGP7
@ RH322 10K_0402_5%
PCH_PECI
SPSGP0 0 SATAGP0 1=SATA 0=PCIE
1
1 m2280_PCIE_SATA# 0=SATA 1=PCIE @ RH74
SPSGP1 10K_0402_5%
SPSGP2 1 HDD_DET# 0=SATA 1=PCIE
2
SPSGP3 0 SATAGP3 1=SATA 0=PCIE
SPSGP4 1 m3042_PCIE#_SATA 1=SATA 0=PCIE
SPSGP5 0 SPTAGP5 1=SATA 0=PCIE
A A
Title
CannonLake PCH-H (1/9)
5 4 3 2 1
5 4 3 2 1
1 2
Vinafix.com @ RH66
+3.3V_RUN
0_0402_5%
@ CH10
1 2
5
D 0.1U_0402_25V6 D
1
P
<7> XDP_DBRESET# B SYS_RESET#
4
2 1 ME_RESET# 2 Y SYS_RESET# <20,21>
G
@ RH70 8.2K_0402_5% A @ UC3
CIS LINK OK 74AHC1G09GW_TSSOP5
3
CNP-H
UH1B
DMI_CTX_PRX_N0 K34 J3 USB20_N1
<6>
<6>
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
J35 DMI0_RXN
DMI0_RXP
USB2N_1
USB2P_1
J2 USB20_P1
USB20_N2
USB20_N1
USB20_P1
<42>
<42>
-----> Ext USB Port 1 Charge(RIGHT)
C33 N13
<6>
<6>
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
B33 DMI0_TXN
DMI0_TXP
USB2N_2
USB2P_2
N15 USB20_P2
USB20_N3
USB20_N2
USB20_P2
<43>
<43>
-----> Ext USB Port 2(LEFT)
G33 K4
<6>
<6>
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
F34 DMI1_RXN
DMI1_RXP
USB2N_3
USB2P_3
K3 USB20_P3
USB20_N4
USB20_N3
USB20_P3
<43>
<43>
-----> Ext USB Port 3(REAR)
C32 M10
<6>
<6>
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
B32 DMI1_TXN
DMI1_TXP
USB2N_4
USB2P_4
L9 USB20_P4 USB20_N4
USB20_P4
<29>
<29>
-----> Type-C
K32 M1
<6> DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI2_RXN USB2N_5
J32 L2
<6> DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI2_RXP USB2P_5 USB20_N6
C31 K7
C
<6>
<6>
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
B31 DMI2_TXN
DMI2_TXP
USB2N_6
USB2P_6
K6 USB20_P6 T300 @ PAD~D
T301 @ PAD~D
-----> M.2 2230 (BT) C
G30 L4
<6> DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI3_RXN USB2N_7
F30 L3
<6> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI3_RXP USB2P_7 USB20_N8
C29 G4
<6>
<6>
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3
DMI_CRX_PTX_P3 B29 DMI3_TXN
DMI3_TXP
USB2N_8
USB2P_8
G5 USB20_P8
USB20_N9
USB20_N8 <35>
USB20_P8 <35>
-----> M.2 3042 (WWAN)
A25 M6
B25 RSVD
RSVD
USB2N_9
USB2P_9
N8 USB20_P9
USB20_N10
USB20_N9 <32>
USB20_P9 <32>
-----> Touch Screen
P24 H3
R24 RSVD
RSVD
USB2N_10
USB2P_10
H2 USB20_P10
USB20_N11
USB20_N10 <39>
USB20_P10 <39>
-----> USH
C26 R10
B26 RSVD
RSVD
USB2N_11
USB2P_11
P9 USB20_P11 USB20_N11 <32>
USB20_P11 <32>
-----> Camera
F26 G1 +3.3V_ALW_PCH
G26 RSVD USB2N_12 G2
B27 RSVD USB2P_12 N3
C27 RSVD USB2N_13 N2 RPH6
RSVD USB2P_13 USB20_N14 USB_OC3# 1 8
L26 E5 USB_OC1#
RSVD USB2N_14 USB20_P14 USB20_N14 <35> 2 7
M26 F6
D29 RSVD USB2P_14 USB20_P14 <35> ----->used for CNVio wireless M.2 USB_OC0#
USB_OC2#
3 6
E28 RSVD AH36 USB_OC0# 4 5
RSVD GPP_E9/USB2_OC0# USB_OC1# USB_OC0# <42>
K29 AL40
RSVD GPP_E10/USB2_OC1# USB_OC2# USB_OC1# <43> 10K_0804_8P4R_5%
M29 AJ44
RSVD GPP_E11/USB2_OC2# USB_OC3# USB_OC2# <43> @RPH7
AL41
GPP_E12/USB2_OC3# USB_OC4# Reserve USB_OC4# 1 8
G17 AV47
PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# USB_OC5# Reserve USB_OC5# 2 7
F16 AR35
PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# USB_OC6# Reserve USB_OC6# 3 6
A17 AR37
PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# USB_OC7# Reserve USB_OC7# 4 5
B17 AV43
PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7# Reserve
R21
P21 PCIE2_RXN/USB31_8_RXN F4 USB2_COMP RH193 1 2 113_0402_1% 10K_0804_8P4R_5%
B18 PCIE2_RXP/USB31_8_RXP USB2_COMP F3 USB2_VBUSSENSE RH364 1 2 1K_0402_5% +3.3V_DSW
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13 T40 @ PAD~D
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 USB2_ID RH365 1 2 10K_0402_5% 3.3V_CAM_EN# 1 2
J18 PCIE3_RXN/USB31_9_RXN USB2_ID 100K_0402_5%
USB2_ID <29> RH602
B19 PCIE3_RXP/USB31_9_RXP BE41 3.3V_CAM_EN#
PCIE3_TXN/USB31_9_TXN GPD7 3.3V_CAM_EN# <32>
C19
N18 PCIE3_TXP/USB31_9_TXP G45
R18 PCIE4_RXN/USB31_10_RXN PCIE24_TXP G46
PCIE4_RXP/USB31_10_RXP PCIE24_TXN Xtal input
D20 Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40 HIGH(DEFAULT) differential
PCIE_PRX_DTX_N5 F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48
<33> PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE5_RXN PCIE23_TXP LOW single-end
G20 G49
<33> PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE5_RXP PCIE23_TXN
B21 W44
LAN ---> <33>
<33>
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5
PCIE_PTX_DRX_P5
PCIE_PRX_DTX_N6
A22 PCIE5_TXN
PCIE5_TXP
PCIE23_RXP
PCIE23_RXN
W43 CFL CRB rev0.5
Xtal input
B K21 H48 B
<34> PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE6_RXN PCIE22_TXP High : differential
J21 H47
<34> PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE6_RXP PCIE22_TXN Low : single-end
D21 U41
Card Reader ---> <34> PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 C21 PCIE6_TXN PCIE22_RXP U40 CNL- PCH EDS rev0.5
<34> PCIE_PTX_DRX_P6 PCIE_PTX_DRX_P7 B23 PCIE6_TXP PCIE22_RXN F46
<35> PCIE_PTX_DRX_P7 PCIE_PTX_DRX_N7 PCIE7_TXP PCIE21_TXP External pull-up is required. Recommend 100K if pulled
C23 G47 up to 3.3V
<35> PCIE_PTX_DRX_N7 PCIE_PRX_DTX_P7 J24 PCIE7_TXN PCIE21_TXN R44
WLAN ---> <35>
<35>
PCIE_PRX_DTX_P7
PCIE_PRX_DTX_N7
PCIE_PRX_DTX_N7 L24 PCIE7_RXP PCIE21_RXP T43
F24 PCIE7_RXN PCIE21_RXN
G24 PCIE8_RXN
B24 PCIE8_RXP
C24 PCIE8_TXN 2 OF 13 @RPH8
PCIE8_TXP USB_OC3# 1 8
Rev1.0
USB_OC1# 2 7
CNP-H_BGA874 USB_OC0# 3 6
USB_OC2# 4 5
15K_0804_8P4R_5%
A A
Title
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
CNP-H
UH1G
BE33
GPP_A16/CLKOUT_48
CPU_24MHZ_R_D RH169 1 2 0_0402_5% PCH_CPU_NSSC_CLK_D D7 Y3 PCH_XDP_CLK_DN_R RH154 1 2 0_0402_5% PCH_XDP_CLK_DN
<7> CPU_24MHZ_R_D CPU_24MHZ_R_D# PCH_CPU_NSSC_CLK_D# CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# PCH_XDP_CLK_DP_R PCH_XDP_CLK_DN <7>
RH170 1 2 0_0402_5% C6 Y4 RH155 1 2 0_0402_5% PCH_XDP_CLK_DP
<7> CPU_24MHZ_R_D# CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P PCH_XDP_CLK_DP <7>
PCH_CPU_BCLK_R_D RH161 1 2 0_0402_5% PCH_CPU_BCLK_D B8 B6 PCH_CPU_PCIBCLK_D# RH168 1 2 0_0402_5% PCH_CPU_PCIBCLK_R_D#
<7> PCH_CPU_BCLK_R_D PCH_CPU_BCLK_R_D# PCH_CPU_BCLK_D# CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_D PCH_CPU_PCIBCLK_R_D# <7>
RH166 1 2 0_0402_5% C8 A6 RH167 1 2 0_0402_5% PCH_CPU_PCIBCLK_R_D
<7> PCH_CPU_BCLK_R_D# CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_R_D <7>
XTAL24_OUT_R1 U9 AJ6 CLK_PCIE_N0
+1.0V_ALW_PCH XTAL24_IN_R1 XTAL_OUT CLKOUT_PCIE_N0 CLK_PCIE_P0 CLK_PCIE_N0 <35>
U10 AJ7 WWAN
XTAL_IN CLKOUT_PCIE_P0 CLK_PCIE_P0 <35>
@RH171 1 2 2.7K_0402_1% XCLK_RBIAS T3 AH9 CLK_PCIE_N1
XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_P1 CLK_PCIE_N1 <35>
1 2 60.4_0402_1% AH10 WLAN
C PCH_RTCX1 CLKOUT_PCIE_P1 CLK_PCIE_P1 <35> C
RH435 BA49
PCH_RTCX2 BA48 RTCX1 AE14
RH123 2 1 10K_0201_5% pop RH171 for KBL-H RTCX2 CLKOUT_PCIE_N2 AE15
+3.3V_RUN pop RH435 for CFL-H , PDG 0.5 CLKREQ_PCIE#0_R CLKOUT_PCIE_P2 WIGIG
WWAN RF@RH10 2 1 0_0402_5% BF31
<35> CLKREQ_PCIE#0 CLKREQ_PCIE#1_R GPP_B5/SRCCLKREQ0# CLK_PCIE_N3
RH124 2 1 10K_0201_5% BE31 AE6
+3.3V_RUN TBT_RTD3_WAKE# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_P3 CLK_PCIE_N3 <40>
WLAN RF@RH11 2 1 0_0402_5% AR32 AE7 M.2 Socket 3 (Key M)
<35> CLKREQ_PCIE#1 CLKREQ_PCIE#3_R BB30 GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_P3 <40>
+3.3V_RUN RH125 2 1 10K_0201_5% GPP_B8/SRCCLKREQ3#
CLKREQ_PCIE#4_R BA30 AC2 CLK_PCIE_N4
WIGIG CLKREQ_PCIE#5_R GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 CLK_PCIE_P4 CLK_PCIE_N4 <33>
RH126 2 1 10K_0201_5% AN29 AC3 LAN
+3.3V_RUN CLKREQ_PCIE#6_R GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 CLK_PCIE_P4 <33>
M.2 Socket 3 RF@RH13 2 1 0_0402_5% AE47
<40> CLKREQ_PCIE#3 CLKREQ_PCIE#7_R GPP_H0/SRCCLKREQ6# CLK_PCIE_N5
+3.3V_RUN RH127 2 1 10K_0201_5% AC48 AB2
RF@RH14 2 1 0_0402_5% AE41 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 AB3 CLK_PCIE_P5 CLK_PCIE_N5 <34>
LAN <33> CLKREQ_PCIE#4 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5 CLK_PCIE_P5 <34> MMI
RH131 2 1 10K_0201_5% AF48
+3.3V_RUN GPP_H3/SRCCLKREQ9#
MMI RF@RH15 2 1 0_0402_5% AC41 W4
<34> CLKREQ_PCIE#5 2 1 AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 W3
+3.3V_RUN RH132 10K_0402_5%
AE39 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
RH133 2 1 10K_0402_5% AB48 GPP_H6/SRCCLKREQ12# W7
+3.3V_RUN GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7
AC44 W6
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
GPP_H9/SRCCLKREQ15# AC14
V2 CLKOUT_PCIE_N8 AC15
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
CLKOUT_PCIE_P15 U2
T2 CLKOUT_PCIE_N9 U3
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
CLKOUT_PCIE_P14 AC9
AA1 CLKOUT_PCIE_N10 AC11
Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 AE9
AC7 CLKOUT_PCIE_N11 AE11
AC6 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
CLKOUT_PCIE_P12 7 OF 13 R6 REFCLK_CNV
CLKIN_XTAL REFCLK_CNV <35>
CNP-H_BGA874 Rev1.0
1
B B
RH110
10K_0402_5%
2
follow intel CFL-H PDG rev0.5, but CRB rev0.5 - CSLP1
follow intel CRB design - CSLP2, EVT
CH4
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1 XTAL24_IN_R1 1 2 XTAL24_IN_R
RH43 0_0402_5% RH436 0_0402_5%
15P_0402_50V8J
1
1
YH1 RH44 RH153

10M_0402_5% 1M_0402_1%
32.768KHZ_12.5PF_9H03200042 YH2
2
24MHZ_12PF_7M24000055
2
2
CH5
PCH_RTCX2 XTAL24_OUT_R1 1 2 XTAL24_OUT_R 1 2 XTAL24_OUT 1 3
1 2
RH152 0_0402_5% RH437 0_0201_1% 1 3
GND1 GND2
15P_0402_50V8J
2 4
1 1
CH14 CH13
15P_0402_50V8J 15P_0402_50V8J
2 2
A A
Title
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH
+3.3V_ALW_PCH
1 2 SIO_EXT_SMI# Vinafix.com
5
RH310 10K_0402_5% UH7
PCH_PLTRST# 1
P
D B PCH_PLTRST#_AND D
4
2 Y RH187 2 1 0_0402_5% PCH_PLTRST#_AND <34,35,39,40>
A
1
PLTRST_TPM# <39>
TC7SH08FU_SSOP5 @ RH65 PCH_PLTRST# 1 2
3
100K_0402_5% @ RH60 0_0402_5%
2
+3.3V_RUN
TOUCH_SCREEN_PD# don't move to RPC,
1 2 TOUCH_SCREEN_PD#
@ RH348 10K_0402_5%
CNP-H
1 2 TOUCHPAD_INTR#
UH1A
RH402 10K_0402_5% PAD~D @ T178 PME# BE36 AV29 PCH_PLTRST# 2 1
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# RH62 2 1 0_0402_5% PLTRST_LAN# <33>
PCH_PLTRST#_EC <38>
RH244 0_0402_5%
PAD~D @ T60 R15 Y47
PAD~D @ T61 R13 RSVD2 GPP_K16/GSXCLK Y46
RSVD1 GPP_K12/GSXDOUT Y48
GPP_K13/GSXSLOAD W46
PAD~D @ T63 AL37 GPP_K14/GSXDIN AA45
PAD~D @ T62 AN35 VSS GPP_K15/GSXSRESET#
TP
PCH_SPI_D0 AU41 AL47 SIO_EXT_SMI#
<7> PCH_SPI_D0 PCH_SPI_D1 SPI0_MOSI GPP_E3/CPU_GP0 TOUCH_SCREEN_PD#
BA45 AM45
PCH_SPI_CS#0 SPI0_MISO GPP_E7/CPU_GP1 TOUCHPAD_INTR# TOUCH_SCREEN_PD# <32>
AY47 BF32
PCH_SPI_CLK AW47 SPI0_CS0# GPP_B3/CPU_GP2 BC33 TOUCHPAD_INTR# <37,44>
+3.3V_SPI SPI0_CLK GPP_B4/CPU_GP3 TOUCH_SCREEN_DET# <32>
PCH_SPI_CS#1 AW48
SPI0_CS1# AE44
PCH_SPI_D2_XDP 1 PCH_SPI_D2 GPP_H18/SML4ALERT#
1 2 GPP_H12 <7> PCH_SPI_D2_XDP
2 AY48
SPI0_IO2 GPP_H17/SML4DATA
AJ46
RH180 0_0402_5% PCH_SPI_D3 BA46 AE43 +RTC_CELL_PCH
@ RH615 2.2K_0402_5% SPI0_IO3 GPP_H16/SML4CLK PCH Signal Glitch Free Implementation Requirements
C AT40 AC47 GPP_H15 C
eSPI Flash sharing mode (GPP_H12) <39> PCH_SPI_CS#2 SPI0_CS2# GPP_H15/SML3ALERT# AD48 PCH_PLTRST#
GPP_H14/SML3DATA 1 2
1
0 = Master Attached Flash Sharing (MAFS) enabled (Default) BE19 AF47
1 = Slave Attached Flash Sharing (SAFS) enabled. GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK @RH635 100K_0201_5%
BF19 AB47 GPP_H12 RH198 PCH_SPI_CLK
GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# 1 2
BF18 AD47 1M_0402_5% @RH634 100K_0201_5%
GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA
1 2 GPP_H15 BE18
GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
AE48
RH601 100K_0402_5% BC17
2
1 2 PCH_SPI_D0 BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 PCH_INTRUDER_HDR#
100K_0402_5% CFL-H PDG rev0.7 GPP_D21/SPI1_IO2 INTRUDER#
RH600 pop 20K for SPI0_IO2/3
1 2 PCH_SPI_D2 CNP-H_BGA874 Rev1.0
RH30 20K_0402_5% CNL- PCH EDS rev0.5
1 2 PCH_SPI_D3 Reserved External pull-up is required. Recommend 100K if pulled
RH335 20K_0402_5% up to 3.3V
1 2 PCH_SPI_D3
@ RH334 1K_0402_5% RPC1
PCH_SPI_D1_R1 1 8 PCH_SPI_D1_0_R
<39> PCH_SPI_D1_R1 PCH_SPI_D3_R1 PCH_SPI_D3_0_R
2 7
PCH_SPI_CLK_R1 3 6 PCH_SPI_CLK_0_R
<39> PCH_SPI_CLK_R1 PCH_SPI_D0_R1 4 5 PCH_SPI_D0_0_R
9/5 MOW <39> PCH_SPI_D0_R1
Opt i on 1: I mpl e ment a 1 k Oh m pull- do wn r esi st or on t he si gnal and de- popul at e t he 33_0804_8P4R_5%
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI
f l as h devi ce on t he pl a t fo rm has HOLD f unct i onal i t y di sabl ed by defaut.l
@RPC2
PCH_SPI_D1_R1 4 5 PCH_SPI_D1_1_R
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y plat f or ms PCH_SPI_D3_R1 3 6 PCH_SPI_D3_1_R
PCH_SPI_CLK_R1 PCH_SPI_CLK_1_R
with ES and SKL S/H plat f or ms wit h pr e- ES1/ES1 sa mpl es. +3.3V_SPI PCH_SPI_D0_R1
2 7
PCH_SPI_D0_1_R
1 8
256Mb Flash ROM CH9
33_0804_8P4R_5%
1 2
0.1U_0201_10V6K
B
UC5 B
PCH_SPI_CS#0_R1 RH37 1 2 0_0402_5% PCH_SPI_CS#0_R2 1 8
PCH_SPI_D1_0_R 2 CS# VCC 7 PCH_SPI_D3_0_R
PCH_SPI_D2_R1 RH3511 2 33_0402_5% PCH_SPI_D2_0_R 3 DO HOLD#_RESET# 6 PCH_SPI_CLK_0_R
4 WP# CLK 5 PCH_SPI_D0_0_R
9 GND1 DI
GND2
ESPI LPC
W25Q256JVEIQ_WSON8_8X6
CONN@
RH351 33 ohm 15 ohm JSPI1
2 1 PCH_SPI_CS#1_R1 1
0_0402_5% @ RH177 PCH_SPI_CS#1 2 1
RPC1 33 ohm 15 ohm 2 1 PCH_SPI_D0_R1 3 2
4.99_0402_1% RH178 PCH_SPI_D0 4 3
2 1 PCH_SPI_D1_R1 5 4
RH178,RH179,RH181, 0 ohm 25 ohm 4.99_0402_1% RH179 PCH_SPI_D1 6 5
RH182,RH183,RH184 +3.3V_SPI 2 1 PCH_SPI_CLK_R1 7 6
4.99_0402_1% RH181 PCH_SPI_CLK 8 7
@ CH270 2 1 PCH_SPI_CS#0_R1 9 8
reserve SO8 Flash ROM for socket 1 2 0_0402_5% RH182 PCH_SPI_CS#0 10 9
10
2 1 PCH_SPI_D2_R1 11
0.1U_0201_10V6K 4.99_0402_1% RH183 PCH_SPI_D2 12 11
@ UC6 2 1 PCH_SPI_D3_R1 13 12
PCH_SPI_CS#0_R1 @ RH352 1 2 0_0402_5% PCH_SPI_CS#0_R3 1 8 4.99_0402_1% RH184 PCH_SPI_D3 14 13
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R CS# VCC 15 14
PCH_SPI_D1_1_R PCH_SPI_D3_1_R +3.3V_SPI 15
2 7 +3.3V_ALW_PCH
16
SO/SIO1 RESET#/SIO3 17 16
33_0402_5%
33_0402_5%
17
1
PCH_SPI_D2_R1 @ RH353 1 2 33_0402_5% PCH_SPI_D2_1_R 3 6 PCH_SPI_CLK_1_R 18

@EMI@
@EMI@
WP#/SIO2 SCLK 1 2 19 18
RH28
RH29
4 5 PCH_SPI_D0_1_R DH3 RB751S40T1G_SOD523-2 20 19

GND SI/SIO0 21 20
2 1 22 GND1
2
MX25L25645GM2I-10G_SO8 RH185 0_0402_5% GND2

33P_0402_50V8J
33P_0402_50V8J
ACES_50506-02041-P01
@EMI@
@EMI@
A
CIS link OK A
1
1
CH321
CH322
2
Title
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH +3.3V_1.8V_GPPA
ESPI_RESET# 1 2
1 2 MEM_SMBCLK @ RH95 10K_0402_5%
CNP-H ESPI_ALERT#
RH56 1K_0402_5% 1 2
1 2 MEM_SMBDATA UH1F RH340 8.2K_0402_1%
USB3_PTX_DRX_N1 F9 BB39 ESPI_IO0_R RC366 1 2 15_0402_5% SUSACK#_R
RH57 1K_0402_5% <42> USB3_PTX_DRX_N1 USB3_PTX_DRX_P1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 ESPI_IO1_R ESPI_IO0 <37,38> 1 2
F7 AW37 RC367 1 2 15_0402_5%
<42> USB3_PTX_DRX_P1 USB3_PRX_DTX_N1 USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 ESPI_IO2_R ESPI_IO1 <37,38> @ RH327 1K_0402_5%
1 2 SML0_SMBCLK Ext USB Port 1 Charge(RIGHT) D11 AV37 RC368 1 2 15_0402_5%
<42> USB3_PRX_DTX_N1 USB3_PRX_DTX_P1 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 ESPI_IO3_R ESPI_IO2 <37,38>
RH67 499_0402_1% C11 BA38 RC369 1 2 15_0402_5%
<42> USB3_PRX_DTX_P1 USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <37,38>
1 2 SML0_SMBDATA
USB3_PTX_DRX_N2 C3 SYS_RESET#
RH77 499_0402_1% <35> USB3_PTX_DRX_N2 USB3_PTX_DRX_P2 USB31_2_TXN
@ESD@ CC302
SML1_SMBCLK D4 BE38
Vinafix.com
1 2 <35> USB3_PTX_DRX_P2 USB3_PRX_DTX_N2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# ESPI_ALERT# ESPI_CS# <37,38>
0.1U_0402_25V6
M.2 3042 (LTE) B9 AW35
RH80 1K_0402_5% <35> USB3_PRX_DTX_N2 USB3_PRX_DTX_P2 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# ESPI_ALERT# <37>
1 2 SML1_SMBDATA C9 BA36
<35> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0#
1
BE39 SIO_RCIN#
RH81 1K_0402_5% GPP_A0/RCIN#/ESPI_ALERT1# ESPI_RESET#
C17 BF38
D C16 USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <37,38> D
2
G14 USB31_6_TXP BB36 ESPI_CLK EMI@ RH97 1 2 15_0402_5%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK PCI_CLK_LPC1 ESPI_CLK_5105 <37,38>
F14 BB34 @ RH99 1 2 22_0402_5%
USB3_PTX_MRX_N5 C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1
+3.3V_ALW_PCH <28> USB3_PTX_MRX_N5 USB3_PTX_MRX_P5 USB31_5_TXN
B15 T48 CHECK,LPC_CLK FOR DEBUG CARD?
<28> USB3_PTX_MRX_P5 USB3_PRX_MTX_N5 J13 USB31_5_TXP GPP_K19/SMI# T47
Type C <28> USB3_PRX_MTX_N5 USB3_PRX_MTX_P5 USB31_5_RXN GPP_K18/NMI#
K13 ESD Request:place near PCH side
<28> USB3_PRX_MTX_P5 USB31_5_RXP
1 2 PCH_SMB_ALERT#
USB3_PTX_DRX_P3 G12 AH40
RH61 4.7K_0201_5% <43> USB3_PTX_DRX_P3 USB3_PTX_DRX_N3 USB31_3_TXP GPP_E6/SATA_DEVSLP2 HDD_DEVSLP <41> RF Request
TLS CONFIDENTIALITY F11 AH35
<43> USB3_PTX_DRX_N3 USB3_PRX_DTX_P3 C10 USB31_3_TXN GPP_E5/SATA_DEVSLP1 AL48 M2280_DEVSLP <40>
HIGH ENABLE Ext USB Port 2(LEFT) <43> USB3_PRX_DTX_P3 USB3_PRX_DTX_N3 USB31_3_RXP GPP_E4/SATA_DEVSLP0 PAD~D @ T302 ESPI_CLK_5105 1 2
LOW(DEFAULT) DISABLE B10 AP47
<43> USB3_PRX_DTX_N3 USB31_3_RXN GPP_F9/SATA_DEVSLP7 @RF@ CC316 33P_0402_50V8J
AN37
USB3_PTX_DRX_P4 C14 GPP_F8/SATA_DEVSLP6 AN46
<43> USB3_PTX_DRX_P4 USB3_PTX_DRX_N4 B14 USB31_4_TXP GPP_F7/SATA_DEVSLP5 AR47
+3.3V_ALW_PCH <43> USB3_PTX_DRX_N4 USB3_PRX_DTX_P4 USB31_4_TXN GPP_F6/SATA_DEVSLP4 m3042_DEVSLP <35>
Ext USB Port 3(REAR) J15 AP48
<43> USB3_PRX_DTX_P4 USB3_PRX_DTX_N4 USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3
K16 SML0_SMBCLK 1 2
<43> USB3_PRX_DTX_N4 USB31_4_RXN
1 2 GPP_C5 @RF@ CC318 33P_0402_50V8J
CNP-H_BGA874 Rev1.0
ESPI@ RH78 4.7K_0201_5%
EC interface SML1_SMBCLK 1 2
HIGH ESPI @RF@ CC319 33P_0402_50V8J
LOW(DEFAULT) LPC
MEM_SMBCLK 1 2
@RF@ CC320 33P_0402_50V8J
+3.3V_ALW_PCH
Place close PCH side
@RF@1 2 1 2 CNP-H
1 2 SPKR CH268 47P_0402_50V8J @RH637 100K_0201_5% UH1D

1 2 HDA_BIT_CLK BD11 BF36
@ RH86 4.7K_0201_5% <36> HDA_BIT_CLK_R HDA_SDIN0 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
TOP SWAP STRAP EMI@ RH46 33_0402_5% BE11 AV32 CLKRUN# +3.3V_LAN
<36> HDA_SDIN0 HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
HIGH ENABLE 1 2 BF12
<36> HDA_SDOUT_R ME_FWP_PCH RH45 1 2 33_0402_5% BG13 HDA_SDO/I2S0_TXD BF41 PM_LANPHY_ENABLE
LOW(DEFAULT) DISABLE PM_LANPHY_ENABLE <33> LAN_WAKE# 2 1
RH328 1 2 1K_0402_5% HDA_SYNC HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC
<36> HDA_SYNC_R @RL70 10K_0402_5%
RH48 1 2 33_0402_5% HDA_RST# BE10 BD42 SIO_SLP_WLAN#
<36> HDA_RST#_R HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# SIO_SLP_WLAN# <37,46>
RH50 33_0402_5% BF10 +3.3V_ALW_PCH
+3.3V_ALW_PCH BE12 HDA_SDI1/I2S1_RXD BB46 DDR4_DRAMRST#_PCH
C 1 2 I2S1_TXD/SNDW2_DATA DRAM_RESET# DDR4_DRAMRST#_PCH <14>
C
@RH636 100K_0201_5% BD12 BE32 VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
1 2 KB_DET#
GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29
RC74 10K_0402_5% AUD_AZACPU_SDO AUD_AZACPU_SDO_R GPP_B0/GSPI0_CS1# VRALERT# 1 2
1 2 CNV_RF_RST# 1 2 AM2 R47 @ RH203 10K_0402_5%
<9> AUD_AZACPU_SDO AUD_AZACPU_SDI_R AN3 HDACPU_SDO GPP_K17/ADR_COMPLETE AP29
RH617 75K_0402_5% RH39 30_0402_5% SIO_SLP_LAN# 1 2
CLKREQ_CNV <9> AUD_AZACPU_SDI_R AUD_AZACPU_SCLK 1 2 AUD_AZACPU_SCLK_R AM3 HDACPU_SDI GPP_B11/I2S_MCLK AU3 SYS_PWROK
1 2 <9> AUD_AZACPU_SCLK HDACPU_SCLK SYS_PWROK SYS_PWROK <7,37> @ RH204 10K_0402_5%
RH618 75K_0402_5% RH38 30_0402_5%
AV18 BB47 PCH_PCIE_WAKE#
GPP_D8/I2S2_SCLK WAKE# SIO_SLP_A# PCH_PCIE_WAKE# <37,38>
AW18 BE40
BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# BF40 SIO_SLP_LAN# SIO_SLP_A# <21,37> +3.3V_DSW
+3.3V_ALW_PCH <35> CLKREQ_CNV GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# SIO_SLP_S0# SIO_SLP_LAN# <37,46>
BE16 BC28
<35> CNV_RF_RST# TBT_PWR_EN GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# SIO_SLP_S3# SIO_SLP_S0# <11,21,39,54> PCH_PCIE_WAKE# 1 2
T269@ PAD~D
BF15 BF42
IR_CAM_DET# BD16 GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# BE42 SIO_SLP_S4# SIO_SLP_S3# <21,37,38> RH92 1K_0402_5%
2
<32> IR_CAM_DET# GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# SIO_SLP_S5# SIO_SLP_S4# <11,21,37,51,52> LAN_WAKE# 1 2

AV16 BC42
RH329 KB_DET# AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# SIO_SLP_S5# <21,37> RH93 10K_0402_5%
150K_0402_5% <44> KB_DET# GPP_D17/DMIC_CLK1/SNDW3_CLK PCH_BATLOW# 1 2
BE45 SUSCLK
GPD8/SUSCLK PCH_BATLOW# SUSCLK <35,40> RH94 8.2K_0402_5%
+RTC_CELL_PCH BF44
GPD0/BATLOW# SUSACK#_R @RH443 1 AC_PRESENT 1 2
BE35 2 0_0402_5%
1
PCH_RTCRST# GPP_A15/SUSACK# ME_SUS_PWR_ACK_R RH444 1 SUSACK# <37>

GPP_B23 1 2 BE47 BC37 2 0_0402_5% RH243 10K_0402_5%
RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK ME_SUS_PWR_ACK <37>
RH2001 220K_0402_5% SRTCRST# BD46
SRTCRST#
WEAK INTERNAL PD ~20K RH201 20K_0402_5%
PCH_PWROK LAN_WAKE#
CFL-H CRB rev0.5
AY42 BG44
<55> PCH_PWROK PCH_RSMRST#_AND PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT LAN_WAKE# <33,37>
BA47 BG42
Intel DCI-OOB <7,44> PCH_RSMRST#_AND RSMRST# GPD1/ACPRESENT BD39 AC_PRESENT <37> +3.3V_RUN
SLP_SUS# SIO_PWRBTN# SIO_SLP_SUS# <37> SIO_RCIN#
HIGH ENABLED BE46
SIO_PWRBTN# <7,37> PAD~D @ T286
PCH_DPWROK AW41 GPD3/PWRBTN# AU2 SYS_RESET#
LOW(DEFAULT) DIABLED <37> PCH_DPWROK PCH_SMB_ALERT# DSW_PWROK SYS_RESET# SYS_RESET# <17,21>
BE25 AW29 SPKR CLKRUN#
MEM_SMBCLK GPP_C2/SMBALERT# GPP_B14/SPKR H_PWRGD SPKR <36> PAD~D @ T287
BE26 AE3 H_PWRGD <7>
MEM_SMBDATA GPP_C0/SMBCLK CPUPWRGD SYS_PWROK 1 2
If USB 3.0 Port 1 is used for 4-wire DCI.OOB (BSSB), and alternate functionality is also used on the pin, BF26
pull up to V3.3S with >100K resistor to avoid noise. GPP_C5 GPP_C1/SMBDATA ITP_PMODE_CPU PAD~D @ T192 RH199 100K_0402_5%
BF24 AL3
SML0_SMBCLK GPP_C5/SML0ALERT# ITP_PMODE PCH_JTAGX ITP_PMODE_CPU <7>
BF25 AH4 DDR_XDP_WAN_SMBDAT 1 2
If USB 3.0 Port 1 is used for DCI.OOB (BSSB) 4-wire BSSB, and NO alternate functionalityis used, <33> SML0_SMBCLK SML0_SMBDATA GPP_C3/SML0CLK PCH_JTAGX PCH_JTAG_TMS PCH_JTAGX <7>
BE24 AJ4 PCH_JTAG_TMS <7> RH374 2.2K_0402_5%
leave float. <33> SML0_SMBDATA GPP_B23 BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 PCH_JTAG_TDO DDR_XDP_WAN_SMBCLK 1
GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO PCH_JTAG_TDO <7> 2
SML1_SMBCLK BF27 AH2 PCH_JTAG_TDI
If DCI.OOB (BSSB) 2+2 functionality is used, pull up to V3.3S with a 4.7K resistor. <37> SML1_SMBCLK GPP_C6/SML1CLK PCH_JTAG_TDI PCH_JTAG_TDI <7> RH333 2.2K_0402_5%
SML1_SMBDATA BE27 4 OF 13 AJ3 PCH_JTAG_TCK IR_CAM_DET#
B <37> SML1_SMBDATA GPP_C7/SML1DATA PCH_JTAG_TCK PCH_JTAG_TCK <7> 1 2 B
Rev1.0
RH373 100K_0402_5%
CNP-H_BGA874 @ T182 PCH_JTAG_TCK 1 2
PAD~D
PAD~D @ T183 @ RH313 51_0402_5%
HDA_SDIN0 HDA_SYNC HDA_BIT_CLK HDA_SDOUT PAD~D @ T186 PCH_PWROK 1 2
PAD~D @ T187 @ RH424 10K_0402_5%
2P_0402_50V8C
@EMI@ CA73
2P_0402_50V8C
@EMI@ CA74
2P_0402_50V8C
@EMI@ CA75
2P_0402_50V8C
@EMI@ CA76
PAD~D @ T188 SUSCLK 1 2

1
@ RH83 1K_0402_5%
1 2 SRTCRST#
CH41 1U_0402_6.3VAK
2
1 2 PCH_RTCRST#
SIO_SLP_SUS# RH441 1 2 0_0402_5%
CH40 1U_0402_6.3VAK <22> VCCDSW_EN_GPIO PCH_PRIM_EN <11,46,52,53>
NDS3@ DH1 DS3@
<21,37> PCH_RTCRST# RH445 +1.0V_VCCSTG
1 2 2 1 VCCDSW_EN_Q RH442 1 2 0_0402_5%
place close to UH1 place close to UH1 place close to UH1 place close to UH1 <37> VCCDSW_EN
RB751S40T1G_SOD523-2 NDS3@ PCH_JTAG_TMS
1 2 0_0402_5% 1 2
1 2 Service Mode Switch: RH312 51_0402_5%
PCH_JTAG_TDI 1 2
1 2
Add a switch to ME_FWP signal to unlock the ME region and <44,50> ALW_PWRGD_3V_5V
RB751S40T1G_SOD523-2 RH314 51_0402_5%
@ CMOS1 SHORT PADS~D
allow the ent ir e r egi on of t he SPI f l ash to be updat ed us i ng FPT NDS3@ DH2
PCH_JTAG_TDO 1 2
RH315 51_0402_5%
+3.3V_ALW_PCH
ME_FWP 1 2 ME_FWP_PCH For DS3:
Pop RE349, RE536, RH439, RH441, RH443 PCH Signal Glitch Free Implementation Requirements
@ RH100 0_0402_5% SIO_SLP_S3# SIO_SLP_S3#
Depop DH1, RH215, RH440, RH442 1 2 1 2
RH215 PT,ST pop RH101 and SW1; MP pop RH100
1
@CH341 0.033U_0402_16V7 @RH626 100K_0201_5%

For NDS3 : SIO_SLP_S4# 1 2 SIO_SLP_S4# 1 2
POP NO Support Deep sleep RH101 +3.3V_RUN Pop DH1, RH215, RH440, RH442
@CH342 0.033U_0402_16V7 @RH627 100K_0201_5%
1K_0402_5% Depop RE349, RE536, RH439, RH441, RH443 SIO_SLP_A# SIO_SLP_A#
DE-POP Support Deep sleep 1 2 1 2
@CH343 0.033U_0402_16V7 @RH628 100K_0201_5%
SIO_SLP_WLAN# 1 2 SIO_SLP_WLAN# 1 2
2
PCH_DPWROK 1 2 PCH_RSMRST#_AND SW1

RH215 0_0402_5% 1 @CH344 0.033U_0402_16V7 @RH629 100K_0201_5%
<37> ME_FWP A SIO_SLP_SUS# 1 2 SIO_SLP_SUS# 1 2
2
NDS3@ 2
B
1
ME_FWP_PCH 3 @CH345 0.033U_0402_16V7 @RH630 100K_0201_5%

0.01U_0402_25V7K~D
100K_0402_5%
1 C SIO_SLP_LAN# 1 2 SIO_SLP_LAN# 1 2
1
PCH_JTAGX
10K_0402_5%
@
A 4 MEM_SMBCLK 6 1 1 2 A
G1 DDR_XDP_WAN_SMBCLK <7,14,15,41> @CH346 0.033U_0402_16V7 @RH631 100K_0201_5%
CH266
RH308
RC75
5 @ESD@ CC305 0.1U_0402_25V6 SIO_SLP_S5# SIO_SLP_S5# 1 2

G2 PCH_JTAG_TDI 1 2 1 2
QH4A @CH347 0.033U_0402_16V7 @RH632 100K_0201_5%
2 SS3-CMFTQR9_3P @ESD@ CC304 0.1U_0402_25V6 ESPI_RESET#
DMN65D8LDW-7_SOT363-6 ESPI_RESET# 1 2
2
PCH_JTAG_TDO 1 1 2
5
ME_FWP PCH has internal 20K PD. 2 @RH633 75K_0201_5%

2
@ESD@ CC303 0.1U_0402_25V6 @CH348 0.033U_0402_16V7

(suspend power rail) MEM_SMBDATA 3 4
DDR_XDP_WAN_SMBDAT <7,14,15,41> ESD request,Place near PCH side.
FLASH DESCRIPTOR SECURITY OVERRIDE DELL CONFIDENTIAL/PROPRIETARY
QH4B
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
DMN65D8LDW-7_SOT363-6 Security Classification Compal Secret Data
Title
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
1 2 FFS_INT2
RH378 10K_0402_5%
1 2 PCH_TBT_PERST#
@ RH207 100K_0402_5% Reserved CNP-H
1 2 PCH_3.3V_TS_EN UH1K
@ RH375 100K_0402_5%
1 2 LPSS_UART2_TXD BBS_BIT6 BA26 BA20 MEM_INTERLEAVED
@ RH360 49.9K_0402_1% PCH_3.3V_TS_EN BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 DGPU_HOLD_RST#
LPSS_UART2_RXD <32> PCH_3.3V_TS_EN TPM_PIRQ#_B20 GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK AR_DET# T37 @ PAD~D
1 2 AU26 BB16
GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO DGPU_PWR_EN
Vinafix.com
@ RH361 49.9K_0402_1% 1 2 <41> HDD_FALL_INT AW26 AN18
1 2 HDD_FALL_INT GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI T38 @ PAD~D
@ RC561 0_0402_5%
RH355 10K_0402_1% NRB_BIT BE30 BF14
TPM_PIRQ#_B20 TPM_PIRQ#_R GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN ISH_UART0_CTS# <35> +3.3V_RUN
1 2 1 2 BD29 AR18
<39> TPM_PIRQ# ONE_DIMM# GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN ISH_UART0_RTS# <35>
RH339 10K_0402_5% RC560 0_0402_5% BF29 BF17
D
1 2 NRB_BIT MEDIACARD_IRQ# BB26 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL BE17 ISH_UART0_TXD <35> WLAN D
<34> MEDIACARD_IRQ# GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA ISH_UART0_RXD <35>
@ RH331 4.7K_0402_5%
PCH STRAPS IF SAMPLED HIGH[ NO REBOOT ] BB24 LCD_CBL_DET# RC370 1 2 10K_0402_5%
<38> SBIOS_TX PCH_TBT_PERST# BE23 GPP_C9/UART0A_TXD
TYPEC_CON_SEL2 AP24 GPP_C8/UART0A_RXD
TYPEC_CON_SEL1 BA24 GPP_C11/UART0A_CTS# PCH_DP2_CTRL_DATA RH221 1 2 2.2K_0402_5%
+3.3V_ALW_PCH GPP_C10/UART0A_RTS# AG45 PCH_DP1_CTRL_CLK RH222 1 2 2.2K_0402_5%
RH625 2 10_0402_5% HDD_EN_PCH BD21 GPP_H20/ISH_I2C0_SCL AH46 PCH_DP1_CTRL_DATA RH223 1 2 2.2K_0402_5%
<37,41> HDD_EN LCD_CBL_DET# AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA PCH_DP3_CTRL_CLK RH224 1 2 2.2K_0402_5%
<32> LCD_CBL_DET# RTD3_CIO_PWR_EN GPP_C14/UART1_RTS#/ISH_UART1_RTS# PCH_DP3_CTRL_DATA
2 1 PCH_TBT_PERST# T259@ PAD~D AP21 AH47 RH225 1 2 2.2K_0402_5%
SIO_EXT_WAKE# AU24 GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL AH48
@ RC557 100K_0402_5% <37> SIO_EXT_WAKE# GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
1 2 SIO_EXT_WAKE#
PAD~D @ T304 GPP_C23 AV21
RH309 10K_0402_5% CNV_EN# GPP_C23/UART2_CTS#
LPSS_UART2_TXD @ RH623 2 1 0_0402_5% AW21
1 2 RH624 2 1 0_0402_5% LPSS_UART2_TXD BE20 GPP_C22/UART2_RTS# AV34 LID_CL#_PCH
@ RH330 49.9K_0402_1% <37> CNV_DET#_R LPSS_UART2_RXD BD20 GPP_C21/UART2_TXD GPP_A23/ISH_GP5 AW32 TPM_TYPE PAD~D @ T268
1 2 LPSS_UART2_RXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33
RH376 49.9K_0402_1% I2C1_SCK_TP BE21 GPP_A21/ISH_GP3 BE34
<44> I2C1_SCK_TP I2C1_SDA_TP GPP_C19/I2C1_SCL GPP_A20/ISH_GP2
BF21 BD34
EDP_HPD <44> I2C1_SDA_TP GPP_C18/I2C1_SDA GPP_A19/ISH_GP1
1 2 BC22 BF35 CLKDET#
PAD~D @ T59 BF23 GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 BD38 PAD~D @ T258
RH1 100K_0402_5%
CNV_EN# PAD~D @ T58 GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
1 2
TBT_FORCE_PWR BE15
RH622 75K_0402_5% T260@ PAD~D GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
LPSS_UART2_TXD FFS_INT2 BE14 11 OF 13
1 2 <41> FFS_INT2 GPP_D23/ISH_I2C2_SCL/I2C3_SCL
RH621 75K_0402_5%
CNP-H_BGA874 Rev1.0
RTD3@ 2 1 PCH_TBT_PERST#
RC558 100K_0402_5%
TPM_TYPE 1 2
Reserved @ RH379 100_0402_1%
C C
+3.3V_ALW_PCH
1
@ RH311
8.2K_0201_5%
2
+3.3V_ALW_PCH +3.3V_ALW_PCH
BBS_BIT6
2
CNP-H
@ RH555 @ RH553
BOOT BIOS Dest i nat i on(Bi t 6
) UH1E
10K_0402_5% 10K_0402_5%
AL13 PCH_DP1_CTRL_CLK
GPP_I5/DDPB_CTRLCLK PCH_DP1_CTRL_DATA PCH_DP1_CTRL_CLK <26>
HIGH LPC GPP_I6/DDPB_CTRLDATA
AR8
PCH_DP1_CTRL_DATA <26>
PCH_DP1_HPD
1
LOW(DEFAULT) SPI AT6 AN13
<26> PCH_DP1_HPD PCH_DP2_HPD GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK PCH_DP2_CTRL_DATA
AN10 AL10
<28,29> PCH_DP2_HPD PCH_DP3_HPD GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA PCH_DP3_CTRL_CLK
AP9 AL9 TYPEC_CON_SEL1 TYPEC_CON_SEL2
<25> PCH_DP3_HPD AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3 PCH_DP3_CTRL_DATA PCH_DP3_CTRL_CLK <25>
GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40 PCH_DP3_CTRL_DATA <25>
1
GPP_F23/DDPF_CTRLDATA AT49
GPP_F22/DDPF_CTRLCLK
@ RH556 @ RH554
AP41
EDP_HPD GPP_F14/PS_ON# 10K_0402_5% 10K_0402_5%
AN6
<32> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
2
M45
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 T45
GPP_K21 T46
5 OF 13 GPP_K20 AJ47
GPP_H23/TIME_SYNC0
CNP-H_BGA874 Rev1.0
Vendor JAE FOXCON TBD TBD
B B
TYPEC_CON_SEL1 LOW LOW HIGH HIGH
TYPEC_CON_SEL2 LOW HIGH LOW HIGH
+3.3V_ALW_PCH +3.3V_ALW_PCH Check ME about wire to board PN

JAPS1
+3.3V_ALW_PCH
1
+3.3V_RUN 2 1
<20,37,38> SIO_SLP_S3# 2
3
+3.3V_ALW 3
10K_0201_5%
4
<20,37> SIO_SLP_S5# 4
2
2
@ RH267
5
@ RH371 <11,20,37,51,52> SIO_SLP_S4# 5
RH400 6
<20,37> SIO_SLP_A# 6
10K_0201_5% 10K_0201_5% 7
+3.3V_ALW 7
8
9 8
1
1
<20,37> PCH_RTCRST# 10 9
ONE_DIMM# 11 10
MEM_INTERLEAVED AR_DET# <38,45> POWER_SW#_MB 11
12
12
1
10K_0201_5%
13
<17,20> SYS_RESET# 13
14
14
RH268
15
<11,20,39,54> SIO_SLP_S0# 15
16
16
1
17
2
18 17
RH372 @ RH401
19 18
10K_0201_5% 10K_0201_5% GND
20
GND
2
DIMM TYPE AR_DET# CONN@

DIMM Detect ACES_50506-01841-P01
Intel Management Engine Test Suite
A HIGH 1 DIMM HIGH Interleave HIGH NON AR A
LOW 2 DIMM
LOW Non-Interleave LOW AR
Title
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM +1.0V_ALW_PCH +3.3V_ALW_PCH +3.3V_ALW_PCHRES +1.8V_PRIM +1.8V_ALW_PCHRES +RTC_CELL_PCH +3.3V_PRTC
1 2 0.000416A
1 2 1 2 2 1
RH254 0_1206_5% RH279 0_1206_5% 0_0603_5% RH247 RH297 0_0402_5%
CNP-H
+1.0V_ALW_PCH
+3.3V_ALW_PCHRES Vinafix.com +1.8V_PRIM +1.8V_PRIM_PCH
+1.0V_PRIM
5.95A
AA22
AA23
UH1H
VCCPRIM_1P051
VCCPRIM_1P052
VCCPRIM_3P32
AW9 +3.3V_PHVC
AB20 BF47
VCCPRIM_1P053 DCPRTC1
0.1U_0201_10V6K
D eSPI Power AB22 BG47 +VCCRTCEXT D
+1.0V_DSW +3.3V_1.8V_GPPA AB23 VCCPRIM_1P054 DCPRTC2
1 2 VCCPRIM_1P055 1
CH68
+1.8V_ALW_PCHRES RH242 0_0603_5% AB27 V23 +3.3V_PUSB2
1 2 0.0454A 1 2 0.101A 2 1 AB28 VCCPRIM_1P056 VCCPRIM_3P35
@ RH255 0_0402_5% RH291 0_0402_5% RH294 0_0402_5% AB30 VCCPRIM_1P057 AN44 +3.3V_1.8V_SPI
LPC@ ESPI@ AD20 VCCPRIM_1P058 VCCSPI 2
+1.0V_PRIM_FUSE +1.8V_PHVLDO AD23 VCCPRIM_1P059 BC49
+3.3V_PGPPBC VCCPRIM_1P0510 VCCRTC1 +3.3V_PRTC
AD27 BD49
1 2 0.0012A 1 2 0.343A AD28 VCCPRIM_1P0511 VCCRTC2
0.882A 1 2 VCCPRIM_1P0512 +3.3V_PGPPG
RH256 0_0402_5% RH304 0_0402_5% AD30 AN21
@ RH239 0_0603_5% VCCPRIM_1P0513 VCCPGPPG_3P3
AF23 AY8
+1.0V_PRIM_CNV_HVLO AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7 +3.3V_PHVLDO
+3.3V_1.8V_GPPD VCCPRIM_1P0517 VCCPRIM_3P34
+1.8V_ALW_PCHRES AF30
1 2 0.2A VCCPRIM_1P0518 AC35
1 2 0.14A 2 1 VCCPGPPHK1
RH257 0_0402_5% RH293 0_0402_5% @ RH296 0_0402_5% +1.0V_MPHY U26 AC36 +3.3V_PGPPHK
U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35
+1.0V_SRC V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36 +3.3V_PGPPEF
+3.3V_PGPPEF +1.24V_DPHY +1.24V_LDOSRAM VCCPRIM_1P0525 VCCPGPPEF2
V27
1 2 0.169A V28 VCCPRIM_1P0526 AN24 +3.3V_1.8V_GPPD
1 2 0.174A VCCPRIM_1P0527 VCCPGPPD
RH258 0_0402_5% RH303 0_0402_5% 1 2 V30 AN26
V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 +3.3V_PGPPBC
RH237 0_0402_5% VCCPRIM_1P0529 VCCPGPPBC2
+1.0V_BCLKPLL2 +3.3V_PGPPG
+1.0V_PRIM_FUSE AD31 AN32 +3.3V_1.8V_GPPA
1 2 0.021A 1 2 0.145A VCCPRIM_1P0514 VCCPGPPA
RH259 0_0402_5% RH305 0_0402_5% +1.0V_PRIM_CNV_HVLO AE17 AT44 +3.3V_FUSE
VCCPRIM_1P0515 VCCPRIM_3P31 BE48
+1.0V_DUSB +3.3V_PGPPHK W22 VCCDSW_3P31 BE49 +3.3V_DSW
+1.0V_DUSB W23 VCCDUSB_1P051 VCCDSW_3P32
1 2 0.262A VCCDUSB_1P052
1 2 0.42A BB14 +3.3V_1.8V_AZIO_R 2 1
RH306 0_0402_5% VCCHDA +3.3V_1.8V_AZIO
RH286 0_0402_5% +1.0V_DSW BG45 AG19 BLM15GA750SN1D_2P
0.1U_0201_10V6K
BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20
1 LC1
0.1U_0201_10V6K
+1.0V_CLPLLEBB W31 VCCDSW_1P052 VCCPRIM_1P84 AN15
+2.8V_FHV0
CC310
VCCPRIM_MPHY_1P05 VCCPRIM_1P85 1
+3.3V_1.8V_SPI AR15 +1.8V_PRIM_PCH
CC329
1 2 0.0859A +1.8V_ALW_PCHRES VCCPRIM_1P86
D1 BB11 0.766A
RH287 0_0402_5% 1 2 0.05A 2 1 +1.0V_AZPLL E1 VCCPRIM_1P0521 VCCPRIM_1P87 2
RH246 0_0402_5% @ RH250 0_0402_5% C49 VCCPRIM_1P0522 AF19 +1.8V_PHVLDO 2
C VCCAMPHYPLL_1P051 VCCPRIM_1P81 @ C
+2.8V_FHV1 D49 AF20
+1.0V_OCPLL1 1 2 +1.0V_AMPHYPLL E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82
1 2 0.193A BLM15GA750SN1D_2P VCCAMPHYPLL_1P053 AG31 +2.8V_FHV1
+3.3V_1.8V_AZIO +1.8V_ALW_PCHRES VCCPRIM_1P0520
RH288 0_0402_5% LC3 P2 AF31 +2.8V_FHV0
+1.0V_XTAL P3 VCCA_XTAL_1P051 VCCPRIM_1P0519 AK22
1 2 0.00767A 2 1 VCCA_XTAL_1P052 VCCPRIM_1P241
+1.0V_MPHY W19 AK23
0.1U_0201_10V6K
0.1U_0201_10V6K
RH292 0_0402_5% @ RH295 0_0402_5% +1.24V_LDOSRAM
PJP3 1 1 +1.0V_SRC VCCA_SRC_1P051 VCCPRIM_1P242 PAD~D @ T74
W20
VCCA_SRC_1P052
CC332
CC331
2 1 6.66A AJ22
2 1 +1.0V_OCPLL1_R VCCDPHY_1P241
C1 AJ23 +1.24V_DPHY
JUMP_43X79 +3.3V_FUSE C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5 +1.24V_DPHY_MAR
2@ 2 VCCAPLL_1P055 VCCDPHY_1P243 PAD~D @ T75
+1.0V_CLPLLEBB +1.0V_OC V19
1 2 0.106A VCCA_BCLK_1P05 K47
1 2 0.109A RH300 0_0402_5% VCCMPHY_SENSE VCCMPHY_SENSE <53>
B1 K46
RH290 0_0402_5% +1.0V_BCLKPLL2_R VCCAPLL_1P051 VSSMPHY_SENSE VSSMPHY_SENSE <53>
+3.3V_PHVC B2
1 2 B3 VCCAPLL_1P052 8 OF 13
+1.0V_OC +1.0V_BCLKPLL2 VCCAPLL_1P053
1 2 0.182A BLM15GA750SN1D_2P PAD~D @ T76
RH299 0_0402_5% CNP-H_BGA874 Rev1.0
1 2 0.0085A LC2 PAD~D @ T77
RH260 0_0402_5% +3.3V_PHVLDO
0.1U_0201_10V6K
0.1U_0201_10V6K
+1.0V_OCPLL1 1 2 0.97A 1 1
RH298 0_0402_5%
CC330
CC311
1 2 0.0198A
RH240 0_0402_5% +3.3V_PUSB2
2@ 2
1 2 0.095A
RH302 0_0402_5%
CNP-H
B B
UH1J
+3.3V_DSW Y14
RSVD7 PAD~D @ T73
+3.3V_ALW_PCH
Y15 @ T72
RSVD8 PAD~D
0.113A U37 @
2 1 RSVD6 PAD~D T71
U35 @
RH440 0_0402_5% RSVD5 PAD~D T70
NDS3@ +3.3V_ALW N32
RSVD3 PAD~D @ T69
R32
RSVD4 PAD~D @ T68
1 2
AH15
@ RH434 0_0402_5% RSVD2 PAD~D @ T67
AH14
RSVD1 PAD~D @ T66
QH7
LP2301ALT1G_SOT23-3
AL2 PCH_XDP_PREQ#
PREQ# PCH_XDP_PRDY# PCH_XDP_PREQ# <7>
1 2 +3.3V_ALW_DSW_R 1 3 AM5
D
PRDY# CPU_XDP_TRST# PCH_XDP_PRDY# <7>

RH439 0_0402_5% AM4
CPU_TRST# PCH_2_CPU_TRIGGER_R CPU_XDP_TRST# <7>
DS3@ AK3
499K_0402_1%
TRIGGER_OUT CPU_2_PCH_TRIGGER
1
AK2
CPU_2_PCH_TRIGGER <10>
G
TRIGGER_IN
2
RH432
10 OF 13
CNP-H_BGA874 Rev1.0
2
100K_0402_5%
2
RF Request
0.1U_0402_25V6K
49.9K_0402_1%
RH431
1
RH433
@ PCH_2_CPU_TRIGGER_R 1 2 PCH_2_CPU_TRIGGER
CH340
+3.3V_1.8V_AZIO_R +1.0V_CLPLLEBB PCH_2_CPU_TRIGGER <10>

RH42 30_0402_5%
2
1
2
L2N7002WT1G_SC-70-3
1 1
2.2P_0402_50V8C
2.2P_0402_50V8C
A A
RF@ CC327
RF@ CC328
D
2 2
QH6
2 VCCDSW_EN_GPIO <20>
G
S
3
Title
5 4 3 2 1
5 4 3 2 1
+1.0V_ALW_PCH +1.0V_AMPHYPLL +1.0V_ALW_PCH +1.0V_AZPLL +1.0V_ALW_PCH +1.0V_XTAL
1 2 1 2
Vinafix.com
1 2 0.213A 0.0015A 0.00428A
RH289 0_0603_5% RH241 0_0603_5% RH238 0_0603_5%
1U_0402_6.3VAK
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1U_0402_6.3VAK
1U_0402_6.3VAK
1U_0402_6.3VAK
1 1 1 1 1 1
@ CH46
@ CH45
@ CH324
@ CH29
D D
CH32
CH267
2 2 2 2 2 2
+1.0V_BCLKPLL2_R +1.0V_DSW +1.0V_PRIM +1.0V_MPHY +1.0V_CLPLLEBB +1.0V_DUSB
+1.0V_OC
+1.0V_OCPLL1
0.1U_0201_10V6K
1
1U_0402_6.3VAK
1U_0402_6.3VAK
1U_0402_6.3VAK
22U_0603_6.3V6M
1U_0402_6.3VAK
0.1U_0402_25V6
@ CH44
1
0.1U_0402_25V6
1 1 1
1U_0402_6.3VAK
1 1 1 1
CH31
CH35
CH34
CH47
CH36
CH66
CH38
CH20
2
2 2 2 2 2 2 2 2
+1.8V_PRIM_PCH +1.24V_DPHY_MAR
C C
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1U_0402_6.3VAK
1 1 1
CH30
CH22
CH21
2 2 2
+3.3V_PRTC +3.3V_PGPPHK +3.3V_PGPPEF +3.3V_DSW

+3.3V_PHVLDO
0.1U_0201_10V6K
0.1U_0201_10V6K
@ CH62
0.1U_0402_25V6
4.7U_0402_6.3V6M
1U_0402_6.3VAK
0.1U_0402_25V6
@ CH64
1 1 1 1 1
@ CH63
1U_0402_6.3VAK
0.1U_0402_25V6
1 1 1
@ CH323
CH33
CH65
CH37
CH67
2 2 2 2 2
2 2 2
B B
CFL-H PDG rev0.5

4.7uF x1
CRB-H rev0.7
0.1uF x1, 1uF x1
A A
Title
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
CNP-H CNP-H
UH1I UH1L
A2 AL12
A28 VSS VSS AL17 BG3 M24
A3 VSS VSS AL21 BG33 VSS VSS M32
A45 VSS VSS AL33 C12 VSS VSS N12
A46 VSS VSS AL38 C25 VSS VSS N16
A47 VSS VSS AM1 C30 VSS VSS N34
AA19 VSS VSS AN12 D12 VSS VSS P26
AA28 VSS VSS AP4 D33 VSS VSS R12
AA30 VSS VSS AP46 D8 VSS VSS R16
AA31 VSS VSS AR12 E10 VSS VSS R26
AB19 VSS VSS AR38 E17 VSS VSS R34
AB25 VSS VSS AT1 E19 VSS VSS R38
AB31 VSS VSS AT16 E22 VSS VSS R4
AC12 VSS VSS AT18 E24 VSS VSS T17
C AC17 VSS VSS AT21 E26 VSS VSS T18 C
AD1 VSS VSS AT34 E42 VSS VSS T7
AD19 VSS VSS AT45 E8 VSS VSS U12
AD2 VSS VSS AV11 F41 VSS VSS U15
AD22 VSS VSS AV39 F43 VSS VSS U17
AD25 VSS VSS AW10 F47 VSS VSS U21
AD49 VSS VSS AW4 G44 VSS VSS U24
AE12 VSS VSS AW40 G6 VSS VSS U33
AE33 VSS VSS AW46 H8 VSS VSS U38
AE38 VSS VSS B47 J10 VSS VSS V20
AF22 VSS VSS BA12 J4 VSS VSS V46
AF25 VSS VSS BA14 J40 VSS VSS W25
AF28 VSS VSS BA44 J46 VSS VSS W27
AG1 VSS VSS BA5 J47 VSS VSS W28
AG22 VSS VSS BA6 J48 VSS VSS W30
AG23 VSS VSS BB41 J9 VSS VSS Y10
AG25 VSS VSS BB43 K11 VSS VSS Y12
AG27 VSS VSS BB9 K39 VSS VSS Y17
AG28 VSS VSS BC10 M16 VSS VSS Y33
AG30 VSS VSS BC13 M18 VSS VSS Y38
AG49 VSS VSS BC15 M21 VSS 12 OF 13 VSS Y9
AH12 VSS VSS BC19 VSS VSS
AH17 VSS VSS BC24 CNP-H_BGA874 Rev1.0
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
AJ27 VSS VSS BC8
B AJ28 VSS VSS BD43 B
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0
A A
Title
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
+3.3V_RUN
+3.3V_RUN
2 1 CPU_DP3_AUXN_RD
RV71 100K_0402_5%
0.01UF_0402_25V7K
0.1U_0201_10V6K
1
CV62
CV61
2
2
2 1 DP_RP_CADET
RV74 1M_0402_5%
2 1 DP_RP_I2C
RV76 100K_0402_5%
12
25
32
36
CPU_DP3_AUXP_RD
1
6
2 1 UV9
RV77 100K_0402_5%
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
CV65 1 2 0.1U_0201_10V6K CPU_DP3_P0_C_RD 38 23
<9> CPU_DP3_P0 CPU_DP3_N0_C_RD IN0p OUT0p CPU_DP3_P0_RD <27>
CV66 1 2 0.1U_0201_10V6K 39 22
<9> CPU_DP3_N0 CPU_DP3_P1_C_RD IN0n OUT0n CPU_DP3_N0_RD <27>
CV67 1 2 0.1U_0201_10V6K 41 20
<9> CPU_DP3_P1 1 2 CPU_DP3_N1_C_RD 42 IN1p OUT1p 19 CPU_DP3_P1_RD <27>
CV68 0.1U_0201_10V6K
+3.3V_RUN <9> CPU_DP3_N1 CPU_DP3_P2_C_RD IN1n OUT1n CPU_DP3_N1_RD <27>
@ CV69 1 2 0.1U_0201_10V6K 44 17
<9> CPU_DP3_P2 CPU_DP3_N2_C_RD IN2p OUT2p
@ CV70 1 2 0.1U_0201_10V6K 45 16
<9> CPU_DP3_N2
@ CV71 1 2 0.1U_0201_10V6K CPU_DP3_P3_C_RD 47 IN2n OUT2n 14 VGA
<9> CPU_DP3_P3 CPU_DP3_N3_C_RD IN3p OUT3p
@ CV72 1 2 0.1U_0201_10V6K 48 13
<9> CPU_DP3_N3 IN3n OUT3n
2
DP_RP_I2C DP_RP_CFG1 +3.3V_RUN

4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
3 40
I2C_ADDR CFG1
RV79
RV81
RV83
C DP_RP_PEQ 4 46 C
DP_RP_CFG0 5 SCL_CTL/PEQ NC
SDA_CTL/CFG0
10K_0402_5%
@ @ @ 35 DP_RP_RST#
1
1
RST#
RV621
@ RV89 1
2 DP_RP_PD# 26 10 DP_RP_CADET
4.7K_0402_5% PD# CAD_SNK
DP_RP_CFG0 DP_RP_REXT 7 11
REXT HPD_SINK PCH_DP3_RD_HPD <27>
DP_RP_CFG1
2
8
CAD_SRC
DP_RP_PEQ DP_RP_RST#
9 28
<21> PCH_DP3_HPD HPD_SRC AUX_SNKP CPU_DP3_AUXP_RD <27>
2.2U_0402_6.3V6M
27
AUX_SNKN CPU_DP3_AUXN_RD <27>
for support TMDS signal need contact SCL/SDA to P33,34 1
33
<21> PCH_DP3_CTRL_CLK SCL_DDC
CV631
34
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1
<21> PCH_DP3_CTRL_DATA SDA_DDC DP_RP_CEXT

2
CEXT 2
RV80
RV82
RV84
15
CV73 1 2 0.1U_0201_10V6K CPU_DP3_AUXP_C_RD 30 NC2 21
<9> CPU_DP3_AUXP CPU_DP3_AUXN_C_RD AUX_SRCP NC3
2.2U_0402_6.3V6M
@ CV74 1 2 0.1U_0201_10V6K 29 37
<9> CPU_DP3_AUXN AUX_SRCN NC4
1
@ @
CV75
43
2
NC5
DP_RP_REXT
2
GND1
GND2
GND3
EPAD
1
4.99K_0402_1%
RV50
PS8330BQFN48GTR2-A0_QFN48_7X7
18
24
31
49
2
DP_RP_CFG0 :
B Configuration pin for automatic EQ and AUX interception; Internal pull down at ~150kΩ , 3. 3V I / O. B
L: default, automatic EQ enable & AUX interception enable
H: automatic EQ disable & AUX interception enable
M: automatic EQ disable & AUX interception disable, no pre-emphasis, 600mVpp swing
DP_RP_CFG1 :
Configuration pin for auto test and input offset cancellation, 3.3V IO, internal pull up at ~150K
H: default, auto test disable & input offset cancellation enable
L: auto test enable & input offset cancellation enable
M: auto test disable & input offset cancellation disable
DP_RP_PEQ :
Programmable input equalization levels; Internal pull down at ~150kΩ , 3. 3V I / O.
L: default, LEQ, compensate channel loss up to 12dB @ HBR2
H: HEQ, compensate channel loss up to 15dB @ HBR2
M: LLEQ, compensate channel loss up to 5dB @ HBR2
A A
Title
DP SW2 PS8338
5 4 3 2 1
5 4 3 2 1
For Breckenridge 15
Vinafix.com +5V_RUN
D D
0.1U_0201_10V6K
1
1
CV39
+VHDMI_VCC
2
IN
AP2330W-7_SC59-3
UV2
0.1U_0201_10V6K
10U_0603_10V6M
@
EMI@ RV24 1 2 5.6_0402_5% 1
1
HDMI_L_TX_N2
CV40
CV41
GND
OUT
HCM1012GH900BP_4P
2
1 2 HDMI_TX_N2 2 3 EMI@
2
<9> CPU_DP1_N0 2 3 2
CV32 0.1U_0402_25V6 RV26
3
200_0402_5%
<9> CPU_DP1_P0
CV31
1 2
0.1U_0402_25V6
HDMI_TX_P2 1
1 4
4
HDMI connector
1
@EMI@ LV3 HDMI_L_TX_P2
1 2
EMI@ RV25 5.6_0402_5%
JHDMI1 CONN@
EMI@ RV27 1 2 5.6_0402_5% HDMI_HPD 19
HDMI_L_TX_N1 18 HP_DET
HCM1012GH900BP_4P 17 +5V
DDC/CEC_GND
2
1 2 HDMI_TX_N1 2 3 EMI@ +3.3V_RUN HDMI_CTRL_DATA 16
<9> CPU_DP1_N1 2 3 HDMI_CTRL_CLK SDA
CV34 0.1U_0402_25V6 RV29 15
14 SCL
200_0402_5% Reserved
1 2 HDMI_TX_P1 1 4 2 1 HDMI_CEC 13
<9> CPU_DP1_P1 1 4 HDMI_L_CLKN 12 CEC 20
CV33 0.1U_0402_25V6 10K_0402_5% @ RV19
1
@EMI@ LV6 HDMI_L_TX_P1 11 CK- GND 21
1 2 HDMI_L_CLKP 10 CK_shield GND 22
EMI@ RV28 5.6_0402_5% HDMI_L_TX_N0 9 CK+ GND 23
8 D0- GND
C
EMI@ RV30 1 2 5.6_0402_5% HDMI_L_TX_P0 7 D0_shield C
HDMI_L_TX_N0 HDMI_L_TX_N1 6 D0+
HCM1012GH900BP_4P 5 D1-
D1_shield
2
1 2 HDMI_TX_N0 2 3 EMI@ HDMI_L_TX_P1 4
<9> CPU_DP1_N2 2 3 HDMI_L_TX_N2 D1+
CV36 0.1U_0402_25V6 RV32 3
2 D2-
200_0402_5% D2_shield
1 2 HDMI_TX_P0 1 4 HDMI_L_TX_P2 1
<9> CPU_DP1_P2 1 4 D2+
CV35 0.1U_0402_25V6
1
@EMI@ LV9 HDMI_L_TX_P0 CONCR_099BKAC19YBLCNF
1 2
EMI@ RV31 5.6_0402_5%
EMI@ RV33 1 2 5.6_0402_5% LINK 099BKAC19YBLCNF DONE

HDMI_L_CLKN
HCM1012GH900BP_4P
2
2 1 HDMI_CLKN 2 3 EMI@ HDMI_TX_P2 RV10 1 2 470_0402_1% HDMI_OB
<9> CPU_DP1_N3 0.1U_0402_25V6 2 3 HDMI_TX_N2 1 2
CV38 RV35 RV11 470_0402_1%
HDMI_TX_P1 RV12 1 2 470_0402_1%
200_0402_5%
2 1 HDMI_CLKP 1 4 HDMI_TX_N1 RV13 1 2 470_0402_1%
<9> CPU_DP1_P3 0.1U_0402_25V6 1 4 HDMI_TX_P0
CV37 RV14 1 2 470_0402_1%
1
@EMI@ LV12 HDMI_L_CLKP HDMI_TX_N0 RV15 1 2 470_0402_1%
HDMI_CLKP RV16 1 2 470_0402_1%
1 2 HDMI_CLKN RV17 1 2 470_0402_1%
EMI@ RV34 5.6_0402_5%
1
D
+3.3V_RUN RV18 1 2 10K_0402_5% 2 QV4

G L2N7002WT1G_SC-70-3
S
3
+3.3V_RUN
B B
1M_0402_5%
2
RV20
2
G
1
3 1 HDMI_HPD 1 2
<21> PCH_DP1_HPD
S
RV21 20K_0402_5%
QV5
L2N7002WT1G_SC-70-3
+3.3V_RUN
QV3A +VHDMI_VCC
2
DMN65D8LDW-7_SOT363-6
1 6 HDMI_CTRL_CLK 1 2
<21> PCH_DP1_CTRL_CLK
RV22 2.2K_0402_5%
5
4 3 HDMI_CTRL_DATA 1 2
<21> PCH_DP1_CTRL_DATA
RV23 2.2K_0402_5%
A QV3B A
Title
HDMI CONN
5 4 3 2 1
5 4 3 2 1
For TBT SW2_DP2

For non-TBT SW1_DP2
For Realtek Solution
+3.3V_RUN +3.3V_RUN Place near UV6.4 Place near UV6.25 Place near UV6.26
+3.3V_RUN
Vinafix.com
60ohm/1A
+3.3V_VGA
UV6
+VDD_DAC_33
60ohm/1A
+VCCK_12
0.1U_0402_25V6
0.1U_0402_25V6
2.2U_0402_25V6K
+3.3V_RUN 1 2 1 20 2 1
+VCCK_12 AVC33 VDD_DAC_33 1 1 1
0.1U_0402_25V6
CV103
CV104
CV105
0.1U_0402_25V6
LV14 BLM15PX600SN1D_2P 4 BLM15PX600SN1D_2P LV30 1
AVCC_12 +VCCK_12
CV106
D 14 25 D
VCC_33 VCCK_12 1
CV100
2 1 ISPSCL 0.1U_0402_10V7K 1 2 CV111 CPU_DP3_AUXP_C 2 26 2 2 2
<25> CPU_DP3_AUXP_RD CPU_DP3_AUXN_C AUX_P PVCC_33 +3.3V_RUN 2
@ RV106 4.7K_0402_5% 0.1U_0402_10V7K 1 2 CV112 3 +CRT_VCC
2 1 ISPSDA <25> CPU_DP3_AUXN_RD AUX_N 2
@ RV107 4.7K_0402_5% 0.1U_0402_10V7K 1 2 CV107 CPU_DP3_P0_C 5 17
<25> CPU_DP3_P0_RD CPU_DP3_N0_C LANE0_P HVSYNC_PWR VSYNC_CRT
0.1U_0402_10V7K 1 2 CV108 6 18
<25> CPU_DP3_N0_RD CPU_DP3_P1_C LANE0_N VSYNC HSYNC_CRT
0.1U_0402_25V6
4.7U_0402_6.3V6M
0.1U_0402_10V7K 1 2 CV109 7 19
<25> CPU_DP3_P1_RD CPU_DP3_N1_C LANE1_P HSYNC
0.1U_0402_10V7K 1 2 CV110 8 1 1
PCH_DP3_RD_HPD <25> CPU_DP3_N1_RD LANE1_N
CV101
CV102
2 1
RV102 100K_0402_5%
+3.3V_RUN
RV123
RV124
1
1
2 4.7K_0402_5%
2 4.7K_0402_5%
10
9 POL1/SPI_CEB
POL2
RTD2166 BLUE_P
21
22
BLUE_CRT
GREEN_CRT 2 2
RV620 1 2 4.7K_0402_5% 11 GREEN_P
RV622 1 2 4.7K_0402_5% 12 GPI1/SPI_CLK 23 RED_CRT
13 GPI2/SPI_SI RED_P
GPI3/SPI_SO
CLK_DDC2_CRT 15 +3.3V_RUN
DAT_DDC2_CRT 16 VGA_SCL
VGA_SDA 27
ISPSCL 30 LDO_RSTB 28
ISPSDA 29 SMB_SCL EXT_CLK_IN 31 @RF@
SMB_SDA EXT1.2V_CTRL
0.1U_0402_25V6
PCH_DP3_RD_HPD 32 24
<25> PCH_DP3_RD_HPD HPD GND 1
33
CV7
EPAD_GND
RTD2166-CG_QFN32_4X4
2
Operation Mode Table

C POL1(P10) C
0 1
0 X X
POL2
(P9) 1 ROM EEPROM
+5V_RUN
3
PJDLC05C_SOT23-3
PJDLC05C_SOT23-3
@ESD@ DV5
@ESD@ DV6
1
UV4
IN
AP2330W-7_SC59-3
GND
OUT
RED_CRT 1 2
EMI@ LV16 BLM15BB470SN1D_2P
3
B GREEN_CRT 1 2 +CRT_VCC B
BLUE_CRT 1 2
40mils
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
3.3P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
1
1
1
75_0402_1%
75_0402_1%
75_0402_1%
1 1 1
1 1 1 CV134
RV116
RV117
RV118
CV129
CV130
CV131
1U_0402_6.3V6K
2 JCRT1
2 2 2
CV126
CV127
CV128
6
2
2
2 @ 2 @ 2 @ @ T200PAD~D JCRT-11 11
RED 1
7
12
+CRT_VCC GREEN 2
8
HSYNC_CONN 13
BLUE 3
9
2
2.2K_0402_5%
2.2K_0402_5%
VSYNC_CONN 14
1K_0402_5%
1K_0402_5%
RV119 M_ID2# 4 G 16
RV120
@ RV121
@ RV122
10 G 17
15
5
1
1
DAT_DDC2_CRT
.1U_0402_16V7K
1 CCM_C070546HR015M29CZR
CLK_DDC2_CRT
CV135
CONN@
HSYNC_CRT 1 2
EMI@ RV1650 100_0402_5% 2
VSYNC_CRT 1 2
2P_0402_50V8C~D
2P_0402_50V8C~D
EMI@ RV1651 100_0402_5%
A A
1 1
CV132
CV133
2 2
Title
DP to VGA & VGA Conn
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
LA-F711P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN_UT9 +3.3V_CPS
+1.2V_VDD_DM_D1
+1.2V_RUN +1.2V_VDD_R1 +1.2V_RUN
Vinafix.com LT602 LT605

1 2 1 2 1 2
LT11 BLM18KG331SN1D_2P BLM18KG331SN1D_2P BLM18KG331SN1D_2P +3.3V_RUN_UT9
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.01UF_0402_25V7K
4.7U_0402_6.3V6M
0.1U_0201_10V6K
4.7U_0402_6.3V6M
0.1U_0402_25V6
4.7U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
CT118
D 1 1 1 1 1 1 1 1 1 D
CT44
CT48
CT618
CT617
CT614
CT615
CT616
CT117
1
CT625
CT628
2
2
2 2 2 2 2 2 2 2 2 10K_0402_5%
RT246
2
PS8802_RST#
+3.3V_RUN +3.3V_RUN_UT9 1
CT122
+1.2V_RUN +1.2V_VDD_A2 +1.2V_VDD_A1 +3.3V_RUN_UT9 +3.3V_VDD_DCI
+1.2V_RUN +1.2V_VDD_R2 +1.2V_RUN 1U_0402_6.3V6K
2
1 2 LT603 LT604
@ RT397 0_0603_5% LT601 1 2 1 2 RT303
1 2 1 2
BLM18KG331SN1D_2P BLM18KG331SN1D_2P
0.01UF_0402_25V7K
+3.3V_VDD_PIC BLM18KG331SN1D_2P
0.01UF_0402_25V7K
0.1U_0402_25V6
4.7U_0402_6.3V6M
0.1U_0402_25V6
0.01UF_0402_25V7K
1U_0402_6.3V6K
0_0402_5%
4.7U_0402_6.3V6M
0.1U_0402_25V6
4.7U_0402_6.3V6M
1 1 1 1 1 1 1
CT45
CT46
CT626
CT119
1
CT611
CT612
1 1
CT610
CT47
CT627
CT629
1 2 2 2 2 2 2 2 2 +3.3V_RUN_UT9
2 2 2
RT398 0_0603_5% MUX1_USB_SEL 1 2
RT308 4.7K_0402_5%
PS8802_CSCL 1 2
@ RT305 4.7K_0402_5%
PS8802_CSDA 1 2
@ RT304 4.7K_0402_5%
CPU_DP2_AUXN_C_MUX 1 2
RT131 100K_0402_5%
C +3.3V_RUN_UT9 C
CPU_DP2_AUXP_C_MUX 1 2
RT130 100K_0402_5%
PS8802_SBU1_R 1 2
RT414 2M_0402_5%
PS8802_SBU2_R 1 2
2
2
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
UT9 RT415 2M_0402_5%

@ RT135
@ RT137
@ RT139
@ RT141
+1.2V_VDD_DM_D1 +3.3V_CPS
1 27
1
10 VDD_DM VDD33 52
16 VDD_DM VDD33
PS8802_ADDR VDD_DM +3.3V_VDD_DCI
38 49
VDD_DM VDD_DCI
PS8802_DPEQ +1.2V_VDD_R1 6 19 PS8802_ADDR
7 VDD_R1 ADDR0 22 PS8802_DPEQ
+1.2V_VDD_R2 VDD_R2 ADDR1
PS8802_CEQ
+1.2V_VDD_A1 13 43 PS8802_RST#
PS8802_SSEQ 47 VDD_A1 RESET#
+1.2V_VDD_A2 VDD_A2
+1.2V_VDD_DM_D1 30 33 PS8802_SBU1_R 1 2
VDD_D1 SBU1 PS8802_SBU2_R DP2_MIC_SBU1 <29,31>
34 RT132 1 2 0_0402_5%
SBU2 DP2_MIC_SBU2 <29,31>
1
1
4.7K_0402_5%
@ RT136
4.7K_0402_5%
@ RT138
4.7K_0402_5%
@ RT140
4.7K_0402_5%
@ RT142
RT133 0_0402_5%
2
USB3_PRX_C_MTX_P5 12 RX1p USB3_DP2_1_MRX_DTX_P5 <31>
1 2 3
<20> USB3_PRX_MTX_P5 SSRXp RX1n USB3_DP2_1_MRX_DTX_N5 <31>
CT111 1 2 0.22U_0402_10V6K USB3_PRX_C_MTX_N5 11
<20> USB3_PRX_MTX_N5 CT112 0.22U_0402_10V6K SSRXn 9
USB3_DP2_2_MRX_DTX_P5 <31>
2
1 2 USB3_PTX_C_MRX_P5 15 RX2p 8
<20> USB3_PTX_MRX_P5 SSTXp RX2n USB3_DP2_2_MRX_DTX_N5 <31>
CT113 1 2 0.22U_0402_10V6K USB3_PTX_C_MRX_N5 14
<20> USB3_PTX_MRX_N5 SSTXn
CT114 0.22U_0402_10V6K 41
TX1p 42 USB3_DP2_1_MTX_DRX_P5 <31>
1 2 CPU_DP2_P0_C 17 TX1n USB3_DP2_1_MTX_DRX_N5 <31>
<9> CPU_DP2_P0 2 0.22U_0402_10V6K CPU_DP2_N0_C ML0p
CT103 1 18 45
<9> CPU_DP2_N0 ML0n TX2p USB3_DP2_2_MTX_DRX_P5 <31>
CT104 0.22U_0402_10V6K 44
B 1 2 CPU_DP2_P1_C 20 TX2n USB3_DP2_2_MTX_DRX_N5 <31> B
<9> CPU_DP2_P1 ML1p
CT105 1 2 0.22U_0402_10V6K CPU_DP2_N1_C 21
<9> CPU_DP2_N1 ML1n 28
ADDR: I2C control bus address. Internally pull down at 150k, 3.3V I/O CT106 0.22U_0402_10V6K PS8802_CSCL <29>
L: Slave address 0x10-0x2F(default) 1 2 CPU_DP2_P2_C 23 CSCL 29
<9> CPU_DP2_P2 ML2p CSDA PS8802_CSDA <29>
H: Slave address 0x30-0x4F CT107 1 2 0.22U_0402_10V6K CPU_DP2_N2_C 24
<9> CPU_DP2_N2 ML2n MUX1_DP_SEL
CT108 0.22U_0402_10V6K 35
CPU_DP2_P3_C CE_DP MUX1_USB_SEL MUX1_DP_SEL <29>
1 2 25 36
<9> CPU_DP2_P3 2 0.22U_0402_10V6K CPU_DP2_N3_C ML3p CE_USB MUX1_FLIP_SEL MUX1_USB_SEL <29>
DPEQ:DP Receiver equalization setting; Internally pull down at 150k, 3.3V I/O CT109 1 26 37
L: Compensation for channel loss up to 12dB(Default) <9> CPU_DP2_N3 ML3n FLIP MUX1_FLIP_SEL <29>
CT110 0.22U_0402_10V6K
H: Compensation for channel loss up to 18dB 1 2 CPU_DP2_AUXP_C_MUX 31 40 PS8802_HPD 2 1
<9,29> CPU_DP2_AUXP AUXp IN_HPD PCH_DP2_HPD <21,29>
CT115 1 2 0.1U_0402_25V6 CPU_DP2_AUXN_C_MUX 32 0_0402_5% RT380
<9,29> CPU_DP2_AUXN AUXn PS8802_REXT
CT116 0.1U_0402_25V6 39
REXT 4
CEQ: USB Type-C connector facing Rx channel receiver equalization setting; RSV1
DCI_CLK
@@
Internally pull down at 150k, 3.3V I/O. RT307 1 2 0_0402_5% 50 5
4.99K_0402_1%
DCI_CLK RSV2
1
L: Compensation for channel loss up to 16dB(Default) RT306 1 2 0_0402_5% DCI_DATA 51 46 PS8802_SSEQ
H: Compensation for channel loss up to 18dB DCI_DATA RSV3 48 PS8802_CEQ
RT300
RSV4
SSEQ: USB Host facing Rx channel receiver equalization setting;
Internally pull down at 150k, 3.3V I/O. 53
2
L: Compensation for channel loss up to 12dB(Default) ePAD
H: Compensation for channel loss up to 18dB
PS8802QFN52GTRA2_QFN52_6P5X4P5
change from SA0000AIM10(A1) to SA0000AIM20(A2)
A A
Title
DP/USB3 Re-timer PS8802
Date: Wednesday, January 31, 2018 Sheet 28 of 63
5 4 3 2 1
5 4 3 2 1
+3.3V_TBTA_FLASH +3.3V_TBTA_FLASH
+3.3V_VDD_PIC
For Non-AR config
2
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
.1U_0402_16V7K
1
1
RT50
CT70
RT51
RT52
RT53
1
1 6 UPD1_SMBCLK_Q
<37> UPD1_SMBCLK
@ QT1A
2
2
2
RT58 1 2 0_0402_5%
UT6
Vinafix.com
5
8 1 TBTA_ROM_CS#_PD_R
TBTA_ROM_HOLD#_PD 7 VCC CS# 2 TBTA_ROM_DO_PD_R
TBTA_ROM_CLK_PD_R 6 HOLD#(IO3) DO(IO1) 3 TBTA_ROM_WP#_PD 4 3 UPD1_SMBDAT_Q
TBTA_ROM_DI_PD_R CLK WP#(IO2) <37> UPD1_SMBDAT
5 4
D DI(IO0) GND @ QT1B D
GD25Q80CSIGR_SO8 DMN66D0LDW-7_SOT363-6
RT59 1 2 0_0402_5%
TBTA_ROM_CLK_PD_R 0_0402_5% 2 1 RT54 TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD_R 0_0402_5% 2 1 RT55 TBTA_ROM_DI_PD
TBTA_ROM_DO_PD_R 0_0402_5% 2 1 RT56 TBTA_ROM_DO_PD RT60 1 2 0_0402_5% UPD1_SMBUS_ALERT#
TBTA_ROM_CS#_PD_R TBTA_ROM_CS#_PD <37> UPD1_SMBINT#
0_0402_5% 2 1 RT57
+3.3V_TBTA_FLASH
JDB1
1
1 TBTA_ROM_CLK_PD_R
2 +5V_ALW
2 TBTA_ROM_DI_PD_R
3
3 TBTA_ROM_DO_PD_R
4 PJP8 TI is 1x47uf+1x0.1uf
7 4 TBTA_ROM_CS#_PD_R
5 1 2 RF requeat
8 GND 5 6
GND 6 PAD-OPEN 1x3m +TBTA_Vbus_1 +5V_ALW_PDA
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
JXT_FP241AH-006GAAM 1 1 1 1
CT75
CT76
CT77
CT78
CONN@
100P_0402_50V8J~D
RF@ CT22
1
2 2 2 2
2
+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO RT64 @ 1 2 0_0402_5%
+VCC1V8A_TBTA_LDO
RT65 @ 1 2 0_0402_5%
+3.3V_VDD_PIC +3.3V_VDD_PIC_PDA
HV_GATE1_A
HV_GATE2_A
2.2U_0402_25V6K
2.2U_0402_25V6K
2.2U_0402_25V6K
PJP7
1 1 1
TI is 3x1uf 1 2
+5V_ALW_PDA
CT71
CT72
CT73
PAD-OPEN1x1m
1U_0402_10V6K
2 2 2 1
CT74
1 2
RT63 0_0402_5%
C C
H10
C11
D11
A11
B11
B10
A10
2
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
UT5
+3.3V_TBTA_FLASH F1
DIV = R2/(R1+R2)
VIN_3V3
VDDIO
LDO_1V8A
PP_CABLE
PP_5V0
PP_5V0
PP_5V0
PP_5V0
SENSEP
HV_GATE1
HV_GATE2
LDO_1V8D
LDO_BMC
GND
GND
GND
GND
SENSEN
Factory Device Description I2C_ADDR
Configuration RT378 2 1 10K_0402_5% D1
DIV_min DIV_max RT379 2 1 10K_0402_5% D2 I2C_SDA1 +TBTA_Vbus_1
+3.3V_TBTA_FLASH C1 I2C_SCL1
UFP only +3.3V_TBTA_FLASH I2C_IRQ1_N TI has 1x1uf
5V @0.9A Sink capability with "Ask for Max/" for +3.3V_ALW
0.00 0.08 0 anything from 0.9 -3.0A @ RT66 2 1 3.3K_0402_5% UPD1_SMBDAT_Q A5 +3.3V_PDA_VOUT +3.3V_TBTA_FLASH
TBT Alternate Modes not supported 1 3.3K_0402_5% UPD1_SMBCLK_Q I2C_SDA2
1U_0603_25V6K
@ RT67 2 B5 H11
2
1
DisplayPort Alternate Modes not supported @ RT68 2 1 10K_0402_5% UPD1_SMBUS_ALERT# B6 I2C_SCL2 VBUS J10
TI VID supported RT76 I2C_IRQ2_N VBUS
CT82
J11
10U_0603_6.3V6M
1U_0402_10V6K
10K_0402_1% MUX1_FLIP_SEL MUX1_FLIP_SEL_R VBUS 1 1
CT83
RT69 2 1 0_0402_5% B2 K11
<28> MUX1_FLIP_SEL
2
EN_PD_HV_1_R GPIO0 VBUS
CT84
UFP only RT70 2 1 0_0402_5% C2
<60> EN_PD_HV_1 GPIO1
5V @0.9A Sink capability with "Ask for Max/" for RT71 2 1 1M_0402_5% PD1_GPIO2 D10
1
0.10 0.18 1 anything from 0.9 -3.0A PD1_GPIO8 RT72 2 1 0_0402_5% AC1_DISC#_R G11 GPIO2 2 2
TBT Alternate Modes not supported <49,60> AC1_DISC# PCH_DP2_HPD_R GPIO3
RT73 2 1 0_0402_5% C10
1
DisplayPort Alternate Modes -Sink, C and D pin configuration <21,28> PCH_DP2_HPD RT74 2 1 0_0402_5% OTG_ID E10 GPIO4 H2
TI VID supported <17> USB2_ID PD1_GPIO6 GPIO5 VOUT_3V3
RT377 @ RT75 2 1 0_0402_5% G10
@ RT339 2 1 0_0402_5% PD1_GPIO7 D7 GPIO6
43K_0402_1%
UFP only PD1_GPIO8 H6 GPIO7
0.20 0.28 2 5V @3.0A Source capability GPIO8 G1
2
TBT Alternate Modes not supported TBTA_ROM_CLK_PD A3 LDO_3V3

DisplayPort Alternate Modes not supported TBTA_ROM_DI_PD B4 SPI_CLK
TI VID supported TBTA_ROM_DO_PD A4 SPI_MOSI
TBTA_ROM_CS#_PD B3 SPI_MISO K6
SPI_SS_N C_USB_TP SW_USB20_2_P4 <31>
UFP only L6 SW_USB20_2_N4 <31>
0.30 0.38 3 5V @3.0A Source capability L5 C_USB_TN
TBT Alternate Modes not supported UART_MOSI <17> USB20_P4 USB_RP_P
2 1 K5
DisplayPort Alternate Modes -Sink, C and D pin configuration UART_MOSI <17> USB20_N4 USB_RP_N
RT81 100K_0402_5%
TI VID supported 2 1 UART_MISO RT83 2 1 0_0402_5% E2 K7
UART_MISO UART_TX C_USB_BP SW_USB20_1_P4 <31>
@ RT82 1M_0402_5% F2 L7 SW_USB20_1_N4 <31>
DRP UART_RX C_USB_BN
5V @0.9-3.0A Sink capability TI SPEC: 100K PD @ RT84 2 1 0_0402_5% F4
5V @3.0A Source capability @ T219 PAD~D SWD_DATA
0.40 0.48 INTEL SCH :1M PD @ RT85 2 1 0_0402_5% G4 TI has 2x220pf
TBT Alternate Modes not supported @ T220 PAD~D SWD_CLK TBTA_CC1 <31>
4 L9
DisplayPort Alternate Modes not supported C_CC1 L10
TI VID supported C_CC2 WHEN
470P_0402_50V7K
470P_0402_50V7K
Accepts data and power role swaps, but does not CONNECT BUSPOWERZ TO GND, TBTA_CC2 <31>
RT86 2 1 1M_0402_5% TBTA_MRESET E11
initiate. MRESET
CONNECT ALSO RPD_Gn to C_CCn 1 1
B B
CT85
CT86
K9 RT104 1 2 0_0402_5%
DRP @ RT87 1 2 0_0402_5% TBTA_LSTX_R L4 RPD_G1 K10 RT105 1 2 0_0402_5%
5V @0.9-3.0A Sink capability @ RT88 1 2 0_0402_5% TBTA_LSRX_R K4 TBT_LSTX/R2P RPD_G2 +3.3V_TBTA_FLASH 2 2
5V @3.0A Source capability TBT_LSRX/P2R
0.50 0.58 5 TBT Alternate Modes not supported
DisplayPort Alternate Modes - Source, C, D, and E MUX1_DP_SEL/MUX1_USB_SEL control by: 1 2 TBTA_DEBUG3 L3 E4 TBTA_DBG_CTL1 RT106 1 2 10K_0402_5%
pin configurations. GPIO: Pop RT69,RT90;Depop RT375,RT376 <28> MUX1_DP_SEL MUX1_USB_SEL RT89 1 2 0_0402_5% TBTA_DEBUG4 K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 TBTA_DBG_CTL2 RT107 1 2 10K_0402_5%
TI VID supported I2C:Depop RT69,RT90;pop RT375,RT376 <28> MUX1_USB_SEL DIG_AUD_N/DEBUG4 DEBUG_CTL2
Accepts power role swaps but will not initiate. RT90 0_0402_5%
Accepts data role swap to UFP and can initiate. PS8802_CSCL RT375 1 2 0_0402_5% UPD1_SMBCLK_Q 1 2 TBTA_DEBUG1 L2
<28> PS8802_CSCL PS8802_CSDA DEBUG1
DRP RT376 1 2 0_0402_5% UPD1_SMBDAT_Q RT92 1 2 0_0402_5% TBTA_DEBUG2 K2
5V @0.9-3.0A Sink capability <28> PS8802_CSDA DEBUG2
RT93 0_0402_5%
5V @3.0A Source capability K8 DP2_AUXP_SBU1 1 2
TBT Alternate Modes not supported CPU_DP2_AUXP_C J1 C_SBU1 DP2_MIC_SBU1 <28,31>
0.60 0.68 6 @ CT80 1 2 0.1U_0201_10V6K @ RT108 0_0402_5%
DisplayPort Alternate Modes - Source, C, D, and E <9,28> CPU_DP2_AUXP CPU_DP2_AUXN_C J2 AUX_P DP2_AUXN_SBU2
Route in pass through manner so AUX can be snooped by 546 @ CT81 1 2 0.1U_0201_10V6K L8 1 2
pin configurations. <9,28> CPU_DP2_AUXN AUX_N C_SBU2 DP2_MIC_SBU2 <28,31>
TI VID supported @ RT109 0_0402_5%
Accepts power role swaps but will not initiate.
Accepts data role swap to DFP and can initiate. F10
BUSPOWER_N F11 TBTA_RESET_N_EC_R @ RT110 2 1 0_0402_5%
0.70 1.00 7 Infinite boot retry from Flash to Host I/F cycles. +3.3V_TBTA_FLASH RESET_N
HRESET
TBTA_ROSC G2
+3.3V_TBTA_FLASH R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
15K_0402_0.1%
SS
2
@
0_0402_5%
RT100
TPS65982_BGA96
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
CPU_DP2_AUXN_C
RT98
2 1
RT95 100K_0402_5%
2
1
2 1 CPU_DP2_AUXP_C
RT96 100K_0402_5% +VCC1V8D_TBTA_LDO 1 2
100K_0402_5%
@ RT97 0_0402_5%
0_0402_5%
1
1
RT101
RT103
0_0402_5%
CT87
RT99
0.22U_0402_16V7K
2 @
2
2
change TPS65982DB -> DC

A A
Title
[Type C]PD Controller TI
5 4 3 2 1
5 4 3 2 1
+5V_ALW
DT1 +5V_PD_VDD +3.3V_VDD_PIC

2 1
+5V_TBT_VBUS UT7
1N4148WS-7-F_SOD323-2 1 5
VCC VOUT
2
DT2
1
Vinafix.com 2
100K_0402_5%
GND
1
@
0.1U_0201_10V6K
1U_0402_10V6K
1N4148WS-7-F_SOD323-2 3 4
RT393
1 1 EN ADJ/NC
2.2U_0402_10V6M
0.1U_0402_25V6K
D 1 D
1
CT88
CT89
@
CT91
CT92
1 2 AP2112K-3.3TRG1_SOT23-5
2
2 2 RT111 100K_0402_5%
2
2
1
CT90
1U_0402_10V6K
2
+TBTA_Vbus_1
UT8
place near UT7
1
VCC
1U_0603_25V6K
DT3 1
1 2+5V_TBTA_VBUS_D 3
VOUT
CT94
2
1N4148WS-7-F_SOD323-2 GND
AP2204R-5.0TRG1_SOT89-3 2
1U_0402_10V6K
1
CT93
C C
B B
A A
Title
[Type C]PD Power
5 4 3 2 1
5 4 3 2 1
For NON AR Config
Vinafix.com
D D
CT630~633 use SD043000080 (0 ohm) for CSLP3 build
+TBTA_VBUS +TBTA_VBUS +TBTA_VBUS
JUSBC1
A1 B12
GND_A1 GND_B12
1 2 USB3_DP2_1_MTX_C_DRX_P5 A2 B11 USB3_DP2_1_MRX_C_DTX_P5 2 1
<28> USB3_DP2_1_MTX_DRX_P5
CT95 1 2 0.22U_0201_6.3V6K USB3_DP2_1_MTX_C_DRX_N5 A3 TX1+ RX1+ B10 USB3_DP2_1_MRX_C_DTX_N5 0.33U_0201_6.3V6M 2 1 CT632 USB3_DP2_1_MRX_DTX_P5 <28> RF Request
<28> USB3_DP2_1_MTX_DRX_N5
2
CT96 0.22U_0201_6.3V6K TX1- RX1- 0.33U_0201_6.3V6M CT633 USB3_DP2_1_MRX_DTX_N5 <28>
2 1 A4 B9 1 2 +TBTA_VBUS ESD@ DT4
CT99 0.01U_0201_25V6K~D VBUS_A4 VBUS_B9 CT100 0.01U_0201_25V6K~D L30ESD24VC3-2_SOT23-3
TBTA_CC1 A5 B8 DP2_MIC_SBU2
<29> TBTA_CC1 CC1 SBU2 DP2_MIC_SBU2 <28,29>
EMI@ RT120 1 2 0_0402_5% SW_USB20_2_P4_R A6 B7 SW_USB20_1_N4_R EMI@ RT122 1 2 0_0402_5%
<29> SW_USB20_2_P4 SW_USB20_2_N4_R D+_A6 D-_B7 SW_USB20_1_P4_R SW_USB20_1_N4 <29>
EMI@ RT121 1 2 0_0402_5% A7 B6 EMI@ RT123 1 2 0_0402_5%
Bottom
<29> SW_USB20_2_N4 D-_A7 D+_B6 SW_USB20_1_P4 <29>
TOP
DP2_MIC_SBU1 A8 B5 TBTA_CC2
<28,29> DP2_MIC_SBU1 TBTA_CC2 <29>
1
SBU1 CC2
12P_0402_50V8J
RF@ CT189
82P_0402_50V8J
RF@ CT190
1 1
2 1 A9 B4 1 2
C VBUS_A9 VBUS_B4 C
0.01U_0201_25V6K~D CT101 CT102 0.01U_0201_25V6K~D
1 2 USB3_DP2_2_MRX_C_DTX_N5 A10 B3 USB3_DP2_2_MTX_C_DRX_N5 2 1
<28> USB3_DP2_2_MRX_DTX_N5 RX2- TX2- USB3_DP2_2_MTX_DRX_N5 <28>
CT630 1 2 0.33U_0201_6.3V6M USB3_DP2_2_MRX_C_DTX_P5 A11 B2 USB3_DP2_2_MTX_C_DRX_P5 0.22U_0201_6.3V6K 2 1 CT98 2 2
<28> USB3_DP2_2_MRX_DTX_P5 RX2+ TX2+ USB3_DP2_2_MTX_DRX_P5 <28>
CT631 0.33U_0201_6.3V6M 0.22U_0201_6.3V6K CT97
A12 B1
GND_A12 GND_B1
1 4
2 GND1 GND4 5
3 GND2 GND5 6
GND3 GND6
JAE_DX07BD24JJ2
CONN@
USB3_DP2_2_MRX_C_DTX_N5 @ RT416 1 2 220K_0201_5%

USB3_DP2_2_MRX_C_DTX_P5 @ RT417 1 2 220K_0201_5%
USB3_DP2_1_MRX_C_DTX_P5 @ RT418 1 2 220K_0201_5%
USB3_DP2_1_MRX_C_DTX_N5 @ RT419 1 2 220K_0201_5%
ESD@ DT13 ESD@ DT5
USB3_DP2_1_MTX_DRX_P5 2 1 USB3_DP2_1_MRX_DTX_P5 2 1
B AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2 B
ESD@ DT14 ESD@ DT6
USB3_DP2_1_MTX_DRX_N5 2 1 USB3_DP2_1_MRX_DTX_N5 2 1
AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2
ESD@ DT17 ESD@ DT9
USB3_DP2_2_MRX_DTX_N5 2 1 USB3_DP2_2_MTX_DRX_P5 2 1
ESD@ DT18 ESD@ DT10
USB3_DP2_2_MRX_DTX_P5 2 1 USB3_DP2_2_MTX_DRX_N5 2 1
change typeC ESD part from SC40000AR00 to SC40000DF00
DT39 ESD@ DT40 ESD@

A SW_USB20_2_P4_R 1 SW_USB20_2_P4_R SW_USB20_1_N4_R SW_USB20_1_N4_R A
1 10 9 1 1 10 9
SW_USB20_2_N4_R 2 9 8 SW_USB20_2_N4_R SW_USB20_1_P4_R
2 2 9 8
SW_USB20_1_P4_R
2
DP2_MIC_SBU2 4 4 7 DP2_MIC_SBU2 TBTA_CC1 4 4 TBTA_CC1
7 7 7
DP2_MIC_SBU1 5 5 6 6 DP2_MIC_SBU1 TBTA_CC2 5 5 6 6
TBTA_CC2
3 3 3 3
8 8
L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9 Security Classification Compal Secret Data
Title
USB 3.0 CONN TYPE C
5 4 3 2 1
5 4 3 2 1
TOUCH_PANEL_INTR#:
Close lid >> TP_EN = 0 >> Disable touch events
JEDP1 +5V_TSP Open lid >> TP_EN = 1 >> Enable touch events EXC24CQ900U_4P
1 2
2 3
3 4
1
USB20_N9_R
USB20_P9_R
4 3
USB20_N9 <17>
For Breckenridge 14
1 2
4 5 USB20_P9 <17>
5 6 TOUCH_SCREEN_PD# <19> LV27 EMI@
Vinafix.com
6 7
AZC199-02SPR7G_SOT23-3
DMIC0 <36>
3
7 8
@ESD@
8 9
3
9 10 DMIC_CLK0 <36>
10 11 +3.3V_RUN
11 12 USB20_N11_R +3.3V_CAM +PWR_SRC
1
27P_0402_50V8J
RF@
82P_0402_50V8J
RF@
D D
12 13 USB20_P11_R
DV4
1
1
1
13 14
14 15 CAM_MIC_CBL_DET# <16> For BL_PWR_SRC & LCDVDD monitor +LCDVDD
3
15 16 Pin15: LOOP_BACK
CA5
CA6
2
2
16 17
17 18 +BL_PWR_SRC
18 19 2
ESD depop locat i on +3.3V_RUN
19 20
100K_0402_5%
10K_0402_5%
1
20 21 BIA_PWM
10K_0402_5%
EMI@ LV1 1 2
1
+BL_PWR_SRC
2
21 22 DISP_ON
RV623
BLM15PX221SN1D_2P
RV8
RF Request
RV627
22 23 QV18
23 24
1
MMBT3906H_SOT23-3
24 25
2
25 26 +LCDVDD
47K_0402_5%
2
EDP_HPD <21>
1
26 27 TOUCH_SCREEN_DET#
1
27 28 EDP_HPD 2 1 PANEL_PWRGD 1 2
1 2
RV625
28 29 PANEL_MONITOR <37>
@ RV7 100K_0402_5% RV628 0_0402_5%
0.1U_0402_25V6
LCD_TST <37> If touch panel, GPIO Low-> Touch Mic. EQ ; DV11
2200P_0402_50V7K
29 30
200K_0402_5%
0.1U_0402_25V6
others the GPIO is High -> Non-Touch Mic. RB751S40T1G_SOD523-2
1M_0402_5%
30 31
1
Reserve for EA
CV634
1
+LCDVDD
1
31 32 TOUCH_SCREEN_DET# EQ
2
CV633
1
RV626
CV632
1
1TOUCH_SCREEN_DET#
EDP_AUXN_C <19>
RV624
32 33 CV1 2 0.1U_0402_25V6 C
33 34 EDP_AUXP_C EDP_AUXN <9> BL_PWR_MONITOR
2
CV2 2 1 0.1U_0402_25V6 2
2
34 35 EDP_TXP0_C EDP_AUXP <9> B
2
CV3 2 1 0.1U_0402_25V6
35 36 EDP_TXN0_C EDP_TXP0 <9>
2
41 CV4 2 1 0.1U_0402_25V6 QV19 E
2
EDP_TXN0 <9>
42 G1 36 37 EDP_TXP1_C CV5 2 1 0.1U_0402_25V6 MMBT3904WT1G SC70-3
G2 37 38 EDP_TXN1_C EDP_TXP1 <9>
43 CV6 2 1 0.1U_0402_25V6
EDP_TXN1 <9>
44 G3 38 39
45 G4 39 40
G5 40 LCD_CBL_DET# <21>
ACES_50398-04041-001
CONN@ +3.3V_ALW +3.3V_RUN
1 2 1 2
@ RV1656 0_0402_5% RV632 0_0402_5%
3
CONN@ JIR1
+BL_PWR_SRC +LCDVDD +3.3V_CAM +5V_TSP +3.3V_RUN 1
1 IR_CAM_DET# <20>
2
100P_0402_50V8J
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
RF@ CV11
2 3 2
1 1 1 1 3 4
1
@ CZ1
@ CZ2
@ CA7
@
4 5
10K_0402_5%
CV12
1
6 +LCDVDD
6 +PWR_SRC
7
RV631
2
C 2 2 2 2 QV20 C
GND 8
1
GND MMBT3906H_SOT23-3
ACES_50208-0060N-P01
47K_0402_5%
2
1
Close to JEDP1.17~19 Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10
2 1
RV630
0.1U_0402_25V6
DV12
2200P_0402_50V7K
200K_0402_5%
RB751S40T1G_SOD523-2
1
DV1 DV2
CV636
2
CV635
RV629
1
3 BIA_PWM_PCH 3 C
BIA_PWM_PCH <16> PANEL_BKEN_PCH <16> LCDVDD_MONITOR
2
2
2
BIA_PWM 1 DISP_ON 1 B
BIA_PWM_EC
2
2 2 QV21 E
3
BIA_PWM_EC <37> PANEL_BKEN_EC <37> MMBT3904WT1G SC70-3
1
4.7K_0402_5%
4.7K_0402_5%
1
BAT54CW_SOT323-3 BAT54CW_SOT323-3
RV1
RV2
2
RF Request
+5V_TSP For Touchscreen +5V_TSP
RF Request +5V_ALW +5V_RUN
QV8
47K_0402_5%
2
+LCDVDD +3.3V_CAM +BL_PWR_SRC LP2301ALT1G_SOT23-3
47K_0402_5%
2
@
RV6
+PWR_SRC +3.3V_RUN 1 3
S
RV9
+5V_RUN
12P_0402_50V8J
RF@ CV18
82P_0402_50V8J
RF@ CV19
1 1
100K_0402_5%
1
100P_0402_50V8J
RF@ CZ3
G
1
2
1
1
RV326
2 2
12P_0402_50V8J
RF@ CV20
82P_0402_50V8J
RF@ CV21
12P_0402_50V8J
RF@ CV22
82P_0402_50V8J
RF@ CV23
12P_0402_50V8J
RF@ CV24
82P_0402_50V8J
RF@ CV25
1 1 1 1 1 1 1 2
2
RV1400 0_0402_5%
L2N7002WT1G_SC-70-3
2 2 2 2 2 2
B B
1
D
0.1U_0402_25V6K
RF Request
1
3.3V_TS_EN_R
QV7
RV323 1 2 0_0402_5% 2 @
<37> 3.3V_TS_EN
CV1635
G
0.1U_0402_25V6K
@ RV324 1 2 0_0402_5%
1
<21> PCH_3.3V_TS_EN @ S
2
CV1638
2
WebCAM Backlight POWER +BL_PWR_SRC_P
+BL_PWR_SRC
+PWR_SRC QV1 PJP13

1 2
+3.3V_CAM +3.3V_RUN 6
D
4 5 LCDVDD POWER
S
QZ1 2 PAD-OPEN1x2m +LCDVDD +EDP_VDD

LP2301ALT1G_SOT23-3 1 @ RZ90 +3.3V_ALW
1000P_0402_50V7K
0.1U_0603_50V7K
1 2
G
@ CV16 PJP12 UV24

270K_0402_5%
2
1 3 AO6405_TSOP6 0.01_1206_1%
D
2 1 1 2 1
3
CV13
2
VOUT
RV4
5
CV15
10U_0603_10V6M VIN
Co-lay: PAD-OPEN1x1m 2
G
2
GND
0.01UF_0402_25V7K
Short PJP13;Depop RZ90 @ RZ93 4
1
EN
@
1 2
3.3V_CAM_EN#_R
1
1 2
CV17
<17> 3.3V_CAM_EN# 0.01_1206_1% 3
RZ1380 0_0402_5% BL_PWR_SRC_ON /OC
0.1U_0402_25V6K
Co-lay: G524B1T11U_SOT23-5
1
2
@ QV2 DV3
Short PJP12;Depop RZ93
CZ1200
L2N7002WT1G_SC-70-3
0.01U_0402_50V7K
1 2
2
1 2 1 3 <37> LCD_VCC_TEST_EN EN_LCDPWR

1
D
S
CV14
RV5 47K_0402_5%
3
2 <16> ENVDD_PCH
2
100K_0402_5%
G
EXC24CQ900U_4P
2
RV3
4 3 USB20_P11_R
A <17> USB20_P11 BAT54CW_SOT323-3 A
<37> EN_INVPWR
1 2 USB20_N11_R
1
<17> USB20_N11
LZ1 EMI@
Title
eDP CONN & Touch screen
5 4 3 2 1
5 4 3 2 1
Layout Not i ce : Pl ace bead as

+3.3V_LAN UL1 close UL4 as possible
2 1 TP_LAN_JTAG_TMS CLKREQ_PCIE#4 48 13 LAN_MDIP0 RL71 1 2 2.2_0603_5% LAN_MDIP0_L
<18> CLKREQ_PCIE#4 CLK_REQ_N MDI_PLUS0 LAN_MDIN0 LAN_MDIN0_L
@ RL1 10K_0402_5% 36 14 RL72 1 2 2.2_0603_5%
TP_LAN_JTAG_TCK <19> PLTRST_LAN# PE_RST_N MDI_MINUS0
2 1
@ RL2 10K_0402_5% 44 17 LAN_MDIP1 RL73 1 2 2.2_0603_5% LAN_MDIP1_L
Vinafix.com
CLKREQ_PCIE#4 <18> CLK_PCIE_P4 PE_CLKP MDI_PLUS1 LAN_MDIN1 LAN_MDIN1_L
2 1 45 18 RL74 1 2 2.2_0603_5%
<18> CLK_PCIE_N4
PCIE
1 2 PCIE_PRX_C_DTX_P5 PE_CLKN MDI_MINUS1
MDI
@ RL4 4.7K_0402_5%
<17> PCIE_PRX_DTX_P5 LAN_MDIP2 LAN_MDIP2_L
CL1 0.1U_0402_25V6 38 20 RL75 1 2 2.2_0603_5%
1 2 PCIE_PRX_C_DTX_N5 39 PETp MDI_PLUS2 21 LAN_MDIN2 RL76 1 2 2.2_0603_5% LAN_MDIN2_L
<17> PCIE_PRX_DTX_N5 PETn MDI_MINUS2
CL2 0.1U_0402_25V6
D +3.3V_LAN 1 2 PCIE_PTX_C_DRX_P5 41 23 LAN_MDIP3 RL77 1 2 2.2_0603_5% LAN_MDIP3_L D
<17> PCIE_PTX_DRX_P5 PERp MDI_PLUS3 LAN_MDIN3 LAN_MDIN3_L
CL5 0.1U_0402_25V6 42 24 RL78 1 2 2.2_0603_5%
1 2 PCIE_PTX_C_DRX_N5 PERn MDI_MINUS3
<17> PCIE_PTX_DRX_N5
CL6 0.1U_0402_25V6
2
VCT_LAN_R1
10K_0402_5%
28 6 1 2
<20> SML0_SMBCLK
SMBUS
31 SMB_CLK SVR_EN_N 0_0402_5% RL3
<20> SML0_SMBDATA SMB_DATA +RSVD_VCC3P3_1
1 4.7K_0402_5% 1 2 RL6
RL5 @
RSVD_VCC3P3_1 +3.3V_LAN
2 5
1
1 2 <20,37> LAN_WAKE# LAN_DISABLE#_R 3 LANWAKE_N VDD3P3_IN
<20> PM_LANPHY_ENABLE LAN_DISABLE_N +3.3V_LAN_OUT
RL7 0_0402_5% SMBus Device Address 0xC8 4 1 2 +3.3V_LAN
VDD3P3_4 0_0603_5% RL8
10K_0402_5%
15 1
1
LOM_ACTLED_YEL# VDD3P3_15
@ RL9
0.1U_0201_10V6K
22U_0805_6.3V6M
26 19
LOM_SPD100LED_ORG# LED0 VDD3P3_19 RF Request
CL7
CL28
27 29 Place CL28 close to UL1.5
LOM_SPD10LED_GRN# LED1 VDD3P3_29
LED
25 +0.9V_LAN +3.3V_LAN_OUT
2
LED2 2
47
2
VDD0P9_47 46
@ T88 PAD~D TP_LAN_JTAG_TDI 32 VDD0P9_46 37
@ T89 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37
JTAG
+0.9V_LAN TP_LAN_JTAG_TMS 33 JTAG_TDO 43
TP_LAN_JTAG_TCK JTAG_TMS VDD0P9_43
@RF@ CL29
@RF@ CL30
35
JTAG_TCK
12P_0402_50V8J
82P_0402_50V8J
11 1 1
VDD0P9_11
XTALO_R 1 2 XTALO 9 40
XTAL_OUT VDD0P9_40
22U_0603_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
RL34 0_0402_5% XTALI 10 22
1
XTAL_IN VDD0P9_22 16 2 2
1 1 1 1
1
VDD0P9_16 +0.9V_LAN
CL9
CL10
CL11
CL8
8
YL1 LAN_TEST_EN VDD0P9_8
CL12
RL11 30
25MHZ_20PF_XRCGB25M000F2P18R0 1M_0402_5% TEST_EN
2
2 2 2 2 RES_BIAS 12 7 +REGCTL_PNP10 1 2 +3.3V_LAN
2
3 1 RBIAS CTRL0P9 4.7UH_BRC2012T4R7MD_20% LL1
3 1
0.1U_0201_10V6K
10U_0603_10V6M
49 Idc_min=500mA
1
27P_0402_50V8J
NC NC VSS_EPAD
1K_0402_5%
3.01K_0402_1%
DCR=100mohm 1 @
1
27P_0402_50V8J
CL3
CL4
WGI219LM-SLKJ2-A0_QFN48_6X6~D
1
CL14
4 2
RL12
RL13
Note:
CL13
+1.0V_LAN will work at 0.95V to 1.15V
2
2
470P_0402_50V7K
change to SA000081G1L, S IC WGI219LM QREF A0 QFN 48P PHY
2
0.1U_0201_10V6K
1
CL18
CL19
C C
Place CL3, CL4 and LL1 close to UL1
RJ45 LOM circuit
2
2
+3.3V_LAN:20mils
JLOM1 CONN@
LAN_ACTLED_YEL# 1 2 LAN_ACTLED_YEL_R# 10
RL14 150_0402_5% Yellow LED-
9
Yellow LED+
RJ45_MDIN3 8
8
RJ45_MDIP3 7
7
RJ45_MDIN1 6
6
RJ45_MDIN2 5
5
RJ45_MDIP2 4
4
RJ45_MDIP1 3
3
RJ45_MDIN0 2
2 15
RJ45_MDIP0 1 GND_2
1 14
LED_10_GRN# 1 2 LED_10_GRN_R# 11 GND_1
RL19 150_0402_5% Green LED-
LED_100_ORG# 1 2 LED_100_ORG_R# 13
RL20 150_0402_5% Orange LED-
When LAN & WLAN are exist at the same time, WLAN will disable 12
TL1 Green-Orange LED+
1 24 Z2805
TCT1 MCT1 SANTA_130456-831
+3.3V_LAN LAN_MDIN3_L 2 23 RJ45_MDIN3
TD1+ MX1+
@ CL15 LAN_MDIP3_L 3 22 RJ45_MDIP3
1 2 TD1- MX1-
4 21 Z2807
0.1U_0201_10V6K TCT2 MCT2
B B
5
LAN_MDIN1_L 5 20 RJ45_MDIN1
LOM_SPD100LED_ORG# 1 TD2 MX2+
P
B 4 LAN_MDIP1_L 6 19 RJ45_MDIP1
LOM_SPD10LED_GRN# 2 O LOM_CABLE_DETECT# <37> TD2- MX2-
G
A UL2 7 18 Z2806
TC7SH08FU_SSOP5~D TCT3 MCT3
3
LAN_MDIN2_L 8 17 RJ45_MDIN2
TD3+ MX3+
LAN_MDIP2_L 9 16 RJ45_MDIP2
TD3- MX3-
10 15 Z2808
QL1A TCT4 MCT4
DMN65D8LDW-7_SOT363-6 LAN_MDIN0_L 11 14 RJ45_MDIN0
LOM_ACTLED_YEL# 1 6 LAN_ACTLED_YEL# TD4+ MX4+
LAN_MDIP0_L RJ45_MDIP0
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
12 13
TD4- MX4-
1
+3.3V_LAN
2
CL16
CL17
CL20
CL21
350UH_IH-160
LED_MASK#
2
LED_MASK# <37,45>
1
RL29
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
1M_0402_5%
QL1B
2
LOM_SPD100LED_ORG#
4 3 LED_100_ORG#
+3.3V_LAN
5
1
LED_MASK#
RL30
1M_0402_5%
RL15 2
RL16 2
RL17 2
RL18 2
QL2A
2
LOM_SPD10LED_GRN# 1 6 LED_10_GRN#
GND 1 2 +GND_CHASSIS
EMI@ CL22 10P_1808_3KV8J
CHASSIS use 40mil trace if necessary
2
LED_MASK#
For WLAN can't recognize during enable
A Unobtrusive mode(BITS152312) A
QL2B
4 3
5

Title
LAN Clarkvillie & RJ45
5 4 3 2 1
5 4 3 2 1
For PCIE Interface
Vinafix.com
D D
+3.3V_RUN +3.3V_MMI_IN
PJP14
1 2
+3.3V_MMI_AUX +3.3V_MMI_IN
PAD-OPEN1x2m
+3.3V_MMI_IN +3.3V_MMI_AUX
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0402_6.3V6M
1 2
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/of f 3V3AUX)
1 1 1 1
CR4
0_0603_5% R274 @
CR3
CR1
CR2
2 2 2 2
+3.3V_MMI_AUX
2 1 MEDIACARD_IRQ# 7/18 Vender suggest.

RR19 10K_0402_5%
27
11
UR1
3V3aux
3V3_IN
1 12
<19,35,39,40> PCH_PLTRST#_AND PERST# CARD_3V3 +DV33_18 +3.3V_RUN_CARD
2 18 1 2
<18> CLKREQ_PCIE#5 CLK_REQ# DV33_18 CR22 1U_0402_6.3V6K
5
<18> CLK_PCIE_P5 REFCLKP SD_1_DAT1 SD_1_DAT1_R
6 15 RR9 1 2 0_0402_5%
RF Request <18> CLK_PCIE_N5 REFCLKN SP1 16 SD_1_DAT0 RR10 1 2 0_0402_5% SD_1_DAT0_R
+3.3V_MMI_AUX +3.3V_MMI_IN CR11 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P6 3 RTS5242 SP2 17 SD_1_CLK EMI@ RR5 1 2 0_0402_5% SD_1_CLK_R
<17> PCIE_PTX_DRX_P6 PCIE_PTX_C_DRX_N6 HSIP SP3 SD_1_CMD SD_1_CMD_R
@EMI@ CR21
CR12 1 2 0.1U_0402_25V6 4 19 RR6 1 2 0_0402_5%
<17> PCIE_PTX_DRX_N6 PCIE_PRX_C_DTX_P6 HSIN SP4 SD_1_DAT3 SD_1_DAT3_R
5P_0402_50V8C
CR13 1 2 0.1U_0402_25V6 7 20 RR7 1 2 0_0402_5%
<17> PCIE_PRX_DTX_P6 CR14 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_N6 8 HSOP SP5 21 SD_1_DAT2 RR8 1 2 0_0402_5% SD_1_DAT2_R
1
<17> PCIE_PRX_DTX_N6 HSON SP6 29 SDWP
SP7
32
2
<21> MEDIACARD_IRQ# WAKE#
@RF@ CR27
@RF@ CR28
@RF@ CR25
@RF@ CR26
31
SD_1_CD# MS_INS#
12P_0402_50V8J
82P_0402_50V8J
12P_0402_50V8J
82P_0402_50V8J
1 1 1 1 30
C +1.2V_LDO SD_CD# C
7/18 Vender suggest
CR13 close to UR2.10 22 SD_1_P1 EMI depop locat i on
SD_LN1_P 23 SD_1_N1
2 2 2 2
CR9 CR10 close to UR2.14 SD_LN1_M
10
14 AV12 26 SD_1_P0
DV12S SD_LN0_P 25 SD_1_N0
SD_LN0_M
4.7U_0603_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
13
+1.8V_RUN_CARD SD_VDD2
1 1 24 +SDREG2 CR15 1 2
E-PAD
1
SDREG2
CR5
+RREF 9 28 1U_0402_6.3V6K
CR6
CR7
RREF GPIO SD_GPIO 2 1 +3.3V_MMI_AUX
10K_0402_5% RR3
2
2 2 RTS5242-GR_QFN32_4X4
33
1
6.2K_0402_1%
RR4
2
B B
QR1
L2N7002WT1G_SC-70-3
HOST_SD_W P# SDW P_Q SDW P STATUS
SDWP 1 3 SDWP_Q JSD1 CONN@
S
4
+3.3V_RUN_CARD VDD/VDD1
High High Write Protect(SD LOCK) 14
+1.8V_RUN_CARD SD_1_CMD_R VDD2
2
G
2
High SD_1_CLK_R 5 CMD
Low Low Write Enable CLK
<16> HOST_SD_WP# SD_1_CD# 18
SDWP_Q 19 CARD DETECT
High High Write Protect(SD& FW LOCK) WRITE PROTEC
Low SD_1_DAT0_R 7
SD_1_DAT1_R 8 DAT0/RCLK+
Low High Write Protect(FW LOCK) SD_1_DAT2_R 9 DAT1/RCLK-
+3.3V_RUN_CARD +1.8V_RUN_CARD SD_1_DAT3_R 1 DAT2
SD_1_P0 11 CD/DAT3
SD_1_N0 12 D0+
SD_1_P1 16 DO-
SD_1_N1 15 D1+ 20
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
D1- GND1 21
2 2
2
3 GND2 22
CR17
CR19
CR20
6 VSS1 GND3 23
CR18
10 VSS2 GND4 24
1
1 1 13 VSS3 GND5 25
17 VSS4 GND6 26
VSS5 GND7
T-SOL_156-2000302608_NR
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14

LINK SP070011U00 DONE
A A
Title
Card Reader
5 4 3 2 1
5 4 3 2 1
+3.3V_WWAN
NGFF slot B Key B

2 1 WWAN_PWR_EN
RZ43 47K_0402_5% +3.3V_WWAN
100P_0402_50V8J
RF@ CZ198
JNGFF2 CONN@
1 2
<37> NGFF_CONFIG_3
1
3 CONFIG_3 3.3V_2 4
GND_3 3.3V_4 WWAN_PWR_EN
5 6
NGFF slot E Key E
Vinafix.com
USB20_P8_R 7 GND_5 FUL_CARD_PWR_OFF# 8 WWAN_RADIO_DIS#_R +3.3V_ALW
2
USB20_N8_R 9 USB_D_P W_DISABLE1# 10 SLOT2_SATA_LED# 1 2
USB_D_N LED1# SATALED# <16,40,45>
11 @ RN101 0_0402_5%
100K_0402_5%
@
GND_11
RZ380
1
+3.3V_WLAN
D D
JNGFF1
20 1 2
21 I2S_CLK 22 USB20_P14_R GND_1 3.3VAUX_2
<37> NGFF_CONFIG_0 3 4
23 CONFIG_0 I2S_RX 24 USB20_N14_R USB_D+ 3.3VAUX_4
5 6
2
<37> WWAN_WAKE# WOWWAN# I2S_TX HW_GPS_DISABLE#_R USB_D- LED1#
2 1 25 26 7 8
@RF@ RZ326 0_0402_5% 27 DPR W_DISABLE2# 28 CNV_PRX_DTX_N1 GND_7 PCM_CLK CNV_RF_RST#_R
9 10
PCIE_PRX_L_DTX_N18 29 GND_27 I2S_WA 30 UIM_RESET <16> CNV_PRX_DTX_N1 CNV_PRX_DTX_P1 SDIO_CLK PCM_SYNC
11 12
PCIE_PRX_L_DTX_P18 31 USB3.0_TX_N UIM_RESET 32 UIM_CLK <16> CNV_PRX_DTX_P1 CNV_DET# SDIO_CMD PCM_OUT CLKREQ_CNV_R
<37> CNV_DET#
13 14
33 USB3.0_TX_P UIM_CLK 34 UIM_DATA CNV_PRX_DTX_N0 SDIO_DAT0 PCM_IN
15 16
0_0402_5%
RZ7
PCIE_PTX_L_DRX_N18 PCIE_PTX_C_DRX_N18 GND_33 UIM_DATA <16> CNV_PRX_DTX_N0
1
RZ1 1 2 0_0402_5% 35 36 JNGFF1.pin13 : CNV_PRX_DTX_P0 17 SDIO_DAT1 LED2# 18
PCIE_PTX_L_DRX_P18 PCIE_PTX_C_DRX_P18 USB3.0_RX_N UIM_PWR +SIM_PWR <16> CNV_PRX_DTX_P0
RZ2 1 2 0_0402_5% 37 38 CNVi => GND 19 SDIO_DAT2 GND_18 20
USB3.0_RX_P N/C_38 m3042_DEVSLP <20> other => floating CLK_CNV_PRX_DTX_N SDIO_DAT3 UART_WAKE CNV_BRI_PRX_DTX_R
39 40 21 22 RZ1381 2 1 22_0402_5%
41 GND_39 GNSS_SCL 42 <16> CLK_CNV_PRX_DTX_N CLK_CNV_PRX_DTX_P SDIO_WAKE UART_TX CNV_BRI_PRX_DTX <16>
reserved CKT 23
<16> PCIE_PRX_DTX_P17 43 PET_N0 GNSS_SDA 44 <16> CLK_CNV_PRX_DTX_P SDIO_RST
<16> PCIE_PRX_DTX_N17 PET_P0 GNSS_IRQ
2
45 46 32 CNV_RGI_PTX_DRX_R RZ1382 2 1 22_0402_5%
CZ10 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_N17 47 GND_45 SYSCLK 48 UART_RX CNV_RGI_PRX_DTX_R CNV_RGI_PTX_DRX <16>
<16> PCIE_PTX_DRX_N17 9/24: Reserve for embedded locat i on , r ef er I nt el P DG 0. 9 33 34 RZ1383 2 1 22_0402_5%
CZ11 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P17 49 PER_N0 TX_BLANKING 50 PCH_PLTRST#_AND
CZ12 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P7 35 GND_33 UART_RTS 36 CNV_BRI_PTX_DRX_R RZ1384 2 1 22_0402_5% CNV_RGI_PRX_DTX <16>
<16> PCIE_PTX_DRX_P17 PER_P0 PERST# <17> PCIE_PTX_DRX_P7 PCIE_PTX_C_DRX_N7 PET_RX_P0 UART_CTS CNV_BRI_PTX_DRX <16>
51 52 CZ13 1 2 0.1U_0402_25V6 37 38
GND_51 CLKREQ# PCIE_WAKE# CLKREQ_PCIE#0 <18> <17> PCIE_PTX_DRX_N7 PET_RX_N0 CLink_RST PCH_CL_RST1# <16>
53 54 39 40
<18> CLK_PCIE_N0 REFCLKN PEWAKE# GND_39 CLink_DATA PCH_CL_DATA1 <16>
55 56 41 42
<18> CLK_PCIE_P0
57 REFCLKP REF_RFFE2_SCLK 58 @ RZ132 2
WWAN_COEX3
1 0_0402_5%
HOST_DEBUG_TX <37,38>
WLAN <17> PCIE_PRX_DTX_P7 43 PER_TX_P0 CLink_CLK 44 WLAN_COEX3 PCH_CL_CLK1 <16>
59 GND_57 REF_RFFE2_SDATA 60 @RF@ RZ128 1 2 0_0201_5% WLAN_COEX3 <17> PCIE_PRX_DTX_N7 45 PER_TX_N0 COEX3 46 WLAN_COEX2
61 ANTCTL0 COEX3 62 WWAN_COEX2 @RF@ RZ129 1 2 0_0201_5% WLAN_COEX2 GND_45 COEX2 WLAN_COEX1
47 48
63 ANTCTL1 COEX2 64 WWAN_COEX1 @RF@ RZ130 1 2 0_0201_5% WLAN_COEX1 <18> CLK_PCIE_P1 REFCLK_P0 COEX1 WIGIG_32KHZ
49 50 0_0402_5% 2 1 RZ56
65 ANTCTL2 COEX1 66 SIM_DET <18> CLK_PCIE_N1 REFCLK_N0 SUSCLK(32KHz) PCH_PLTRST#_AND SUSCLK <20,40>
51 52
67 N/C_65 SIM_DETECT 68 GND_51 PERST0# BT_RADIO_DIS#_R PCH_PLTRST#_AND <19,34,39,40>
PAD~D @ T225 53 54
69 RESET# N/C_68 70 @RF@ RZ373 1 2 0_0201_5% CNV_COEX1 <18> CLKREQ_PCIE#1 PCIE_WAKE# CLKREQ0# W_DISABLE2# WLAN_WIGIG60GHZ_DIS#_R
<37> NGFF_CONFIG_1 CNV_COEX1 <16> 55 56
71 CONFIG_1 3.3V_70 72 @RF@ RZ372 1 2 0_0201_5% CNV_COEX2 <38,40> PCIE_WAKE# PEWAKE0# W_DISABLE1# ISH_UART0_RXD_R @ RZ78 2
CNV_COEX2 <16> 57 58 1 0_0402_5%
73 GND_71 3.3V_72 74 @RF@ RZ374 1 2 0_0201_5% CNV_COEX3 CNV_PTX_DRX_N1 GND_57 I2C_DAT ISH_UART0_TXD_R @ RZ79 2 0_0402_5% ISH_UART0_RXD <21>
CNV_COEX3 <16> 59 60 1
75 GND_73 3.3V_74 <16> CNV_PTX_DRX_N1 CNV_PTX_DRX_P1 RSVD/PCIE_RX_P1 I2C_CLK ISH_UART0_CTS#_R @ RZ80 2 ISH_UART0_TXD <21>
<37> NGFF_CONFIG_2 61 62 1 0_0402_5%
CONFIG_2 <16> CNV_PTX_DRX_P1 RSVD/PCIE_RX_N1 I2C_IRQ ISH_UART0_RTS#_R @ RZ81 2 ISH_UART0_CTS# <21>
63 64 1 0_0402_5%
CNV_PTX_DRX_N0 GND_63 RSVD_64 ISH_UART0_RTS# <21>
65 66
77 76 <16> CNV_PTX_DRX_N0 CNV_PTX_DRX_P0 RSVD/PCIE_TX_P1 RSVD_66
67 68 0_0402_5% 2 1 RZ371
GND1 GND2 <16> CNV_PTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68 REFCLK_CNV <18>
69 70
CONCR_213BAAA42FA CLK_CNV_PTX_DRX_N 71 GND_69 RSVD_70 72
<16> CLK_CNV_PTX_DRX_N CLK_CNV_PTX_DRX_P RSVD_71 3.3VAUX_72
73 74
<16> CLK_CNV_PTX_DRX_P RSVD_73 3.3VAUX_74 9/24: Reserve for embedded locat i on , r ef er I nt el P DG 0. 9
75
GND_75 76
77 GND1
1 2 WWAN_RADIO_DIS#_R GND2
<37> WWAN_RADIO_DIS#
LCN_DAN05-67406-0102
C
+3.3V_WWAN
RF Request DZ5 CONN@ C
+3.3V_WWAN
1 2 HW_GPS_DISABLE#_R
<37> GPS_DISABLE#
100P_0402_50V8J
100P_0402_50V8J
47P_0402_50V8J
100P_0402_50V8J
2200P_0402_50V7K
DZ6
RF@
@RF@ CZ4
@RF@ CZ5
.047U_0402_16V7K
.047U_0402_16V7K
33P_0402_50V8J
22U_0603_6.3V6M
33P_0402_50V8J
RF@ CZ24
100U_B2_6.3VM_R35M
RF@ CZ26
1 RB751S40T1G_SOD523-2
RF@ CZ25
1
1
+
1 2
1
CZ23
@RF@ RI27 0_0402_5%

CZ17
CZ18
CZ19
CZ20
CZ21
2
2
2
2
LI16 RF@ @ RZ3 CNV_RF_RST#_R

PCIE_PRX_SW_DTX_N18 1 2 PCIE_PRX_L_DTX_N18 1 2 0_0201_5%
<20,35> CNV_RF_RST#
@ RZ4 1 2 0_0201_5% CLKREQ_CNV_R
<20,35> CLKREQ_CNV
PCIE_PRX_SW_DTX_P18 4 3 PCIE_PRX_L_DTX_P18
HCM1012GH900BP_4P
1 2
@RF@ RI28 0_0402_5% +1.8V_PRIM_PCH
+3.3V_WLAN
100K_0402_5%
1 2
RZ378
1
@RF@ RI29 0_0402_5%
STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type m3042_PCIE#_SATA LI17 RF@ +3.3V_ALW
PCIE_PTX_SW_DRX_N18 1 2 PCIE_PTX_L_DRX_N18
0.01UF_0402_25V7K
0.1U_0201_10V6K
10U_0603_10V6M
0.01UF_0402_25V7K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
100K_0402_5%
CNV_RF_RST#_R
2
0 GND GND GND GND SSD-SATA High
RZ377
PCIE_PTX_SW_DRX_P18 PCIE_PTX_L_DRX_P18
1
4 3 1 1 1
1
3
CZ28
CZ30
CZ27
CZ29
CZ31
CZ32
1 GND HIGH GND GND SSD-PCIE(2 lane) Low HCM1012GH900BP_4P
QZ17B
2
1 2 2 2 2
2
8 HIGH GND GND GND W WAN Low @RF@ RI30 0_0402_5% 5
<37> CNV_RF_RST
4
14 HIGH GND HIGH HIGH HCA-PCIE(1 lane) Low
6
RF Request
B 15 HIGH HIGH HIGH HIGH NA Low 1 2 Place near JNGFF1.72/JNGFF1.74 Place near JNGFF1.2/JNGFF1.4 B
2
@RF@ RI47 0_0402_5% <20,35> CNV_RF_RST#
75K PD at PCH side
1
QZ17A
SIM Card Push-Push <17> USB20_P8

1
LI8 RF@
2 USB20_P8_R
+1.8V_PRIM_PCH
+3.3V_WLAN
RF Request
+SIM_PWR USB20_N8_R
4 3
<17> USB20_N8
1
10K_0402_5%
JSIM1 CONN@
RZ376
MCM1012B900F06BP_4P
4.7U_0402_6.3V6M
1 5
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
UIM_RESET VCC GND
@RF@ CZ9
2 6 +3.3V_ALW
RF@ CZ33
RF@ CZ34
RF@ CZ35
RF@ CZ36
@RF@ CZ6
@RF@ CZ7
@RF@ CZ8
100P_0402_50V8J~D
1
UIM_CLK 3 RST VPP 7 UIM_DATA 1 2

CLK I/O @RF@ RI48 0_0402_5% 1
CZ37
100K_0402_5%
2
4 8
1
CLKREQ_CNV_R
RFU1 RFU2
RZ381
1
2
9 SIM_DET
DTSW
2
2
3
10
11 GND 14
+SIM_PWR QZ18B
12 GND GND 15
2
GND GND UIM_CLK DMN65D8LDW-7_SOT363-6
13 16 5
GND GND
@RF@ RZ335
47P_0402_50V8J
T
-
S
O
L
_
5
-
9
9
1
5
0
3
0
0
4
0
0
0
-
6
L
I
N
K
D
O
N
E
1
15K_0402_5%
@RF@ CZ38
4
T-SOL_5-991503004000-6
6
1
RF Request
2
2
<20,35> CLKREQ_CNV 1 2
UIM_DATA
75K PD at PCH side @RF@ RI49 0_0402_5%
1
@RF@ RZ334
+3.3V_WWAN QZ18A
1
33P_0402_50V8J
51_0402_5%
@RF@ CZ39
UZ29
USB3_PRX_DTX_P2 19 1
1
<20> USB3_PRX_DTX_P2 USB3_PRX_DTX_N2 B0+ VDD

18 6
<20> USB3_PRX_DTX_N2 B0- VDD
2 0.1U_0402_10V7K USB3_PTX_C_DRX_P2
.1U_0402_16V7K
.1U_0402_16V7K
CZ150 1 17 10
2
<20> USB3_PTX_DRX_P2 B1+ VDD

CZ151 1 2 0.1U_0402_10V7K USB3_PTX_C_DRX_N2 16 LI9 RF@
2
<20> USB3_PTX_DRX_N2 B1- 1 1 USB20_P14_R

4 3
PCIE_PRX_DTX_P18 PCIE_PRX_SW_DTX_P18 <17> USB20_P14
CZ154
CZ155
15 3
<16> PCIE_PRX_DTX_P18 PCIE_PRX_DTX_N18 14 C0+ A0+ 4 PCIE_PRX_SW_DTX_N18
<16> PCIE_PRX_DTX_N18 C0- A0- WLAN_WIGIG60GHZ_DIS#_R USB20_N14_R
A
CZ152 1 2 0.22U_0402_10V6K PCIE_PTX_C_SW_DRX_P18 13 7 PCIE_PTX_SW_DRX_P18 2 2
<37> WLAN_WIGIG60GHZ_DIS#
1 2
<17> USB20_N14
1 2
A
<16> PCIE_PTX_DRX_P18 C1+ A1+
CZ153 1 2 0.22U_0402_10V6K PCIE_PTX_C_SW_DRX_N18 12 8 PCIE_PTX_SW_DRX_N18
<16> PCIE_PTX_DRX_N18 C1- A1- DZ1 MCM1012B900F06BP_4P
NGFF_CONFIG_1 9 5 RB751S40T1G_SOD523-2
SEL GND UIM_RESET +SIM_PWR
11
2 GND 20 BT_RADIO_DIS#_R
1 2
PD GND <37> BT_RADIO_DIS# 1 2
33P_0402_50V8J
1
@RF@ RI50 0_0402_5%

@RF@ CZ40
21 DZ2
PGND
0.1U_0402_25V6
RF@ CZ41
1
RZ360 PI3PCIE3212ZBEX_TQFN20_2P5X4P5 1
10K_0402_5%
Function SEL OEn DELL CONFIDENTIAL/PROPRIETARY
2
TI SA00009A100
2
B to A L L S IC HD3SS3212RKSR VQFN 20P MUX/DEMUX SW
2nd SA00006EJ00
Title
C to A H L Issued Date 2016/01/01 Deciphered Date 2017/01/01
NGFF Card
All ports Hi-Z, Size Document Number Rev
IC power down X H RF Request AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.5
5 4 3 2 1
5 4 3 2 1
SPKR_R
100P_0402_50V8J
10K_0402_5%
1
1
BEEP_R
@ CA72
@ RA51
+5V_RUN_AUDIO
100P_0402_50V8J
10K_0402_5%
LA13
+5V_RUN_PVDD_Lplace close to pin41 place close to pin46
1
@ CA62
@ RA45
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.) 1 2
HCB2012VF-601T20_2P
Internal Speakers Header
2
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
1 1 1 1 600 Ohm/2A 1 1
2
CA45
CA47
CA60
CA46
CA48
CA59
40 mils trace keep 20 mil spacing CONN@
2
JSPK1
INT_SPK_L+ EMI@ LA6 1 2 BLM15PD800SN1D_2P INT_SPKR_L+ 1 2 2 2 2 2 2
Vinafix.com
INT_SPK_L- EMI@ LA7 1 2 BLM15PD800SN1D_2P INT_SPKR_L- 2 1
INT_SPK_R+ EMI@ LA8 1 2 BLM15PD800SN1D_2P INT_SPKR_R+ 3 2
INT_SPK_R- EMI@ LA9 1 2 BLM15PD800SN1D_2P INT_SPKR_R- 4 3
5 4 +3.3V_RUN_AUDIO
G1
L03ESDL5V0CC3-2_SOT23-3
6
3
D G2 +5V_RUN_AUDIO D
+3.3V_RUN_AUDIO_IO
@ESD@
@ESD@
ACES_50278-00401-001 2 1 LA5
LA12 BLM15PX600SN1D_2P +VDDA_AVDD1 1 2
place close to pin26
@EMI@ CA22
@EMI@ CA23
@EMI@ CA19
@EMI@ CA24
0.1U_0201_10V6K
10U_0603_10V6M
BLM15PX600SN1D_2P
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
10U_0603_10V6M
0.1U_0201_10V6K
1 RF Request
1
1
CA55
CA56
2 1 1
1
+5V_RUN_AUDIO
DA6
DA7
CA8
LA14 BLM15PX600SN1D_2P
CA9
2
2
2
0.1U_0201_10V6K
10U_0603_10V6M
1
2
2
1
1
CA10
CA61
place close to pin9
+1.8V_RUN
2
2 +3.3V_RUN_AUDIO_DVDD
+1.8V_RUN_AUDIO
12P_0402_50V8J
RF@ CA63
68P_0402_50V8J
RF@ CA64
place close to pin40 1 2 1 1
Close to UA1 RA3 0_0603_5%
10U_0603_10V6M
0.1U_0201_10V6K
place close to pin1 1
1
2 2
CA58
CA57
2
2
41
46
26
40
36
1
9
UA1
Close to UA1 pin6
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
CPVDD
HDA_BIT_CLK_R DMIC_CLK0 11
I2C_SDA AUD_HP_OUT_L
@EMI@ RA17
12 31 +LINE1-VREFO-L RA57 1 2 4.7K_0402_5%

I2C_SCL LINE1-VREFO-L AUD_HP_OUT_R
100P_0402_50V8J~D
RF@ CA54
30 +LINE1-VREFO-R RA58 1 2 4.7K_0402_5% AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

1
LINE1-VREFO-R
33_0402_5%
10 29 +MIC2-VREFO
<20> HDA_SYNC_R HDA_BIT_CLK_R SYNC MIC2-VREFO
6 28 1 2
<20> HDA_BIT_CLK_R HDA_SDOUT_R 5 BIT-CLK VREF 35 CA35 2.2U_0402_6.3V6M
RF Request
Place RA9 close to codec HDA_SDIN0_R
2
<20> HDA_SDOUT_R SDATA-OUT CBN +1.8V_RUN_AUDIO +1.8V_RUN

1 2 8 37 2 1
<20> HDA_SDIN0 RA9 33_0402_5% SDATA-IN CBP CA29 1U_0603_10V6K
Place CA29 close to Codec
2
100K_0402_5%1 2 RA52 4 20 @ RA53 1 2 0_0402_5% +5V_ALW

EAPD/DC DET 5VSTB
10P_0402_50V8J
@EMI@ CA33
2 RA54 1 2 0_0402_5%
<32> DMIC0 DMIC_CLK0 1 GPIO0/DMIC-DATA12 +RTC_CELL
place close to UA1 pin3 2 DMIC_CLK_CODEC 3 34 1 2 1 2 RING2
1
<32> DMIC_CLK0 EMI@ RA14 22_0402_5% 47 GPIO1/DMIC-CLK CPVEE CA49 1U_0603_10V6K RA5 2.2K_0402_5%
PDB
RF@ CA69
+3.3V_RUN_AUDIO 10K_0402_5% 2 1 RA18 PD# 48 +MIC2-VREFO 1 2 SLEEVE
SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI
33P_0402_50V8J
2 1 SLEEVE/RING2 please keep 40 mils trace width RA6 2.2K_0402_5%
2
12P_0402_50V8J
RF@ CA65
68P_0402_50V8J
RF@ CA66
100K_0402_5% 2 1 RA44 27 1 1 1
C 1U_0603_10V6K LDO1-CAP AUD_PC_BEEP SPKR_R C
2 1 CA31 10U_0603_10V6M 2 1 CA51 39 17 RING2 2 1 1 2
LDO2-CAP MIC2-L/RING2 BEEP_R SPKR <20>
10U_0603_10V6M 2 1 CA52 7 18 SLEEVE CA27 2 1 0.1U_0402_25V6 RA12 1 2 1K_0402_5%
LDO3-CAP MIC2-R/SLEEVE BEEP <37>
10U_0603_10V6M CA53 19 1 2 CA28 0.1U_0402_25V6 RA13 1K_0402_5%
MIC-CAP 24 10U_0603_10V6M CA25 2 2 2
INT_SPK_L+ 42 LINE2-L 23
INT_SPK_L- 43 SPK-L+ LINE2-R 22 LINE1_L 1 2 HP_OUT_L
INT_SPK_R- 44 SPK-L- LINE1-L 21 LINE1_R 10U_0603_10V6M 1 2 CA43 HP_OUT_R AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
INT_SPK_R+ 45 SPK-R- LINE1-R 16 AUD_PC_BEEP
10U_0603_10V6M CA44
SPK-R+ PCBEEP 32 HP_OUT_L 1 2 AUD_HP_OUT_L
AUD_SENSE_A 13 HP-OUT-L 33 HP_OUT_R 16.2_0402_1% 1 2 RA7 AUD_HP_OUT_R
100K_0402_5% 1 2 RA61 AUD_SENSE_B 14 HP/LINE1 JD1 HP-OUT-R 16.2_0402_1% RA8
+3.3V_RUN_AUDIO MIC2/LINE2 JD2
+3.3V_RUN_AUDIO 15 25
SPDIFO/FRONT JD3/GPIO3 AVSS1 38
AVSS2 49
Place closely to Pin 13. THERMAL PAD
100K_0402_1% 200K_0402_1%
1
ALC3246-CG_MQFN48_6X6 RF Request
RA59
+3.3V_RUN_AUDIO
2
AUD_SENSE_A
0.1U_0402_25V6
1
@ CA41
RA60
12P_0402_50V8J
RF@ CA67
68P_0402_50V8J
RF@ CA68
1 1
2
AUD_HP_NB_SENSE
Add for solve
pop noise and
detect issue 2 2
CLASS-D POWER DOWN CONTROL CIRCUIT

Add this Filter to avoid other HP-Out-Right Nokia-MIC
components/chips be influenced
HP-Out-Lef t iPhone-MIC
B B
1 2
RA48 0_0402_5%
680P_0402_50V7K
@ESD@ CA13
@ DA8 1 2 1
<37> NB_MUTE#
RB751S40T1G_SOD523-2 PD#
Global Headset
<20> HDA_RST#_R
1 2 2 Universal Jack
@ RA50 0_0402_5%
HDA_Link is 3.3V,no need level shift circuit
JHP1 CONN@
RE313@one control line if DVDD is 3.3V RING2 ESD@ LA10 1 2 BLM15PX330SN1D_2P RING2_R 3
DE2@two control lines1 AUD_HP_OUT_L EMI@ LA15 1 2 BLM15PX330SN1D_2P AUD_HP_OUT_L1 1
Normal
Open
5
Only BR15U UMA use LA2,LA3,because 6L
AUD_HP_NB_SENSE 6
AUD_HP_OUT_R EMI@ LA16 1 2 BLM15PX330SN1D_2P AUD_HP_OUT_R1 2 7
SLEEVE_R G
SLEEVE ESD@ LA11 1 2 BLM15PX330SN1D_2P 4
PJP17
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN
330P_0402_50V8J
330P_0402_50V8J
680P_0402_50V7K
1 2
680P_0402_50V7K
+5V_RUN +5V_RUN_AUDIO SINGA_2SJ3095-059111F
ESD@
@EMI@ CA2
@EMI@ CA3
ESD@
ESD@ ESD@ ESD@
3
+5V_RUN_AUDIO PAD-OPEN1x2m DA1 DA2 DA3
2.5A
AZ5123-02S.R7G_SOT23-3
AZ5123-02S.R7G_SOT23-3
680P_0402_50V7K
@ESD@ CA12
2 1 1 1 1
Reserve for support D3 cold
1
CA1
CA4
PJP18
@ PJP15 1 2
+3.3V_RUN +3.3V_RUN_AUDIO 1 2 2 2 2
PAD-OPEN1x1m place at AGND and DGND plane
+5V_RUN PAD-OPEN1x1m
500mA
1 2
@ UZ5
2
1
1 14 +5V_RUN_AUDIO_UZ5 1 2 RA35 0_0402_5%
2 VIN1 VOUT1 13 @ CZ125 0.1U_0201_10V6K
VIN1 VOUT1
A 3 12 1 2 1 2 PJP19 A
<16> AUD_PWR_EN ON1 CT1 220P_0402_50V7K RA36 0_0402_5% 1 2
@ CZ126
4 11
+5V_ALW VBIAS GND PAD-OPEN1x1m
5 10 1 2 1 2
ON2 CT2 @ CZ127 1000P_0402_50V7K RA37 0_0402_5%
6 9 @ PJP16
+3.3V_RUN VIN2 VOUT2 +3.3V_RUN_AUDIO_UZ5
7 8 1 2
VIN2 VOUT2 +3.3V_RUN_AUDIO
15
GPAD PAD-OPEN1x1m
EM5209VF_DFN14_3X2 1
@ CZ128
2
0.1U_0201_10V6K
Title
Codec ALC3246
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
GPIO223 GPIO224 GPIO227 GPIO016 GPIO056 GPIO055
eSPI NA NA *PRIM_PW RGD NA NA PCH_RSMRST# UPD1_SMBDAT 1 2
2 1 +RTC_CELL_VBAT LPC SHD_IO0 SHD_IO1 SHD_IO2 SHD_IO3 SHD_CLK SHD_CS# RE302 2.2K_0402_5%
+RTC_CELL UPD1_SMBCLK
RE32 0_0402_5% * For Version B IC 1 2
0.1U_0201_10V6K
1 RE303 2.2K_0402_5%
UPD1_SMBINT#
CE11
GPIO204 GPIO011 GPIO100 GPIO021 GPIO067 1 2
+3.3V_ALW_UE1 eSPI NA NA NA SIO_RCIN# NA RE91 100K_0402_5%
LPC RSMRST# SIO_EXT_SMI# SIO_EXT_SCI# LPCPD# CLKRUN# UPD2_SMBINT# 1 2
2
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
PJP22 RE92 100K_0402_5%
1 2 LOM_CABLE_DETECT# 1 2
+3.3V_ALW 1 1
1
CE13
CE14
CE23
@ RE505 100K_0402_5%
PBAT_CHARGER_SMBDAT
10U_0603_6.3V6M
PAD-OPEN1x1m 1 2
1
RE37 2.2K_0402_5%
2
2 2 PBAT_CHARGER_SMBCLK
CE16
1 2
Vinafix.com RE43 2.2K_0402_5%
2
UE1 SIO_SLP_SUS#_R 1 2
F2 TYPEC_ID
TYPEC_ID <38> NDS3@ RE561 100K_0402_5%
A2 GPIO033/RC_ID0 J10 SYSTEM_ID
+3.3V_ALW_UE1 VBAT GPIO034/RC_ID1/SPI0_CLK BOARD_ID SYSTEM_ID <38> RPE12
J13 BOARD_ID <38>
D GPIO036/RC_ID2/SPI0_MISO UPD2_SMBDAT GPU_SMCLK 1 8 D
B7 E7
VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# UPD2_SMBCLK GPU_SMDAT 2 7
2 1 D7
+3.3V_ALW_UE1 GPIO004/SMB00_CLK/SPI0_MOSI UPD2_SMBCLK 3 6
0.1U_0201_10V6K
0.1U_0201_10V6K
100_0402_1% RE314 K2
VREF_ADC UPD2_SMBDAT 4 5
22U_0603_6.3V6M
0.1U_0201_10V6K
1 1 1 1 G3 RUNPWROK
+3.3V_EC_PLL GPIO057/VCC_PWRGD GPS_DISABLE#
CE19
CE20
@ CE17
F1 H5
VTR_PLL GPIO060/KBRST/48MHZ_OUT GPS_DISABLE# <35> 2.2K_0804_8P4R_5%
CE18
G11
GPIO104/UART0_TX HOST_DEBUG_TX <35,38>
H1 G12
2 2 2 2 VTR_REG GPIO105/UART0_RX ME_FWP <20>
B13 RPE9
GPIO127/A20M/UART0_CTS# UPD1_SMBINT# ME_SUS_PWR_ACK <20> NGFF_CONFIG_1
G8 F10 1 8
M9 VTR1 GPIO225/UART0_RTS# UPD1_SMBINT# <29> NGFF_CONFIG_2 2 7
+VSS_PLL +3.3V_ALW_UE1 VTR2 PCIE_WAKE#_R NGFF_CONFIG_0
close to pin G8/M9 +1.8V_3.3V_ALW_VTR3 N5 N13 3 6
VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12 PCIE_WAKE#_R <38> NGFF_CONFIG_3 4 5
+3.3V_ALW_UE1 PCH_DPWROK_EC GPIO026/TIN1 SIO_SLP_S4# <11,20,21,51,52>
RE536 1 2 0_0402_5% F8 M11
<20> PCH_DPWROK RUN_ON_EC GPIO020 GPIO027/TIN2 SIO_SLP_A# <20,21>
0.1U_0201_10V6K
DS3@ E8 H9 100K_0804_8P4R_5%
RF Request 1
1 2
<38> RUN_ON_EC SIO_EXT_WAKE#_EC M12 GPIO045 GPIO030/TIN3 SIO_SLP_LAN# <20,46>
+3.3V_ALW <21> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120 VGA_IDENTIFY
CE15
RE703 0_0402_5% C2 L9 RPE11

<35> BT_RADIO_DIS# GPIO166 GPIO017/GPTP-IN5 USB_POWERSHARE_VBUS_EN
F9 M10 1 8
2 <48,49> PBAT_PRES# SIO_SLP_SUS#_R GPIO175 GPIO151/ICT4 NGFF_CONFIG_1 <35> USB_PWR_EN2#
1 2 N4 N9 2 7
<20> SIO_SLP_SUS# PANEL_MONITOR GPIO230 GPIO152/GPTP-OUT3 NGFF_CONFIG_0 <35> USB_POWERSHARE_EN#
RE349 43K_0402_1%<32> PANEL_MONITOR M8 3 6
DS3@ K8 GPIO231 C11 USB_PWR_EN1# 4 5
<20> AC_PRESENT GPIO233 GPIO156/LED0 BREATH_LED# <45>
D10
GPIO157/LED1 BAT1_LED# <45>
Close to pin H1 E11 D11 VCCDSW_EN 100K_0804_8P4R_5%
<20> SML1_SMBDATA GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <45> AC_DIS
D8 E1 1 2
0.1U_0402_25V6
<20> SML1_SMBCLK WWAN_WAKE# GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <32>
12P_0402_50V8J
RF@ CE59
68P_0402_50V8J
RF@ CE60
1 1 M13 @ RE83 100K_0402_5%

<35> WWAN_WAKE# K12 GPIO110/PS2_CLK2 E5 GPS_DISABLE# 1 2
@ CE66
<20> SUSACK# WLAN_WIGIG60GHZ_DIS# L13 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_EXPANDER_SMBDAT <39>
B3 RE12 100K_0402_5%
1
<35> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 USH_EXPANDER_SMBCLK <39> WLAN_WIGIG60GHZ_DIS#
K11 M7 1 2
2 2 <7,20> SIO_PWRBTN# VCCST_PWRGD_EC K10 GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 DGPU_PWROK VCCDSW_EN <20>
1 2 M4 @ RE525 1 2 0_0402_5% RE8 100K_0402_5%
<7,38> VCCST_PWRGD RE308 @ 0_0402_5% N11 GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 M3 PBAT_CHARGER_SMBDAT WWAN_WAKE# 1 2
2
<38> LID_CL_SIO# GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <48,49>
1 2 E10 N2 RE38 10K_0402_5%
<46> SLP_WLAN#_GATE <44> CLK_TP_SIO_I2C_DAT GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK <48,49> LED_MASK#
RE552 0_0402_5% C12 N10 NGFF_CONFIG_2 <35> 1 2
<44> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA LED_MASK#
A12 RE21 10K_0402_5%
JTAG_TDI GPIO140/SMB06_CLK/ICT5 GPU_SMDAT LED_MASK# <33,45>
E9 B6 THERMTRIP1# 1 2
<38> JTAG_TDI JTAG_TDO F6 GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# F7 GPU_SMCLK RE301 10K_0402_5%
<38> JTAG_TDO JTAG_CLK C8 GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# B4 UPD1_SMBDAT PCIE_WAKE#_R 1 2
<38> JTAG_CLK JTAG_TMS GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# UPD1_SMBCLK UPD1_SMBDAT <29>
C5 C3 RE35 10K_0402_5%
<38> JTAG_TMS JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_SMBCLK <29> GPU_PWR_LEVEL 1 2
G13
JTAG_RST# J4 I_BATT_R RE64 1 2 300_0402_5% @RE5 10K_0402_5%
T141 @ PAD~D GPIO200/ADC00 I_SYS_R I_BATT <49>
PJP20 E3 J5 RE312 1 2 300_0402_5%
I_SYS <49,55>
2 0_0402_5% <38>
@ RE566 1 TACH_FAN1 HDD_EN_EC GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 DCIN3_EN
1 2 <21,41> HDD_EN D1 J6
+1.8V_PRIM +1.8V_3.3V_ALW_VTR3 LCD_TST GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 PAD~D @ T262
1 RE100 1 2 0_0201_5% M2 G2 RE318 1 2 0_0402_5%
<35> CNV_RF_RST <32> LCD_TST GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 USH_PWR_STATE# TOUCHPAD_INTR# <19,44>
PAD-OPEN1x1m L10 H2
C <38> PWM_FAN1 CNV_DET#_EC GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_POWERSHARE_VBUS_EN USH_PWR_STATE# <39> +3.3V_RUN C
CE22 <35> CNV_DET# @ RE562 1 2 0_0201_5% L11 J2
0.1U_0201_10V6K PCH_RSMRST# M5 GPIO054/PWM1/GPWM1 GPIO205/ADC05 J3 USB_POWERSHARE_EN# USB_POWERSHARE_VBUS_EN <42>
2 @ RE101 1 2 0_0201_5%<44> PCH_RSMRST# GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 USB_PWR_EN1# USB_POWERSHARE_EN# <42> 3.3V_TS_EN 1 2
<21> CNV_DET#_R J8 K3
<48> PS_ID GPIO056/PWM3/SHD_CLK GPIO207/ADC07 USB_PWR_EN1# <43> @RE547 100K_0402_5%
1 CE21 <32> BIA_PWM_EC N1 D3
TBT_RESET_N_EC_R L8 GPIO001/PWM4 GPIO210/ADC08 LOM_CABLE_DETECT# AUX_EN_WOWL <46>
@ PJP21 0.1U_0201_10V6K D2 I_BATT_R
GPIO002/PWM5 GPIO211/ADC09 LOM_CABLE_DETECT# <33> CE3 1 2 2200P_0402_50V7K
+3.3V_ALW
1 2 N6 E2
<48,49,60> HW_ACAVIN_NB GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 USB_PWR_EN2# BC_INT#_ECE1117 <44>
Close to pin N5 J9 G5 I_SYS_R
2 <32> PANEL_BKEN_EC GPIO015/PWM7 GPIO213/ADC11 UPD2_SMBINT# USB_PWR_EN2# <43> CE4 1 2 2200P_0402_50V7K
PAD-OPEN1x1m H11 F5
+3.3V_ALW <36> BEEP D9 GPIO035/PWM8/CTOUT1 GPIO214/ADC12 K4 DCIN1_EN
<20,46> SIO_SLP_WLAN# AC_DIS GPIO133/PWM9 GPIO215/ADC13 DCIN1_EN <60>
<49> AC_DIS
H12 L1
WWAN_RADIO_DIS# BCM5882_ALERT# GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 PCH_PCIE_WAKE# <20,38>
2 1 G10 L3
<39> BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <20,33>
RE10 100K_0402_5% MSCLK H10
BT_RADIO_DIS# <38> MSCLK GPIO170/TFDP_CLK/UART1_TX CV2_ON_R
2 1 MSDATA G9 H8 RE539 1 2 100_0402_5%
<38> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ 3.3V_TS_EN CV2_ON <39>
RE11 100K_0402_5% J7
BC_DAT_ECE1117 GPIO223/SHD_IO0 MASK_SATA_LED# 3.3V_TS_EN <32>
2 1 RE362
A4 L6
<36> NB_MUTE# EN_INVPWR GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 MASK_SATA_LED# <45> USB_POWERSHARE_VBUS_EN
RE365 100K_0402_5% B2 L7 1.8V_1.0V_PWRGD <52,53> 1 2
<32> EN_INVPWR RESET_IN# GPIO023/GPTP-IN1 GPIO227/SHD_IO2 VBUS1_ECOK
2 1 C1 M6 @ RE702 1M_0402_5%
+3.3V_ALW IMVP_VR_ON_EC GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 VBUS1_ECOK <60>
RPE10 N7
8 1 IMVP_VR_ON_EC 100K_0402_5% <38> IMVP_VR_ON_EC K9 GPIO031/GPTP-OUT1 D6
RUN_ON_EC <20,21,38> SIO_SLP_S3# GPIO032/GPTP-OUT0 BGPO0 EC_FPM_EN <39>
7 2 N8 C7 PCH_RSMRST# 1 2
<20,21> SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <49>
6 3 A5
CV2_ON_R RTD3_SELECT_EC VCI_OUT ALWON <50> +PECI_VREF RE342 10K_0402_5%
5 4 F13 D5 2 1 SYS_PWROK
T264 @ PAD~D AC_DISC# GPIO121/PVT_IO0 GPIO163/VCI_IN0# VCI_IN1# POWER_SW_IN# <38> +1.0V_VCCST 1 2
E13 B5 RE59 0_0402_5%
<48,60> AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# VCI_IN2# @ RE56 10K_0402_5%
0.1U_0201_10V6K
100K_0804_8P4R_5% C13 D4 I_SYS_R 1 2
<39> USH_DET# GPU_PWR_LEVEL GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# POA_WAKE#
E12 E4
POA_WAKE# <39> @ RE313 10K_0402_5%
1
TBT_RESET_N_EC_R GPIO126/PVT_IO3 GPIO000/VCI_IN3# RE59 close to UE2 at least 250mils
CE25
1 2 LCD_TST 1 2
@ RE95 100K_0402_5% RTCRST_ON F11
WWAN_RADIO_DIS# F12 GPIO122/BCM0_DAT/PVT_IO1 RE20 100K_0402_5%
C6 EN_INVPWR 1 2
<35> WWAN_RADIO_DIS#
2
BC_DAT_ECE1117 D12 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN <46>
<44> BC_DAT_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT RE55 100K_0402_5%
D13 F3 @ CE54 1 2 10P_0402_50V8J
<44> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT
F4
+3.3V_ALW <35> NGFF_CONFIG_3 GPIO041/SYS_SHDN# +PECI_VREF
@ RE57 2 1 1K_0402_5% B1 J11
+3.3V_ALW2 SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R
T143 @ PAD~D GPIO011 K7 K13 RE60 1 2 33_0402_5%
H_PECI <7,16>
1
VBUS2_ECOK N3 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT J12 m3042_PCIE#_SATA

<48,60> VBUS2_ECOK m3042_PCIE#_SATA <16> +RTC_CELL
GPIO021/LPCPD# GPIO043/SB-TSI_CLK REM_DIODE1_N
100K_0402_5%
K6 A8 CE24 1 2 2200P_0402_50V7K
USH_DET# <20,38> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P REM_DIODE1_N
RE58
1 2 H7 A7
<20> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE1_P REM_DIODE1_N <38>
@ RE526 10K_0402_5% K1 A10 CE26 1 2 2200P_0402_50V7K VCI_IN1# 1 2
BCM5882_ALERT# <38> PCH_PLTRST#_5105 GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE2_N REM_DIODE1_P <38>
1 2 G7 A9 RE507 100K_0402_5%
REM_DIODE2_N <38>
2
RE532 4.7K_0402_5% <20,38> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9 REM_DIODE2_P VCI_IN2# 1 2

<20,38> ESPI_CS# GPIO066/LFRAME#/ESPI_CS# DN3_DP3A REM_DIODE2_P <38>
K5 B8
<20,38> ESPI_IO0 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N RE508 100K_0402_5%
B L4 A11 CE27 1 2 2200P_0402_50V7K POA_WAKE# B
<20,38> ESPI_IO1 GPIO071/LAD1/ESPI_IO1 DN4_DP4A REM_DIODE4_P REM_DIODE4_N 1 2
G6 B10
<20,38> ESPI_IO2 GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP REM_DIODE4_P REM_DIODE4_N <38> RE324 100K_0402_5%
+3.3V_ALW L5 C10
<20,38> ESPI_IO3 ENABLE_DS# GPIO073/LAD3/ESPI_IO3 VIN VSET_5105 REM_DIODE4_P <38>
L2 C9 VSET_5105 <38>
100K_0402_5%
GPIO100 M1 GPIO067/CLKRUN# VSET B11

T144 @ PAD~D I_ADP <49>
2
SYS_PWROK RE548 1 2 0_0402_5% RESET_OUT G4 GPIO100/nEC_SCI VCP H3 THERMTRIP2#
VSS_ANALOG
THERMTRIP2# <38>
RE63
<7,20> SYS_PWROK L12 GPIO106/PWROK GPIO103/THERMTRIP2# B12 THERMTRIP1# +RTC_CELL_PCH +RTC_CELL

<48> DCIN2_EN @ RE551
GPIO107/nSMI THERMTRIP1# PROCHOT#_R1
VSS_ADC
H13 RE288 1 2 100_0402_5% 1 2
VSS_PLL
VR_CAP
MEC_XTAL1 A1 GPIO160/PWM11/PROCHOT# PROCHOT# <7,49,55>
0_0402_5%
MEC_XTAL2_R A3 XTAL1 must to check H_PROCHOT# with PWR team
VSS1
VSS2
VSS3
1
XTAL2
JTAG_RST# MEC5105_WFBGA169_11X11 @ RE94

A6
A13
E6
H4
1+VR_CAP J1
C4
G1
1 2
1U_0402_6.3V6K
75_0402_5% PCH_RTCRST# <20,21>

1
1
D
1U_0402_6.3V6K
+VSS_PLL
+RTC_CELL_PCH +RTC_CELL RTCRST_ON
1
2 @ QE12
1
@SHORT PADS~D
100_0402_1%
QE15 G
1
L2N7002WT1G_SC-70-3
@ JTAG1
@ RE65
1
LP2301ALT1G_SOT23-3 S
CE30
3
@ RE93
1 3
2
S
CE31
100K_0201_5%
2
1U_0402_6.3V6K
10K_0402_5%
2
2
1
G
2
1
RE546
2
CE63
+3.3V_RUN
2
DE2 +3.3V_ALW
2
2 1
2
+3.3V_ALW
10K_0402_5% DMN65D8LDW-7_SOT363-6
RE67
VGA_IDENTIFY 1 2
1
D RE543 RE84 100K_0402_5%
RTCRST_ON_R RTCRST_ON_R1 VGA_IDENTIFY 1 2
QE17 2 1 2 1 2 RTCRST_ON
100K_0402_5%
1
2
RUNPWROK L2N7002WT1G_SC-70-3 G RE565 0_0402_5% @ RE85 100K_0402_5%

MEC_XTAL2_R
0.1U_0402_25V6
For EMI request +1.8V_3.3V_ALW_VTR3 1M_0402_5%
RE68
22P_0402_50V8J
100K_0402_5%
ESPI_CLK_5105
@ CE64
3
1
1
RE541
1
1
QE2B
CE65
RE549
33_0402_5%
1
RE290
@EMI@
32 KHz Clock 100K_0402_5% RUN_ON# 5
2
0_0402_5% <46> RUN_ON#
RE350
1
A A
VGA_ID0
2
Deep Sleep support

4
2
ENABLE_DS# Discrete 0
6
2
YE1
33P_0402_50V8J
QE2A
MEC_XTAL1 MEC_XTAL2
1 2 non Deep Sleep 1 UMA 1
@EMI@
1
1
2
12P_0402_50V8J
12P_0402_50V8J
@ RE550 Deep Sleep 0 <11,38,46,52,54> RUN_ON

CE57
32.768KHZ_9PF_X1A000141000200
1
100K_0402_5%
1
2
CE28
CE29
2
2

Title
EC MEC5105
5 4 3 2 1
5 4 3 2 1
+1.8V_3.3V_ALW_VTR3
+3.3V_ALW For BR UMA
2
UE6
RE340
1 5 10K_0402_5%
NC VCC
2
1
<19> PCH_PLTRST#_EC A 4
3 Y PCH_PLTRST#_5105 <37>
GND
74AUP1G07GW_TSSOP5
+RTC_CELL
PCIE_WAKE# <35,40>
1
100K_0402_5%
RE31
@ CE10
Vinafix.com 1 2
1U_0402_6.3V6K
<37> PCIE_WAKE#_R
RE275
2 1
0_0402_5% 0_0402_5%
1 2
@ RE274
PCH_PCIE_WAKE# <20,37>
2
1 2 Stuff RE275 and no stuff RE274 keep E5 design
<37> POWER_SW_IN# POWER_SW#_MB <21,45>
RE33 1K_0402_5% Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
2.2U_0402_6.3V6M
D D
CE12
2 1
2
0_0402_5% @ RE304
CONN@ +3.3V_RUN
JESPI +3.3V_ALW
1 @ CE53
1 2 +3.3V_ALW 1 2
2
100K_0402_5%
3 UE4 +3.3V_ALW
3 ESPI_IO0 <20,37>
1
RE25
4 ESPI_IO1 <20,37> 0.1U_0402_25V6K
4
5
5 ESPI_IO2 <20,37> 1 5
5 6 IMVP_VR_ON_EC 1 NC VCC
P
6 ESPI_IO3 <20,37> <37> IMVP_VR_ON_EC B IMVP_VR_ON
7 4 2
7 8 20_0402_5% PCH_PLTRST#_EC ESPI_CS# <20,37> SIO_SLP_S3# O A
LPC@ RE375 1 RE26 <20,21,37,38> SIO_SLP_S3#
2 4
2
8 20_0402_5% ESPI_RESET# LID_CL_SIO# A Y VCCST_PWRGD <7,37>
G
11 9 @ RE560 1 2 1 UE3 3
GND 9 ESPI_RESET# <20,37> <37> LID_CL_SIO# LID_CL# <45> GND
.047U_0402_16V7K
12 10 TC7SH08FU_SSOP5~D
ESPI_CLK_5105 <20,37>
3
GND 10 10_0402_5% 74AUP1G07GW_TSSOP5
1
JXT_FP241AH-010GAAM
CE8
RF Request
2
IMVP_VR_ON <55>
+3.3V_ALW 1 2
0_0402_5% @ RE280
68P_0402_50V8J
1
RUN_ON_EC
RF@ CE61
2 1
<37> RUN_ON_EC RUN_ON <11,37,46,52,54>
0_0402_5% @ RE292
2
+3.3V_ALW
@ CE52
1 2
0.1U_0402_25V6K
5
1
P
B 4
2 O
A
G
UE5
TC7SH08FU_SSOP5~D
3
+3.3V_ALW +3.3V_ALW
+3.3V_ALW 15P@
RE300
1
15U@
RE343 RE79 RE300
C C
240K_0402_5% 62K_0402_5% 8.2K_0402_5%
2
<37> TYPEC_ID <37> BOARD_ID <37> SYSTEM_ID 2K_0402_5%
1
CE62 CE40 CE47
4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K
2
RE343 CE62 REV RE79 CE40 REV PANEL SIZE
RE300 CE47
* 240K 4700p Single Port ACE w/o AR 240K 4700p X00
Single Port ACE w/AR
240K 4700p 11"
130K 4700p 130K 4700p X01 130K 4700p 12"
62K 4700p Dual Port ACE w/o AR
* 62K 4700p X02 62K 4700p 13"
33K 4700p Dual Port ACE w/AR 33K 4700p X03
Dual Port ACE (w/AR +w/o AR)
33K 4700p 14"
8.2K 4700p 8.2K 4700p * 8.2K 4700p BR15 H
4.3K 4700p 4.3K 4700p A00 4.3K 4700p 17"
2K 4700p 2K 4700p * 2K 4700p BR15 P
1K 4700p 1K 4700p 1K 4700p
PD_ACE_DET# rise t i mei s meas ur ed fr o m5 %~68 %. BOARD_ID rise t i mei s meas ur ed fr o m5 %~68 %. PANEL_ID rise t i mei s meas ur ed fr o m5 %~68 %.
VSET_5105
VSET_5105 <37>
0.1U_0402_25V6
1
1.58K_0402_1%
1
CE38
RE77
2
+3.3V_ALW
2
1
5
6
7
8
10K_8P4R_5%
10_0402_1%
RE71
RPE7
Rest=1.58K , Tp=96 degree
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
@ RE75
CONN@
4
3
2
1
RE72
RE73
RE74
B JDEG1 B
1 +EC_DEBUG_VCC
1 2 JTAG_TDI Link 50271-0040N-001 DONE
2
2 3 JTAG_TMS JTAG_TDI <37>
JFAN1
3 4 JTAG_CLK JTAG_TMS <37> 1
4 5 JTAG_TDO JTAG_CLK <37> 1 2 PWM_FAN1
RE86
5 6 JTAG_TDO <37> 2 3 TACH_FAN1 PWM_FAN1 <37>
MSCLK 10K_0402_5%
6 7 1 2 +3.3V_RUN 3 4 TACH_FAN1 <37>
MSDATA +5V_RUN
7 8 HOST_DEBUG_TX 4
8 DEBUG_TX
10U_0603_6.3V6M
11 9 5
GND 9 GND1
1
12 10 6 @
GND 10 PWM_FAN1 GND2
1
1 2 1 2 DE1
<21> SBIOS_TX
CE32
JXT_FP241AH-010GAAM @ RE306 RE48 10K_0402_5% ACES_50271-0040N-001 BZV55-B5V6_SOD80C2
0_0402_5% 1 2 TACH_FAN1 CONN@
2
RE51 10K_0402_5%
HOST_DEBUG_TX <35,37>
2
MSDATA <37>
1 2 MSCLK <37>
RE30
0_0402_5%
Thermal diode mapping

5105 Channel Locat i on
Place under CPU
Place CE35 close to the QE3 as possible
DP1/DN1 CPU (QE3)
REM_DIODE1_P <37>
100P_0402_50V8J
DP2/DN2 WiGig (QE5)
1
C
@ CE35
2
DN2a/DP2a DDR (QE7) B
1
E QE3
3
LMBT3904WT1G SC70-3
DP3/DN3 NA REM_DIODE1_N <37>
DP2/DN2 for WiGig on QE5, place QE5 close

DP4/DN4 CPU VR (QE6) to Type-C and CE37 close to QE5
DP4/DN4 for Skin on

CHECK RE69 QE6, place QE6 close to DN2a/DP2a for DDR on QE7, place QE7 close
Vcore VR choke. to DDR and CE46 close to QE7
0.1U_0402_25V6
1 2
+1.0VS_VCCIO +3.3V_ALW THERMTRIP2# <37>
REM_DIODE4_P <37> REM_DIODE2_P <37>
<20,21,37,38> 8.2K_0402_5%
LMBT3904WT1G SC70-3
SIO_SLP_S3#
1
LMBT3904WT1G SC70-3
CE36
100P_0402_50V8J
@ QE11
2
1
100P_0402_50V8J
100P_0402_50V8J
@ CE37
QE7
E C
G
1
@ CE46
C C B
2 2
2
QE4
@CE39
A 1 3 1 2 2 2 B A
2
RE70 2.2K_0402_5% B B E QE5
C
D
3
+1.0V_VCCST E E QE6 LMBT3904WT1G SC70-3
3
L2N7002WT1G_SC-70-3 LMBT3904WT1G SC70-3
REM_DIODE2_N <37>
RE90 1 2 0_0402_5%
<7,14,15,16> H_THERMTRIP# REM_DIODE4_N <37>
Title
MEC5105 SUPPORT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
5 4 3 2 1
5 4 3 2 1
For NUVOTON TPM RF Request RF Request

+3.3V_ALW +3.3V_M_TPM
650@ RZ366
+3.3V_M_TPM
Vinafix.com
+3.3V_M_TPM
@ RZ367 1 2 0_0402_5% +3.3V_M_TPM
750@ RZ365
2
2
1 0_0402_5%
1 0_0402_5%
12P_0402_50V8J
RF@ CZ57
68P_0402_50V8J
RF@ CZ58
12P_0402_50V8J
RF@ CZ59
68P_0402_50V8J
RF@ CZ60
1 2 +3.3V_RUN 1 1 1 1
+3.3V_RUN
+3.3V_ALW RZ89 0_0402_5%
D +UZ12_TPM +UZ12_VHIO D
@ RZ369 1 2 0_0402_5% 2 2 2 2
10U_0402_6.3V6M
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
+3.3V_ALW_PCH
1 1 1 1 1
CZ75
RZ368 1 2 0_0402_5%
CZ50
CZ55
CZ54
CZ53
2 2 2 2 2
1 2 TPM_PIRQ#
RZ69 10K_0402_5% place CZ50, CZ75 as close as UZ12.8 CZ53,CZ55 as close as UZ12.14
CZ54 as close as UZ12.22
+3.3V_ALW
1 2 USH_EXPANDER_SMBCLK
RZ8 4.7K_0402_5%
1 2 USH_EXPANDER_SMBDAT
+3.3V_ALW +3.3V_ALW_UZ12
RZ9 4.7K_0402_5%
+3.3V_RUN PJP391
1 2
1 2 USH_PWR_STATE#
1
PAD-OPEN1x1m RZ10 100K_0402_5%

@ RZ362
10K_0402_5%
UZ12
1
USH CONN
2
1 2 TPM_GPIO0 29 VSB
<11,20,21,54> SIO_SLP_S0# 30 GPIO0/SDA/XOR_OUT 8 +UZ12_TPM
750@RZ112 0_0402_5%
C 1 2 TPM_LPM# 3 GPIO1/SCL VDD 14 +UZ12_VHIO CONN@ C
650@RZ363 0_0402_5% 6 GPIO2/GPX VHIO 22 JUSH1
0.1U_0201_10V6K
10U_0603_10V6M
GPIO3/BADD VHIO 1 1 2 +PWR_SRC_R
+PWR_SRC 1
RZ58 1 2 33_0402_5% PCH_SPI_D1_2_R 24 2 1 1 2 RF@ LZ2 BLM15AX221SN1_2P
<19> PCH_SPI_D1_R1 RZ59 1 2 33_0402_5% PCH_SPI_D0_2_R 21 LAD0/MISO NC 7 3 2
CZ51
CZ52
<19> PCH_SPI_D0_R1 18 LAD1/MOSI NC 10 <37> CV2_ON POA_WAKE#_R 3
RZ364 1 2 100_0402_5% 4
<21> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11 <37> POA_WAKE# 5 4
2 2 <37> EC_FPM_EN
LAD3 NC 25 6 5
EMI@ RZ60 1 2 33_0402_5% PCH_SPI_CLK_2_R 19 NC 26 7 6
<19> PCH_SPI_CLK_R1 PCH_SPI_CS#2_R 20 LCKL/SCLK NC 7
RZ61 1 2 0_0402_5% 31 8
<19> PCH_SPI_CS#2 17 LFRAME#/SCS# NC <17> USB20_N10 9 8
<19> PLTRST_TPM# 27 LRESET#/SPI_RST#/SRESET# 9 <17> USB20_P10 10 9
TPM_GPIO4 13 SERIRQ GND 16 11 10
T283@ PAD~D CLKRUN#/GPIO4/SINT# GND place CZ51,CZ52 as close as UZ12.1 <37> USH_EXPANDER_SMBCLK 11
28 23 12
LPCPD# GND <37> USH_EXPANDER_SMBDAT 12
1
650@
10K_0402_5%
32 13
GND <37> BCM5882_ALERT# 13
RZ62
4 33 14
5 PP PGND 12 15 14
TEST Reserved 16 15
+3.3V_ALW 16
NPCT750JAAYX_QFN32_5X5 17
2
18 17
+5V_ALW 18
19
+3.3V_RUN 19
20
+5V_RUN USH_RST#_R 20
@ RZ114 1 2 0_0402_5% 21
<19,34,35,40> PCH_PLTRST#_AND 22 21
<37> USH_PWR_STATE# 23 22
CONTACTLESS_DET#_R 24 23
2 1
<16> CONTACTLESS_DET# 25 24
DZ8 RB751S40T1G_SOD523-2 USH_DET#_R 25
26
2018/01/04: change to MP sample : SA0000AQ220 RZ87 1 2 0_0402_5%
26
<37> USH_DET# 27
PCH_SPI_CLK_2_R
need to link SA0000AQ200 2
@ DZ7
1
28 GND1
GND2
33_0402_5%
B CVILU_CF5026FD0RK-05-NH B
2
@EMI@
RZ63
Pop Depop Comment

1
0.1U_0402_25V6
VDD - V_RUN Power

NPCT65x RZ89, RZ366, RZ62, RZ363 RZ365, RZ367, RZ112 VHIO - V_SPI Power Close to JUSH1
1
PCH_PLTRST#_AND
@EMI@
CZ56
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW

Option1 (recommended)
.047U_0402_16V7K
ESD@ CZ61
NPCT75x RZ89, RZ365, RZ112 RZ367, RZ366, RZ62, RZ363
2
VDD and VHIO - V_RUN power
100P_0201_25V7K~D
100P_0201_25V7K~D
100P_0201_25V7K~D
100P_0201_25V7K~D
Option2 (for Z1 sample [early sample])
RF@ CZ64
RF@ CZ66
RF@ CZ67
RF@ CZ68
NPCT75x RZ367, RZ366 RZ89, RZ365, RZ62 VDD and VHIO - V_SPI power 1 1 1 1
2
For ESD solution 2 2 2 2
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW

RF Request
RF Request
68P_0402_50V8J
RF@ CZ69
68P_0402_50V8J
RF@ CZ71
68P_0402_50V8J
RF@ CZ72
68P_0402_50V8J
RF@ CZ73
USH_EXPANDER_SMBCLK 1 2 1 1 1 1
RF@ CZ62 100P_0402_50V8J
USH_EXPANDER_SMBDAT 1 2
A 2 2 2 2 A
RF@ CZ63 100P_0402_50V8J
Title
USH & TPM
0.5
Custom
LA-F711P
5 4 3 2 1
5 4 3 2 1
For Breckenridge 15
RF Request
+3.3V_HDD_M2
Vinafix.com +3.3V_HDD_M2
D D
68P_0402_50V8J
@RF@ CN60
0.1U_0201_10V6K
0.1U_0201_10V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1 @ 1
1
CN61
CN62
CN63
CN64
2
2
2 2
Place near HDD CONN

2280 SSD
+3.3V_HDD_M2 NGFF slot C Key M Co-lay:

M2280_DEVSLP Short PJP31;Depop RZ99
1 2
@ RN37 10K_0402_5% if signal is PCIE GEN3/SATA GEN3 maybe change C value @ RZ99
or no need for DG0.9 SATA EXPRESS HDD 1 2 2.8A
+3.3V_HDD_M2 0.01_1206_1% +3.3V_RUN
JNGFF3 CONN@ PJP31

1 2 1 2
3 GND 3.3VAUX 4
5 GND 3.3VAUX 6 PAD-OPEN1x3m
<16> PCIE_PRX_DTX_N9 PERn3 N/C
7 8
<16> PCIE_PRX_DTX_P9 PERp3 N/C NVME_LED#
9 10 1 2
PCIE_PTX_C_DRX_N9 GND DAS/DSS# SATALED# <16,35,45>
CN65 2 1 0.22U_0402_10V6K 11 12 @ RN100 0_0402_5%
C <16> PCIE_PTX_DRX_N9 CN66 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_P9 13 PETn3 3.3VAUX 14 C
<16> PCIE_PTX_DRX_P9 15 PETp3 3.3VAUX 16
17 GND 3.3VAUX 18
<16> PCIE_PRX_DTX_N10 PERn2 3.3VAUX
19 20
<16> PCIE_PRX_DTX_P10 PERp2 N/C
21 22
CN67 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N10 23 GND N/C 24
<16> PCIE_PTX_DRX_N10 PCIE_PTX_C_DRX_P10 PETn2 N/C
<16> PCIE_PTX_DRX_P10 CN68 2 1 0.22U_0402_10V6K 25 26
27 PETp2 N/C 28
29 GND N/C 30
<16> PCIE_PRX_DTX_N11 PERn1 N/C
31 32
<16> PCIE_PRX_DTX_P11 PERp1 N/C
33 34
<16> PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_P11 PETn1 N/C
CN70 2 1 0.22U_0402_10V6K 37 38
<16> PCIE_PTX_DRX_P11 PETp1 DEVSLP M2280_DEVSLP <20>
39 40
41 GND N/C 42
<16> PCIE_PRX_DTX_P12 43 PERn0/SATA B+ N/C 44
<16> PCIE_PRX_DTX_N12 45 PERp0/SATA B- N/C 46
<16> PCIE_PTX_DRX_N12 PCIE_PTX_C_DRX_P12 PETn0/SATA A- N/C
CN72 2 1 0.22U_0402_10V6K 49 50
<16> PCIE_PTX_DRX_P12 PETp0/SATA A+ PERST# PCH_PLTRST#_AND <19,34,35,39>
51 52
GND CLKREQ# PCIE_WAKE# CLKREQ_PCIE#3 <18>
53 54
<18> CLK_PCIE_N3 55 REFCLKn PEWake# 56 PCIE_WAKE# <35,38>
<18> CLK_PCIE_P3 REFCLKp N/C
57 58
GND N/C
67 68 SUSCLK_R 1 2
Lane reversal N/C SUSCLK SUSCLK <20,35>
69 70 RN99 0_0402_5%
<16> M2280_PCIE_SATA# 71 PEDET 3.3VAUX 72
73 GND 3.3VAUX 74
75 GND 3.3VAUX
GND
77 76
B MTG77 MTG76 B
LCN_DAN05-67356-0103
A A
Title
M2 2280 Socket
5 4 3 2 1
5 4 3 2 1
p
i
n
1
6
+3.3V_HDD
p
i
n
1
3
p
i
n
1
8
p
i
n
3
p
i
n
6
+3.3V_HDD
P
e
r
i
c
o
m
N
C
N
C
@
TDet_B# TDet_A# TDeT_EN
1
+3.3V_RUN
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
G
N
D
G G
N N
D D
D R
E E
W X
2 T
D
E
W
1
G
N
D
@ RN10
@ RN12
@ RN14
@ RN16
@ RN18
@ RN20
Vinafix.com
RN6
RN8
T r
I a
1
0.01UF_0402_25V7K
0.1U_0201_10V6K
4.7K_0402_5%
D
E
W
@
1 1
P
a
d
e
2
B_EQ2
RN226
A_EQ2
D SATA Repeater HDD_A_PRE D
CN16
CN17
2
2 2 HDD_UN7_EN
UN7 HDD_B_PRE
DEW2 6 10
DEW1 16 NC VDD 20 HDD_A_EQ
NC VDD
1
D
3 13 HDD_B_EQ2 HDD_B_EQ HDD_DET# 2 QN6
HDD_A_EQ 17 TDet_B# TDet_A# 19 HDD_B_EQ G
A_EQ B_EQ L2N7002WT1G_SC-70-3
HDD_A_PRE 9 8 HDD_B_PRE DEW2 S
3
HDD_UN7_EN 1 2 HDD_UN7_EN_R 7 A_EM B_EM 18 HDD_A_EQ2
EN TDeT_EN +5V_HDD
@RN227 0_0402_5% DEW1
CN12 1 2 0.01UF_0402_25V7K SATA_PTX_C_RD_DRX_P2 1 15 SATA_PTX_RD_DRX_P2
<16> SATA_PTX_DRX_P2 AI+ AO+
CN13 1 2 0.01UF_0402_25V7K SATA_PTX_C_RD_DRX_N2 2 14 SATA_PTX_RD_DRX_N2 HDD_B_EQ2
1
100K_0402_5%
<16> SATA_PTX_DRX_N2 AI- AO-
@ RN1
<16> SATA_PRX_DTX_N2 CN14 1 2 0.01UF_0402_25V7K SATA_PRX_C_RD_DTX_N2 4 12 SATA_PRX_RD_DTX_N2 HDD_A_EQ2
+3.3V_RUN
CN15 1 2 0.01UF_0402_25V7K SATA_PRX_C_RD_DTX_P2 5 BO- BI- 11 SATA_PRX_RD_DTX_P2
<16> SATA_PRX_DTX_P2 BO+ BI+
1
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
7.87K_0402_1%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
2
21
1
100K_0402_5%
GND
@ RN17
@
FFS_INT2_Q
RN7
RN9
RN11
RN13
RN15
RN19
RN21
RN2
3
PI3EQX6741STZDEX_TQFN20_4X4
1
QN1B
HDD_A_EQ HDD_B_EQ HDD_A_EQ2 HDD_B_EQ2 DEW1 DEW2 HDD_A_PRE HDD_B_PRE 5
PIN17 PIN19 PIN18 PIN13 PIN16 PIN6 PIN9 PIN8
4
6
Pericom PI3EQX6741ST PD PD PD PD NC NC PD PD
(RN21) (RN19) (RN7) (RN9)
QN1A
(RN11) (RN13) FFS_INT2 2
+3.3V_RUN
TI SN75LVCP601 PD NC PD PD NC NC PH PH
1
(RN11) (RN21) (RN19) (IPU) (IPU) (RN6) (RN8)
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
C
Parade PS8527C PD PD PD PD NC PD NC NC C
1
(RN21) (RN19) (RN15) (1/2 VDD) (1/2 VDD)
(RN11) (RN13) (1/2 VDD)
Free Fall Sensor
CN1
CN2
CN3
2
2
LGA1
A_EQ B_EQ A_EM B_EM LNG2DM
10 5 INT1/IN2:Push-Pull,active high
9 VDD_IO RES
VDD 12
0 3dB 3dB 0 0dB 0dB 3 INT 1 11 FFS_INT2 HDD_FALL_INT <21>
4 SDO/SA0 INT 2 FFS_INT2 <21>
Main Pericom NC 6dB 6dB NC <7,14,15,20> DDR_XDP_WAN_SMBDAT
1 SDA/SDI/SDO 6
<7,14,15,20> DDR_XDP_WAN_SMBCLK SCL/SPC GND 7
1 9dB 9dB 1 1.5dB 1.5dB 2 GND 8
CS GND
0 7dB 7dB 0 0dB 0dB LNG2DMTR_LGA12_2X2
2nd TI NC 0dB 0dB NC -4dB -4dB

1 14dB 14dB 1 -2dB -2dB
+3.3V_HDD
EQ2 EQ1 A_EQ B_EQ A_EM B_EM
1 2 HDD_DEVSLP
@ RN3 10K_0402_5%
(M = VDD/2)
CONN@
0 M 2.4dB 2.4dB JSATA1
1
0 0 7.4dB 7.4dB SATA_PTX_RD_DRX_P2 CN4 2 1 0.01UF_0402_25V7K SATA_PTX_C_DRX_P2 2 1
B 3rd Parade 14.4dB 14.4dB SATA_PTX_RD_DRX_N2 CN5 2 1 0.01UF_0402_25V7K SATA_PTX_C_DRX_N2 3 2 B
0 1 0 0dB 0dB 4 3
SATA_PRX_RD_DTX_N2 CN6 1 0.01UF_0402_25V7K SATA_PRX_C_DTX_N2 4
M M 12.2dB 12.2dB M -3.5dB -3.5dB SATA_PRX_RD_DTX_P2 CN7
2
2 1 0.01UF_0402_25V7K SATA_PRX_C_DTX_P2
5
6 5
7 6
M 0 9.4dB 9.4dB 1 -6dB -6dB PJP34 8 7
+3.3V_HDD 8
M 1 13.3dB 13.3dB +3.3V_RUN
1 2 9
10 9
11 10
*c
r
er
dr
c
ot
l
oe
rt
sn
i
PAD-OPEN1x2m
1 M 6.2dB 6.2dB <20> HDD_DEVSLP
12 11
u
e
n
s
t
i
g
12
1 0 11.2dB 11.2dB <16> HDD_DET#
13
14 13
+5V_HDD +3.3V_HDD 15 14
1 1 5dB 5dB +5V_HDD
16 15
+5V_RUN +5V_HDD 17 16
PJP33 18 17
Co-lay: FFS_INT2_Q 18
1000P_0402_50V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
Short PJP32;Depop RZ102 2 1 19
20 19
20
1
+3.3V_RUN
CN8
CN9
@ CN10
CN11
21
@ RZ102 PAD-OPEN1x1m 22 G1
1 2 @ RZ108 23 G2
+5V_HDD source
2
1 2 24 G3
0.01_1206_1% G4
1
0.01_1206_1%
@ RN4 @ PJP32
10K_0402_5% @ UZ23
1 2 1.5A+5V_HDD ACES_59003-02006-002
+5V_ALW
PAD-OPEN1x1m
2
1 7
HDD_EN 2 VIN VOUT 8 +5V_HDD_UZ23 1 2
VIN VOUT @ CZ129 0.1U_0201_10V6K
3 6 1 2
Place near HDD CONN
<21,37> HDD_EN ON CT @ CZ130 470P_0402_50V7K
1
@ RN5 4
VBIAS 5
10K_0402_5% GND
A 9 A
GND
2
AOZ1336DI_DFN8_2X2
Title
HDD CONN
5 4 3 2 1
5 4 3 2 1
For PWR SW + Charger combine IC
Vinafix.com +5V_USB_CHG_PWR
JUSB1
D
1 D
DI4 ESD@ CHR_USB20_N1_R VBUS
150U_B2_6.3VM_R35M
2
USB3_PRX_DTX_N1 USB3_PRX_DTX_N1 CHR_USB20_P1_R D-
100U_1206_6.3V6M
0.1U_0201_10V6K
1 1 10 9 3
<20> USB3_PRX_DTX_N1 @ 4 D+
USB3_PRX_DTX_P1 USB3_PRX_DTX_P1 1 1 1 USB3_PRX_DTX_N1 GND
CI17
2 2 9 8 5
<20> USB3_PRX_DTX_P1 USB3_PRX_DTX_P1 SSRX-
CI32
CI14
+ 6 10
SSRX+ GND
2
2 1 USB3_PTX_C_DRX_N1 4 4 7 7 USB3_PTX_C_DRX_N1 7 11
<20> USB3_PTX_DRX_N1 2 2 USB3_PTX_C_DRX_N1 GND GND
ESD@ DI5
CI13 0.1U_0402_25V6 8 12
2
2 1 USB3_PTX_C_DRX_P1 5 5 6 USB3_PTX_C_DRX_P1 2 USB3_PTX_C_DRX_P1 9 SSTX- GND 13
6
<20> USB3_PTX_DRX_P1 SSTX+ GND
CI16 0.1U_0402_25V6
1
3 3 J-L_TNBNRAC70030009
CONN@
1
8
L05ESDL5V0NA-4_SLP2510P8-10-9
RF Request
+5V_USB_CHG_PWR
LI7 EMI@
CHR_USB20_N1 1 2 CHR_USB20_N1_R
CHR_USB20_P1 4 3 CHR_USB20_P1_R
12P_0402_50V8J
RF@ CI43
68P_0402_50V8J
RF@ CI44
1 1
EXC24CQ900U_4P
+5V_ALW
C +5V_USB_CHG_PWR 2 2 C
UI3
1 12
VIN VOUT
2
<17> USB20_N1 DM_OUT
3
<17> USB20_P1 DP_OUT CHR_USB20_P1
10
13 DP_IN 11 CHR_USB20_N1
<17> USB_OC0# FAULT# DM_IN
ILIM_SEL 4
ILIM_SEL
5 15
<37> USB_POWERSHARE_VBUS_EN EN ILIM_L 16 RI14 2 1
ILIM_HI 22.1K_0402_1%
6
<37> USB_POWERSHARE_EN# 7 CTL1 9
8 CTL2 NC 14
CTL3 GND 17
Thermal Pad
SLGC55544CVTR_TQFN16_3X3
+5V_ALW
RI13 2 1 ILIM_SEL
10K_0402_5%
+5V_ALW
47U_0603_6.3V6M
47U_0603_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
B B
1 1 1 1
@ CI34
@ CI33
@ CI31
CI19
2 2 2 2
Place near UI3.1
A A
Title
USB SW
5 4 3 2 1
5 4 3 2 1
For Breckenridge 14&15/Steamboat 14

DI1 ESD@
USB3_PRX_DTX_N3 1 1 USB3_PRX_DTX_N3 +USB_EX2_PWR
10 9 RF Request
<20> USB3_PRX_DTX_N3
USB3_PRX_DTX_P3 2 2 9 8 USB3_PRX_DTX_P3 +USB_EX2_PWR JUSB2
<20> USB3_PRX_DTX_P3 1
2 1 USB3_PTX_C_DRX_N3 4 4 7 USB3_PTX_C_DRX_N3 USB20_N2_R 2 VBUS
7
<20> USB3_PTX_DRX_N3 USB20_P2_R 3 D-
CI5 0.1U_0402_25V6
USB3_PTX_C_DRX_P3 USB3_PTX_C_DRX_P3 D+
0.1U_0201_10V6K
2 1 5 5 6 6 4
<20> USB3_PTX_DRX_P3 USB3_PRX_DTX_N3 GND
Vinafix.com
100U_1206_6.3V6M
CI4 0.1U_0402_25V6 1 5
SSRX-
1
USB3_PRX_DTX_P3
CI3
3 3 6 10
SSRX+ GND
CI1
7 11
GND GND
2
USB3_PTX_C_DRX_N3
12P_0402_50V8J
RF@ CI45
68P_0402_50V8J
RF@ CI46
8 1 1 8 12
2
2 USB3_PTX_C_DRX_P3 SSTX- GND
ESD@ DI2
9 13
2
D SSTX+ GND D
J-L_TNBNRAC70030009
2 2
1
CONN@
1
LI3 EMI@
USB20_P2 4 3 USB20_P2_R
<17> USB20_P2
USB20_N2 1 2 USB20_N2_R
<17> USB20_N2
EXC24CQ900U_4P
DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P) +USB_EX2_PWR
Pitch change from 0.5mm to 0.55mm
+5V_ALW
UI1
1
5 OUT
IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
4
<37> USB_PWR_EN1# EN 3
1 OCB USB_OC1# <17>
@ CI6
CI7
SY6288D20AAC_SOT23-5
2
2
C C
RF Request
+USB_EX3_PWR
+USB_EX3_PWR
JUSB3
DI6 ESD@ 1
USB3_PRX_DTX_N4 1 1 USB3_PRX_DTX_N4 USB20_N3_R VBUS
10 9 2
<20> USB3_PRX_DTX_N4 USB20_P3_R 3 D-
USB3_PRX_DTX_P4 USB3_PRX_DTX_P4 D+
100U_1206_6.3V6M
0.1U_0201_10V6K
2 2 9 8 4
<20> USB3_PRX_DTX_P4 USB3_PRX_DTX_N4 GND
12P_0402_50V8J
RF@ CI47
68P_0402_50V8J
RF@ CI48
1 1 1 5
SSRX-
1
USB3_PTX_C_DRX_N4 USB3_PTX_C_DRX_N4 USB3_PRX_DTX_P4
CI10
2 1 4 4 7 7 6 10
<20> USB3_PTX_DRX_N4 SSRX+ GND
CI8
CI27 0.1U_0402_25V6 7 11
USB3_PTX_C_DRX_P4 USB3_PTX_C_DRX_P4 USB3_PTX_C_DRX_N4 GND GND
2 1 5 5 6 6 8 12
<20> USB3_PTX_DRX_P4
2
SSTX- GND
2
CI28 0.1U_0402_25V6 2 2 2 USB3_PTX_C_DRX_P4 9 13
SSTX+ GND
ESD@ DI3
3 3
2
J-L_TNBNRAC70030009
8
CONN@
1
1
B B
+USB_EX3_PWR
LI4 EMI@
USB20_P3 4 3 USB20_P3_R +5V_ALW
<17> USB20_P3
UI2
1
USB20_N3 1 2 USB20_N3_R 5 OUT
<17> USB20_N3 IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
EXC24CQ900U_4P 4
<37> USB_PWR_EN2# EN
@ CI11
1 3
OCB USB_OC2# <17>
CI12
100P_0402_50V8J
RF@ CI9
1 SY6288D20AAC_SOT23-5
2
2
A A
Title
JUSB2&JUSB3
5 4 3 2 1
5 4 3 2 1
RF Request
Touch Pad KB_DET#
Vinafix.com
1 2
+3.3V_TP +3.3V_TP RF@ CZ84 68P_0402_50V8J
+3.3V_RUN +3.3V_TP BC_INT#_ECE1117 1 2

D 1 @RF@ CZ85 68P_0402_50V8J D
4.7K_0402_5%
4.7K_0402_5%
BC_DAT_ECE1117 1 2
1
PJP35 RF@CZ83
1 2 68P_0402_50V8J @RF@ CZ86 68P_0402_50V8J
RZ18
RZ19
2
PAD-OPEN1x1m BC_CLK_ECE1117 1 2
PS2 @RF@ CZ87 68P_0402_50V8J
2
DAT_TP_SIO_R DAT_TP_SIO_R 1 2
2 1
<37> DAT_TP_SIO_I2C_CLK @RF@ CZ88 68P_0402_50V8J
@ RZ22 0_0402_5%
2 1 CLK_TP_SIO_R
<37> CLK_TP_SIO_I2C_DAT CLK_TP_SIO_R 1 2
@ RZ23 0_0402_5%
@RF@ CZ89 68P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1
1
I2C1_SDA_TP_R
CZ80
CZ81
2 1
RZ346 0_0402_5%
2
2 1 I2C1_SCK_TP_R
RZ347 0_0402_5%
I2C From EC
Keyboard CONN@
JKBTP1
22
21 GND
GND
+3.3V_TP +3.3V_TP
KB_DET# 20
<20> KB_DET# 19 20
10K_0402_5%
10K_0402_5%
18 19
1
C @ @ 18 C
17
1
2.2K_0402_5%
2.2K_0402_5%
RZ116
RZ117
16 17
RZ20
RZ21
+5V_RUN 16
15
+3.3V_ALW BC_INT#_ECE1117 15 +3.3V_TP +3.3V_ALW +5V_RUN
14
<37> BC_INT#_ECE1117 BC_DAT_ECE1117 14
2
13
<37> BC_DAT_ECE1117 13
2
2
12
BC_CLK_ECE1117 11 12
1 2 I2C1_SDA_TP_R <37> BC_CLK_ECE1117 11
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
<21> I2C1_SDA_TP 10 1 1 1
RZ26 0_0402_5% 10
@
1 2 I2C1_SCK_TP_R 9
+3.3V_TP DAT_TP_SIO_R 9
CZ90
CZ91
CZ92
<21> I2C1_SCK_TP 8
RZ29 0_0402_5% CLK_TP_SIO_R 8
7
6 7 2 2 2
I2C From CPU 5 6
<19,37> TOUCHPAD_INTR# 4 5
I2C1_SDA_TP_R 3 4
I2C1_SCK_TP_R 2 3
1 2
1 Place close to JKBTP1
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7) CVILU_CF5020FD0RK-05-NH
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues
B B
RSMRST circuit
+3.3V_ALW
@ CZ82
1 2
0.1U_0201_10V6K
5
1
P
<37> PCH_RSMRST# B 4 PCH_RSMRST#_AND <7,20>

2 O
<20,50> ALW_PWRGD_3V_5V A
G
UZ6
3
TC7SH08FU_SSOP5~D
A A
Title
Keyboard
5 4 3 2 1
5 4 3 2 1
HDD LED MUX Bat t er y LE D

means EC can switch battery white led and HDD LED by hot key “ Fn+ H”
Vinafix.com
<37> MASK_SATA_LED#
BATT_WHITE#
1 2 BATT_WHITE#
<37,45> BAT2_LED#
5
D RZ361 150_0402_5% D
4 3 BAT2_LED#_R
<16,35,40> SATALED#
@ QZ2B
3
DMN65D8LDW-7_SOT363-6 1 2 BATT_YELLOW#
<37> BAT1_LED#
R1=47k/R2=10k RZ28 330_0402_5%
R2
2
@ QZ3
R1
+3.3V_ALW DDTA144VCA-7-F_SOT23-3
1
2
1 6 BAT2_LED#_R
<37,45> BAT2_LED#
1 2
@ QZ2A @ RZ25 150_0402_5%
LED P/N change to SC50000FL00 from SC50000BA00
Breath LED
+5V_ALW
C C
QZ7B LED3
DMN65D8LDW-7_SOT363-6 LTW-C193DC-C_WHITE
4 3 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF# 1 2
<37> BREATH_LED#
RZ32 330_0402_5%
Place LED3 close to SW3
5
+3.3V_ALW
MASK_BASE_LEDS#
@ CZ93
1 2
0.1U_0201_10V6K
5
1
P
<33,37> LED_MASK# B MASK_BASE_LEDS#

4
2 O
<38,45> LID_CL#
G
A UZ10
TC7SH08FU_SSOP5~D
3
POWER & INSTANT ON SWITCH

LED board CONN
JLED1
SW3
2 1 CONN@
<21,38> POWER_SW#_MB
+5V_ALW 8
GND2 7
6 GND1
4 3 BATT_YELLOW# 5 6
BATT_WHITE# 4 5
SKRBAAE010_4P 3 4
B B
2 3
<38,45> LID_CL# 2
+3.3V_ALW 1
1
CVILU_CF5006FD0R0-05-NH
LED Circuit Control Table

Fiducial Mark
@ FD1
1
SYS_LED_MASK# LID_CL#
FIDUCIAL MARK~D
@ FD2
Mask All LEDs (Unobtrusive mode) 0 X
1
Mask Base MB LEDs (Lid Closed) 1 0
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1
@ FD3
1
FIDUCIAL MARK~D
@ FD4
1 CPU NGFF Standof f
FIDUCIAL MARK~D @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14 @ H16 @ H17 @ H18 @ H19 @ H20 @ H21 @ H22 @ H23
H_3P8 H_3P8 H_3P8 H_3P8 H_1P0N H_1P0N H_3P2 H_3P2 H_2P6 H_2P6 H_5P2 H_2P4N H_2P4 H_2P4 H_3P8 H_4P6 H_2P4 H_5P0x4P0N H_5P0x4P0N H_2P4 H_5P1 H_5P2
1
A A
eDP Standof f For JAE JSIM1 boss hole PCH

@ H34 @ H35 @ H42 @ H43 @ H49 @ H46
H_3P3 H_3P3 H_0P7N H_0P9N H_3P2N H_2P4x1P8N
1

Title
PAD, LED
5 4 3 2 1
5 4 3 2 1
+3.3V_WWAN/+3.3V_LAN source +1.8V_RUN source

PJP41
1 2
+3.3V_ALW +3.3V_WWAN
1
2
UZ2
VIN1
Vinafix.com
VOUT1
14
13
+3.3V_WWAN_UZ2
CZ119
PAD-OPEN1x3m
1 2
0.1U_0201_10V6K
2.5A
+1.8V_PRIM UZ8
1
PJP42
2
0.025A
+1.8V_RUN
VIN1 VOUT1 PAD-OPEN1x1m
D 3.3V_WWAN_EN D
3 12 1 2 1 7
<37> 3.3V_WWAN_EN ON1 CT1 2 VIN VOUT 8 +1.8V_RUN_UZ8 1 2
CZ109 470P_0402_50V7K
4 11 +3.3V_WWAN_UZ2 VIN VOUT CZ120 0.1U_0201_10V6K
+5V_ALW VBIAS GND RUN_ON_1.8V
1 2 3 6 1 2
<11,37,38,46,52,54> RUN_ON ON CT
5 10 1 2 RZ345 0_0402_5% CZ121 470P_0402_50V7K
<20,37> SIO_SLP_LAN# ON2 CT2 CZ110 470P_0402_50V7K 1
6 9 +5V_ALW 4
7 VIN2 VOUT2 8 +3.3V_LAN_UZ2 1 2 RF@ CZ124 VBIAS 5
VIN2 VOUT2 CZ111 0.1U_0201_10V6K 2200P_0402_50V7K GND 9
GND
1
1 2 3.3V_WWAN_EN 15 2
RZ40 100K_0402_5% GPAD PJP37 @ CZ197
EM5209VF_DFN14_3X2 1 2 +3.3V_LAN 470P_0402_50V7K AOZ1336DI_DFN8_2X2
2
PAD-OPEN1x1m
1A RF Request
Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V
+3.3V_ALW_PCH/+3.3V_RUN source
PJP38 1.102A +5V_RUN
1 2
+3.3V_ALW_PCH
PAD-OPEN1x1m
C C
1
+3.3V_ALW @
UZ3 RZ370
1 14 +3.3V_ALW_PCH_UZ3 1 2
VIN1 VOUT1 100_0603_5%
2 13 CZ112 0.1U_0201_10V6K
VIN1 VOUT1
2
@ RZ65 1 2 0_0402_5% 3 12 1 2
ON1 CT1 +5V_RUN_CHG
RZ64 1 2 0_0402_5% CZ113 470P_0402_50V7K
<11,20,52,53> PCH_PRIM_EN
1
4 11 D
+5V_ALW VBIAS GND
2 @
RUN_ON 5 10 1 2 <37> RUN_ON#
ON2 CT2 G QZ4
CZ114 1000P_0402_50V7K S L2N7002WT1G_SC-70-3
3
6 9
7 VIN2 VOUT2 8 +3.3V_RUN_UZ3 1 2
VIN2 VOUT2 CZ115 0.1U_0201_10V6K
15
GPAD
EM5209VF_DFN14_3X2 PJP39
1 2
+3.3V_RUN
PAD-OPEN1x3m Reserve for S3 no power issue (+5V_RUN discharge circuit)
4.677A
+3.3V_ALW +3.3V_ALW_PCH
+5V_RUN/+3.3V_WLAN source
100K_0402_5%
1
RZ518
1
100K_0402_5%
20K_0402_5%
B @ B
RZ375
RZ379
2
<37> SLP_WLAN#_GATE
2
G
PJP40 3.076A 1 3 1 2
1 2
S
+5V_RUN @ QZ16 @ RZ71 0_0402_5%
LP2301ALT1G_SOT23-3
2
+5V_ALW DZ9
G
UZ4 PAD-OPEN1x2m
1 14 +5V_RUN_UZ4 1 2 SLP_WLAN#_M
VIN1 VOUT1 1 3 3
2 13 CZ116 0.1U_0201_10V6K <20,37> SIO_SLP_WLAN#
S
VIN1 VOUT1 WLAN_PWR_EN
1
3 12 1 2 QZ15 2
<11,37,38,46,52,54> RUN_ON ON1 CT1 CZ117 470P_0402_50V7K BSS138W-7-F_SOT323-3
4 11
VBIAS GND
<37> AUX_EN_WOWL BAT54CW_SOT323-3
WLAN_PWR_EN 5 10 1 2
ON2 CT2 CZ118 470P_0402_50V7K 1 2
6 9 +3.3V_WLAN_UZ4 1 2
+3.3V_ALW @RZ70 0_0402_5%
7 VIN2 VOUT2 8 CZ122 0.1U_0201_10V6K
VIN2 VOUT2 EC request to reserve OR gate for WLAN power enable
15 PJP36
GPAD 1 2 +3.3V_WLAN
EM5209VF_DFN14_3X2
PAD-OPEN1x2m
@ RZ96 2A
1 2 WLAN_PWR_EN 1 2
RZ38 100K_0402_5% 0.01_1206_1%
Co-lay:
Short PJP36;Depop RZ96
A A
Title
Power control
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM
VCCPRIM_1P0 PCH SIO_PWRBTN# 8
Timing Diagram for S5 to S0 mode VCCPRIM_CORE
DCPDSW_1P0
VCCAPLL_1P0
PWRBTN#
RSMRST#
PCH_RSMRST#_AND
6
VCCCLK1~6 SIO_SLP_SUS#
VCCMPHYGT_1P0 SLP_SUS#
VCCSRAM_1P0 SIO_SLP_S5#
VCCAMPHYPLL_1P0 SLP_S5#
VCCAPLLEBB
SIO_SLP_S4#
9
SLP_S4# 10
SIO_SLP_S3#
+3.3V_ALW_DSW SLP_S3#
Vinafix.com +3.3V_SPI 4 +3.3V_ALW_PCH

VCCDSW_3P3
SLP_A#
SIO_SLP_A#
D VCCST_PWRGD
CPU
+VCC_CORE VCCHDA SLP_LAN#
SIO_SLP_LAN#
11 D
VCCSPI
12 VCCST_PWRGD VCC VCCPRIM_3P3
VCCPGPPA~E
SLP_WLAN#/GPD9
SIO_SLP_WLAN#
+1.0VS_VCCIO VCCRTCPRIM RESET_OUT#
VCCIO +1.8V_PRIM SYS_PWROK
H_CPUPWRGD
4 16
15 PROCPWRGD +VCC_GT VCCPGPPA PCH_PWROK
PCH_PWROK
PCH_PLTRST#
VCCGT
+RTC_CELL 14
+1.35V_MEM
17 PLTRST#
VDDQ
VCCRTC
VCCST_PWRGD
VCCST_PWRGD
12
VDDQC
0.6V_DDR_VTT_ON
VCCPLL_OC +1.0V_PRIM
12 DDR_VTT_CNTL +1.0V_VCCST 11 SIO_SLP_S0# PROCPWRGD
H_CPUPWRGD
15
VCCST TPS22961 PCH_PLTRST#
VCCSTG
VCCPLL RUN_ON
17 PLTRST#
+VCC_SA
VCCSA
PCH_DPWROK
7 DSW_PWROK
+3.3V_ALW
ENVDD_PCH
+LCDVDD AP2821K EDP_VDDEN
+PWR_SRC
3
PCH_PRIM_EN
+1.0V_PRIM @SIO_SLP_SUS# +3.3V_ALW
4 TLV62130
SIO_SLP_LAN#
+3.3V_ALW 11 +3.3V_LAN EM5209VF SLP_LAN#
4 +1.8V_PRIM
RT8097
+5V_RUN
C 3.3V_TS_EN C
+5V_TSP LP2301ALT1G GPP_B21
+3.3V_RUN
3.3V_CAM_EN#
+3.3V_CAM LP2301ALT1G GPD7
Power Button
EC 5105
1BAT 2AC
11 SIO_SLP_WLAN#
11 ADAPTER
+PWR_SRC
+5V_ALW ALWON
+5V_ALW2
RUN_ON
EC 5105 SYX198
+5V_ALW
+5V_RUN +5V_HDD 1BAT
EM5209VF
+PWR_SRC
+3.3V_ALW +3.3V_RTC_LDO
BATTERY SYX198
+3.3V_ALW2 2AC
EM5209VF +3.3V_RUN +3.3V_HDD +3.3V_ALW
B 3 B
+5V_ALW PCH_PRIM_EN
+3.3V_ALW
+3.3V_ALW SIO_SLP_WLAN# SY8057QDC +1.0VS_VCCIO PCH_RSMRST#

5 EM5209VF
@SIO_SLP_SUS# +3.3V_ALW_PCH 4
RESET_OUT#
11 +3.3V_WLAN EM5209VF AUX_EN_WOWL 16
Pop option
+3.3V_ALW
SIO_SLP_SUS#
+3.3V_SPI
10 SIO_SLP_S4#
SIO_SLP_S5#
9
SIO_SLP_LAN#
11 SIO_SLP_S3# +PWR_SRC
SIO_SLP_A# EN_INVPWR
AO6405 +BL_PWR_SRC 18
+PWR_SRC
12
+VCC_SA IMVP_VR_ON +PWR_SRC
13 +VCC_CORE NCP81215 SIO_SLP_S4#
+VCC_GT +1.2V_MEM VDDQ
SY8210A VTT
DDR
+0.6V_DDR_VTT
PCH_PWROK
12
0.6V_DDR_VTT_ON
A
14 A
Title
Power Sequence
Date : Thursday, January 18, 2018 Sheet 47 of 63
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
2200P_0402_50V7K
1
PR2
1
RF@ PC2
1K_0402_5%
+3.3V_RTC_LDO
+Z4012 2
2
Vinafix.com +COINCELL
@ JRTC1
1
2 1 G
3
4
2 G
D D
ACES_50271-0020N-001
2
+RTC_CELL
1
ESD@ PD1 ESD@ PD2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMC@ PL1 PD3
1
FBMJ4516HS720NT_2P
+3.3V_ALW BAS40CW SOT-323 1
3
1 2 PC3
Primary Battery Connector 1U_0603_25V7K
EMC@ PL2
1
FBMJ4516HS720NT_2P 2
PBATT+_C 1 2 +PBATT
@PBATT1 PR1
1
1 2 100K_0402_5%
2
2 3 PRP1
3 4 PBAT_SMBCLK_C 8 1
2200P_0402_50V7K
4 5 PBAT_SMBDAT_C 7 2
5 PBAT_PRES#_C PBAT_CHARGER_SMBDAT <37,49>
6 6 3
PBAT_CHARGER_SMBCLK <37,49> PBAT_PRES# <37,49>
1
6 7 5 4
EMC@ PC1
7 8
8 9 100_0804_8P4R_5%
2
9 10
10 11
GND 12
GND
DEREN_40-42251-01001RHF +3.3V_ALW
PR3
0_0402_5%
2
GND 1 @ 2
PR4
2.2K_0402_5%
C EMC@ PL3 PR5 C
1
BLM15AG102SN1D_2P 33_0402_5%
NB_PSID 2 1 1 3 1 2 PS_ID
S
PS_ID <37>
PQ2
2
FDV301N-G_SOT23-3 +5V_ALW
G
2
PR6
100K_0402_1%
3
PD4 ESD@
3
1
AZC199-02SPR7G_SOT23-3 C
2 PQ3 PR7
1
B MMST3904-7-F_SOT323~D 10K_0402_1%
E
1
3
2
2
PR8
15K_0402_1%
1
PD5
5A 100V 15UA 0.88V TO227-3
+3.3V_VDD_DCIN +DC_IN
2
PC7 can't over 1000P DC_IN+ Source 1 PU2
1000P_0603_50V7K
3 1
+DC_IN 3 VIN
VOUT
PC11
EMC@ PL2002 S1 S2 +SDC_IN 2
GND
5A_Z80_0805_2P +DC_IN_SS
2
1 2 PQ9 PQ4 AP2204R-3.3TRG1_SOT89-3
1
AON7409_DFN8-5 AON7409_DFN8-5
EMC@ PL4 1 1 +SDC_IN PC10
5A_Z80_0805_2P 2 2 2.2U_0402_6.3V6M
2
1 2 3 5 5 3
0.022U_0603_50V7K
PC4
1
1
PR11
DFLS160-7_POWERDI123-2
499K_0402_1%
1
3
S
PR10
4
4
1
B G B
2
1M_0402_1%
300K_0402_5%
0.022U_0603_50V7K
2
@ PD6
2
2 PR12
PC6
1000P_0603_50V7K
2
1
@ PJPDC1 +3.3V_VDD_DCIN
100K_0402_5%
10U_0805_25V6K
0.1U_0603_25V7K
1
1
1
4.7K_0805_5%
7
D
AO3409_SOT23-3
2
1
1
GND 6
EMC@ PC5
PC7
PC8
2
GND -DCIN_JACK
PR14
PQ5
5
PR13
5 4
2
1
4 3 +DCIN_JACK
@EMC@
3 2 PR15 PR17
@
2 1
1 100K_0402_5% 100K_0402_5%
1
CVILU_CI0805M1HRC-NH
2
PC9
0.1U_0402_25V6 PR18
PQ1A
+3.3V_VDD_DCIN
6
2 1 1M_0402_1% DMN65D8LDW-7_SOT363-6
2
49.9K_0402_1%
1
2 2 @ 1
PR16
PR21 PU1 PR19 0_0402_5%

5
L2N7002WT1G 1N SC-70-3
0_0402_5% MC74VHC1G08DFT2G SC70 5P AND
1
1
3
1 @ 2 1 D
P
<37,49,60> HW_ACAVIN_NB B
PQ6
4 2 @ 1 2 PR25
1 2 2 O
PQ1B
@ G 0_0402_5%
G
A
L2N7002WT1G 1N SC-70-3
PR23 S PR20 5 2 @ 1
AC_DISC# <37,60>
3
D
PR22 0_0402_5% 0_0402_5%
3
PQ7
0_0402_5% 2 1 @ 2
4
G
1
S
3
PQ8 VBUS2_ECOK <37,60>

PR26 L2N7002WT1G 1N SC-70-3 PR30
1
0_0402_5% 100K_0402_5%
S
1 @ 2 3 1
<37> DCIN2_EN
2
PR24
100K_0402_5%
G
2 2
2
1
A A
100K_0402_5%
1
PR28
PR29
@ 0_0402_5%
PR27
2
100K_0402_5%
1
+3.3V_VDD_DCIN
+3.3V_ALW
Title
+DCIN
5 4 3 2 1
A B C D
+PWR_SRC_AC
+SDC_IN +CHARGER_SRC
PR901 EMC@
0.01_1206_1% PL901
1UH +-20% 6.6A 5X5X3 MOLDING
1 4 2 1
2 3 +PWR_SRC
DFLS160-7_POWERDI123-2
2200P_0402_50V7K
0.1U_0402_25V6
15U_B2_25VM_R100M
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
1
1
Vinafix.com
RF@ PC902
RF@ PC903
@ PJP901
1
PC911
PC904
PC905
PC906
PC909
JUMP_43X118 +
PD906
1 2
1 2
2
1
footprint with solder mask 2 1
2
(-NPM)
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
15U_B2_25VM_R100M
15U_B2_25VM_R100M
1 1
1
PC914
PC915
PC913
PC916
PC921
PC922
+ +
2
2 2
1
PR909 PR910
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
2_0603_1% 2_0603_1%
1
PC951
PC952
PC953
PC954
2
2
CSIN_ISL88738
PC925
CSIP_ISL88738
4.7U_0402_6.3V6M
2200P_0402_50V7K
1 2
100P_0402_50V8J
100P_0402_50V8J
0.1U_0402_25V6
@EMC@ PC958
@EMC@ PC959
1U_0402_25V6K
1U_0402_25V6K
1U_0402_25V6K
1U_0402_25V6K
1
1
EMC@ PC928
RF@ PC957
EMC@ PC929
RF@ PC956
1
PC927
PC926
2
2
2
2
PC930
+SDC_IN PR943
0_0603_5% 0.22U_0603_25V7K
2 1
2 1 2 1 ADP_ISL88738
+PWR_SRC PD901
30MA_30V_0.5UA_0.4V_SOD323-2 PR914
1
3.3_0603_1%
PR944
2 1
+VBUS_DC_SS 442K_0402_1%
1
2
PD903 2
RB520SM-30T2R_EMD2-2
42Whr - 3S1P
2
BOOT1_ISL88738
ACIN_ISL88738 51Whr - 3S1P
CSIP_ISL88738
CSIN_ISL88738
UG1_ISL88738
LX1_ISL88738
LG1_ISL88738
68Whr - 2S2P
1
2 1
0.1U_0402_25V6
+DC_IN_SS
1
5
92Whr - 3S2P
PC955
PD904 PR945 PR915
UG2_ISL88738
30MA_30V_0.5UA_0.4V_SOD323-2 100K_0402_5% 4.7_0603_5% PQ902
2
1 2 VDD_ISL88738 AON6354_N_DFN56-8-5
2
PR916
2
PU901
16
15
14
13
12
11
10
33
1_0805_5%~D
9
PC931 1U_0603_25V6 ISL9538HRTZTS277_TQFN32_4X4~D UG1_ISL88738 4 Batt in max=11.33A (68Whr/6V by 2S battery)
PQ1302
BOOT1
UGATE1
PHASE1
LGATE1
CSIN
PAD
ADP
CSIP
ASGATE
1
1 2 DCIN_ISL88738 PC932 AON6962 2N DFN5X6D-8

1U_0402_6.3V6K ADP 130W*0.9/7.4V(2S battery)=15.8A +VCHGR PQ906
2
1 @ 2 17 8 VDDP_ISL88738 2 1 PR917 AON7409_DFN8-5
3
2
1
DCIN VDDP
PR960 0_0402_5% PL902 0.005_1206_1% 1 +PBATT
G1
D1
2 1 VDD_ISL88738 18 7 LG2_ISL88738 2
VDD LGATE2 1UH_MMD-10DZ-1R0M-X1A_18A_20%
2
1 4 3 5
PC933 PR918 @ PR919 ACIN_ISL88738 19 6 LX2_ISL88738 LX1_ISL88738 1 2 7
1U_0402_6.3V6K 0_0402_5% ACIN PHASE2 D2/S1 2 3
100K_0402_1%
1 2 OTGEN/CMIN 20 5 UG2_ISL88738 LX1_ISL88738
4
CMIN UGATE2 PC934 PR921
G2
LX2_ISL88738
S2
S2
S2
1
5
ACAV_IN1 1 @ 2 21 4 BOOT2_ISL88738 2 1 2 1
10U_0805_25VAK
10U_0805_25VAK
<37,48> PBAT_CHARGER_SMBDAT SDA BOOT2 PQ903
1
PR920 0_0402_5%
4.7_1206_5%
4.7_1206_5%
3
1
EMC@ PR923
EMC@ PR924
PQ909 1 @ 2 22 3 0.22U_0603_25V7K 4.7_0603_5%
4700P_0402_25V7K
<37,48> PBAT_CHARGER_SMBCLK SCL VSYS AON6354_N_DFN56-8-5
1
1
D
PC935
PC936
L2N7002WT1G 1N SC-70-3 PR925 PR922 0_0402_5%
2
2 PROCHOT#_ISL8873823 CSOP_ISL88738
LG2_ISL88738
PC937
2 154K_0402_1% 1 @ 2
<7,37,55> PROCHOT# PROCHOT# CSOP
AMON/BMON
<37> AC_DIS G PR926 0_0402_5% LG1_ISL88738 4
1SNUB_CHG1 2
1SNUB_CHG2 2
2
1
CSON_ISL88738
BATGONE
S <60> PROCHOT#_ISL88738
24 1
3
1
ACOK CSON Layout source connect to current sensor @
CMOUT
BGATE_ISL88738
BGATE
COMP
PROG
(PR929.2 to PR917.1)
PSYS
VBAT
1 2 ACOK_ISL88738 1 2
680P_0603_50V7K
680P_0603_50V7K
@ @
3
2
1
PR927 PR928 0_0402_5% PR929 0_0402_5% +PWR_SRC
2
1M_0402_1% @ PR930 PC938

25
26
27
28
29
30
31
BGATE_ISL88738 32
EMC@ PC940
EMC@ PC941
100K_0402_1% 10P_0402_50V8J
PR931 1 2 1 2 1 @ 2
0_0402_5%
105K_0402_1%
<37,48> PBAT_PRES# 100K_0402_1%
2
2 PR932 1
3
1 2 PC939 3
VBAT1_ISL88738
PR933 0.1U_0402_25V6
100K_0402_1%
1
1 2
+3.3V_ALW
@
1 @ 2
<60> CMOUT
PR949
PR951 0_0402_5%
2
COMP_ISL88738 PC942
1U_0402_25V6K
1 @ 2
0_0402_5%
1
PR934
0_0402_5%
560P_0402_50V7K
1
PC947
0_0402_5%
0_0402_5%
10.2K_0402_1%
0.1U_0402_25V6
1
1
@ PC943
PR948
1 2
1
@ PR937 1_0603_1%
2
@
2
PC945
0.012U_0402_16V7K~D
2
1
PR936
PC944
1U_0402_25V6K
2
@ @ 1 2
PR938 1_0603_1%
2
LM393_P
PR935
PR947
2
@ PR950
1 2 0_0402_5%
I_SYS <37,55> 1 2
PC946
0.22U_0402_25V6K
I_BATT
I_ADP
PD905 PC949
BAT54CW_SOT323-3 0.1U_0402_25V6
<29,60> AC1_DISC#
1 @ 2 3 1 2 PU903
PR939 0_0402_5% MC74VHC1G08DFT2G SC70 5P AND
I_BATT <37> 1
5
I_ADP <37> +PBATT 1 2 2 1
PR946
@ 0_0402_5%
P
<37,48,60> HW_ACAVIN_NB B <37> ACAV_IN
2 1 PR941 0_0402_5% 4 1 @ 2
ACAV_IN1 1 @ 2 2 Y
Close to EC ADP_I pin
0_0402_5% A
G
PR940 PR942
2
1
4
100_0402_1% 4
3
@ PC950 PR953
0.1U_0402_25V6 100K_0402_1%
1
Adp=130W, Battery Max=12.9V*9.7A=125.13W
2
Psys_max = 255.13W, Set PSYS=225W
Ipsys = (1.493/2) * Psys_max + 1.43 = 169.39uA
Rpsys = 2 / Ipsys=11.8kOhm DELL CONFIDENTIAL/PROPRIETARY
Place at CPU_VR side Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/01/01 Title
2017/01/01 Deciphered Date
PWR_CHARGER_ISL9237 (Colay)
0.5
Custom
LA-F711P
A B C D
A B C D E
Vinafix.com PGOOD_3V 1
PR119
@ 2
0_0402_5% ALW_PWRGD_3V_5V <20,44>
PGOOD_5V 1 @ 2
1 PR120 0_0402_5% 1
PR102
499K_0402_1%
ENLDO_3V5V 1 2
+PWR_SRC 3V_VIN PR100 PC102 +PWR_SRC
PJP100 0_0603_5% 0.1U_0603_25V7K
1
3V_VIN BST_3V1
499K_0402_1%
1 2 2 1 2
PR103
PAD-OPEN 1x2m~D
1
100P_0402_50V8J
100P_0402_50V8J
1U_0402_25V6K
1U_0402_25V6K
PU100
2
10U_0805_25V6K
10U_0805_25V6K
BS
IN
IN
IN
IN
1
1
RF@ PC133
RF@ PC134
RF@ PC135
LX_3V 6
@EMC@ PC136
PC105
PC104
20 PL100
LX LX 1.5UH_9A_20%_7X7X3_M Vout = 3.319V~3.37V~3.421V
2
2
7 19 LX_3V 1 2
GND
SY8288BRAC_QFN20_3X3 LX
+3.3V_ALWP
RF@ PR106
8 18 PR104 7x7x3
GND GND
4.7_1206_5%
0_0402_5%
Rdson=14~15mohm
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
9 17 1 @ 2
PG LDO +3.3V_ALW2 Irms=9A
1
PC106
PC107
PC108
PC109
PC110
PC129
10 16 Isat=18A
NC NC 1 @ 2 +3.3V_RTC_LDO
OUT
2
EN2
EN1
21
NC
PR105
3VALWP
FF
GND 0_0402_5%
1 3V_SN 2
PR107 TDC=7.61A
11
12
13
14
15
680P_0603_50V7K
100K_0402_5% 3.3V LDO 150mA~300mA
Peak Current=10.87A
RF@ PC112
2 1 2 2
+3.3V_ALW
1
OCP=10~14 A
ENLDO_3V5V
Fs=600KHz PC111
4.7U_0603_6.3V6K
2
PGOOD_3V
PJP102
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1000P_0402_50V7K 1K_0402_5% 1 2
3V5V_EN 3V_FB 1 2 1 2 JUMP_43X118
PJP103
+PWR_SRC 5V_VIN PR111 PC114 +5V_ALWP 1 2 +5V_ALW
PJP101 0_0603_5% 0.1U_0603_25V7K 1 2
1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X118
PAD-OPEN 1x2m~D 7x7x3

NONAR@ Rdson=18~20mohm
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
1U_0402_25V6K
Irms=8A
5
1
10U_0805_25V6K
10U_0805_25V6K
EMC@ PC115
0.1U_0402_25V6
PU102
1
Isat=14A
RF@ PC137
RF@ PC138
RF@ PC139
RF@ PC140
AR@, 5V=5.177V
BS
IN
IN
IN
IN
PC117
PC118
LX_5V 6 20 PL101 NONAR@, 5V=5.1V

2
LX LX 2.2UH +-20% 7.8A 7X7X3 MOLDING

7 19 LX_5V 1 2
3 GND LX +5V_ALWP 3
8 SY8288CRAC_QFN20_3X3 18
GND GND
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC119 RF@
1
9 17 1 2 PR112
PC120
PC121
PC122
PC123
PC124
PC130
PG VCC
4.7_1206_5%
10 16
2
NC NC 4.7U_0603_6.3V6K
1 5V_SN
OUT
LDO
2
EN2
EN1
21
FF
GND
RF@
11
12
13
14
15
PR113 PC125
100K_0402_5% 680P_0603_50V7K
+5V_ALW2
2
1 2
+3.3V_ALW
ENLDO_3V5V
5V LDO 150mA~300mA
3V5V_EN
PGOOD_5V
PC126
4.7U_0603_6.3V6K
PR114
0_0402_5% Fs=600KHz 5VALWP
2
1 @ 2
<37> ALWON
TDC=5.461A
3V5V_EN
Peak Current=7.801A
@ 2 1 OCP=10A
1M_0402_1%
4.7U_0402_6.3V6M
PD100
1
RB520SM-30T2R_EMD2-2
1
PR116
PC128
PC127 PR117
1000P_0402_50V7K 1K_0402_5%
5V_FB 1 2 1 2
2
2
PU102 AR@
4 4
EN1 and EN2 dont't floating
SYV828CRAC_QFN20_3X3 DELL CONFIDENTIAL/PROPRIETARY

Title
+5V_ALW/3.3V_ALW
0.5
Custom
LA-F711P
A B C D E
5 4 3 2 1
Vinafix.com
D D
7x7x3
+PWR_SRC Rdson=6.7~7.4mohm
PJP202 Irms=12A
1 2 +1.2V_DDR_B+ Isat=15A
RF@
RF@
PU200
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
PAD-OPEN 1x2m~D RF@ RF@

1
10 19 PR202 PC204
PC200
PC201
+3.3V_ALW
IN OT
PC202
PC203
4.7_1206_5% 680P_0603_50V7K
13 18 PR203 PC205 1 2 1 2
2
BYP PG
1U_0402_6.3V6K
14 12
0_0603_5% 0.1U_0603_16V7K
1 2 1 2 PL201
+1.2V_DDRP
VCC BS
1
PC206
C 1UH_11A_20%_7X7X3_M C
1
LX_DDR
2.2U_0402_6.3V6M
4 11 1 2
VTTGND LX
PC207
2
330P_0402_50V7K
2 9 16
PGND FB
1
102K_0402_1%
EMC@
EMC@
1
+1.2V_DDRP
PC208
PR204
15 8 PC209
+3.3V_ALW SGND VDDQSNS
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2200P_0402_50V7K
22U_0603_6.3V6M
R1
100P_0402_50V8J
7 1 2
2
VLDOIN
1
PC210
PC211
PC212
PC213
PC223
PC214
PC216
PC217
2
2
@ ILMT_DDR 17 6
PR205 ILMT VTT +0.6VSP
2
1 5
Current limit: 0_0402_5% S5 VTTSNS
1
Pull Low = 8A
100K_0402_1%
2 3
1
S3 VTTREF
22U_0603_6.3V6M
PR206
Fs=600KHz R2
Floating = 12A
1
ILMT_DDR
1U_0402_6.3V6K
PC218
PC219
SY8210AQVC_QFN19_4X3
Pull High = 16A
EN_1.2V
2
2
@
EN_0.6V
PR207
0_0402_5%
Vout = 0.6V*(1+102K/100K)
1
=1.212V
PR208
0_0402_5%
2 @ 1
B B
0.1U_0402_25V6
<11,20,21,37,52> SIO_SLP_S4#
1M_0402_5%
1
2 @ 1
PC221
PR209
+1.2V_DDRP +1.2V_MEM +0.6VSP +0.6V_DDR_VTT

PJP200 PJP201
2
JUMP_43X118 JUMP_43X39
1 2 1 2
PR210 1 2 1 2
0_0402_5%
<14> 0.6V_DDR_VTT_ON
2 @ 1
0.1U_0402_25V6
1M_0402_5%
1
@ PC222
+1.2V_MEM 0.6V +/- 5%

PR212
TDC=7.91A TDC=0.788A
2
Mode S3 S5 VOUT VTT

Normal H H on on Peak Current=11.3A Peak Current=1.125A
2
Stadby L H on off OCP=12A OCP=2A fix by IC

Shutdown L L off off
Note: S3 - sleep ; S5 - power off
A A
Title
+1.2V_MEN/+0.6V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
PC502
22U_0603_6.3V6M
1 2 PJP502
@EMC@ PL502 1 2
3A_Z120_40M_0603_2P +1.8VALWP +1.8V_PRIM
1 2 VIN_1.8VALW
+3.3V_ALW PAD-OPEN1x1m
Vinafix.com 1
PJP501
2
2.5x3.2x1.2
Rdson=48mohm
Irms=3.3A
PAD-OPEN1x1m Isat=4.6A
D D
PU501
RT8097ALGE_SOT23-6 PL501 Vout = 0.6*(1+20K/10K)
+3.3V_ALW 2 1
LX_1.8VALW
1UH_1277AS-H-1R0N-P2_3.3A_30% =1.8V
PR517 4 3 1 2
100K_0402_5% IN LX +1.8VALWP
1
2 1 PG_1.8VALW 5 2
68P_0402_50V8J
<37,53> 1.8V_1.0V_PWRGD PR2011 0_0402_5% PG GND RF@
1SNUB_1.8VALW
22U_0603_6.3V6M
22U_0603_6.3V6M
1
6 1 PR502
PC503
1
1
FB EN 4.7_0603_5%
PC501
PC504
PR501
2
PR504 20K_0402_1%
2
0_0402_5%
1 @ 2 EN_1.8VALW
<11,20,46,52,53> PCH_PRIM_EN Rup
2
RF@
Fs=1000KHz PC506
1
680P_0402_50V7K
2
1
PR505 @ PC505
1M_0402_1% @ .1U_0402_16V7K
2
FB_1.8VALW
1
PR506
Rdown +1.8V_PRIM
10K_0402_1% TDC=1.55A
Note: Peak Current=2.214A
2
When design Vin=5V, please stuff snubber OCP=3.5A fix by IC
to prevent Vin damage
C C
For TypeC-SW PS8802

+1.2V_RUN
TDC 0.4 A
Peak Current=0.6 A
OCP=1.3A fix by IC
PU502
PJP503
EM1109V-AD_DFN3308-8_3X3 PJP504
2 1 +1.2V_VIN 9
+3.3V_ALW GND 1 1.2VSP 1 2
8 OUT
+1.2V_RUN
1
PAD-OPEN1x1m IN 2
5.1K_0402_1%
NC PAD-OPEN1x1m
1
PC508 7
0.01UF_0402_25V7K
4.7U_0603_6.3V6K NC 3 ADJ_1.2V
PR512
PC509
2
PR511 6 ADJ/NC
2
NC
1
0_0402_5% 4
1 2 EN_1.2RUN 5 GND PC511
@
<11,20,46,52,53> PCH_PRIM_EN
2
EN 22U_0805_6.3V6M
2
1
PR2010
0_0402_5% PR509 @ PC510
1
1 @ 2 1M_0402_1% @
<11,37,38,46,54> RUN_ON Vout = 0.8*(1+5.1K/10.2K)
2
.1U_0402_16V7K
PR510 =1.2V
2
10.2K_0402_1%
2
B B
+2.5V_MEM
TDC=0.315A
Peak current=0.45A.
OCP=1.3A fix by IC
PU503
PJP505
EM1109V-AD_DFN3308-8_3X3 PJP506
1 2 +2.5V_VIN 9
+3.3V_ALW GND 1 2.5VSP 1 2
OUT
+2.5V_MEM
1
8
PAD-OPEN1x1m PC514 IN 2
NC PAD-OPEN1x1m
1
4.7U_0603_6.3V6K 7 PR515
2
NC 3 21.5K_0402_1% PC515
PR513 6 ADJ/NC 0.01UF_0402_25V7K
2
NC
1
0_0402_5% 4
1 2 5 GND PC516
@
<11,20,21,37,51> SIO_SLP_S4# EN 22U_0603_6.3V6M
2
1
PR514 @
1M_0402_1%
PC513
PR516 Vout = 0.8*(1+21.5K/10.2K)
2
.1U_0402_16V7K 10.2K_0402_1% =2.486V

2
A A
Title
+1.8VALWP/+1.2V_RUN/2.5V_MEN
5 4 3 2 1
5 4 3 2 1
Vinafix.com +1.0V_PRIM (1.05V)

D 14HU/15HU D
TDC=5.53A
Peak Current=7.9A
15HD
+3.3V_ALW TDC=5.88A PJP302
Peak Current=8.4A +1.0VALWP 1
1 2
2 +1.0V_PRIM
OCP=9.5A JUMP_43X118
1
PR2013
@ 100K_0402_5%
RF@ RF@ RF@
PL302 PR2012 PR303 PC302
2
5A_Z80_0805_2P 0_0402_5% 4.7_1206_5% 680P_0603_50V7K
SNUB_+1VALWP
1 2
+1VALWP_B+ 1 @ 2 1.8V_1.0V_PWRGD <37,52> 1 2 1 2
+PWR_SRC @ PJP301 PU301

PG_+1VALWP
1 2 2 9 PC304 PR304
IN PG 0.1U_0603_25V7K 0_0603_5%
10U_0603_25V6M
10U_0603_25V6M
3 1 BST_+1VALWP 1 2 BST_+1VALWP_R 1 2 PL301
PAD-OPEN 1x2m~D IN BS +1.0VALWP
1
0.68UH_7.9A_20%_5X5X3_M
PC305
PC306
4 6 LX_+1VALWP 1 2
IN LX
2
5 19 5x5x3
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
Rdson=11~12mohm
1
7 20
Irms=8.5A
1
GND LX
PC308
PC309
PC310
PC311
PC315
PC316
100_0402_5%
8 14 FB_+1VALWP Isat=14A
PR313
2
GND FB
PR312 18 17 LDO_3V Vout = 0.6*(1+15K/20K) @ @
GND VCC
15K_0402_1% =1.05V
2
1
1 2 EN_+1VALWP 11 10
<11,20,46,52> PCH_PRIM_EN EN NC PC312
1
ILMT_+1VALWP 13 12 PR314
4.7U_0603_6.3V6K
2
1
ILMT NC 0_0402_5%
C PR302 PC314 15 16 1 @ 2 C
1M_0402_1% 0.1U_0402_25V6
+3.3V_ALW BYP NC VCCMPHY_SENSE <22>
330P_0402_50V7K
+3.3V_ALW
2
21
2
2
PAD
SY8286RAC_QFN20_3X3
PC307
1
1
PC313
1
1
4.7U_0603_6.3V6K
2
@ PR607 PR306
0_0402_5% 15K_0402_1%
1
Fs=500KHz
1K_0402_1%
PR2008
2
2
EN :H>0.8V ; L<0.4V
1
2
@ PR609
EN pin don't floating
0_0402_5%
If have pull down resistor at HW side,
please delete PR601.
2
1
PR311
20K_0402_1%
PR315
2
0_0402_5%
Current limit: 1 @ 2
Pull Low = 6.5~8.5A VSSMPHY_SENSE <22>
1
0_0402_5%
Floating = 9.5~11.5A
PR316
Pull High = 12.5~14.5A
2
B B
A A
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+1VALWP
Size Document Number Rev
0.5
LA-F711P
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D
PR2009
0_0402_5% +3.3V_ALW D
1 2
<11,16> CPU_C10_GATE#
1
PR425
0_0402_5% PR405
<11,20,21,39> SIO_SLP_S0# 1 @ 2 @ 0_0402_5%
2
PJP401
PR402 1 2
0_0402_5% +1VS_VCCIOP 1 2 +1.0VS_VCCIO
1 @ 2 JUMP_43X118
<11,37,38,46,52> RUN_ON
EN_1VS_VCCIO
0.1U_0402_25V6
1
1
@ PC415
PR403
1M_0402_1%
2
2
@EMC@ PL405
13
14
15
16
17
3A_Z120_40M_0603_2P
1 2
Vin=3~17V
VIN_1VS_VCCIO +1.0VS_VCCIO
EN
PGND
PGND
LP
TP
PJP402
+5V_ALW VIN_1VS_VCCIO Peak Current=6.4A
1 2 12
PVIN OUT
1
+1VS_VCCIOP
PAD-OPEN 1x2m~D PL401
10U_0603_10V6M
10U_0603_10V6M
1UH_PCMB042T-1R0MS_4.5A_20%
0.1U_0402_25V6
1
1
LX_1VS_VCCIO
PC407
11 2 1 2
+1VS_VCCIOP
PC404
PC408
PVIN LX
PU401 4.5x4x2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
2
SY8057BQDC_QFN16_3X3
Rdson=24~27mohm
1
10 3
RF@
PC410
PC411
PC412
PC401
SVIN LX Irms=4.5A
+3.3V_ALW Isat=7A
2
1
VID0_VCCIO 9 4
1SNUB_1VS_VCCIO
VID0 PG RF@
C C
PR404
MODE
SGND
4.7_0603_5%
VID1
FBS
2
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
5
1
Fs=1.2MHz RF@ 0 X X 0(LPM)
SS_1VS_VCCIO
PR417 @ PR418 PC403 +1VS_VCCIOP
10K_0402_1% 10K_0402_1% VID1_VCCIO 470P_0402_50V7K SY8057 1 0 0 0.85
1
2
VID0_VCCIO PR414
@ 0_0402_5%
1 0 1 0.875
VID1_VCCIO
1 1 0 0.95
470P_0402_50V7K
2
2
1
1 1 1 0.975
200K_0402_1%
1
@ 2 @ 1
PR427
PC409
PR415 0_0402_5% VCC_IO_SENSE <11>
2
@ PR419 PR420
10K_0402_1% 10K_0402_1%
1
2 @ 1
CFL-H (45W)
2
PR416 0_0402_5% VSS_IO_SENSE <11>

VCCIO: 0.95V, Max current=6.4A
Preset the different pull down resistor to choose

the required power rail
(VCCIO/PCH/EDRAM/EOPIO applications.)
RMODE>500k or floating = Vcc_PRIM_CORE.
B RMODE=200k = Vcc_IO. B
RMODE=0 = Vcc_EDRAM.
A A
Title
+1VS_VCCIO
5 4 3 2 1
5 4 3 2 1
H42@
PR1741 Place close to Choke in VCCSA first phase circuit
20.5K_0402_1%
PR1701 PR1702 PR1199 NA, need confirm
12K_0402_1% 7.5K_0603_1%
PC1700 PH1700 1 2 1 2 1 2 +1.0V_VCCST
PR1700 2200P_0402_50V7K
<58> CSN_1PH SW_1PH <58> TSM0B224J4702RE
1
1 2
100_0402_1%
100_0402_1% 100K_0402_1%_TSM0B104F4251RZ
7.2329K@105C
2
1 2
499_0402_1%
PR1703 Layout need to be clean.
45.3_0402_1%
45.3_0402_1%
1 2 R15/0.9m
PR1704
PR1705
PR1706
PR1707
PR1708 PR1709 10_0402_1% PH1700 close to SA choke PC1702
H42@ 0_0402_5% 1K_0402_1% PH1700.1, PR1701.2, PR1702.2 differential to IC 0.1U_0402_25V6
1
PR1758 <11> VSS_SA_SENSE
1 @ 2 1 2 VSN_1PH PC1701 R47/6.2m
2
68.1K_0402_1% 0.01UF_0402_25V7K
2
@
2
FAE modify item_20170518 1 2 @
PC1703
Vinafix.com
1
CSP_1PH
1000P_0402_50V7K PR1711 PC1705 PR1712
1
1.74K_0402_1% 2200P_0402_50V7K PR1713 100_0402_1%
470P_0402_50V8J
1
1 2 1 2 VSP_1PH CSN_1PH_R 28K_0402_1% 81215_VR_HOT
1 2
PC1706
<11> VCC_SA_SENSE @
PROCHOT# <7,37,49>
PR1714 PR1710 +3.3V_RUN
1
D 100_0402_1% 0_0402_5% PC1708 D
2
1 2 1 2 1 2 1000P_0402_50V7K 81215_SCLK 2 1
+VCC_SA PC1704 1 2 PR1715
VR_SVID_CLK <7>
IMON_1PH
2
PWM1_1PH/ICCMAX1 <58>
1
PR1771 PC1707 49.9_0402_1%
2.21K +-1% 0402 1000P_0402_50V7K 3300P_0402_25V7K PR1718 81215_ALERT 2 @ 1
VR_SVID_ALERT# <7>
Pull high at HW side already 12K_0402_1% PR1716 PR1717 0_0402_5%
PC1704 need to close to pin48 1 2 10K_0402_1% PR1722
PR1721 38.3K +-1% 0402 81215_SDIO 1 2
2
VR_SVID_DATA <7>
100_0402_1% PR1720 PC1709 PR1719 10_0402_1%
PCH_PWROK <20>
1 @ 2 1.5K_0402_1% 0.015U_0402_16V7K 1 2
+VCC_CORE PR1723 1 2 1 2
0_0402_5% 81215_SCLK
1 @ 2 VSP_4PH 81215_ALERT 1 @ 2
<12> VCC_SENSE
1 2 81215_SDIO PR1724 0_0402_5%
IMVP_VR_ON <38> Cout:
2
H42@ IA=330uF * 3, DY*1
PC1724 PC1711 PC1710 PR1725
120P_0402_50V8 1000P_0402_50V7K PR1727 100P_0402_50V8J 100_0402_1% 22uF * 24, DY*8
1
1 @ 2
1.78K_0402_1%
1 2 VSN_4PH VSN_1PH PR1728
1 2
+VCC_GT 10uF*21
<12> VSS_SENSE
PR1729 0_0402_5% 1uF * 24, DY*24
ILIM_1PH
COMP_1PH
100_0402_1%
1 @ 2
PR1726
0_0402_5% 1 2 VSP_1PH
1 @ 2 VCC_GT_SENSE <11> GT=470uF * 2
PC1713 22uF * 13, DY*6
1
PC1712 1000P_0402_50V7K
Pull low at HW side already 2200P_0402_50V7K PR1730
10uF * 10, DY*5
2.05K_0402_1% 1uF * 12
2
1 2 1 @ 2
PR1736
VSS_GT_SENSE <11> SA=22uF * 15
PR1735 100_0402_1% 10uF * 7
1 2 0_0402_5% 1 2
PC1714 PR1731 PC1715 PU1700
53
52
51
50
49
48
47
46
45
44
43
42
41
40
47P_0402_50V8J 49.9_0402_1% 470P_0402_50V8J NCP81215DPA0MNTXG_QFN52_6X6 PC1719
1 2 1 2 1 2 PR1732 2200P_0402_50V7K
TAB
VR_RDY
SCLK
ALERT#
SDIO
VSP_1PH
VSN_1PH
COMP_1PH
ILIM_1PH
CSN_1PH
CSP_1PH
IMON_1PH
PWM_1PH/ICCMAX_1PH
EN
26.1K_0402_1%
PR1737 PR1734 1 2 PR1738 PC1720 PC1717
3.65K_0402_1% 1K_0402_1% PR1733 49.9_0402_1% 470P_0402_50V8J 47P_0402_50V8J
1 2 1 2 1 2 30.1K_0402_1% 1 2 1 2 1 2
PC1718 VSP_4PH 1 39 81215_VR_HOT 1 2
PC1716 470P_0402_50V8J VSN_4PH 2 VSP_4PH VRHOT# 38 VSP_2PH PC1722 2 1 1 2 1 2
2200P_0402_50V7K 1 2 3 VSN_4PH VSP_2PH 37 VSN_2PH 470P_0402_50V8J PR1739 PR1740 PC1721
DIFFOUT_4PH 4 IMON_4PH VSN_2PH 36 1 2 1K_0402_1% 3.65K_0402_1% 2200P_0402_50V7K
FB_4PH 5 DIFFOUT_4PH IMON_2PH 35 DIFFOUT_2PH
C COMP_4PH FB_4PH DIFFOUT_2PH FB_2PH C
6 34
H62@ 1 2 ILIM_4PH 7 COMP_4PH FB_2PH 33 COMP_2PH
Place close to Choke in VCORE CSCOMP_4PH ILIM_4PH COMP_2PH ILIM_2PH
PR1741 30.1K_0402_1% 8 32 1 2
first phase circuit
1
CSSUM_4PH 9 CSCOMP_4PH ILIM_2PH 31 CSCOMP_2PH

75K_0402_1%
PR1742 13K_0402_1%
1
10 CSSUM_4PH CSCOMP_2PH 30 CSSUM_2PH
PR1743
75K_0402_1%
PH1701 PH1702
680P_0402_50V7K
68P_0402_50V8J
CSP1_4PH 11 CSREF_4PH CSSUM_2PH 29
PR1744
220K_0402_5%_ERTJ0EV224J
680P_0402_50V7K
68P_0402_50V8J
1
CSP2_4PH CSP1_4PH CSREF_2PH CSP1_2PH
PWM1_4PH/ICCMAX_4PH
PWM1_2PH/ICCMAX_2PH
12 28
H62@ PC1724
PC1725
220K_0402_5%_ERTJ0EV224J
PWM4_4PH/ROSC_MPH
2
1
CSP3_4PH CSP2_4PH CSP1_2PH
PWM2_2PH/ROSC_1PH
13 27 2 1
PC1726
PC1728
+5V_ALW Place close to Choke in VCCGT first phase circuit
2
1 2
CSP3_4PH CSP2_2PH
TTSENSE_1PH/PSYS
165K_0402_1%
PR1747 PC1723
2
1 2
2
PWM3_4PH/VBOOT
165K_0402_1%
113K_0603_1% PR1745
PWM2_4PH/ADDR
1 0.1U_0402_25V7K
2
1 2
PR1746
1K_0402_1% PC1727
<55,56> SW1_4PH
TTSENSE_2PH
PR1748
PR1750 0.1U_0402_25V7K
TSENSE_4PH
2
113K_0603_1% PR1749
CSP4_4PH
1 2 76.8K_0603_1%
<55,56> SW2_4PH
2
PR1751 1 2
SW1_2PH <55,58>
2
DRON
VRMP
113K_0603_1%
VCC
1 2
<55,57> SW3_4PH
PR1752
113K_0603_1% PR1753
14
15
16
17
18
19
20
21
22
23
24
25
26
H62@ 1 2 1K_0402_1%
<55,57> SW4_4PH
1 2 PC1729
CPU_B+ CSP4_4PH I_SYS <37,49>
0.1U_0402_25V6
CSREF_4PH PC1730 2 1 TSENSE_4PH PC1731
<56,57> CSREF_4PH
0.01U_0402_50V7K 0.1U_0402_25V6 PR1755
1 2 TSENSE_2PH 1 2 11.8K_0402_1% CSREF_2PH
CSREF_2PH <58>
1 2 1 2
+5V_ALW
1 2
<56,57,58> DRON PWM2_2PH/ROSC1
PR1757 PR1754 PR1756
1
7.68K_0402_1% 2.2_0603_5% 25.5K_0402_1%
1U_0603_10V6K
1 2 CSP1_4PH
PC1732
102K +-1% 0402

<55,56> SW1_4PH
1
2
2
H62@ PR1758
24.9K_0402_1%
97.6K_0402_1%
97.6K_0402_1%
4.3K +-1% 0402
PWM1_2PH/ICCMAX2 <58>
1
PC1733 @
PR1759
PR1760
PR1761
PR1762
0.022U_0402_25V7K PR1772 PR1763
1
1K_0402_1% 7.68K_0402_1%
2
CSP1_2PH 1 2
1
CSREF_4PH <56> PWM1_4PH/ICCMAX4 SW1_2PH <55,58>
2
PR1764
7.68K_0402_1% PR1776 PC1734
CSP2_4PH <56> PWM2_4PH/ADDR
1 2 @ 1K_0402_1% 0.022U_0402_25V7K
<55,56> SW2_4PH CFL-H62 (45W)
1
2
B IA: TDC=80A, Icc Max=128A, loadline=1.8mohm B
1
PC1735 @ CSREF_2PH
0.022U_0402_25V7K PR1773
<57> PWM3_4PH/VBOOT
GT: TDC=25A, Icc Max=32A, loadline=2.7mohm
1
1K_0402_1%
SA: TDC=10A, Icc Max=11.1A, loadline=10.3mohm
1
CSREF_4PH
<57> PWM4_4PH/ROSCM
PR1765
7.68K_0402_1% CFL-H42 (45W)
CSP3_4PH +5V_ALW
<55,57> SW3_4PH
1 2 IA: 86A, loadline=1.8mohm
2
PC1736 @
OCP
1
0.022U_0402_25V7K PR1774 H42@

1
TSENSE_4PH TSENSE_2PH
1K_0402_1% PR2007
1K_0402_1%
IA: 166A
GT: 42A
1
CSREF_4PH
1
1
PR1766 SA: 18.6A
2
7.68K_0402_1% PR1767 PR1768

<55,57> SW4_4PH
1 2 CSP4_4PH CSP4_4PH @ 0_0402_5% @ 0_0402_5% OVP
H62@ Place close to H-side,L-side MOS DAC+370mV
2
H62@ FAE required, 07/03 Place close to H-side,L-side MOS in VCCGT first phase
1 2
1 2
1
1
PC1737 @ Pop for H42@. 11/10
in VCORE first phase
0.022U_0402_25V7K PR1775
1
1K_0402_1% PH1703 PR1769 PH1704 PR1770

8.66K +-1% 0402 8.66K +-1% 0402
1
CSREF_4PH 220K_0402_5%_ERTJ0EV224J 220K_0402_5%_ERTJ0EV224J

2
2
2
A A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D NCP81215
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.5
LA-F711P
5 4 3 2 1
5 4 3 2 1
EMC@ PL1800 CPU_B+

+PWR_SRC 5A_Z80_0805_2P
1 2
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_25V7K
0.1U_0402_25V7K
EMC@ PL1801
1
PC1800 RF@
PC1801 RF@
PC1802 RF@
PC1803 RF@
5A_Z80_0805_2P
1 2 1
2
+ PC1804
Vinafix.com 100U 20V M D ESR55M TQC H2.8
15U_B2_25VM_R100M
2 1
2200P_0402_50V7K
0.1U_0402_25V7K
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
1
PC1826
+
PC1806 RF@
PC1807 RF@
D D
PC1808
PC1809
PC1810
PC1811
@ @
+5V_ALW
2
2
PR1800
2_0603_5%
1 2
2
PC2034
2
0.1U_0402_25V6
PC1812
1
1U_0603_25V7K PR1801 PC1813
1
3.9_0603_1% 0.22U_0603_25V7K 7x7x3
PU1800 1 2 1 2
3 8 Rdson=0.9mohm
15 VCC VIN 9 Irms=35A
VCCD VIN Isat=41A
17 5
THWN BOOT
1
16 7 PL1802
<55,56,57,58> DRON 1 DISB# PHASE
PC1814 0.15UH_MMD-06CZER15MEX5L__35A_20%
<55> PWM1_4PH/ICCMAX4 PWM
2.2U_0603_10V7K 2 11 CORE_SW1 1 4 +VCC_CORE
2
SMOD# SW 12
+5V_ALW SW 2 3
4 PR1802
10 CGND 10_0402_1%
14 PGND 1 2
13 PGND 6 CSREF_4PH <55,56,57>
19 GL NC 18
GL AGND
1
C EMC@ C
PC1815
NCP302045MNTXG_PQFN33_5X5 2200P_0603_50V7K
2
SW1_4PH <55>
1
EMC@
PR1803
1_1206_5%
2
CPU_B+
15U_B2_25VM_R100M
1
2200P_0402_50V7K
0.1U_0402_25V7K
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
1
1
PC1816 EMC@
PC1817 EMC@
PC1828
+
PC1818
PC1819
PC1820
PC1821
@ @
2
2
2
+5V_ALW
PR1804
2_0603_5%
B 1 2 B
2
PC2035
2
0.1U_0402_25V6
1
PC1822 PR1805 PC1823

1U_0603_25V7K 3.9_0603_1% 0.22U_0603_25V7K
1
1 2 1 2 7x7x3
PU1801
3 8 Rdson=0.9mohm
VCCD VIN Isat=41A
17 5
THWN BOOT
1
PC1824 16 7 PL1803
<55,56,57,58> DRON DISB# PHASE
1 0.15UH_MMD-06CZER15MEX5L__35A_20%
<55> PWM2_4PH/ADDR PWM
2
SMOD# SW 12
+5V_ALW SW 2 3
4 PR1806
10 CGND 10_0402_1%
PGND
1
14 EMC@ 1 2
13 PGND 6 PC1825 CSREF_4PH <55,56,57>
19 GL NC 18 2200P_0603_50V7K
2
GL AGND
NCP302045MNTXG_PQFN33_5X5
1
EMC@
PR1807 SW2_4PH <55>
1_1206_5%
2
A A

Issued Date 2017/01/01 Deciphered Date 2018/01/01 Title
+VCC_CORE_Phase1&2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.5
5 4 3 2 1
5 4 3 2 1
CPU_B+
15U_B2_25VM_R100M
1
2200P_0402_50V7K
0.1U_0402_25V7K
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
1
1
+
PC1920
PC1901 RF@
PC1902 RF@
PC1903
PC1904
PC1905
PC1906
@ @
2
2
+5V_ALW
Vinafix.com
D PR1900 D
2_0603_5%
1 2
2
PC2033
2
0.1U_0402_25V6
1
PC1900
1U_0603_25V7K PR1901 PC1907
1
3.9_0603_1% 0.22U_0603_25V7K 7x7x3
PU1900 1 2 1 2
3 8 Rdson=0.9mohm
VCCD VIN Isat=41A
17 5
THWN BOOT
1
16 7 PL1900
<55> PWM3_4PH/VBOOT PWM
2
SMOD# SW 12
+5V_ALW SW 2 3
4 PR1902
10 CGND 10_0402_1%
14 PGND 1 2
PGND CSREF_4PH <55,56,57>
1
13 6 EMC@
19 GL NC 18 PC1909
GL AGND 2200P_0603_50V7K
2
NCP302045MN_PQFN33_5X5
SW3_4PH <55>
1
C EMC@ C
PR1903
1_1206_5%
2
CPU_B+
15U_B2_25VM_R100M
1
2200P_0402_50V7K
0.1U_0402_25V7K
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
1
1
+
H62@EMC@ PC1910
H62@EMC@ PC1911
H62@ PC1912
H62@ PC1913
PC1914
PC1915
H62@ PC1922
+5V_ALW @ @
2
2
H62@
PR1904
2_0603_5%
1 2
2
H62@
2
H62@ PC2032
PC1916 0.1U_0402_25V6
1
1U_0603_25V7K
1
H62@ H62@
PR1905 PC1917
H62@ 3.9_0603_1% 0.22U_0603_25V7K 7x7x3
PU1901 1 2 1 2
B 3 8 Rdson=0.9mohm B
VCCD VIN Isat=41A
17 5 H62@
THWN BOOT
1
H62@ 16 7 PL1901
<55,56,57,58> DRON DISB# PHASE
PC1918 1 0.15UH_MMD-06CZER15MEX5L__35A_20%
<55> PWM4_4PH/ROSCM PWM
2
SMOD# SW 12
+5V_ALW SW 2 3 H62@
4 PR1906
10 CGND 10_0402_1%
14 PGND 1 2
13 PGND 6 CSREF_4PH <55,56,57>
19 GL NC 18
GL AGND
1
H62@EMC@
NCP302045MN_PQFN33_5X5 PC1919
2200P_0603_50V7K
2
SW4_4PH <55>
1
H62@EMC@
PR1907
1_1206_5%
2
A A

+VCC_CORE_Phase3&4
5 4 3 2 1
5 4 3 2 1
+PWR_SRC @ PJP2000
2 1 VCC_GT_B+
2 1
2200P_0402_50V7K
0.1U_0402_25V7K
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
1
1
PC2001 RF@
RF@
JUMP_43X118
PC2003
PC2004
PC2005
PC2006
PC2022
PC2023
100U 20V M D ESR55M TQC H2.8
1
2
+
PC1805
PC2002
+5V_ALW
Vinafix.com 2
D PR2000 D
2_0603_5%
1 2
2
PC2021
2
0.1U_0402_25V6
1
PC2000
1U_0603_25V7K PR2001 PC2007
1
3.9_0603_1% 0.22U_0603_25V7K
PU2000 1 2 1 2 7x7x3
3 8
15 VCC VIN 9 Rdson=0.9mohm
VCCD VIN Irms=35A
17 5 Isat=41A
THWN BOOT
1
16 7 PL2000
<55> PWM1_2PH/ICCMAX2 2 PWM 11 GT_SW1 1 4
2.2U_0603_10V7K
2
SMOD# SW
+5V_ALW SW
12 +VCC_GT
2 3
4 PR2002
10 CGND 10_0402_1%
14 PGND 1 2
PGND CSREF_2PH <55>
1
13 6 EMC@
19 GL NC 18 PC2009
GL AGND 2200P_0603_50V7K
2
NCP302045MN_PQFN33_5X5
SW1_2PH <55>
1
C EMC@ C
PR2003
1_1206_5%
14HU/HD is +PWR_SRC for layout routing
VCC_SA_B+
2
CPU_B+ @ PJP2001
VCC_SA_B+
15U_B2_25VM_R100M
2 1 1
2 1
2200P_0402_50V7K
0.1U_0402_25V7K
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
4.7U_0603_25VAK
1
1
PC2010 EMC@
PC2011 EMC@
+
PC2024
JUMP_43X118
PC2012
PC2013
PC2014
PC2015
+5V_ALW 2 @ @
2
2
PR2004
2_0603_5%
1 2
2
PC2016 PC2020
1U_0603_25V7K 0.1U_0402_25V6
1
PR2005 PC2017
3.9_0603_1% 0.22U_0603_25V7K 5.7x5.4x3
PU2001
1 2 1 2
3 8 Rdson=6.2mohm
15 VCC VIN 9 Irms=12.2A
VCCD VIN Isat=16A
B 17 5 B
THWN BOOT
1
16 7 PL2001
PC2018 0.47UH_MMD05CZR47M_12A_20%
<55> PWM1_1PH/ICCMAX1 2 PWM 11 SA_SW 1 4
2
SMOD# SW
2.2U_0603_10V7K
SW
12 +VCC_SA
2 3
4
10 CGND
14 PGND
13 PGND 6 CSN_1PH <55>
19 GL NC 18
GL AGND
1
EMC@
PC2019
NCP302045MN_PQFN33_5X5 2200P_0603_50V7K
2
SW_1PH <55>
1
EMC@
PR2006
1_1206_5%
2
A A

+VCC_GT/+VCC_SA
5 4 3 2 1
A
B
C
D
2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
2 1 2 1 PC1021 PC1162 PC1132 PC1103 PC1074 PC1111 PC1041
+VCC_CORE
330U_D2_2.5V_R6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
+VCC_CORE
PC800 PC821
@
@
2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 PC1022 PC1163 PC1133 PC1104 PC1075 PC1112 PC1042
5
5
PC801 PC822
@
@
2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 PC1171 PC1164 PC1134 PC1105 PC1076 PC1113 PC1043
PC802 PC823
@
@
2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
1U_0201_6.3V6M 1U_0201_6.3V6M
PC1165 PC1135 PC1106 PC1077 PC1114 PC1044
@
2 1 2 1 PC2026
Back Side.

PC803 PC824
@
@
2 1 2 1 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 1U_0201_6.3V6M
Primary Side.
2 1 2 1 PC1166 PC1136 PC1107 PC1078 PC1115 PC1045

1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC804 PC825
@
@
2 1 2 1 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 PC1167 PC1137 PC1108 PC1079 PC1116 PC1046
PC805 PC826
@
@
2 1 2 1 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 1U_0201_6.3V6M
VCC_CORE Place on CPU
2 1 2 1 PC1168 PC1138 PC1109 PC1080 PC1172 PC1047

PC806 PC827
@
@
2 1 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 PC1169 PC1139 PC1081 PC1173 PC1048
1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC819 PC828
@
@
@
2 1 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 PC1170 PC1140 PC1082 PC1174 PC1049
22U_0603 * 11 pcs+330u_D2*3 pcs
PC820 PC829
@
@
@
2 1 2 1 2 1 2 1
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 PC1141 PC1083 PC1175 PC1050
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC833 PC830
@
@
@
2 1 2 1 2 1 2 1
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 PC1142 PC1084 PC1176 PC1051
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC851 PC831
@
@
@
2 1 2 1 2 1 2 1
1U_0201_6.3V6M 1U_0201_6.3V6M
@
+VCC_CORE Place on CPU

2 1 2 1 PC1143 PC1085 PC1177 PC1052
4
4
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC852 PC832
@
@
@
2 1 2 1 2 1 2 1
1U_0201_6.3V6M 1U_0201_6.3V6M
PC1144 PC1086 PC1178 PC1053
1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1 2 1 2 1
1U_0201*24 pcs (placeholder)

Vinafix.com
Follow
PC1145 PC1087 PC1179 PC1054

1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1 2 1
22U_0603 * 13 pcs + 10U_0402*21 pcs + 1U_0201*24 pcs
PC1146 PC1180 PC1055

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1
Intel
PC1181 PC1056
22U_0603_6.3V6M 22U_0603_6.3V6M
Cout:
10uF * 7
1uF * 12
10uF*21
GT=470uF * 2
SA=22uF * 15
IA=330uF * 3, DY*1
10uF * 10, DY*5

22uF * 13, DY*6
1uF * 24, DY*24
22uF * 24, DY*8
3
3
Issued Date
+VCC_SA
Security Classification
2 1 2 1 2 1 2 1 2 1
2
1
+
PC834 PC815 PC848 PC1088 PC1023 PC1001

+VCC_GT
10U_0402_6.3V6M 22U_0603_6.3V6M 470U_X_2VM_R6M 1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1 2 1
2
1
+
PC835 PC816 PC849 PC1089 PC1024 PC1002

10U_0402_6.3V6M 22U_0603_6.3V6M 470U_X_2VM_R6M 1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1
PC836 PC817 PC1014 PC1090 PC1025 PC1003

@
2017/01/01
2 1 2 1 2 1 2 1 2 1 2 1
Back Side.
PC837 PC818 PC1015 PC1091 PC1026 PC1004

@

Primary Side.
2 1 2 1 2 1 2 1 2 1 2 1
PC838 PC807 PC1016 PC1092 PC1027 PC1005

@

2 1 2 1 2 1 2 1 2 1 2 1
@
VCC_GT Place on CPU
PC839 PC811 PC1017 PC1093 PC1028 PC1006

@

2 1 2 1 2 1 2 1 2 1 2 1
2
2
Compal Secret Data

PC840 PC810 PC1018 PC1094 PC1029 PC1007
@
Deciphered Date
2 1 2 1 2 1 2 1 2 1
PC812 PC1019 PC1095 PC1030 PC1008

@

2 1 2 1 2 1 2 1
22U_0603 * 7 pcs +470u_D2*2 pcs
PC808 PC1096 PC1031 PC1009

22U_0603_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC813 PC1097 PC1032 PC1010

2018/01/01
22U_0603_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M

@
2 1 2 1 2 1 2 1
Back Side.
PC809 PC1098 PC2027 PC1011

22U_0603_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
Primary Side.
@
2 1 2 1 2 1 2 1
22U_0603 * 5pcs
Reduce SA acoustic
PC841 PC1099 PC2028 PC1012

22U_0603_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1 2 1
@
VCC_SA Place on CPU
Title
Date:
PC842 PC2029 PC1013

Custom
22U_0603_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M

22U_0603 * 6 pcs +10U_0402*10 pcs +1U_0201*12 pcs
2 1 2 1
@
PC843 PC2030
22U_0603_6.3V6M 10U_0402_6.3V6M
@
2 1 2 1
LA-F711P
PC844 PC2031
Size Document Number
22U_0603_6.3V6M 10U_0402_6.3V6M
Thursday, January 18, 2018
22U_0603 * 10 pcs + 10U_0402*7 pcs
1
1
Sheet
PROCESSOR DECOUPLING
59
of
63
Rev
0.5
A
B
C
D
5 4 3 2 1
PD1202
5A 100V 15UA 0.88V TO227-3
2
DCIN_AC_Detector 1
3
@ PC1201
0.01UF_0402_25V7K
1 2
PD1801 S4 S5
Vinafix.com
+3.3V_VDD_DCIN BAT54CW_SOT323-3
+DC_IN +3.3V_VDD_DCIN 3 +3.3V_VDD_DCIN PQ1213 +VBUS_DC_SS PQ1202
AON7409_DFN8-5 AON7409_DFN8-5
1 LM393_P 1 1
+AC_IN 2 2
D 2 3 5 5 3 +SDC_IN D
+3.3V_VDD_PIC
1
0.47U_0402_25V6K
3
3
S S
PR1203 PR1251 PR1202
499K_0402_1%
1500P_0402_50V7K
4
4
1
1
G G
1.8M_0402_1% 2 2
PC1202
499K_0402_1%
300K_0402_5% 300K_0402_5%
1
1 2
PR1205
PR1207
PR1206
PC1203
2
2
2
2
1K_0402_1%
2
+3.3V_VDD_PIC
LM393_P
D D
240K_0402_1%
AO3409_SOT23-3
2
1
1
1
1
102K_0402_1%
2
PR1252
PQ1203
PR1201
AO3409_SOT23-3
1
+3.3V_VDD_PIC
PQ1215
PR1208
100K_0402_5%
PR1209
PU1201A
1
100K_0402_5%
49.9K_0402_1%
2
6 2
8
LM393DGKR_VSSOP8 PR1253 PR1213 PR1214
PR1212
3 100K_0402_5% 49.9K_0402_1% 100K_0402_5%
P
2
(>17.6V) + 1 HW_ACAVIN_NB
2 O HW_ACAVIN_NB <37,48,49,60>
PQ1214A
2
3 2
2
G
3
EN_PD_HV_1#
2
PR1218
23.2K_0402_1%
1200P_0402_50V7K
100P_0402_50V8J
220P_0402_50V8J
4
1
PR1220 0_0402_5%
PQ1204B
84.5K_0402_1%
<37,60> VBUS1_ECOK
1
1
1
0_0402_5% 5 2 @ 1
PQ1201B
PR1219
PC1205
PC1206
6
VBUS1_ECOK 2 @ 1 5
PR1217
PC1207
2
4
2
PQ1214B
PQ1201A
<29,60> EN_PD_HV_1
2
4
1
5 2
2
6
4
1
PR1222 PR1223
100K_0402_5% 0_0402_5%
PQ1204A
2
2 2 @ 1 AC_DISC# <37,48,60>
PR1262
100K_0402_5%
1
PC1204 +3.3V_VDD_PIC 1 2
0.1U_0402_25V6
2 1
1
@ PR1254
PR1210 0_0402_5% PR1216
1M_0402_5% 1 2 @ 0_0402_5%
@ PJP1202 2 1
1 2 PR1211
2
1 2
5
0_0402_5%
JUMP_43X118 1 @ 2 1
P
C <29,60> EN_PD_HV_1 B C
4
EMI Part (From TI GPIO1) 1 @ 2 2 O
+TBTA_Vbus_1 PQ1206 S3
G
EMC@ PL1201 A
5A_Z80_0805_2P AON7409_DFN8-5 PR1215 PU1200
3
1 2 1 0_0402_5% MC74VHC1G08DFT2G SC70 5P AND
2
1 2 +TBTA_Vbus_1 5 3
+TBTA_VBUS EMC@ PL1202
5A_Z80_0805_2P
100P_0402_50V8J
100P_0402_50V8J
100K_0402_5%
4
PQ1205
1
1000P_0402_50V7K
1500P_0402_50V7K
0.1U_0402_25V6
1
1
PR1221 L2N7002WT1G 1N SC-70-3

EMC@ PC1215
EMC@ PC1208
@EMC@ PC1209
PR1227
EMC@ PC1216
499K_0402_1%
2
0_0402_5%
D
1 2 3 1
PC1210
PR1228
2
2
1
<37> DCIN1_EN
2
+3.3V_ALW +3.3V_ALW +3.3V_ALW
G
1 2
1
100K_0402_5%
2
0_0402_5%
100K_0402_5%
2
PR1225
PR1226
PR1255 @ PR1231
PR1224
150K_0402_1% PR1235 PR1233 100K_0402_5%
PC1209 can't over 1000P
2
100K_0402_5% 100K_0402_5%
1
<37,48> VBUS2_ECOK 1 @ 2 @ @ AC_DISC# <37,48,60> CMOUT <49>
PR1242 0_0402_5% PR1245
<37,60> VBUS1_ECOK 1 @ 2 0_0402_5%
PR1257 0_0402_5% 1 @ 2
+3.3V_VDD_PIC
+3.3V_ALW
+TBTA_Vbus_1 +3.3V_VDD_PIC +3.3V_ALW
1
3
3
6
+3.3V_ALW D D D D
S3 OVP 2 5 2 5
PQ1211A
PQ1211B
PQ1210A
1500P_0402_50V7K
2
@ PD1205 G G G G
PQ1210B
1
30MA_30V_0.5UA_0.4V_SOD323-2 PR1229
1
2
1 2 +3.3V_VDD_PIC 49.9K_0402_1% PR1234
PC1217
100K_0402_1%
S S S S
2
4
4
1
100K_0402_5% +3.3V_ALW
2
PR1259
PR1237
1
1 @ 2 @ PR1260 100K_0402_5% @
2
PR1238 0_0402_5%
100K_0402_5%
2
2
0_0402_5% PR1236 1 2 D +3.3V_ALW
<29,60> EN_PD_HV_1
6
1
PR1230
150K_0402_1%
@ 100K_0402_5%
1
PR1240 PR1244 G
PQ1208A
3
2
LM393_P 100K_0402_1% PQ1209A 0_0402_5% D
PQ1208B
PR1239
B 2 DMN65D8LDW-7_SOT363-6 <29,49> AC1_DISC# 1 @ 2 5 S PROCHOT#_ISL88738 <49> B
1
G PR1232
2
PU1201B
3
100K_0402_5%
1
2
1
@ LM393DGKR_VSSOP8 PR1243 D D
S
L2N7002WT1G 1N SC-70-3
5 0_0402_5% @ PR1261 2 PQ1207A 2
PQ1216
P
+ 7 1 @ 2 5 PQ1209B 0_0402_5% G DMN66D0LDW-7_SOT363-6 G

1200P_0402_50V7K
100P_0402_50V8J
6 O 1 2 S
0.01UF_0402_25V7K
3
G
3
1
DMN65D8LDW-7_SOT363-6 D
100K_0402_1%
100K_0402_1%
S
100P_0402_50V8J
1
1
1 @ 2 5
PC1211
PC1213
<37,48,49,60> HW_ACAVIN_NB
4
1
G PQ1207B
PR1246
PR1247
PC1212
PC1214
PR1241 DMN66D0LDW-7_SOT363-6
2
0_0402_5% S
2
4
2
@
2
@ @ @
@
1 2
OVP set t i ng: 5. 5
V @ PR1258
0_0402_5%
L2N7002WT1G 1N SC-70-3
@ PR1248 PT1
1
D 0_0402_5% PAD~D
2 1 2 LPS_PROTECT#
PQ1212
(From EC)
G
1
S
3
PR1249
10K_0402_5% 1 @ 2 EN_PD_HV_1 <29,60>
PR1250 0_0402_5%
2
A A
Title
ParkCity_TypeC_PD
5 4 3 2 1
5 4 3 2 1
+1.0VALWP +PWR_SRC VIN_1VS_VCCIO +1VALWP_B+ +3.3V_ALWP
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
Vinafix.com
100P_0402_50V8J
100P_0402_50V8J
RF@ PC2036
RF@ PC2055
RF@ PC2037
RF@ PC2051
@RF@ PC2038
RF@ PC2039
RF@ PC2040
1
1
RF@ PC405
RF@ PC303
D D
2
2
3V_VIN 5V_VIN +1.2V_DDRP VCC_SA_B+
68P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
RF@ PC2048
RF@ PC2049
RF@ PC2050
RF@ PC2052
1
1
RF@ PC100
RF@ PC103
RF@ PC116
2
2
C C
CPU_B+
100P_0402_50V8J
100P_0402_50V8J
1
1
RF@PC2053
RF@PC2054
2
B B
A A

Title
RF CAP
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Item Date Reason for change Description Phase
1 2017/11/17 Follow Intel design Unpop PC1052 X02
Fine tune PSYS setting to 225W Unpop PR948, change PR1755 to 11.8K ohm
Fine tune PCH sequence Change PR312 to 15K ohm
2 2017/11/17 Update CPU VR circuit to support H42 CPU Change PC1705 to 2.2nF, PC1726 to 68pF, PR1749 to 76.8K, PR1730 to 2.05K, PR1727 to 1.78K,
Vinafix.com
Change PC1724 to 68pF for H62
Unpop PR1752, PR1766, PC1737, PC1910, PC1911, PC1912, PC1913, PC1916, PC1917, PC1918, PC1919, PC1922, PC2032,
X02
PL1901, PR1904, PR1905, PR1906, PR1907, PU1901

D
Pop PR2007 1K ohm D
3 2017/12/08 For RF requirement Add PC2053, PC2054, PC2055 X02

4 2018/01/04 Reserve for power on sequence modified Add PR2010 0ohm, Reserve PR2011, PR2012, modify 1.8V_PRIM_PWRGD to 1.8V_1.0V_PWRGD X02
5 2018/01/08 Change 0ohm to Short PAD Change PR26, PR29, PR21, PR22, PR23, PR20, PR19, PR25, PR960, PR920, PR922, PR926, PR928, PR951, PR947, PR935, X02
PR936, PR929, PR939, PR941, PR942, PR946, PR949, PR104, PR105, PR119, PR120, PR114, PR208, PR210, PR504, PR511,
PR513, PR314, PR315, PR402, PR414, PR1708, PR1710, PR1723, PR1726, PR1767, PR1768, PR1728, PR1735, PR1724,
PR1717, PR1238, PR1250, PR1211, PR1215, PR1216, PR1220, PR1218, PR1223, PR1242, PR1257, PR1244, PR1241, PR1245
to short PAD
Change JUMP to NPM footprint Change PJP901 to JUMP_43X118-NPM
C C
B B
A A
Title
PWR P.I.R
Size Document Number Re v
Custom 0.5
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request Issue Solution
Item Page# Title Date Owner Rev.
Description Description
1 all HW 2017/08/22 COMPAL 1. Add soft start solution(only reserved) on QV8,QZ1 0.2(X01)
(add CV1635, CZ1200, RZ1380,RV1400)
To avoid in-rush current caused voltage drop 2. Add soft start solution(only reserved) on QE15,QH7
(add CH340,RE565)"
3. reserve RV9, CV1638
2 4 HW 2017/08/22 COMPAL do NOT to use PEG reserved for UMA depop RC324 0.2 (X01)
3 37 HW 2017/08/22 COMPAL board ID

1.
2.
remove DZ10 Vinafix.com
Change RE79 to 130Kohm? (rev. X01)
add RZ381, QZ18, RH618

0.2 (X01)
3. add RH621, RH622, RH623, RH624 for PCH CNV_DET connect to EC GPIO054
D
4 35 HW 2017/08/22 COMPAL modify CLKREQ_CNV & detect pin circuit 4. depop RE562, RH330, RZ380 0.2 (X01) D
5. add RZ7 short to GND for Jngff1.13

6. add RE100, RE101 for CNV_DET_EC BOM option
5 21 HW 2017/08/22 COMPAL TPM Pin connectivity requirement Add RC560,RC561(reserved) BOM options. 0.2 (X01)
6 11 HW 2017/08/22 COMPAL External Power Gate control for C10. Add UZ61,CZ544,RZ542,RZ543, RH619, RH620 for 0.2 (X01)
7 35 HW 2017/08/22 COMPAL Intel PDG rev. 1.0 updated add RZ1381~RZ1384 for CNVi RSP & DT 0.2 (X01)
8 37 HW 2017/08/22 COMPAL GPIO map for EC Add RH625, RE566 for HDD_EN BOM option 0.2 (X01)
9 DELL sch. review depop RN5 0.2 (X01)

41 HW 2017/08/22 COMPAL
To avoid USB_POWERSHARE spike

10 37 HW 2017/08/22 COMPAL before EC stable when power up.(follow WH) reserve RE702 for USB_POWERSHARE_VBUS_EN 0.2 (X01)
VGA EA request 1. LV19, LV20 change to RV1650, RV1651(100 ohm) 0.2 (X01)
11 27 HW 2017/08/22 COMPAL 2. CV132, CV133 change to 2P
1. CH13, CH14 change to 15p
Xtal EA request 2. CE28, CE29 change to 12p (CE28 keep 10p for 15HD) 0.2 (X01)
12 all HW 2017/08/22 COMPAL 3. CV606, CV607 change to 18p
4. RV619 change to 1k
1. pop CA5, CV11, CZ62, CZ63, CZ64, CZ66, CZ67, CZ68,

13 all HW 2017/08/22 COMPAL RF request 2. add CI9 0.2 (X01)
3. change RZ85 to LZ2
14 eDP HW 2017/09/20 COMPAL touch screen soft start reserve reserve RV9, CV1638 0.2 (X01)
15 audio HW 2017/09/20 COMPAL aduio EA request depop CH268 0.2 (X01)
16 typeC SW HW 2017/09/20 COMPAL 1. depop RT136, RT142, RT144 0.2 (X01)

typeC EA request 2. pop RT307
17 EC HW 2017/09/20 COMPAL vendor request depop RE57 0.2 (X01)
18 eDP HW 2017/12/13 COMPAL battery life request RV625, RV630 change from 4.7k to 47k 0.3 (X01)
19 CPU&PCH HW 2017/12/13 COMPAL Intel guideline update 1. RH178, RH179, RH181, RH183, RH184 change from 0 ohm to 5 ohm
2. Add CC333(0603) for VCCPLL 0.3 (X01)
3. reserve RH626~RH637 & CH341~CH348 for PCH signal glitich free
C C
20 EC HW 2017/12/13 COMPAL follow EC request for X10 reserve RE703(0 ohm) between PCH to EC 0.3 (X01)
21 eDP HW 2017/12/13 COMPAL DELL request QV20.3 reserve RV1656 (0 ohm) to +3.3V_ALW 0.3 (X01)
22 CPU HW 2017/12/13 COMPAL ESD request 1. CC32, CC269 change BS from XDP@ to ESD@ 0.3 (X01)
2. add CC334, CC335 for +1.0V_VCCSTG
23 CPU HW 2017/12/13 COMPAL add short protection fot typeC add CT630~633, RT416~419 between re-timer and connector 0.3 (X01)
24 CNVi HW 2017/12/13 COMPAL intel MOW50 CNVi WP update RZ1382, RZ1384 change from 33 ohm to 22 ohm 0.3 (X01)
25 EC HW 2017/12/13 COMPAL board ID RE79 change to 62k 0.3 (X01)
26 TPM HW 2018/01/08 COMPAL TPM change to MP part UZ12 change CPN from SA0000AQ200 to SA0000AQ220 0.4 (X02)
27 EC HW 2018/01/08 COMPAL reserve for power on sequence modification 1.8V_PRIM_PWRGD rename to 1.8V_1.0V_PWRGD 0.4 (X02)
28 CPU HW 2018/01/08 COMPAL Intel PDG updated pop CC333 0.4 (X02)
29 typeC SW HW 2018/01/08 COMPAL USB3.1 Gen2 EA fail 14HU & 15HU typeC-SW change to parade solution 0.5 (X02)
B B
A A
EE P.I.R (1/1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Si ze
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.5
Custom
LA-F711P
Dat
Date:
e: Thursday, January 18, 2018 Sheet 63 of 63
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BR-MLK 15 CFL-H Uma MB ps8802 x02 20180118 For DELL

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5 4 3 2 1

Breckenridge MLK 15 UMA

REV : 0.5 (X02) C

XDP@ : XDP Component

NDS3@ : non Deep sleep support DELL CONFIDENTIAL/PROPRIETARY

Breckenridge MLK 15 UMA non-TBT Block Diagram

Vinafix.com Memory BUS (DDR4) DDR4-SO-DIMM X2

CRT CONN VGA DP TO VGA PS8330 USB3.0 Conn

HDA Codec Universal Jack

PCIE[6] PCIE[5] PCIE[17] PCIE[7] CNVi W25Q256

Smart Card TDA8034HN

C PCIE-7 JNGFF1-->M.2 2230(WLAN) 13 NA

S5 S4/AC ON OFF OFF

BATTERY AUD_PW R_EN

D +3.3V_ALW_PCH 200 DIMMB D

Trace width=5 mils

CFG5 30 CFG13 CFG8

XDP@ RC124 1 2 1K_0402_5% H_VCCST_PWRGD_XDP 39 GND12 GND13 40 PCH_XDP_CLK_DP

CFG0 XDP@ RC126 1 2 1K_0402_5% 46 1 ITP_PMODE_CPU <20> enable 0

BR27 XDP_OBS0 @ RC239 1 2 0_0402_5% XDP_OBS0_R

BPM#_0 BT27 XDP_OBS1 @ RC240 1 2 0_0402_5% XDP_OBS1_R

<16> H_PM_DOWN H_PECI PM_DOWN PROC_TMS CPU_XDP_TCLK PAD~D @ T180

RC319 1 2 0_0402_5% BN1 BP27

@RF@ CC325 33P_0402_50V8J

Issued Date Deciphered Date 2017/01/01 Title

RC5 1 2 121_0402_1% DDR_RCOMP0 G1 BN13

Trace width=12-15 mils

CPU_DP1_P0 K36 D29 EDP_TXP0

VSS_A36 RC178 1 2 0_0402_5%

VCCGT67 VCCGT146 UZ61 1

+VCC_CORE +VCC_CORE CFL-H

2 2 VCC38 AE30 VCC39 VCC102 AM34

VCC40 AE32 VCC41 VCC104 AM36

VCC57 AG32 VCC58 VCC121 AP37

DDR_A_D3 21 VSS10 DQ2 22

DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN DDR_A_D25

197 DQ40 VSS67 198 DDR_A_DQS#3

+3.3V_RUN_DIMM1 DDR_A_D29 207 VSS71 VSS72 208 DDR_A_D27

217 DQ49 DQ48 218

227 DQ55 VSS81 228 DDR_A_D52 +1.2V_MEM

Byte[0] DQ[7:0] DQS/DQS#[0] DDR_A_D58

Byte[1] DQ[15:8] DQS/DQS#[1] <7,15,20,41> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM1

* Byte[3] DQ[31:24] DQS/DQS#[3]

* Byte[5] DQ[47:40] DQS/DQS#[5]

149 150 DDR_B_BA0 <8>

DDR_B_D26 203 VSS69 VSS70 204 DDR_B_D31

+3.3V_RUN_DIMM2 213 DQ52 DQ53 214

223 DQS6_t VSS79 224 DDR_B_D55

DDR_B_D62 233 VSS84 DQ60 234

Byte[0] DQ[7:0] DQS/DQS#[0] <7,14,20,41> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM2

Byte[1] DQ[15:8] DQS/DQS#[1]

* Byte[3] DQ[31:24] DQS/DQS#[3] LCN_DAN05-Q0406-0103

Byte[4] DQ[39:32] DQS/DQS#[4]

CONTACTLESS_DET# B38 AH41 SATAGP0

SPSGP2 1 HDD_DET# 0=SATA 1=PCIE

SPSGP4 1 m3042_PCIE#_SATA 1=SATA 0=PCIE

SPSGP5 0 SPTAGP5 1=SATA 0=PCIE

YH1 RH44 RH153

PCH_SPI_D2_R1 @ RH353 1 2 33_0402_5% PCH_SPI_D2_1_R 3 6 PCH_SPI_CLK_1_R 18