Design Report 48V 12V
Design Report 48V 12V
Design Report 48V 12V
Schematic
Design Name: RF-IF Switch Power Supply VinMin: 48V VinMax: 50V Vout: 12V Iout: 2A Part: TPS54260
C5 U1 0.1uF L1 56uH
TPS54260
B360B D1
R6 140K
C9 10uF
1800pF C6 0.015uF
R3 412K
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VinMax: 50V
User Input Nominal
-
Vout: 12V
User Input Maximum
50.00
Calculated Minimum
-
Calculated Nominal
-
Calculated Maximum
-
1000
372.7
43.58
42.57
300
4.00
450
25
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VinMax: 50V
User Input Nominal
12.000
Vout: 12V
User Input Maximum
-
Calculated Minimum
11.543
Calculated Nominal
-
Calculated Maximum
12.471
240
38.9
2.000
0.100
0.713
0.723
2.700
-10
-22
60
67
243
244
25.1
26.2
684.1
1126.6
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Device
C3 (High Freq. Input Cap) C9 (Bulk Output Cap) L1 (Output Inductor) D1 (Catch Diode) U1 (Converter)
Rated Voltage
100V
Calculated Voltage
50.2V
16V
12.1V
3.5A
0.21A
44uW
60V 60V
50.2V 50.2V
2.4A 3A 4A
80C 67C
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Power Stage Gain Power Stage Phase Compensation Gain Compensation Phase Error Amp Gain Total Gain Total Phase
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VinMax: 50V
Part Number
Vout: 12V
Description
Package
GRM55E 2220 0603 0805 0805 0805 X5R SMB XL 0603 0603 0603 0603 0603 0603 0603
Area(mm) Height(mm)
31 2 3 3 3 6 18 144 2 2 2 2 2 2 2 16 2 1 1 1 1 2 3 8 1 1 1 1 1 1 1 1
Capacitor, Ceramic, 4.7uF, GRM55ER72A475KA01L 100V, 15% Standard Standard Standard Standard C3216X5R1C106KT B360B 744770156 Standard Standard Standard Standard Standard Standard Standard TPS54260 Capacitor, Ceramic, 0.01uF, 10V, 20% Capacitor, Ceramic, 0.1uF, 20V, 10% Capacitor, Ceramic, 0.015uF, 20V, 20% Capacitor, Ceramic, 1800pF, 20V, 20% Capacitor, Ceramic, 10uF, 16V, 10% Diode, Schottky, 60V, 3A Inductor, 56uH, 2.4A, 85m Resistor, SurfaceMount, 10.2K, 100mW, 1% Resistor, SurfaceMount, 10K, 100mW, 1% Resistor, SurfaceMount, 348K, 100mW, 1% Resistor, SurfaceMount, 412K, 100mW, 1% Resistor, SurfaceMount, 2.67K, 100mW, 1% Resistor, SurfaceMount, 140K, 100mW, 1% Resistor, SurfaceMount, 10K, 100mW, 1% IC, Converter, 10 pins
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TPS54260 The top layer contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are connections for the remaining pins of the TPS54260 and a large area filled with ground. The bottom layer contains ground and a signal route for the BOOT capacitor. The top and bottom and internal ground traces are connected with multiple vias placed around the board including six vias directly under the TPS54260 device to provide a thermal path from the top-side ground area to the bottom-side ground plane. The input decoupling capacitors (C2 and C3) and bootstrap capacitor (C5) are all located as close to the IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation, the copper VOUT trace past the output capacitors (C8 and C9). For the TPS54260, an additional input bulk capacitor may be required (C1), depending on the EVM connection to the input supply.
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