MCQ'S Practice

Question No: 1 ( Marks: 1 ) - Please choose one
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required
to shift
the value completely out of the register.
►1
►2
►4
►8
In a sequential circuit the next state is determined by ________ and _______
► State variable, current state
► Current state, flip-flop output
► Current state and external input
► Input and clock signal applied
The divide-by-60 counter in digital clock is implemented by using two cascading counters:
► Mod-6, Mod-10
► Mod-50, Mod-10
► Mod-10, Mod-50
► Mod-50, Mod-6
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is
maintained.
► True
► False
The minimum time for which the input signal has to be maintained at the input of flip-flop is called
______ of
the flip-flop.
► Set-up time
► Hold time
► Pulse Interval time
► Pulse Stability time (PST)
74HC163 has two enable input pins which are _______ and _________
► ENP, ENT ► ENI, ENC
► ENP, ENC
► ENT, ENI
____________ is said to occur when multiple internal variables change due to change in one input
variable
► Clock Skew
► Race condition
► Hold delay
► Hold and Wait
The _____________ input overrides the ________ input
► Asynchronous, synchronous
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
A decade counter is __________.
► Mod-3 counter
► Mod-5 counter
► Mod-8 counter
► Mod-10 counter
In asynchronous transmission when the transmission line is idle, _________
► It is set to logic low
► It is set to logic high
► Remains in previous state
► State of transmission line is not used to start transmission
A Nibble consists of _____ bits
►2
►4
►8
► 16
The output of this circuit is always ________.
►1
►0
► A Click here for detail
Excess-8 code assigns _______ to “-8”
► 1110
► 1100
► 1000
► 0000
The voltage gain of the Inverting Amplifier is given by the relation ________
► Vout / Vin = - Rf / Ri
► Vout / Rf = - Vin / Ri
► Rf / Vin = - Ri / Vout
► Rf / Vin = Ri / Vout
LUT is acronym for _________
► Look Up Table
► Local User Terminal
► Least Upper Time Period
► None of given options
The three fundamental gates are ___________
► AND, NAND, XOR
► OR, AND, NAND
► NOT, NOR, XOR
► NOT, OR, AND
The total amount of memory that is supported by any digital system depends upon ______
► The organization of memory
► The structure of memory
► The size of decoding unit
► The size of the address bus of the microprocessor
Stack is an acronym for _________
► FIFO memory
► LIFO memory
► Flash Memory
► Bust Flash Memory
Addition of two octal numbers “36” and “71” results in ________
► 213
► 123
► 127
► 345
___________ is one of the examples of synchronous inputs.
► J-K input
► EN input
► Preset input (PRE)
► Clear Input (CLR)
__________occurs when the same clock signal arrives at different times at different clock inputs due to
propagation delay.
► Race condition
► Clock Skew
► Ripple Effect
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter
counts
upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now
suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
► 0000
► 1101
► 1011
► 1111
In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs
► Current state and outputs
► Previous state and inputs
► Previous state and outputs
________ is used to simplify the circuit that determines the next state.
► State diagram
► Next state table
► State reduction
► State assignment
to
shift the value completely out of the register.
►1
►2
►4
►8
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100.
What
will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
► 1100
► 0011
► 0000
► 1111
► Look Up Table
. Question No: 28 ( Marks: 1 ) - Please choose one
The diagram given below represents __________
► Demorgans law
► Associative law
► Product of sum form
► Sum of product form
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
► Doesn’t have an invalid state
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
A multiplexer with a register circuit converts _________
► Serial data to parallel
► Parallel data to serial
► Serial data to serial
► Parallel data to parallel
A GAL is essentially a ________.
► Non-reprogrammable PAL
► PAL that is programmed only by the manufacturer
► Very large PAL

► Reprogrammable PAL
in ____________, all the columns in the same row are either read or written.
► Sequential Access
► MOS Access
► FAST Mode Page Access
In order to synchronize two devices that consume and produce data at different rates, we can use
_________
► Read Only Memory
► Fist In First Out Memory
► Flash Memory
► Fast Page Access Mode Memory
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
FINALTERM EXAMINATION
Spring 2010
to
►1
►2
►4
►8
A frequency counter ______________
► Counts pulse width
► Counts no. of clock pulses in 1 second
► Counts high and low range of given clock pulse
In a sequential circuit the next state is determined by ________ and _______
► State variable, current state
► Current state, flip-flop output
► Current state and external input
► Input and clock signal applied
► Mod-6, Mod-10
► Mod-50, Mod-10
► Mod-10, Mod-50
► Mod-50, Mod-6
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is
maintained.
► True
► False
Flip flops are also called _____________
► Bi-stable dualvibrators
► Bi-stable transformer
► Bi-stable multivibrators
► Bi-stable singlevibrators
______ of
the flip-flop.
► Set-up time
► Hold time
► ENP, ENT
► ENI, ENC
► ENP, ENC
► ENT, ENI
____________ is said to occur when multiple internal variables change due to change in one input
variable
► Clock Skew
► Race condition
► Hold delay
► Hold and Wait
Given the state diagram of an up/down counter, we can find ________
► The next state of a given present state
► The previous state of a given present state
► Both the next and previous states of a given state
► The state diagram shows only the inputs/outputs of a given states

A logic circuit with an output consists of ________.
► two AND gates, two OR gates, two inverters
► three AND gates, two OR gates, one inverter
► two AND gates, one OR gate, two inverters
► two AND gates, one OR gate
A decade counter is __________.
► Mod-3 counter
► Mod-5 counter
► Mod-8 counter
► Mod-10 counter
►2
►4
►8
► 16
►1
►0
►A
►F
Excess-8 code assigns _______ to “-8”
► 1110
► 1100
► 1000
► 0000
LUT is acronym for ________
► Look Up Table
DRAM stands for __________
► Dynamic RAM
► Data RAM
► Demoduler RAM
The three fundamental gates are ___________
► AND, NAND, XOR
► OR, AND, NAND
► NOT, NOR, XOR
► NOT, OR, AND
Which of the following statement is true regarding above block diagram?
► Triggering takes place on the negative-going edge of the CLK pulse
► Triggering takes place on the positive-going edge of the CLK pulse
► Triggering can take place anytime during the HIGH level of the CLK waveform
► Triggering can take place anytime during the LOW level of the CLK waveform
The total amount of memory that is supported by any digital system depends upon ______
► The organization of memory
► The structure of memory
► The size of decoding unit
► The size of the address bus of the microprocessor
The expression F=A+B+C describes the operation of three bits _____ Gate.
► OR
► AND
► NOT
► NAND
Stack is an acronym for_________
► FIFO memory
► LIFO memory
► Flash Memory
Addition of two octal numbers “36” and “71” results in ________
► 213
► 123
► 127
► 345
Spring 2010
The ANSI/IEEE Standard 754 defines a __________Single-Precision Floating Point format for binary
numbers.
► 8-bit
► 16-bit
► 32-bit
► 64-bit
The decimal “17” in BCD will be represented as _________
► 11101
► 11011
► 10111
► 11110
The basic building block for a logical circuit is _______
► A Flip-Flop
► A Logical Gate
► An Adder
The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1.
► Undefined
► One
► Zero (According to rule)
► No Output as input is invalid.
________ is invalid number of cells in a single group formed by the adjacent cells in K-map
►2
►8
► 12
► 16
The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder.
► AND
► OR
► NOT
► XOR
► J-K input
► EN input
___________ is one of the examples of asynchronous inputs.
► J-K input
► S-R input
► D input
propagation delay.
► Race condition
► Clock Skew
► Ripple Effect
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter
counts
upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now
suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
► 0000
► 1101
► 1011
► 1111

________ is used to minimize the possible no. of states of a circuit.
► State reduction
► State diagram
► State diagram
► State reduction
The best state assignment tends to ___________.
► Maximizes the number of state variables that don’t change in a group of related states
► Minimizes the number of state variables that don‟t change in a group of related states
► Minimize the equivalent states
►1
►0
►A
to

►1
►2
►4
►8
5-bit Johnson counter sequences through ____ states
►7
► 10
► 32
► 25
What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
► 1100
► 0011
► 0000
► 1111
The address from which the data is read, is provided by _______
► Depends on circuitry
► RAM
► Microprocessor
FIFO is an acronym for __________
► First In, First Out
► Fly in, Fly Out
► Fast in, Fast Out

► Look Up Table
______ of a D/A converter is determined by comparing the actual output of a D/A converter with the
expected
output.
► Resolution
► Accuracy
► Quantization
► Missing Code
Above is the circuit diagram of _______.
► Asynchronous up-counter
► Asynchronous down-counter
► Synchronous up-counter
► Synchronous down-counter
The sequence of states that are implemented by a n-bit Johnson counter is
► n+2 (n plus 2)
► 2n (n multiplied by 2)
► 2n (2 raise to power n)
► n2 (n raise to power 2)
Spring 2010
"A + B = B + A" is __________
► Demorgan‟s Law
► Distributive Law
► Commutative Law
► Associative Law
► Demorgans law
► Associative law
Following is standard POS expression
► True
► False
An alternate method of implementing Comparators which allows the Comparators to be easily cascaded
without the need for extra logic gates is _______
► Using a single comparator
► Using Iterative Circuit based Comparators
► Connecting comparators in vertical hierarchy
► Extra logic gates are always required.

Demultiplexer is also called
► Data selector
► Data router
► Data distributor
► Data encoder
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power
dissipation of
the flip-flop is
► 10 mW
► 25 mW
► 64 mW
► 1024
____________ counters as the name indicates are not triggered simultaneously.
► Asynchronous
► Synchronous
► Positive-Edge triggered
► Negative-Edge triggered
► ENP, ENT
► ENI, ENC
► ENP, ENC
► ENT, ENI
► Mod-6, Mod-10
► Mod-50, Mod-10
► Mod-10, Mod-50
► Mod-50, Mod-6
A synchronous decade counter will have _______ flip-flops
►3
►4
►7
► 10
________ is used to minimize the possible no. of states of a circuit.

► State reduction
► State diagram
The alternate solution for a demultiplexer-register combination circuit is _________
► Parallel in / Serial out shift register
► Serial in / Parallel out shift register
► Parallel in / Parallel out shift register
► Serial in / Serial Out shift register
► Very large PAL
►Reprogrammable PAL
►1
►0
► A Click here For detail rep
►
in ____________, all the columns in the same row are either read or written.
► Sequential Access
► MOS Access
► FAST Mode Page Access
► Fly in, Fly Out
_________
► Flash Memory

► n+2 (n plus 2)
►2
(2 raise to power n)
►n
(n raise to power 2)
► FIFO memory
► LIFO memory
► Flash Memory
The 4-bit 2‟s complement representation of “+5” is _____________
► 1010
► 1110
► 1011
► 0101
Spring 2010
The storage cell in SRAM is
►a flip –flop
►a capacitor
►a fuse
►a magnetic domain

What is the difference between a D latch and a D flip-flop?
►The D latch has a clock input.
►The D flip-flop has an enable input.
►The D latch is used for faster operation.
►The D flip-flop has a clock input. Click here for detail
For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will______ if the clock
goes HIGH.
►toggle Click here for detail
►set
►reset
►not change
The OR gate performs Boolean ___________.
►multiplication
►subtraction
►division
►addition
If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will
be
► set
► reset
► invalid
► clear
5. Determine the values of A, B, C, and D that make the sum term A(bar) + B+C(bar)+D equal to zero.
►A = 1, B = 0, C = 0, D = 0
►A = 1, B = 0, C = 1, D = 0 (Lecture 8)
►A = 0, B = 1, C = 0, D = 0
►A = 1, B = 0, C = 1, D = 1
The power dissipation, PD, of a logic gate is the product of the
►dc supply voltage and the peak current Click here for detail
►dc supply voltage and the average supply current
►ac supply voltage and the peak current
►ac supply voltage and the average supply current
A Karnaugh map is similar to a truth table because it presents all the possible values of input variables
and the resulting output of each value.
►True Click here for detail
►False
NOR Gate can be used to perform the operation of AND, OR and NOT Gate
►True
►False
Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer
►A parallel to serial converter circuit
►A counter circuit
►A BCD to Decimal decoder
►A 2-to-8 bit decoder
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
►4
►8
►12
►16

In designing any counter the transition from a current state to the next sate is determined by
►Current state and inputs
►Only inputs
►Only current state
►current state and outputs
Sum term (Max term) is implemented using ________ gates
►OR
►AND
►NOT
►OR-AND
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF
REGISTER AFTER THREE CLOCK PULSES?
►2
►4
►6
►8 (not sure)
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO
_________
►THE FLOP-FLOP IS TRIGGERED
►Q=0 AND Q‟=1

►Q=1 AND Q’=0
►THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED
If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop
►0
►1
►Invalid
►Input is invalid
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop
►0
►1
► Invalid
► Input is invalid
______ of the flip-flop.
►Set-up time
►Hold time
►Pulse Interval time
►Pulse Stability time (PST)
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ
and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by
___________
►Using S-R Flop-Flop
►D-flipflop
►J-K flip-flop
►T-Flip-Flop

A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output
status.
►3
►7
►8
►15
In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first
flip-flop of the shift register.
►Moore machine
►Meally machine
►Johnson counter
►Ring counter
The _________ of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip
after an address is applied at the address input lines
►Write Time
►Recycle Time
►Refresh Time
►Access Time
Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch
its
state
►Ten
►Eight
►Three
►Two

propagation delay.
►Race condition
►Clock Skew
►Ripple Effect
►None of given options
The alternate solution for a multiplexer and a register circuit is _________
►Parallel in / Serial out shift register
►Serial in / Parallel out shift register
►Parallel in / Parallel out shift register
►Serial in / Serial Out shift register
► FIFO memory
► LIFO memory
► Flash Memory
A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry
(Cout) when A = 1 and B = 1?
►= 0, Cout = 0
►= 0, Cout = 1
►= 1, Cout = 0
►= 1, Cout = 1
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________
►GATED FLIP-FLOPS
►PULSE TRIGGERED FLIP-FLOPS

►POSITIVE-EDGE TRIGGERED FLIP-FLOPS
►NEGATIVE-EDGE TRIGGERED FLIP-FLOPS
The design and implementation of synchronous counters start from _________
► Truth table
► k-map
► state table
► state diagram
THE HOURS COUNTER IS IMPLEMENTED USING __________
►ONLY A SINGLE MOD-12 COUNTER IS REQUIRED
►MOD-10 AND MOD-6 COUNTERS
►MOD-10 AND MOD-2 COUNTERS
►A SINGLE DECADE COUNTER AND A FLIP-FLOP
► Look Up Table
expected
output.
► Resolution
► Accuracy
► Quantization
► Missing Code
►State diagram
►Next state table
►State reduction
►State assignment
The high density FLASH memory cell is implemented using ______________
►1 floating-gate MOS transistor
►2 floating-gate MOS transistors
Q2 :=Q1 OR X OR Q3
The above ABEL expression will be
►Q2:= Q1 $ X $ Q3
►Q2:= Q1 # X # Q3 (
►Q2:= Q1 & X & Q3
►Q2:= Q1 ! X ! Q3
Generally, the Power dissipation of _______ devices remains constant throughout their operation.
►TTL
►CMOS 3.5 series
►CMOS 5 Series
►Power dissipation of all circuits increases with time.
When the control line in tri-state buffer is high the buffer operates like a ________gate
►AND
►OR
►NOT
►XOR
3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series.
►Low switching speeds, high power dissipation
►Fast switching speeds, high power dissipation
►Fast switching speeds, very low power dissipation
►Low switching speeds, very low power dissipation
Fall 2009
The output of an AND gate is one when _______
► All of the inputs are one
► Any of the input is one
► Any of the input is zero
► All the inputs are zero
The OR Gate performs a Boolean _______ function
► Addition
► Subtraction
► Multiplication
► Division
and the
resulting output of each value.
► True
► False
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the
output
levels?
► A > B = 1, A < B = 0, A < B = 1
► A > B = 0, A < B = 1, A = B = 0
► A > B = 1, A < B = 0, A = B = 0
► A > B = 0, A < B = 1, A = B = 1
NOT Gate level
OR Gate level
AND Gate level
The diagram above shows the general implementation of _____ form
► boolean
► arbitrary
► POS
► SOP
The device shown here is most likely a
► Comparator
► Multiplexer Click here for detail
► Demultiplexer
► Parity generator
Demultiplexer converts _______ data to __________ data
► Parallel data, serial data
► Serial data, parallel data
► Encoded data, decoded data
► All of the given options.
►0
►1
► Invalid
►0
►1
► Invalid
______ of
the flip-flop.
► Set-up time
► Hold time
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ
and
1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by
___________
► Using S-R Flop-Flop
► D-flipflop
► J-K flip-flop
► T-Flip-Flop
In asynchronous digital systems all the circuits change their state with respect to a common clock
► True
► False
A negative edge-triggered flip-flop changes its state when ________________
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power
dissipation of
the flip-flop is
► 10 mW
► 25 mW
► 64 mW
► 1024
propagation delay.
► Race condition
► Clock Skew
► Ripple Effect
A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output
status.
►3
►7
►8
► 15
A divide-by-50 counter divides the input ______ signal to a 1 Hz signal.
► 10 Hz
► 50 Hz
► 100 Hz
► 500 Hz
► Truth table
► k-map
► state table
► state diagram

►3
►4
►7
► 10
►1
►0
►A
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock
pulses?
►2
►4
►6
►8
In _______ the
output of the last flip-flop of the shift register is connected to the data input of the first flipflop.
► Moore machine
► Meally machine
► Johnson counter
► Ring counter
flip-flop
of the shift register.
► Moore machine
► Meally machine
► Johnson counter
► Ring counter
Which is not characteristic of a shift register?
► Serial in/parallel in
► Serial in/parallel out
► Parallel in/serial out
► Parallel in/parallel out
What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
► 1100
► 0011
► 0000
► 1111
The _________ of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip
after an
address is applied at the address input lines
► Write Time
► Recycle Time
► Refresh Time
► Access Time
► n+2 (n plus 2)
►2
(2 raise to power n)
►n
(n raise to power 2)
Fall 2009
NOR Gate can be used to perform the operation of AND, OR and NOT Gate
► FALSE
► TRUE
The output of an XNOR gate is 1 when ____________
I) All the inputs are zero
II) Any of the inputs is zero
III) Any of the inputs is one
IV) All the inputs are one
► I Only
► IV Only
► I and IV only
► II and III only
NAND gate is formed by connecting _________
► AND Gate and then NOT Gate
► NOT Gate and then AND Gate
► AND Gate and then OR Gate
► OR Gate and then AND Gate
Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND
gate
will be _____
► Zero
► One
► Undefined
► No output as input is invalid
The capability that allows the PLDs to be programmed after they have been installed on a circuit board is
called
__________
► Radiation-Erase programming method (REPM)
► In-System Programming (ISP)
► In-chip Programming (ICP)
► Electronically-Erase programming method(EEPM)
The ABEL symbol for “OR” operation is
►!
►&
►#
►$
►0
►1
► Invalid
For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________
►0
►1
► Q(t)
► Invalid
► True
► False
► J-K input
► S-R input
► D input
Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored
rectangle
in the circuit.
► AND
► NAND
► NOR
► XNOR
In ________ outputs depend only on the combination of current state and inputs.
► Mealy machine
► Moore Machine
► State Reduction table
► State Assignment table
► State diagram
► State reduction

In the following statement
Z PIN 20 ISTYPE „reg.invert‟;
The keyword “reg.invert” indicates ________
► An inverted register input
► An inverted register input at pin 20
► Active-high Registered Mode output
► Active-low Registered Mode output
►2
►4
►8
► 16
►1
►0
►A
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock
pulses?
►2
►4
►6
►8
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is
waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing
________.
► 1110
► 0111
► 1000
► 100
The high density FLASH memory cell is implemented using ______________
► 1 floating-gate MOS transistor
► 2 floating-gate MOS transistors
_________
► Flash Memory
If the FIFO Memory output is already filled with data then ________
► It is locked; no data is allowed to enter
► It is not locked; the new data overwrites the previous data.
► Previous data is swapped out of memory and new data enters

The process of converting the analogue signal into a digital representation (code) is known as
___________
► Strobing
► Amplification
► Quantization
► Digitization
Above is the circuit diagram of _______.
► Asynchronous up-counter
► Asynchronous down-counter
► Synchronous up-counter
► Synchronous down-counter
(A  B)(A  B  C)(A  C)
is an example of ______________
► Demorgans law
► Associative law
Q2 :=Q1 OR X OR Q3
The above ABEL expression will be
► Q2:= Q1 $ X $ Q3
► Q2:= Q1 # X # Q3
► Q2:= Q1 & X & Q3
► Q2:= Q1 ! X ! Q3
Fall 2009
Caveman number system is Base ______ number system
►2
►5
► 10
► 16
The output of an XOR gate is zero (0) when __________
I) All the inputs are zero
II) Any of the inputs is zero
III) Any of the inputs is one
IV) All the inputs are one
► I Only
► IV Only
► I and IV only
► II and III only
The decimal “17” in BCD will be represented as _________10001(right opt is not given)
► 11101
► 11011
► 10111
► 11110
and the
resulting output of each value.
► True
► False
The simplest and most commonly used Decoders are the ______ Decoders
► n to 2n
► (n-1) to 2n
► (n-1) to (2n-1)
► n to 2n-1
The _______ Encoder is used as a keypad encoder.
► 2-to-8 encoder
► 4-to-16 encoder
► BCD-to-Decimal
► Decimal-to-BCD Priority
3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
► True
► False
►0
►1
► Invalid
If the S and R inputs of the gated S-R latch are connected together using a ______gate then there is only
a
single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)
► AND
► OR
► NOT
► XOR
► True
► False
The low to high or high to low transition of the clock is considered to be a(n) ________
► State
► Edge
► Trigger
► One-shot
RCO Stands for _________
► Reconfiguration Counter Output
► Reconfiguration Clock Output
► Ripple Counter Output
► Ripple Clock Output
Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch
its state
► Ten
► Eight
► Three
► Two
► J-K input
► S-R input
► D input
propagation delay.
► Race condition
► Clock Skew
► Ripple Effect
A transparent mode means _____________
► The changes in the data at the inputs of the latch are seen at the output
► The changes in the data at the inputs of the latch are not seen at the output
► Propagation Delay is zero (Output is immediately changed when clock signal is applied)
► Input Hold time is zero (no need to maintain input after clock transition)
In ________ outputs depend only on the current state.
► Mealy machine
► Moore Machine

The alternate solution for a demultiplexer-register combination circuit is _________
Smallest unit of binary data is a ________
► Bit
► Nibble
► Byte
► Word
►2
►4
►8
► 16
► Very large PAL
► Reprogrammable PAL
to shift
►1
►2
►4
►8
► Dynamic RAM
► Data RAM
► Demoduler RAM
► Fly in, Fly Out
Question No: 28 ( Marks: 1 ) - Please choose one (Diagram is missing)

In the circuit diagram of 3-bit synchronous counter shown above, The red rectangle would be replaced
by
which gate?
► AND
► OR
► NAND
► XNOR
► n+2 (n plus 2)
► 2n (2 raise to power n)
► n2 (n raise to power 2)
► FIFO memory
► LIFO memory
► Flash Memory
Fall 2009
► Demorgans law
► Associative law
Excess-8 code assigns _______ to “+7”

► 0000
► 1001
► 1000
► 1111
NOR gate is formed by connecting _________
► OR Gate and then NOT Gate
► NOT Gate and then OR Gate
► AND Gate and then OR Gate
► OR Gate and then AND Gate
A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout)
when A = 1 and B = 1?
►= 0, Cout = 0
►= 0, Cout = 1
►= 1, Cout = 0
►= 1, Cout = 1
A particular half adder has
► 2 INPUTS AND 1 OUTPUT
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT
MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT __________ GATE
► AND
► OR
► NAND
► XOR
A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY
THE MANUFACTURER.
► TRUE
► FALSE
► J-K input
► EN input
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________
► GATED FLIP-FLOPS
► PULSE TRIGGERED FLIP-FLOPS
► POSITIVE-EDGE TRIGGERED FLIP-FLOPS

► NEGATIVE-EDGE TRIGGERED FLIP-FLOPS
► Truth table
► k-map
► state table
► state diagram
THE HOURS COUNTER IS IMPLEMENTED USING __________
► ONLY A SINGLE MOD-12 COUNTER IS REQUIRED
► MOD-10 AND MOD-6 COUNTERS
► MOD-10 AND MOD-2 COUNTERS
► A SINGLE DECADE COUNTER AND A FLIP-FLOP
In ________ outputs depend only on the current state.
► Mealy machine
► Moore Machine
►3
►4
►7
► 10
►Parallel in / Serial out shift register
►Serial in / Parallel out shift register
►Parallel in / Parallel out shift register
►Serial in / Serial Out shift register
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF
REGISTER AFTER THREE CLOCK PULSES?
►2
►4
►6
►8
to shift
►1
►2
►4
►8
5-BIT JOHNSON COUNTER SEQUENCES THROUGH ____ STATES
►7
► 10
► 32
► 25
flip-flop of the shift register.
►Moore machine
►Meally machine
►Johnson counter
►Ring counter
► Dynamic RAM
► Data RAM
► Demoduler RAM
If the FIFO Memory output is already filled with data then ________
► It is locked; no data is allowed to enter
► It is not locked; the new data overwrites the previous data.
► Previous data is swapped out of memory and new data enters
► Look Up Table

expected
output.
► Resolution
► Accuracy
► Quantization
► Missing Code
Question No: 27 ( Marks: 1 ) - Please choose one (Diagram is missing)
In the circuit diagram of 3-bit synchronous counterThe red rectangle, shown above would be replaced
which
gate?
► AND
► OR
► NAND
► XNOR
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO -------
__
► THE FLOP-FLOP IS TRIGGERED
► Q=0 AND Q‟=1
► Q=1 AND Q‟=0
► THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED

► FIFO memory
► LIFO memory
► Flash Memory

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Question No: 1 ( Marks: 1 ) - Please choose one

the value completely out of the register.

Question No: 2 ( Marks: 1 ) - Please choose one

In a sequential circuit the next state is determined by ________ and _______

► State variable, current state

► Current state, flip-flop output

► Current state and external input

► Input and clock signal applied

Question No: 3 ( Marks: 1 ) - Please choose one

Question No: 4 ( Marks: 1 ) - Please choose one

Question No: 5 ( Marks: 1 ) - Please choose one

► Pulse Interval time

► Pulse Stability time (PST)

Question No: 6 ( Marks: 1 ) - Please choose one

► ENP, ENT ► ENI, ENC

Question No: 7 ( Marks: 1 ) - Please choose one

► Hold and Wait

Question No: 8 ( Marks: 1 ) - Please choose one

The _____________ input overrides the ________ input

► Preset input (PRE), Clear input (CLR)

► Clear input (CLR), Preset input (PRE)

Question No: 9 ( Marks: 1 ) - Please choose one

A decade counter is __________.

In asynchronous transmission when the transmission line is idle, _________

► It is set to logic low

► It is set to logic high

► Remains in previous state

► State of transmission line is not used to start transmission

Question No: 11 ( Marks: 1 ) - Please choose one

A Nibble consists of _____ bits

Question No: 12 ( Marks: 1 ) - Please choose one

The output of this circuit is always ________.

► A Click here for detail

Question No: 13 ( Marks: 1 ) - Please choose one

Excess-8 code assigns _______ to “-8”

Question No: 14 ( Marks: 1 ) - Please choose one

Question No: 15 ( Marks: 1 ) - Please choose one

LUT is acronym for _________

► Local User Terminal

► Least Upper Time Period

► None of given options

Question No: 16 ( Marks: 1 ) - Please choose one

The three fundamental gates are ___________

► AND, NAND, XOR

► OR, AND, NAND

► NOT, NOR, XOR

► NOT, OR, AND

Question No: 17 ( Marks: 1 ) - Please choose one

► The organization of memory

► The structure of memory

► The size of decoding unit

► The size of the address bus of the microprocessor

Question No: 18 ( Marks: 1 ) - Please choose one

Stack is an acronym for _________

Question No: 19 ( Marks: 1 ) - Please choose one

Addition of two octal numbers “36” and “71” results in ________

Question No: 20 ( Marks: 1 ) - Please choose one

___________ is one of the examples of synchronous inputs.

► Preset input (PRE)

In a sequential circuit the next state is determined by __ and _

The _____ input overrides the input

In a sequential circuit the next state is determined by __ and _