Lecture 04 ARM Cortex-M4 Processor

Dr. Tushar, Mosaddek Hossain Kamal

Professor

Computer Science and Engineering, University of Dhaka,

BSc Third Year, Semester 2 (July – Dec), Academic Year: 2022

CSE3201: Operating Systems

August 16, 23, 2022

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Outline

1 Learning Outcome

2 A look at Cortex-M4 Processor

Cortex-M4 Execution Mode
Cortex-M4 Core Registers

3 Cortex-M4 Memory Model

MPU – Memory Protection Unit
Cortex-M4 Core Peripheral Units: SysTick

4 Nested Interrupt Vector Controller (NVIC)

Interrupt Management

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Learning Outcome

Learning Outcome
Understand the Cortex-M4 Processor Major Components
NVIC, SysTick, FPU, Special Registers, and so on
Real-time clock
Understand the use of Cortex-M4 lower level programming:
System call, Task and Memory management
thread, Synchronization tools
Exception handling
Understanding ARM Memory map and address space
Flash memory, SRAM
Peripheral address space
Kernel stack frame and process/task stack frame

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A look at Cortex-M4 Processor

ARM Cortex-M4 Architecture Cortex-M4 Architecture

Cortex-M4 Core
Nestetd Interrupt Vector (NVIC)
Memory Protection Unit (MPU)
Optional Floating Point Unit (FPU)
Flash Patch Break Point (FPBP)
Data Watch Point and Trace (DWT)
AHB Access Port (AHB-AP)
Bus Matrix
Instrumentation Trace Microcell (ITM)

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Cortex-M4 Processor – FPBP

Cortex-M4 Processor Components – FPBP

Flash Patch Break Point (FPBP)
Hardware Break Point
Generates a bp event for debug modes
Breakpoint code executed – Halt
Debug monitor exception – debug
monitor
View register’s content, memory
contents, debug using single stepping
To reduce the cost of one-time
programmable memory - ROM
Small system programmable memory
to apply the patch
costly to replace whole ROM – a bug
in the program
Not required when erasing the whole
flash and reprogrammable

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Cortex-M4 Processor Core

Data Watch Point and Trace (DWT) unit

Counts execution cycle and Cycle Per Instruction

AHB Access Port (AHB-AP)

Optional Debug Access Port (SW-DP or SWJ-DP used to access)
Provide Access to all memory and register in the system
mater into Bus-Matrix
Bus Matrix
Arbitrates accesses to both the external memory system and to the
internal System Control Space (SCS) and debug components,
support ARMv7 unaligned accesses, and performs all accesses as
single, unaligned accesses

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Instrumentation Trace Microcell (ITM)

Instrumentation Trace Microcell (ITM) A hardware unit can

transfer diagnostic data of two main types: Debug events generated by
the DWT unit, such as exception events and data watchpoint events.
Software instrumentation (SWIT) events, i.e., custom data logged by
your code. see: Technical Reference Manual

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Cortex-M4 Execution Mode
Processor mode and privilege levels for software execution
Thread mode
Used to execute application software
Enters after reset
Control Register controls: execute in privileged or unprivileged
Handler mode
Used to handle exceptions, execution always in privileged mode
returns thread mode after finishing exception procession
Privileged Level
Unprivileged
limited access: MSR and MRS instructions
no access to CPS instruction, System Timer, NVIC, SCB
restricted Access to memory or peripherals
Must use SVC call to transfer control to privileged
Privileged
Can access all instructions and resources
Can modify CONTROL register to change the privileged level

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Cortex-M4 Core Registers

Figure 1: Processor Core Registers

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Cortex-M4 Core Registers

Figure 2: See STM32F-Programming Manual Pages

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Cortex-M4 Core Registers

R0-R12: General Purpose Register for Data Operation

R13: SP Stack Pointer, Based on Control Register Value – bit[1]
‘0’: Main Stack Pointer (MSP)
‘1’: Process Stack Pointer (PSP)
On reset processor load address ‘0x00000000’ in MSP
R14: Link Register (LR)
Stores subroutine return address; Reset Value: ‘0xFFFFFFFF’
R15: PC; on reset load (Reset Vector): ‘0x00000004’
Program Status Register (PSR)
Application Program Status Register (APSR)
Interrupt Program Status Register (IPSR)
Execution Program Status Register (EPSR)
Bit[]

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Program Status Register

Figure 3: xPSR

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Cortex-M4 Core Registers
PRIMASK
Prevent activation of all Exception with configurable priority
Bit[0]: ‘0’: not effect; ‘1’ masking all priority configurable exception
FAULTMASK
Prevent activation of all Exception except NMI
Bit[0]:‘0’ no effect; ‘1’: prevent from activation except NMI
BASEPRI
µp does not process exception priority value greater than BASEPRI
Bits[7:4]: ‘0x00’ – no effect; NonZero: the lower priority value
CONTROL Register – controls
Stack use (MSP, or PSP)
Privilege level
Bit[2] FPCA: floating point context currently active. ‘0’: No
floating-point context active
Bit[1]: SPSEL: stack pointer section. ‘0’: MSP, ‘1’: PSP
nPRIV – Thread mode privilege level. ‘0’: privilege mode; ‘1’:
unprivileged mode
these
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Contex-M4 Stack

Cortex-M4 Stack
Full descending stack, insert decrements the address
Two stack
Main Stack
Process Stack
Control Register bit[1] determines current stack usage

Figure 4: Processor mode, execution, and stack

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Cortex-M4 Memory Model

4GB of fixed memory

address
Memory-Mapped I/O
Bit-Banding provides
automatic operation
to bit data

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Memory Protection Unit

MPU split memory into regions defines memory type and

attributes
Memory Type Description
Normal The processor can re-order transactions for effi-
ciency, or perform speculative reads.
Device The processor preserves transaction order rela-
tive to other transactions to Device or Strongly-
ordered memory.
Strongly-ordered The processor preserves transaction order rela-
tive to all other transactions
Additional memory attributes: Execute Never (XN): Processor
prevents instruction to access memory; otherwise causes a memory
fault

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Odering Memory Access

Memory access ordering: instruction A1 Appears before instruction

A2. µP does not guarantee access order. It must ensure using the
memory barrier (DMB, DSB, and ISB).

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Behavior of Memory access
For more, see page 30 Cortex-M4 programming manual

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Cortex-M4 Core Peripheral Units: SysTick timer
Textbook Page: 312
Cortex-M4 Small integrated timer – System Tick
A part of the NVIC
Generate SysTick Exception
We need it for context-switch to execute tasks in the different time
schedule
unprivileged application cannot disable the timer
Inside the processor – for portability

SysTick Registers
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SysTick – System Clock

24-bit decrement counter

SYSTICK Control Reg
Decrement using processor
COUNTFLAG –
clock or reference clock
Status(R), ‘1’ if count
reaches ‘0’
CLKSOURCE –
Conf.(RW) ‘1’ if use core
clock, ‘0’ for external clock
TICKINT – ‘1’ enable
systick interrupt
ENABLE – ‘1’ enable
Reload Reg(RW). bit[23:0] SYSTICK Timer.
24-bit reload value

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SysTick – System Clock

SYSTICK Current Reg (RWc)

Read the current value of SYSTICK Calibration Reg (R)
the timer bit[31] – no external reff.
Write ‘0’ to clear clock
bit[30] – ‘1’ calibration
value is not exactly 10ms
otherwise accurate
bit[23:0] – calibration value
for 10ms (reload value
required )

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SysTick – System Clock

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SysTick Timer
How to use
Disable the timer before the configuration; it is optional (disable if
configured before)
SysTick CTRL register set to ‘0’
Set the reload value to SysTick Load Register, must one less the
targeted value
Set current val to ‘0’, VAL register
Enable SysTick to use processor or external clock
Finally, Enable SysTick Timer
Use bit-0 to enable and disable the counter anytime

Tick Counter
Enable interrupt to send signal/interrupt to process or current
process
A counter or variable update to count the tick or time.
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Exception and Interrupt

Nested Interrupt Vector Controller (NVIC)

Interrupt Sources are hardware like pins, I/O,
and peripherals. There are software Interrupts
Interrupt Processing Sequence (e.g.,
peripheral)
The peripheral asserts an interrupt
request to the processor
The processor suspends the currently
executing task
The processor executes an Interrupt
Service Routine (ISR) to service
The processor resumes the previously
suspended task
Exceptions events includes interrupt

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Exception Types

Cortex-M3 and Cortex-M4 have different numbers of interrupts (1-240)

and priority

System Exception [1-15]

1-15 Exceptions are system internal those including
Reset, NMI. HardFault, MemFault, BusFault SVC, SYSTICK,
PenSV
Priority for Reset, NMI, and HardFaults are not alterable, and they
are -3, -2, and -1

External Interrupt [16+]

1-15 Exceptions are system internal those including
All other interrupts are external to the processor
Priority for these are programmable

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Interrupt Management
A set of Registers for Interrupt Management in Cortex-M
processor
Registers are inside NVIC and SCB
Physically SCB is implemented as a part of NVIC
CMSIS-core defines these registers in separate data structure
Special register in processor core such as PRIMASK,
FAULTMASK, and BASEPRI
NVIC and SCB are located inside SCS (System Control Space)
starting from 0xE000E000 (4KB)
SCS contains SysTick, MPU, Debug registers, and so on.
privileged mode can access these registers.
However, Software Trigger Interrupt Register (STIR) can be set
up to access from an unprivileged mode
Reset disable all interrupts with priority-level ‘0’

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Interrupt Management – enabling and using interrupt(s)
Before using interrupt, you need to
Set up the priority of the targeted interrupt
void NVIC SetPriority (IRQn Type IRQn,uint32 t priority)
Enable the interrupt generation control in the peripheral that
triggers the interrupt
Enable IRQ bit of a peripheral such as U SART 2− > CR1|= 1 << 7
Enable the interrupt in the NVIC
void NVIC EnableIRQ (IRQn Type IRQn)
When interrupt triggers corresponding ISR executes
USART2 Handler()
You may need to clear the interrupt in the service routine
Startup code contains ISR in the vector table
(uint32 t) &USART2 Handler
If not, detail the ISR (weak!! definition) – before using it.
void USART2 Handler(void) attribute ((weak,
alias(“Default Handler”)));
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Interrupt Priority Management

Interrupts are executed according to the priority

higher priority interrupt executed and preempt lower priority
(higher priority number) interrupt
Nested interrupt
Some interrupts has fixed priority (-Negative)– you cannot change
such as Reset, NMI, HardFault
Cortex-M4/M3 Support three fixed highest-level priority and up
to 256 level programmable interrupt (128-preemptable)
Other exception has programmable priority from 0 to 255 with 128
preemptive priority
Chip designer decides to reduce the complexity of the NVIC

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Interrupt Registers ARMv7

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Interrupt Priority Management
Interrupt Priority and Setting
Cortex-M4 has 1-byte (8-bits) for priority of the interrupt
Stm32F4xx implements 4-MSB of the 8-bits (LSB-3:0 is always ‘0’)
In reality we do not need more priority (256!)
Therefore, 16-priority level 0x00, 0x10, 0x20, · · · 0xF0
Each 32-bit register presents 4-Interrupt priority; thus
PRI0-PRI59, total 60 registers
Address Range 0xE000E400-0xE000E4EF: total 240 bytes

Figure 6: Cortex-M4 Priority Register

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Interrupt: Grouping, Preemption and Sub-Priority
Priority Group, Pre-empt and Sub-priority
The priority bits are divided into two halve
Preempt priority and sub-priority
Above 4-bit priority: such 2-bit for preempt priority and lower 2-bit
sub-priority
the upper half also known as priority grouping level
Register AIRCR in SCB is used to determine the number of bits
for priority prouping

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Interrupt Enable Register

Interrupt Set Enable Register

Address: 0xE000E100 to 0xE000E11C – NVIC ISER[0] –
NVIC ISER[7]
Example: to enable interrupt 45, calculation for selecting register
and bit position
ISER = N V IC ISER[45/32] or N V IC ISER[45 >> 5] or and
bit position = N V IC ISER[45%32]

Figure 7: Enable Interrupt ‘7’ writing ‘1’ in the shaded region

CMSIS function void NVIC EnableIRQ(IRQn Type IRQn)

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Interrupt Clear Enable Register

Interrupt Set Clear Enable Register

Address: 0xE000E180 to 0xE000E19C – NVIC ICER[0] –
NVIC ICER[7]
Example: to clear enable interrupt 45, calculation for selecting
register and bit position
ICER = N V IC ICER[45/32] or N V IC ICER[45 >> 5] or and
bit position = N V IC ICER[45%32]

Clear interrupt enable bit of ISER register. CMSIS function void

NVIC DisableIRQ(IRQn Type IRQn)

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Interrupt Pending and Clear Pending
Interrupt Pending and Clear Pending
Another interrupt arrives while executing a higher priority
interrupt
The interrupt is pending, and the corresponding bit of Interrupt
Set Pending Register is ‘1’
Clear the interrupt pending bit when a waiting interrupt is active.
completion of an interrupt ISR should clear the active bit

Figure 8: Interrupt Pneding and Clear Register

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Interrupt Active Register

Interrupt Active Register

The active interrupt bit is set when the ISR starts executing
Completion of ISR disable or reset active-bit in the Interrupt
Active bit register (IABR)
IABR is the status register presenting the status of an interrupt

Figure 9: Interrupt Active Register

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Interrupt Life Cycle
Exception/interrupt State
Inactive: The exception is not active or inactive. If a higher priority interrupt
preempts a lower priority active interrupt
Pending: When an interrupt waiting to finish a higher priority or the same group
interrupts in an active state
Active: Currently serving by the processor
Active and Pending: The MCU serves the exception by the processor, and there is a
pending exception from the same source

Figure 10: IRQ’s arrives one after another

Note: When an exception/interrupt occur microprocessor pushes (stacking) register PC,

R0-R3, R12, LR, xPSP and FPU (if FPU active) registers. For sequential interrupts instead
of pop and push operation it is enough to just change the LR and PC
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Interrupt Life Cycle
For an IRQ, the registers listed earlier are stacking. However, if the
ISR overwrites or uses other registers, the developer should take care.

Figure 11: IRQ Life Cycle

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Arm Cortex-M Interrupt and Masking

Sometime the system/application need to disable (Mask) some or all

interrupt to carryout a critical task
Disable or Masking Interrupts
SCB contains three special registers for masking interrupt: (i)
PRIMASK, (ii) FAULTMASK, and (iii) BASEPRI
PRIMASK, a 32 bit register. Bit position ‘0’ is available other bits
are reserved.
Set PRIMASK disable (put mask on) all interrupts except
Hardfault and NMI
void disable irq(); //Set PRIMASK
Clearing PRIMASK disable masking or take-off mask on all
interrupts except Hardfault and NMI
void enable irq(); // Clear PRIMASK
void set PRIMASK(uint32 t priMask); // Set PRIMASK to value
uint32 t get PRIMASK(void); // Read the PRIMASK value

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ARM Cortex-M Interrupt and Masking
Disable or Masking Interrupts
FAULTMASK – same as PRIMASK however it can mask all
interrupts other than NMI
Related functions (you will write) are:
void enable fault irq(void); // Clear FAULTMASK void
disable fault irq(void); // Set FAULTMASK to disable interrupts
void set FAULTMASK(uint32 t faultMask);
uint32 t get FAULTMASK(void);
BASEPRI – 32-bit register, however, only 8-bit is currently
available
The register mask interrupts based on priority,
Writing ‘0’ cancel the masking
use to disable interrupt lower than a certain interrupt level
Writing 0x20 disable interrupts with priority value 0x20 and higher
(lower priority)
Related Functions: set BASEPRI(uint32 t value); // Disable
interrupts with priority // ≥ value
set BASEPRI(0x0); // Turn off BASEPRI masking
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Interrupt Program Status Register (IPSR)

Interrupt Program Status Register (IPSR)

IPSR contains the exception type number of the current Interrupt
Service Routine (ISR) Such as (This is the number of the current
exception)
0: Thread mode
1: Reserved
2: NMI
3: Hard fault
4: Memory management fault
5: Bus fault
6: Usage fault
7: Reserved
···
10: Reserved
11: SVCall
12: Reserved for Debug
and so on · · ·

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