VHDL for Designers 1 wwwrdoulos.comVHDL for Designers a fe. DOULOS ent 2005-2016 by Onn Ath Reeves ‘ita ety tr mcrae pe, ea aN robot ‘Ser eman ts apr of Onocs expect ower ane ro apes ay ‘Sihoe conven mates onan exes aoe mwrangby Ocsos US Dac ts get aan den anata naar 0 esr they a ‘lac nf sua motion cormcag Sean ire tow Hore ‘Serle pce one Oe ay ea Sool ap or onan IRasnraoe roecerts scape stray poe owen neyo! {etc you ane Deus al tenance dey are hrugh 8 Boda SinraSurel owas hes wih warn fan Doo tease at warrant wn eset is infomation, wheter xa Beeptatierrdmoen ncn shal See eae sy dec eee ets ‘pecan ges dares one de ‘cured yous ary mwa pory wnt cancer terse ing Your eos bef olan ung arsten tans fom ough + Goss Vaneg Site Sameera ae cara ou corer aon it Dae Shh 2 Pe $e stay Pc, ute 720, Monette Catto | Senin Cxsori USA 1 Teese texsari203 | Tek v88¢-00 pouLos st ae com at naan wowwdoulos.comContents Contents, Workbook, Directories and Files Exercise 1 (Practical) Project Flow... Exercise 2 (Practical) Simulation Exercise 3 (Practical) Serial OR. Exercise 4 (Practical) Min-Max Circuit Exercise 5 (Practical Rotating and Shitting. Exercise 6 (Practical) ALU... Exercise 7 (Practical) Up Down Counter. Exercise 8 (Practical) Watch Controller Exercise 9 (Practical) RAM Chip. Exercise 10 (Practical) TEXTIO Additional Exercises. Exercise 11 (Practical) Chemical Plant Exercise 12 (Practical) Design Entities and Processes. Exercise 13 (Practical) Flip-flops and Hierarchy. Exercise 14 (Practical) Stop Watch. Exercise Solutions, Solution to Exercise 2 Solution o Exercise 3 Solution to Exercise 4 Solution to Exercise 5 Solution to Exercise 6 BSBRBSESoaes 34 38 4 a2 48 48 st 52 54 37 etSolution to Exercise 7... 65 Solution to Exercise 8. 66 Solution to Exercise 68 Solution to Exercise 10... 10 Solution to Exercise 11... m2 Solution to Exercise 1 18 (Quiz Solutions 7 ‘Syntax Summaries 20 Design Entities (Ex2). at Processes (Ex3). 82 ‘Synthesizing Combinational Logic (Ext). vn 8B Types; Arithmetic (Ex5,6) (Clocks and Registers (Ex) TEXTIO (Ext),Workbook “The fotoning soto conti instructions forthe praccal exercises.rNDirectories and Files “The es forthe exercises are organised ino tothe dretry shucixe shown below: 90! ex02 x03 ae. ammen answers [ source suite implement Fes tro Sonmon Ts bn cach of th exerze rectors, the source deta consis the VOL source fs, te Lita drecery i used forunaing simulans, andthe mplenent decor or synesis, ‘ace and route and downicaing oho development boarExercise 1 (Practical) Project Flow Wie Test Bench => (irvlement Hardware Purpose of the Exercise This exercse takes a simple design tough the complete VHDL detign flow, This involves simulaion, synthesis, place and ove, an frlly downloading to sn evataton board (tone Is ‘alae. ‘About the design e2mtinaonal con of he forint: AND, OR, “This esgn has four outputs, Each up is Iwo ouro Ins we court oure oursSimulation For simulation thre ae & numberof tots availabe. You wil Instutions or the most cammon olin fhe x0 mss fle 12 Follow the README lnstuctons fr the simdator and beard yeu ate ang In the exon fer. 12 tfyour tool is not covered by the README, fallow your simulation “Tel Tour document using the Gating Started vith.” rection. You wil need o simulate the design Logic vis ad he testbonéh Logic th.vh. The ap lal enty (hich you need! 16 lad in smuton) Ic ceated logsc_ eb 12 Once shad, eum here to comin wh te yess nd plco& ou seps ‘Yu have now seen hoo compile some VOL code and run asp simulation, ‘Synthesi is poss (and ute common) that you may be caring cut Synthesis and Place and Route in the se ol, Ask your ebuse leader you ar net clar where sar. Loge syetasis consts in tranfoming an ATL desertion inio 2 hardware equtalent reprasetaton, Synthese ta mull slp process; 2 st sip the sys toll ake an RTL fiece of code, end taneform ino an opize st of Boslean equstins; thas equations are then mapped ino anit gees evatale nthe enoson target ocveloy try. tis part of the eerie you wl be asks to voke your chen syntheas tal an ct he ars technology before executing your frst synthesis an. 12 During synthesis, you wll need 19 set up the requres deuce Infomation = ther Is 2 README fle in he ex0inelementdrecory whch Sls device deals or me, na guides you evough the nocossary steps. 12 your tole not covered by the README, we your chosen eyes “Tool ou” document ‘and flow the ncn, fering to the README leo the dovica deta. For syns, ou ony need 1 rea inthe ee 209 vis ~you dona syhesz th testberchl © Once ished, eum her end continue wit the lace and out sep.A Place & Route ‘The place and rote sep thes an existing gate lev notst along with user cxntaint fe end eas an equivalent iyi! implemeniton inside an FPGA, The place and route tele wi ‘ecge on the mest stable location for your desig elements and provce the requed connections Aor hs step, the newly gonersted programming fle can bo dowroaded tthe FPGA. 1. Folow the appropiate READNE fle inthe exoflmplementoard> elder. 1 I your tots not covered by te README, use your chosen place and eto “Too our document and flow the insctions rested to “Place and Route” (ct the synthesis sector!) Noto thatthe README fle refer to another le which sets the pinocatons~ this fos st et, you can ook at {Once finshed run hare nd contin wih dowlosng tothe boar. Downloading to a Board (if available) 12 Follow he insttons inthe e0implemantcboard> te downlod tothe boar 12 When downoad has completed, test the board using the swe and tutor ‘rerstens aren the READE fe. = again IHyou have time ‘Ask you course leader which elo run ow the placed and oud desig he aia yout of ‘he elements onthe ci. Look atthe consis fe used (ts Inthe inplementicoard> decay) ad make sre you understand hw the pin locations cn the device map back the prtsin the RTL cadeNotesExercise 2 (Practical) Simulation Wiite Test Bench =>) => Cartman —) Intis exercise you wl compe and simul some predesined VHDL sours code wth thea of becoming more failor withthe operation of the VHDL. tools, and of seting fre langue In Detaled instucions for completing this exercise can be found in the REACME fle In the ex02smute cect. your tot isnt covered by te README, use your ence Simdaton Too! Ter document nd flow henson, ‘The example fs -o-1 mutiplener, complete wah a testnch to pode te sin for ‘You shuld done oowing 1. Complete VHOL source cde, wich ein the as fsx02\souroe\muxd.vhd (Avery spe hardware design) fx02\eouroe\mind tbs vhd (The teabenth. 2 Coroct any eros inte source code and r-compl. The VHDL source cinans sever ‘orl The erensous sourcecode lated epost for roference 3. Simla tho testbonch MUXA_T8, 44 Use the wavafrm dsp tonepect the snulaton resus Thor. code iat (rung heer! oppose, (contin on page 12)i Baercise 2 kotor muneipie Snevey mike To [port (SEL 7 Sn STO_LOGIG_VECTORI1 downte 017 PRS? Soe Stocuoste} + Sohgnel SELL, SELLD, S810, SELOB) Sbi0e < noe SEL(0) F< (a and SELB and SE108) oF (@ Gnd SELAp and StLO) oe (¢ and Sei” and SeL08) or {o and Seut ea SeL0 Te 7 signal TSEL: STD_LOGIC_VECTOR(1 downto 017 watt for 10 Ns; | HRS pene for aes owe actos mene | A => TA, wait for 10 .NSy 7 i ror fo ws 1 Beet sey a : ety Sat tor 10 mssSimulation using Seripts ‘Wie wal runsenlston again, but this me using a sore. The adventage ofthe scp is that makes iver sy torn he complete fow reprody and icky, {A lsadvantage i ta sometimes errs canbe arto spot. you get eros, ts probably best ‘otoad the projet inthe graphical too fer debugging 12 yeu nave not stready done so, dose your must and change to ex2'smuee {2 (Windows) Doutie clk on openers. nat open # command prompt 12 (Windows) Run th appropiate do” nat sep (Uns) Run the spropat ot. sh ait (2 The expt do trary creation, compton, simuaton and adn waveonmsto the dep, Programming the Board using Scripts (if available) ‘Wie wil pw donload the design fo the Board using @ sep. Te downoad the mu sig 1 the beard fll teas nsbucton: 1 Browsoto the 2x02\ nplenent dreary (Brows nto the subdirectory forthe para tecnologyboar you ae uting 12 (Windows) Double ek on open 2 (Wns) Rr rappin bat Sop (Gino Ran the appropiate doom ser bat open a command prompt ‘Te complete ow wl un sn downoad tothe bord, ‘Test tne design ~refer toe pa mspeing fe Kent the mapsing of pns to VHDL prs NotesNotes.a Exercise 3 (Practical) Serial OR => wane > => sm) => Cie In this exercise you wil precise th use of process and signa, Wie and test & VHDL design ently for a sera 4 OF gate, having he flouing enty declan, You wil ir a template for {hs design ently in the flo ex03\ssurce\serilor. hd, and @ tstbench in the fle ex03\source\serialor_tbt via "Your code shaw deste te cout shown nis agra Clock“The estench chock tht he opt tom he design coment, nd consis Snel ck which is st FALSE should he ouput become inca 0, lok ot forthe Ok signal on ne waveform spi Note hat tor ae fo separa estan areiectures, one fr each pat ofthis emcee. Make ture you smut the correct aehtechze: 22 (nse 1b vh) forthe fst part and 752 (soit 62h} fer the second par, ‘Smtesize you VHOL code, and make sure that you gest ou Moss and an OR gst (or ‘equieen) onthe output. The easiest way to do this st ook at tho RTL schonac in your ‘Synfes olgrephes!nertace you need a reminder about ung he syhess too, lease fale 10 the READMENl flo in ex0timplrentcdoard> oto your Sytbess Too! Tour ocament Simulation Using Seripts -As nthe preous exercise you may un seul wih sept you nave nt alesdy done eo, doco your sul and change o exis {2 tnthat rectory run the erp fox your simulation to. 12 The serps do itary creatlon compton, siulaton, and adang wavetoms othe disp. You Have Time Pease tum he page!& You Have Time ‘ody your VHOL code to descibe the flowing Grout (rete a secund schiectice and ‘Smulte he second textbench arctectre > 5 [ Clock Nake sir you simulate the comect esthencharitectr (TR2 Inthe fe arty) Yeu ae using aS you wil need 19 eck. you are not ure wht o change loose ask you ‘exces osc. “Ty coding the AND gate and inverter fren ways an comparing he syncs esuts. For erarpie you could use 8 concurentsigal assignment or you could wie an appropiate ‘eroression onthe right ha side fone of he signa sslgnmens nthe process. Ifyou have more time... ‘You can dowel he design to the hardnare boat (foe i eaabe, bt you nll have to dé an enable so thatthe creat operations visible o the LEDs ~ others the LEDs change every 207s, which sto fst see! sty ho ony declaration toad an enable a follows: (see net pce)\erever you have a cocked process, ts he enstle kei. 46 etoing edge {clock then ‘once you've incorporated he enable sigal downs th design a follows 4. Change it tbe e203 \inpienent\boaee> dretoy 2, (Windows) Open a command prompt by runing openere.at 8. Download tothe board ung he (Windows) Balch lest) or (Ln) she ep (sh) or you boar, ‘Check he desgn works —reforto the README fr deta of consi ls and pin assignments NotesExercise 4 (Practical) Min-Max Circuit => weve => Cries) a) => sme) Design and code # combinational mininaxcrcut having te fllonng erty decraon. You wil fed a template for the erty inthe fle ex0¢\source\minnax. yh and tempat forthe tesbonchnleex04\so1re#\minnen_ tn wh When tino is "0%, 216 the minimum of and x and whan Windtend 2%, 2 the ‘maximum of and ,nieting %,¥ and 9s unsigned inary numbers. Incter wor, 2 ether gots the vale of othe vale of depending on which and is the spear, and also depending on the valve of n0von. Whe two numbers ¥ nd have the same val, then iru = maximum ==; you are unsure what his means, se the abe of tet vectors oppose, ‘Anether hint n rer te compare the values of he two Siege vetors x and representing Uunsgnad binary numbers, you can snplyuse the test if > ¥ then ‘You can implement is design ently as single processor a several processes,ite a testbench fo simulate your VHOL design using ho tst vectors gen in the able blow: (Goro tempt o test ho crest wit ol possible input pstems) ‘once the VOL. design series corset, go ant yhosze ho design to goes. ‘You wi ot be downoading is execs othe board You Have Time 1 ou have wrten your VHOL architecture usng mee than one comparison ape (> ee). then rewrite © ue exsety one comparison opesior. Sybase the now archtocir, and ‘compar th suitor hare wth your fat version cand your tertbench to ej tough all possible input vectors by having rine separate processes, one foreach bit oFX, Y and MndMlsr,esch proces epgng its signal at a dent NotesExercise 5 (Practical) Rotating and Shifting => Wie VHOL Wt Tes Bench bn this exercise you wil rite tho uso of vets. Wie, test and sythasi & VHDL. esign lent for 9 cet which oats a 4 bit input vector by a varying emer. The rotting orc he the folowing ently declaration. You wit tnd a template for thi design ny in tho fle fex05\souree\rotator. ha anda tesbench the Ne ex25\source\ tater Hvis “The Inputs apples en th prt Os. The number ois torte by programmed on pot otatetert Is "1", the Dout shoud be rotted lft ethrwse right Encb'e He *0", the ‘put on 000" shoul be the same athe nput. For aarp: pi where the "repasens dont care‘Smulta your design sing the tesherch. Th tsborch has an Ox sia, which ould remain Syntesie your design. Make sue when you syntesze your rei that you do natproduce any lores, To check forte presence of aches, lok your Syhess ana Place & Rute tos for Hfyou have eehes you may leo £08 lich elements athe Pace & Rou reports (hough note that ot al tectnologis have ate. Downloading the Design (ia board is available) Change into the drecloy #x0S\unplement\cboare>. H you are using Windows, open command promgt using the cpenhere.bst Sop, and an the impemertaten bat Srpt Under nu un heh stig. Actin ele to the README and consti est et he design en he boars NotesrN Exercise 6 (Practical) ALU => Wie VHOL WirteTest Bench => Symihesise Ins exes you wl practice wing and stisiang aitmete and vector peat, an se the fc of resource sharing. Wit and synthe » VHDL. design eniy fran appicton specie it ALU, having the flowing ently declaration. You wl find tampa the Re ex06\source\e1s. hd. Thee ig a testbonch in ex06\zcurce\alu tb. vb The tstench {heck the ouput of the ALU by comparing he actual ouput aginst lable of exactod values. gual: out Std_legie) ‘Allouput ae combinational The Equa} ouputis *1* Wand ony fA 9, and others. te ndependen the operon. Note tat A and 8 are ype sta_togic vector. Al atmatic operations are evluted using ‘ype stoned, Port op i of ype sta_togic_ vector. Shen binky codes indost 19 dierent operations and {3 day operations. The same bar codes are to be used forthe opraens wen tho ALU Is ‘sihesizod. The ouputs can be any loge value for cur operations but bo careful not fo ‘syhesze vansparentlaiches,ame | Operation | code | Coutts FFs FaFs FF Fe rouse | ave | “0000 ameuss | A-B | “0001” eminwa | BA | oor" ‘ony | coro | Ao AsAate Auto As Ase ‘oni BIO | Br BrBerBB BBB. ious a | one ious 5 [or cm oF, cinena | eniniet A | stoo0r | Ay Auteatsacaraoo | EAT] ssonuigna | ahitronta | croor | oo ArAeAAeAsAsas | [5] Rotates | rotten | ctoror | Ar MAcAvAsAsAAoAy | OR mene) => (__ tae) So) bn this exerse you wil practso wing and synthesising sequent lope. Wii, test ond symhesze @ VHDL design ety fran 8 bit Binary syntvonou up down coun, having the folowing ently decaraion, You wil fod a template for ts design ery in the fe ox \source\ counter, anda tetbonch nt fle 9x07 \sousee\eouneer vhs POF [looky Reset, Enable, Toad, Upln: in atd_togte Datat'in Std Logie vector (7 downto 6! ‘he ourtr operas on he sng edge he clack, wth he deco ofthe coun define by the sypetrenous UpDn inp Un at ge indeats count op and count down. The Enable and Lead inputs are synchronous and active high, bth having platy over te UpOn out and Enable ‘having poy over Load. When Load is aeve, Daa i eyntronou ase io the counter Wien Enabie i inactive, the counter nether counts nor loads. The Reset is asprchronaus an cvs high The ruth abe a te counters given Below ‘Tho testbanch hasan OK signal hat wl remah TRUE trowghout hee are no Kona eros Inte cour.“Te comple nd test your design you wal need fo complete flowing ls in thi cr: ‘Timing Constraints and Timing Analysis Setingacrurae ining constants isan important pat of he design fow. You wi nw st up same obal aneains and naz the resus 10 Follow he nstctons in th a0 implement README foto ad const (2 Camyanin te same set of srctons fo Syste and Pace & Route the desgn 12 Complete he step inthe README by tuning ing als. Download Your Design (if a board is available DDowniad the desig using the appropiate spt in exGmplementcboae> “Teste design and chock tat your counter i counting a you expect, ncung eect ofthe Enable, Los, UpDn sd Resot functions Not: the cad you dovnion ince extasupporing RTL io civ displays where possible, so ‘you can seo the curr counting, Ths codes inthe commen ceca of the exerci hs, OU swat tay You Have Time Moy your counter to make the rest synchronous Weteed of asynchronous, Resist, _ynitesize and donno he meted desig. You Stl Have Time Croat a new design ently RingCounter based on your exstng binary counter co. The Ot tng counter hs the folowing 8 statesa ‘The varousfunctons of the counter enable, oa, up, down) shou sopra. Simulate the counter wi the exsing tsbench. You wl need oe he erly inslance fo bd the sera secre The tstbonch il fal of couse, because is expect binary counter ‘When the counters loaded wih an ilega state (ore than an it ef), rit your cde such {tot t wil eventually corti and rtum to ene a he 8 logal states whan courting vp oF ‘dwn. For exami, you might implant the folowing sae sequence after the counter has ben lasted wath an log! stata and then courts up: NotesNotesExercise 8 (Practical) Watch Controller => Wite VHOL ite Test Bench => Sra ln tis exercise you wit coe up the fate sate machine controle or an elaconic slopwatch from te state ransion diagram given belo. Tho watch has a taop butDn and a reset baton. Wie simulate and synthesize a sign eit we he ftowing declaration, ‘Buttons: in STD LOGIC VECTOR(T £0 2) ‘Tho cantor chenges site on the ring edge of the Crystal input. The system reset (osysteset) fs egmeroncus aed acive low, and moves the slate machine fo he toro tate, ‘The sate tanstion dagram oppose shows tho 6 stats of the mschine, and te synchvonous ‘ranstons between the sates. Tho esynehvonous system reset rantions frm he oer states book oto aro sat af not shown onthe dagen Note st there ae two resets! The syne i harcwace reset (or when scone rplacos {he bse). Theres aso a rest 3 par of the namal function of he eopwtch ‘You wl i tmp forts design enty nee «x06 \susce\ Sem. wha atest ‘Simulate e design and ay uncon! erosName of Sate outputs i. WatehRunming="1 Wathen = State Machine Optimization Expariment wih changing the sate machine encoding her are basi instr in he Tool Tour for your Syithass and Plo & Route tol ~ and more detaled iretucions in erdaimplment\ for your pareuls boardiecnology& Download Your Dein ator veal) “Thar is supporting crcl uting the counter tem the previous exis) spo, so you an download he design toa cero board by raning the spt in ex08\snplenent\cboarde Read te README and constant le fn how hep reallocate, Ityou have time Fd out te dterence in speed and ares (ater place and routs) when te esto machine Is implemented using ether binary or one ht encoding you have more time Do exercise 14 Stopwatch, NotesNotesaA Exercise 9 (Practical) RAM Chip => Wite VHOL =D (wie Testbench => Inte oxreise you wl wre a madel and tesbench for @ Ram chip. ‘The RAM chip has he atoning enty dears Nddrese | in std-logic vector(9 dovto 0); Setain + in std-logicovector 1 domts 01 ‘Getaout : out std Logie vector(? downto 0} ‘The RAM has an B:bt data busin 8 Bi data bus ou, and a single 10 bt aktess bus. A operations are syctenisd tthe cock (On vary cock cya, the datout signal Is eyneonoutyacsgned the value cated by the adcese input In adton, i tbe we orale is asserted, the value of he dat. kp i writen othe location spaces by these putHore ing dsgrar Wit. Read hHaAppppppe we ade NT iz hel ata 00) vost TE ‘You wi nda fomplat forthe RAM chipin tee «x09\surce\sumb8 he Yeuae o wae the tesbench fom sorte ‘The testbone for the RAM chip shoul pecor atest the folowing operations that he VHOL code ncn comet npe tt 4. Weta some data addess 0 2. Wt semotingsiferent toads 1 3. Read tom adress 0 4 Rese tom adeoss nt to wat for fling lock edge uso the statement Synthesis (once you are hapoy the RAM fe simustng comecty, meke sue you can synthe &. Chock what the synthesis process produces ~ you shou See ano RAM compenont,netthousands ot fipops Download Your Design if a board is available) ‘As in previous exersees, download your design by runing the batch fle io 409} taptenent\cboor. The upportng out to nstnce the RAM you weal supped,a The dspay shows eight bis of ho aareas an ight its of at sou. To rota te actress dda, folow te instucor inthe README and constants les in that der, Generating a RAM For simple RAM model, its posse to wee code that synthases @ RAM, Fr more complex RAMs, and to use advanced feature, you can use an IP generator to crest the RAM. You wil snes the same AM as above, bul his ne using te IP generar em your bos, “Te nsrcons fr this stp are into flr exGo\nplometboae>, bt ti tne unde the healing “Generating & RAM inne README. (Once you have coped the stp, cary on and syne the new design te that its eat to get stn ho inetuctens, 0 pace foo ree to cons wh your course ade. Download and Test Your Design (if board is available) (nce you have crested the IP, you can download the generted version. In the README fe, {oll the instucton for "Downleadeg the Geraated RAM Desi. ‘Simulation ~ If You Have Time seoropfiale simulation rary Rofor tothe instuctons in the README fle in ‘ex0uimplement-oard, folowing the sect “Simting the Generated RAM" ihe READNE. “The README walake you trough he step of ‘+ Ensuring ne appropri smulstion lari are rend for we (comping them ecossory) ‘+ Comping th tetbench and san model ‘+ Running the siulaton NotesNotesExercise 10 (Practical) TEXTIO avo map (— wn testa => Synthesis In his execs you wil use the up/down counter design and teebench from Exes 7. Copies of the testbench (counter tbh) and 2 woking counter (Counter) ara ved nthe ‘exououree decoy, "You may fd hae ar some instucon you snus sulte README Part Wie one tine othe efor each cock eye. Each ine tefl should ne he vals ofa of he inputs sampled on te clock edge (excep or the cock) andthe vest value of th ‘ouput samples ater he ee edge, ‘Be careful abou toting when you same the puts and outputs fhe counteron Upon ° Cont np ouput mast be change ontting gag samoledaferit ‘Sock eone evomos sabe homes ite a sng header neat eto of he Ro abel he columns. ‘You wi nd procecires to help you write values of he fype Std_ogle and ic og wocor fo & fein the Synopsys package St og. eto, Part2 rte soond areietuce for he tstbench 6 read in the test vector le that you gover in pat 1. Dont decoy the old archeture, you may noed to wie the fle agdn! The new Srcsectre shoul aply the Input vectors 4 te Inputs ofthe cour before the clock edge, than, ser he cock edge, check thet he cult f to counter matches the value reed fom the fieAAdditional Exercises “Tese earls maybe include a course loader’ cretion.a Exercise 11 (Practical) Chemical Plant => wane => Comretea —) => Cam) => Cte) inpe warring systom fora chamial processing pnt. You wo design | Tee sensors conmecod to the system can sense te process is going ou of cont and becoming unsafe. Eath sensor has four dsthet out stale: NORMAL, LOW ALERT, HIGH ALERT and SHUTDOWN, eh sucoasve state bing noel (nthe process conta pane! there is mul-clored light which can be Hin GREEN, BLUE, ‘ORANGE or RED, corresponding to the cuput tals ofthe sensors. There ar aoa nunber of large waning igh around th factory which can be Win RED and GREEN. Write behavioural mode which wit examine the thes sensors and repo the highest wang level the conve pane. Also so the lrg warning hts acordng foe obo abe: ‘Cone Panel Waring Ughis_ | _FasoryWaming Lah RED RED ORANGE GREEN awe ‘GREEN (GREEN ‘GREEN‘Ho To alow a por onan entity fe have sn enumeration type the ype must re be cana in a packogo. Fr exami: Notes.Exercise 12 (Practical) Design Entities and Processes 1. Wite 8 VHDL design ensty named AI fo describe the blk of hardware shown inthe schemate below. Describe each ofthe wo gates wth eparteprocoes, ret 2, Wine a second achitocture for your design entity (an aematve arcitectr) which escibes bot ates wih snl process. All 3. Wits a third architocture fer your design ently which desrbes both ges in a single oncurent egal asigement statement, 4. Wt tstoonch tat your design ety, 5 Simulate yur desi 8, end your estbenc to apply al posse vectors tothe np ofthe delon by eying ‘throug al possible combinations using a fr loop.NotesExercise 13 (Practical) Flip-flops and Hierarchy 1. Wie 2 VHDL design entity named FFF to deserbe the block of hardwate shown ne Schematic below. The arctscture Neues an instance of ha component ALA frm the previous exercise. You wl have 4 consider he fact thet no ofthe pope has an FFF ol Bata Q: Clock 2 We fstoonch tet ihis design ety. nla # separate process in ho testbanch o generate tne cockNotesmn Exercise 14 (Practical) Stop Watch => Waite VHOL Wite Test Bench a) =>) In tis exercise you wil practise decaing, using and syntasizng vecor pes, and using tet operaton on hase pes. Extend the electric stopwatch made developed in exercise @ by adding minute end second ‘uo Wits ands VHDL design enty wth be folowing entity decoration ‘Suteona’ tn eto LoGre veeTORID co 2)7 Kinet out sToLlecte-vieton (3 Gownte 017 ‘When the wale is started, the ports Nine an Secs should ineerent rom 000 up to $9.58 ‘essing elapsed tme inthe conventional way, then eee back o 0:00. Wan the wath Is Stopped the fee buton shoud rst the welch, the second buon sould ese the etpuls to 0000. “The srchtocture for SlopVatch shoul Insts the WatehConteke developed in Ererie 8 You wil fod 8 tempaie in the Mo exl4\source\watcn.vhd, and @texbench inthe fle xd \eource\waton, tbe vhd ‘The testbench indies a cock generator (100 ms period) and ayo reset goneator. Because ‘he dock has pai of 100 ms and nt tse, you wll need ove the clock dm bya factor often ators yeu can count seconde,aExercise Solutions “Ts section corn relevant gro he stone oslo econ Col extacs from th Hes ere pind here. The solutions ere also avaiable nfl in the sna etry fhe execs les.Solution to Exercise 2 ere (68h An StD_LoGIc WECTOR(L dowte 6) PS Py gor StB_Loaiel scopstectare MRVIOUR of Kt boat ae ee ‘Sela < seuiays SEuae < not aebialy seuo Seti SeLoe © not ei (01s stp L0stcy — og 2 re and s8108) or nd S510") or fh Sets) oF signal TSE0: STD LOGIC VECTOR downto 014 ‘Signal TA, 8, 1G, 1D, tPr S80 200% begin -= Bus 2 begin in wong place te entity work.MIKA (BEHAWIOUR) port map vo <= Bug 3 wrong signet nanastate for 10 15) spe onySolution to Exercise 3 /Tt'sising edgeiciock) then signal 90, 51, 52, 53, 1) At Std logier bets “Te etaing edgeictoct) thenarchitecture RTLIB of Serial0h i beain process (clock) Te asetog cage tock) thon 30 co Band (not 33) 9 & S0 or SI ar 82 or 53)ort (Clock, Dy Etable: in etd togtes (or out sta ogteds osin process (clock) Yelessing edge (Chock! then 0 & 50 oF Si of 82 oF at)Solution to Exercise 4A Signal xgey? STO Loerer ‘onp: process 0K, Y) ox? process GAgtY, tindtlid, X,Y) and xgey = 10") oF Gea igee 202") thenSsanal Xr £ SoLlocie VecroR (3 dowate 0} Stanal Expected 2, 2 : STOLLocIeLVEcTOR (3 downto 0} Signal OF Boolean ere map intend => Minden, Bnaneice't" ken" 0001"; Yeo" 0000" Expected 2e=¥0001"7 Ninowani °0"15 Ip ce fotners > 11") Tie cm (others out <= mm i8hs F a std logic vector tep(7 downto 03):‘Sr optinal solstson, weing Just one adaer. esanal by Rt Signea(® downto 005 Signal Sins eignea(s aownes 0)? signet AP: Stoned’? downto 0) Signal Ad, 85! Sugned(a downto 0}s begin 29 <& Resive(signed(al, 907 Be So fesizetatanesiel, 9) process (AB, 29, 99, 0p) Shas oats > sen roi00" > KS fetnere > 0717 Thee 31 ES elntes > ons TS "Toenese = 104) ronsa RS tothere © "0", = shiftetghta 2 Se t00m ABT dwt 2) RS loners => 0" oS natn BN GNE ACO) & A817 downto 217 De tethers RS fothere Re (others => *0")3 1 "er foehere RS (othersSolution to Exercise 7 [DOEE Clock, Reset, Enable, Load, Upon: in std logic Process (clock, Reset) 0 sta logte vector(ent):Solution to Exercise 8 Electronic Stopnatch Contecller ~ port (Crystal, nsyoReset: in s70 rocrc; ‘Stopped, Reset, bunye, Sunny) fegisteres process (crystal, asystosst) Tr'asyetesee = 0" een elsif Rising edge(Crystel) thon Se Buttons 2) = 12" then re buttonsTeSattons a} = 12" then ieSahanatng <= 10's end aronitecture RTLSolution to Exercise 9 ° type cam type is arzey (0 to 1023) of atd_logie vector! downto 0) Rankroct process clock) is Te staing etelcloot) then ram(to integer (snssgned(adiress)}} <= dataine ‘seaout <= ram{te_snteger lunsignediedress)})4 ‘signal WE: Std_logicy I togie vector? downto O}7port map (clock => oleek, ‘thile not StopCteck Loop Shook c= "7 ‘end process Clockseny etan'e “Soogapoagty wast upetd sizing edge(etect! wit until rising edgeiclock)s =~ cyete 3 : seats neta cising ede (Lock): ‘ weit unthi rising adge(ctock|; -+ cycle § wit untét rising edge teiock)s UEie lines rissngreaee leiech) + ond process? 2 4Solution to Exercise 10 ution to TEXTTO Exercise (Counter Testbench) SiC enesEy weekecountgg ve eeieland > toed pon => Opn ‘ata, O'=> Os variable Li LINE; = . bese . alt untii Rising edge(Clock) Write, STRING! ("RE2U pata otis Weltelinetes tis lieitecs, Reset) Welte(ty toad,” REGIE, 2) WeteelL, Upon, RIGHT, 2}, WettelL Deta, RIGHT, 10); Meltelty gp’ Ror, 20);bette varleble eset, Vineble, Vioad, Yupon: Std logics Varlable vosta, Wp! sta Logie woctarl? dovato 0)s eaaiinate, Li? vate untst Falling edge(ciock) Resatine(e, 1) Readily VEnablel + Read (L, : Feedtty feedtty att nts) Rising edge(CLook)s 4 ort map (Clock => Clock, Reset => Reset, Enable => Enable, {load => toad pba => Upon, Data => Data, @'™> Oya» Solution to Exercise 11 WORUAL, TOW_ALERT, HIGH ALERT, SHUTDONR) 5 type Factény L2GH 1 (RED, GREE 3 = Chemteal prant pore (Sendori, Seneor2, Sensor + in SENSOR StATEs Factorylevel + out EncvORe Lucie) begin Te" (Sensoel = sHUTOOM) oF {Sancor? = SHVTOONN) oF (Sensce3 ~ SHUTDOM then feit. (Senger! = HIGH ALERT) oF (Senscr2 = HIGH ALERT) ox (Sens0r3 = elsif (Sensort = LOWALERT) or (Sensor? = LOW_ALERT] or (Sensor3 = Factorywarning? process (sntazning)olution to Chemical Plant Exercise test banch Ekgnei Sensoriy Sensor2,Senoor3 + SENSOR STATE Signal wacnsnglevel + FANE TIGHT) Signal FactorgLevel $ FACTORY uta, tur: entity work.chenical Plant Warninglevel => Warninglevel, Yor st in SEIg0R STATE Lo9p, for 89 4m SENSOR STATE 1009 eck: procene(Werninglovel, FactoryLevel) EE ractorybeve) EVENT ‘lott Faczerylavel = Groen and Warnénglavel ~ Red then Se warningtevel /= Red then SOME Warstogtevel J=Solution to Exercise 14 Seer rectors dewts O11 Process iCeystel, nsysnesst) eriable Count? Unaigned|2 dowts 0)7 “hatane aan + Onaigned!s dows 0) 1= To unsigned (59,612 besteQuiz Solutions “This ston contains soon for the quizes nthe Synthase of rthmete section af the couse smanval& Pireercen aa et& Syntax Summaries ‘This section contains summases ofthe syne lnaed cng each section of he course and nooded for eochexersoe "Note that he examples nth seefon wil not comple gen and tat they do not comprise @ formal syntax dion. A pariular name can ony be declared one whine peter region Conventions: Reserved words ae lowercase, User dined names are Captive, "Names dino nstandar packages are UPPER CASE. Names of stax consvets re alle pes. used in ploe of dectraton or sstementsDesign Entities (Ex2) + two minus signe atert @ coment Line Tpteally use fake. s10,Loore 1164 eneity Entityttine de 1 ort Porta! fn, betaine 1 nd entity aneitytanay Datatype ia typically s19_losIe oF St Lete VECTOR (senethina downto 0) architecture Archiane of Entityane ‘Signaitane Sigal Sttane => Signamane) + Eiguene men choice | Choice | chotes => Slottane <= sxpenesion? when Condition alee Exprecaton2s DokeuledapresotonsTypes; Arithmetic (Ex5,6) ‘ype Enuntypetane $2 Tay By cy signal Siotane: Ostatype s= znitia2vatues Signal Sigd: sto Loci ¥ocz0R(3 domes 0) += "9000" Hgnal Sigh: stocuocre_vecroR(7 dewee @) $= "00000000", SERENE Sonetane: bata c= Inltsaliaoe: stanet Signedsig + S1GME0(7 downto 0} anal Gnetgeaiiot OtTGREDC owe’ begin Sig¢ < 819813 downto 0); = siice name Stg8 < 5ig8(6 downto 0} & sige«s — Rotate sate Stenedsig == stovepiinaignedsis| Integersig :~ 1O_KurpaER(stanedsial o> Conversion function Signedsig’ := TOUSIGMED[Integersig, 8); Integersig := T0_INTEGER Uns gnedsi nsignedsig := TOLUNGIGNED [Iategersis, 8);Clocks and Registers (Ex7) arentvecture Arciilane of Eotstysane 42 1_ sb (Ciock! tnen ait unts1 RISING_EDcEICIeck} + abel: process (Enable, Sighane, SigNune} —- complete sensitavity list "Tenable = 134 ehTile Fileiane: TEXT open OpenKind 18 stringEspression: FILE onEN(Fstenana, StzinaBmpreaeion, Openkindl: FILE opew(statue, Fletame, Stringéxpcecetons OpenKind) s wume(uinedane, Expression, side, Width)» MRITELINE PL Teaney Linetanel hLle not ENDFILE(FLLeMaNe) Loop rus ciose(et2etane) + Scala:typovions nu (Strlnasspeeaston| ~~ fetuses Scolsetpe