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 HUFA76413DK8T
January 2003

HUFA76413DK8T
N-Channel Logic Level UltraFET® Power MOSFET
60V, 4.8A, 56mΩ
General Description
These N-Channel power MOSFETs are manufactured us- Applications
ing the innovative UltraFET® process. This advanced pro-
cess technology achieves the lowest possible on- • Motor and Load Control
resistance per silicon area, resulting in outstanding perfor- • Powertrain Management
mance. This device is capable of withstanding high energy
in the avalanche mode and the diode exhibits very low re- Features
verse recovery time and stored charge. It was designed for • 150°C Maximum Junction Temperature
use in applications where power efficiency is important, • UIS Capability (Single Pulse and Repetitive Pulse)
such as switching regulators, switching convertors, motor • Ultra-Low On-Resistance rDS(ON) = 0.049Ω, VGS = 10V
drivers, relay drivers, low-voltage bus switches, and power • Ultra-Low On-Resistance rDS(ON) = 0.056Ω, VGS = 5V
management in portable and battery-operated products.

D1 (8) D1 (7) D2 (6) D2 (5)

1
SO-8
S1 (1) G1 (2) S2 (3) G2 (4)

MOSFET Maximum Ratings TA = 25°C unless otherwise noted

Symbol Parameter Ratings Units
VDSS Drain to Source Voltage 60 V
VGS Gate to Source Voltage ±16 V
Drain Current
Continuous (TC = 25oC, VGS = 10V) 5.1 A
ID Continuous (TC = 25oC, VGS = 5V) 4.8 A
Continuous (TC = 125oC, VGS = 5V, RθJA = 228oC/W) 1 A
Pulsed Figure 4 A
EAS Single Pulse Avalanche Energy (Note 1) 260 mJ
Power dissipation 2.5 W
PD
Derate above 25oC 0.02 W/oC
TJ, TSTG Operating and Storage Temperature -55 to 150 oC

Thermal Characteristics
o
RθJA Thermal Resistance Junction to Ambient SO-8 (Note 2) 50 C/W
o
RθJA Thermal Resistance Junction to Ambient SO-8 (Note 3) 191 C/W
RθJA Thermal Resistance Junction to Ambient SO-8 (Note 4) 228 oC/W

This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.

©2003 Fairchild Semiconductor Corporation Rev. B

 HUFA76413DK8T
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
76413DK8 HUFA76413DK8T SO-8 330mm 12mm 2500 units

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 60 - - V
VDS = 50V - - 1
IDSS Zero Gate Voltage Drain Current µA
VGS = 0V TA = 150oC - - 250
IGSS Gate to Source Leakage Current VGS = ±16V - - ±100 nA

On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1 - 3 V
ID = 5.1A, VGS = 10V - 0.041 0.049
ID = 4.8A, VGS = 5V - 0.048 0.056
rDS(ON) Drain to Source On Resistance Ω
ID = 4.8A, VGS = 5V
- 0.091 0.106
TA = 150oC

Dynamic Characteristics
CISS Input Capacitance - 620 - pF
VDS = 25V, VGS = 0V,
COSS Output Capacitance - 180 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 30 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V 18 23 nC
Qg(5) Total Gate Charge at 5V VGS = 0V to 5V VDD = 30V - 10 13 nC
Qg(TH) Threshold Gate Charge VGS = 0V to 1V ID = 4.8A - 0.6 0.8 nC
Qgs Gate to Source Gate Charge Ig = 1.0mA - 1.8 - nC
Qgd Gate to Drain “Miller” Charge - 5 - nC

Switching Characteristics (VGS = 5V)

tON Turn-On Time - - 44 ns
td(ON) Turn-On Delay Time - 10 - ns
tr Rise Time VDD = 30V, ID = 1A - 19 - ns
td(OFF) Turn-Off Delay Time VGS = 5V, RGS = 16Ω - 45 - ns
tf Fall Time - 27 - ns
tOFF Turn-Off Time - - 108 ns

Drain-Source Diode Characteristics

ISD = 4.8A - - 1.25 V
VSD Source to Drain Diode Voltage
ISD = 2.4A - - 1.0 V
trr Reverse Recovery Time ISD = 4.8A, dISD/dt = 100A/µs - - 43 ns
QRR Reverse Recovered Charge ISD = 4.8A, dISD/dt = 100A/µs - - 55 nC
Notes:
1: Starting TJ = 25°C, L = 20mH, IAS = 5.1A
2: RθJA is 50 oC/W when mounted on a 0.5 in2 copper pad on FR-4 at 1 second.
3: RθJA is 191 oC/W when mounted on a 0.027 in2 copper pad on FR-4 at 1000 seconds.
4: RθJA is 228 oC/W when mounted on a 0.006 in2 copper pad on FR-4 at 1000 seconds.

©2003 Fairchild Semiconductor Corporation Rev. B

 HUFA76413DK8T
Typical Characteristics TA = 25°C unless otherwise noted

1.2 6

1.0
POWER DISSIPATION MULTIPLIER

VGS = 10V, RθJA=50oC/W

-ID, DRAIN CURRENT (A)

0.8 4

0.6

0.4 2

0.2
VGS = 5V, RθJA=228oC/W

0 0
0 25 50 75 100 125 150 25 50 75 100 125 150
TA , AMBIENT TEMPERATURE (oC) TA, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs

Ambient Temperature Case Temperature

DUTY CYCLE - DESCENDING ORDER

0.5
1
0.2
0.1 RθJA=50oC/W
THERMAL IMPEDANCE

0.05
ZθJA, NORMALIZED

0.02
0.01
0.1
PDM

VGS = 10V
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
SINGLE PULSE
PEAK TJ = PDM x ZθJA x RθJA + TA
0.001
10-5 10-4 10-3 10-2 10-1 100 101 102 103
t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

300
TA = 25oC
RθJA=50oC/W
TRANSCONDUCTANCE FOR TEMPERATURES
MAY LIMIT CURRENT
100 ABOVE 25oC DERATE PEAK
IN THIS REGION
IDM, PEAK CURRENT (A)

CURRENT AS FOLLOWS:

VGS = 5V I = I25 175 - TA

150

VGS = 10V
10

2
10-5 10-4 10-3 10-2 10-1 100 101 102 103
t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

©2003 Fairchild Semiconductor Corporation Rev. B

 HUFA76413DK8T
Typical Characteristics TA = 25°C unless otherwise noted

200 15
If R = 0
100 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
10 If R ≠ 0

IAS, AVALANCHE CURRENT (A)

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
ID, DRAIN CURRENT (A)

100µs

10
STARTING TJ = 25oC
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
1
SINGLE PULSE STARTING TJ = 150oC
TJ = MAX RATED
TA = 25oC
0.2 1
1 10 100 0.1 1 10 40
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)

Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching
Capability

25 25
PULSE DURATION = 80µs VGS = 5V
VGS = 10V
DUTY CYCLE = 0.5% MAX
20 VDD = 15V 20 VGS = 3.5V
ID , DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)

15 15
TJ = 150oC VGS = 3V

10 10

o TJ = -55oC
TJ = 25 C
TA = 25oC
5 5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

0 0
1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0
VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

100 2.0
PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE

DUTY CYCLE = 0.5% MAX

90
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)

ID = 5.1A
ON RESISTANCE

80 1.5

70

60 1.0

ID = 1A
50
VGS = 10V, ID =5.1A

40 0.5
2 4 6 8 10 -80 -40 0 40 80 120 160
VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC)

Figure 9. Drain to Source On Resistance vs Gate Figure 10. Normalized Drain to Source On
Voltage and Drain Current Resistance vs Junction Temperature

©2003 Fairchild Semiconductor Corporation Rev. B

 HUFA76413DK8T
Typical Characteristics TA = 25°C unless otherwise noted

1.2 1.2
VGS = VDS, ID = 250µA ID = 250µA

NORMALIZED DRAIN TO SOURCE

BREAKDOWN VOLTAGE
THRESHOLD VOLTAGE
NORMALIZED GATE

1.0 1.1

0.8 1.0

0.6 0.9
-80 -40 0 40 80 120 160 -80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)

Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature

2000 10
VGS , GATE TO SOURCE VOLTAGE (V)

1000 CISS = CGS + CGD VDD = 30V

8
C, CAPACITANCE (pF)

CRSS = CGD 6

100
COSS ≅ CDS + CGD 4

WAVEFORMS IN
2 DESCENDING ORDER:
ID = 4.8A
VGS = 0V, f = 1MHz ID = 1A
10 0
0.1 1 10 60 0 5 10 15 20
VDS , DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)

Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant
Voltage Gate Currents

150

VGS = 5V, VDD = 30V, ID = 1A

td(OFF)
SWITCHING TIME (ns)

100

tf

50
tr

td(ON)

0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE (Ω)

Figure 15. Switching Time vs Gate Resistance

©2003 Fairchild Semiconductor Corporation Rev. B

 HUFA76413DK8T
Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS

+
VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0.01Ω 0

tAV

Figure 16. Unclamped Energy Test Circuit Figure 17. Unclamped Energy Waveforms

VDS
VDD Qg(TOT)
RL
VDS
VGS = 10V

VGS Qg(5)
+

VDD VGS = 5V
VGS
-

DUT VGS = 1V
Ig(REF) 0
Qg(TH)
Qgs Qgd

Ig(REF)
0

Figure 18. Gate Charge Test Circuit Figure 19. Gate Charge Waveforms

VDS tON tOFF

td(ON) td(OFF)

RL tr tf
VDS
90% 90%

+
VGS
VDD
10% 10%
- 0

DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0

Figure 20. Switching Time Test Circuit Figure 21. Switching Time Waveforms

©2003 Fairchild Semiconductor Corporation Rev. B

 HUFA76413DK8T
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
300
the maximum allowable device power dissipation, PDM, in an
RθJA = 103.2 - 24.3 * ln(AREA)
application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W) 250
228 oC/W - 0.006in2
must be reviewed to ensure that TJM is never exceeded.

Rθβ, RθJA (oC/W)

200 191 oC/W - 0.027in2
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
150
(T –T )
JM A (EQ. 1)
P = ----------------------------- 100
DM RθJA
50
In using surface mount devices such as the SO-8 package, Rθβ = 46.4 - 21.7 * ln(AREA)
the environment in which it is applied will have a significant 0
influence on the part’s current and maximum power 0.001 0.01 0.1 1
dissipation ratings. Precise determination of PDM is complex AREA, TOP COPPER AREA (in2) PER DIE
and influenced by many factors:
Figure 22. Thermal Resistance vs Mounting
1. Mounting pad area onto which the device is attached and Pad Area
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 22
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 22 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.

R θ JA = 103.2 – 24.3 ln ( Area ) (EQ. 2)

The dual die SO-8 package introduces an additional thermal

coupling resistance, RθB. Equation 3 describes RθB as a
function of the top copper mouting pad area.

R θ B = 46.4 – 21.7 ln ( Area ) (EQ. 3)

The thermal coupling resistance vs. copper area is also

graphically depicted in Figure 22.

©2003 Fairchild Semiconductor Corporation Rev. B

 HUFA76413DK8T
PSPICE Electrical Model
.SUBCKT HUFA76413DK8T 2 1 3 ; rev April 2002
CA 12 8 7.8e-10
CB 15 14 9.8e-10 LDRAIN
CIN 6 8 5.8e-10 DPLCAP 5 DRAIN
2
10
DBODY 7 5 DBODYMOD RLDRAIN
DBREAK 5 11 DBREAKMOD RSLC1
51 DBREAK
DPLCAP 10 5 DPLCAPMOD +
RSLC2
5 ESLC 11
EBREAK 11 7 17 18 67.4 51
-
EDS 14 8 5 8 1 50 +
EGS 13 8 6 8 1 -
RDRAIN 17 DBODY
6
ESG 6 10 6 8 1 ESG 8
EBREAK 18
EVTHRES 6 21 19 8 1 EVTHRES -
+ 16
EVTEMP 20 6 18 22 1 + 19 - 21
LGATE EVTEMP MWEAK
8
GATE RGATE + 18 - 6
IT 8 17 1 1 22 MMED
9 20
RLGATE MSTRO
LDRAIN 2 5 1e-9
LSOURCE
LGATE 1 9 1.34e-9 CIN
8 SOURCE
7 3
LSOURCE 3 7 0.59e-9
RSOURCE
RLSOURCE
MMED 16 6 8 8 MMEDMOD
S1A S2A
MSTRO 16 6 8 8 MSTROMOD 12 RBREAK
13 14 15
MWEAK 16 21 8 8 MWEAKMOD 8 13
17 18

S1B S2B RVTEMP

RBREAK 17 18 RBREAKMOD 1
13 CB 19
RDRAIN 50 16 RDRAINMOD 22.5e-3 CA
IT
+ + 14 -
RGATE 9 20 2.2
6 5 VBAT
RLDRAIN 2 5 10 EGS EDS +
8 8
RLGATE 1 9 13.4 - - 8
RLSOURCE 3 7 5.9 22
RSLC1 5 51 RSLCMOD 1e-6 RVTHRES
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 15.3e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),2.5))}

.MODEL DBODYMOD D (IS = 8e-13 RS = 1.58e-2 TRS1 = 1e-3 TRS2 = 3e-6 XTI=3.2 CJO = 8e-10 TT = 3.2e-8 M = 0.54)
.MODEL DBREAKMOD D (RS = 1.18 TRS1 = 2e-3 TRS2 = -2.6e-5)
.MODEL DPLCAPMOD D (CJO = 5.7e-10 IS = 1e-30 N = 10 M = 0.87)
.MODEL MMEDMOD NMOS (VTO = 1.68 KP = 2 IS =1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.2)
.MODEL MSTROMOD NMOS (VTO = 2.05 KP =35 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.48 KP = 0.04 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.15e-3 TC2 = -7.5e-7)
.MODEL RDRAINMOD RES (TC1 = 8.5e-3 TC2 = 1.2e-5)
.MODEL RSLCMOD RES (TC1 = 3e-2 TC2 = 5.3e-7)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.4e-3 TC2 = -7e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 2e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.0 VOFF= -1.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.0 VOFF= -5.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.2 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.2)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2003 Fairchild Semiconductor Corporation Rev. B

 HUFA76413DK8T
SABER Electrical Model
REV April 2002
template HUFA76413DK8T n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 8e-13, rs = 1.58e-2, trs1 = 1e-3, trs2 = 3e-6, xti = 3.2, cjo = 8e-10, tt = 3.2e-8, m = 0.54)
dp..model dbreakmod = (rs = 1.18, trs1 = 2e-3, trs2 = -2.6e-5)
dp..model dplcapmod = (cjo = 5.7e-10, isl =10e-30, nl =10, m = 0.87)
m..model mmedmod = (type=_n, vto = 1.68, kp = 2, is =1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.05, kp = 35, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.48, kp = 0.04, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.0, voff = -1.0)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.0, voff = -5.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.2, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.2)
LDRAIN
DPLCAP 5 DRAIN
2
c.ca n12 n8 = 7.8e-10 10
RLDRAIN
c.cb n15 n14 = 9.8e-10 RSLC1
c.cin n6 n8 = 5.8e-10 51
RSLC2
dp.dbody n7 n5 = model=dbodymod ISCL
dp.dbreak n5 n11 = model=dbreakmod 50 DBREAK
dp.dplcap n10 n5 = model=dplcapmod -
6 RDRAIN
ESG 8 11
i.it n8 n17 = 1 EVTHRES DBODY
+ 16
+ 19 - 21
LGATE EVTEMP MWEAK
l.ldrain n2 n5 = 1e-9 8
GATE RGATE + 18 - 6
l.lgate n1 n9 = 1.34e-9 1 MMED EBREAK
9 22 +
l.lsource n3 n7 = 0.59e-9 20
RLGATE MSTRO 17
18 LSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u CIN - SOURCE
8 7
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u 3
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u RSOURCE
RLSOURCE
S1A S2A
res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = -7.5e-7 12 RBREAK
13 14 15
res.rdrain n50 n16 = 22.5e-3, tc1 = 8.5e-3, tc2 = 1.2e-5 17 18
8 13
res.rgate n9 n20 = 2.2
res.rldrain n2 n5 = 10 S1B S2B RVTEMP
res.rlgate n1 n9 = 13.4 13 CB 19
CA
IT
res.rlsource n3 n7 = 5.9 + + 14 -
res.rslc1 n5 n51= 1e-6, tc1 = 3e-2, tc2 =5.3e-7 6 5 VBAT
EGS 8 EDS 8 +
res.rslc2 n5 n50 = 1e3
- - 8
res.rsource n8 n7 = 15.3e-3, tc1 = 1e-3, tc2 =1e-6 22
res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 2e-7 RVTHRES
res.rvthres n22 n8 = 1, tc1 = -1.4e-3, tc2 = -7e-6

spe.ebreak n11 n7 n17 n18 = 67.4

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2.5))
}
}

©2003 Fairchild Semiconductor Corporation Rev. B

 HUFA76413DK8T
SPICE Thermal Model
REV April 2002 th JUNCTION
HUFA76413DK8T
Copper Area = 0.493in2

CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3 RTHERM1 CTHERM1
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2 8
CTHERM6 4 3 1.5e-1
CTHERM7 3 2 7.5e-1
CTHERM8 2 tl 3 RTHERM2 CTHERM2

RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1 7
RTHERM3 7 6 2
RTHERM4 6 5 8
RTHERM5 5 4 18 RTHERM3 CTHERM3
RTHERM6 4 3 20
RTHERM7 3 2 23
6
RTHERM8 2 tl 25

SABER Thermal Model RTHERM4 CTHERM4

SABER thermal model HUFA76413DK8T

Copper Area = 0.493in2 5
template thermal_model th tl
thermal_c th, tl
{ RTHERM5 CTHERM5
ctherm.ctherm1 th 8 =8.5e-4
ctherm.ctherm2 8 7 =1.8e-3
4
ctherm.ctherm3 7 6 =5.0e-3
ctherm.ctherm4 6 5 =1.3e-2
ctherm.ctherm5 5 4 =4.0e-2
RTHERM6 CTHERM6
ctherm.ctherm6 4 3 =1.5e-1
ctherm.ctherm7 3 2 =7.5e-1
ctherm.ctherm8 2 tl =3 3

rtherm.rtherm1 th 8 =3.5e-2
rtherm.rtherm2 8 7 =6.0e-1 RTHERM7 CTHERM7
rtherm.rtherm3 7 6 =2
rtherm.rtherm4 6 5 =8
rtherm.rtherm5 5 4 =18 2
rtherm.rtherm6 4 3 =20
rtherm.rtherm7 3 2 =23
rtherm.rtherm8 2 tl =25 RTHERM8 CTHERM8
}

tl CASE

©2003 Fairchild Semiconductor Corporation Rev. B

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