ED-2002-099 Mixed Analog Module (2364) User Manual
ED-2002-099 Mixed Analog Module (2364) User Manual
Series of PLCs
2 Channel Analog
Voltage/Current Input
+
2 Channel Analog
Voltage Output
(2364)
User Manual
2 Ch Analog Voltage/Current Input + 2 Ch Analog Voltage Output (2364) 2
Contents
1. Overview ....................................................................................................4
2. Specifications ..............................................................................................5
3. Wiring .......................................................................................................... 7
4. Module memory ..........................................................................................8
4.1 Input channel configuration ............................................................8
4.2 Input channel data ........................................................................10
4.3 Output channel configuration ......................................................12
4.4 Output channel data ......................................................................12
4.5 Module status. ..............................................................................13
5. I/O Memory................................................................................................15
6. Configuration ............................................................................................16
7. Programming ............................................................................................18
7.1 Programming analog input ............................................................18
7.2 Programming analog output..........................................................24
ETH
Voltage input is connected between terminals 'V+n' and 'V-n', where n is channel
no. as 0 to 1.
Current input is connected between terminal 'I+n' and 'V-n', where n is channel
no. as 0 to 1. For current input, it is necessary to connect 'V+n' and 'I+n'
terminals to each other.
It is recommended to connect SH terminals directly to good quality earth in the
control panel avoiding any ground loop.
The figure below shows connections of delivering voltage output.
Shielded twisted cable Voltage output
+ V+n
Load >
5KΩ
V-n
Invalid 1 1 1 1 1
--- 0 0 0
Reserved
--- 0 0 0
Open Zero 0 0
Upper scale 0 1
Circuit
Lower scale 1 0
Value Invalid 1 1
Reserved --- 0
Channel Disabled 0
Status Enabled 1
Reserved 0 0 0 0
Input type
Channel can be configured as voltage (±10 V / ± 5 V) or current (0 to 20 mA/ 4
to 20 mA) input type. By default, input channel is configured for voltage input
type ± 10 V. Depending on input type, data is available as below.
>
32767 32767
32000 32000
10.23 V
5.12 V
Channel
Channel
data
data
-10 V -5 V
< > < >
0 10 V 0 5V
Analog Input Analog Input
-10.23 V
-5.12 V
-32000 -32000
-32768 -32768
<
<
The figures below show graphs of analog input versus channel data for current
input types.
>
>
32767 32767
32000 32000
20.47 mA
20.47 mA
Channel
Channel
data
data
> >
0 20 mA 0 4 mA 20 mA
Analog Input Analog Input
Module memory Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MMB 5220
Channel enable-By default two channels
are enabled. (Hence holds value 3 at
power ON) Reserved Ch1 Ch0
Output ch0 enable 1
Output ch0 disable 0
Output ch1 enable 1
Output ch1 disable 0
10.23 V
10 V
32767
Output
Analog
-32000
0 32000
Digital Input
-32767
Data
-10 V
-10.23 V
Invalid 1 1 1 1 1
--- 0 0 0
Reserved
--- 0 0 0
Open Zero 0 0
Upper scale 0 1
Circuit
Lower scale 1 0
Value Invalid 1 1
Reserved --- 0
Channel Disabled 0
Status Enabled 1
Open Channel OK 0
circuit Open circuit 1
Under No under range 0
range Under range 1
Over No over range 0
range Over range 1
0001
System variable_WRACK_0_REG_STATUS.0 provide bitwise slot status.
_WRACK_0_REG_STATUS.0 slot_0ok
0002
Input image bit 7 provides status of module supply
0003
Input image bit 6 provides status of ADC circuit.
0005
Input image bit 1 is TRUE if input channel1 is enabled and healthy.
0006
Read all channel data module memory starting from MMW 1000 only if module is registered and
there is no ADC fault. Store data in array analog data. Successful execution of IM_Read function
returns TRUE. i.e. Data RdDn becomes TRUE.
0007
If channel error is detected via module input image. Read individual channel status.
InCh0_OK IM_Read
EN
0 Slot STATUS0_RdDN
100 MMW
ADR(Ch0_Status) Data_Adr
2 Len
0008
Ch0_Status bit 14 is TRUE if channel0 input signal is under range i.e. below -10.035V in this case.
0009
Ch0_Status bit 15 is TRUE if channel0 input signal is over range i.e. above +10.035V in this case.
InCh1_OK IM_Read
EN
0 Slot STATUS1_RdDN
102 MMW
ADR(Ch1_Status) Data_Adr
2 Len
0011
Ch1_Status bit 14 is TRUE if channel1 input signal is under range i.e. below -10.035V in this case.
0012
Ch1_Status bit 15 is TRUE if channel1 input signal is over range i.e. above +10.035V in this case.
If user need any other input type e.g. 4 to 20 mA, user has to write configuration
by executing function IM_Write. Typical application program example if user
require both channels, channel 0 and channel 1 to accept 4 to 20 mA current
input is as shown below. User has to write channel configuration by executing
function IM_Write. After successful configuration, channel data can be read.
Individual channel status can be read by executing IM_Read function. Input
image provides channel and module status.
This program type POU named AIn_current should be called in main program
PLC_PRG.
0001
System variable_WRACK_0_REG_STATUS.0 provide bitwise slot status.
_WRACK_0_REG_STATUS.0 slot_0ok
0002
Analog input channel configuration is written once
InCh0 and Inch1 are configured for 4 to 20 mA current input.
slot_0ok IM_Write
EN
0 Slot AI2_ConfigDn
ADR(AI2_Config) MMW
5200- Data_Adr
8 Len
0003
Input image bit 7 provides status of module supply
0004
Input image bit 6 provides status of ADC circuit.
0006
Input image bit 1 is TRUE if input channel1 is enabled and healthy.
0007
Read all channel data module memory starting from MMW 1000 only if module is registered and there is
no ADC fault. Store data in array analog data. Successful execution of IM_Read function returns TRUE
i.e. Data RdDn becomes TRUE.
0008
If channel error is detected via module input image. Read individual channel status.
InCh0_OK IM_Read
EN
0 Slot STATUS0_RdDN
100 MMW
ADR(Ch0_Status) Data_Adr
2 Len
0009
Ch0_Status bit12 is TRUE if channel0 configuration is invalid.
0010
Ch0_Status bit13 is TRUE if channel0 input signal is open or signal is less than 2.5 mA or
signal polarity is reverse.
0012
Ch0_Status bit 15 is TRUE if channel0 input signal is over range i.e. above 20.04 mA in this case.
0013
If channel error is detected via module input image. Read individual channel status.
InCh1_OK IM_Read
EN
0 Slot STATUS1_RdDN
102 MMW
ADR(Ch1_Status) Data_Adr
2 Len
0014
Ch1_Status bit12 is TRUE if channel1 configuration is invalid.
0015
Ch1_Status bit13 is TRUE if channel0 input signal is open or signal is less than 2.5 mA or
signal polarity is reverse.
0016
Ch1_Status bit14 is TRUE if channel1 input signal is under range i.e. below 3.5 mA in this case.
0017
Ch1_Status bit15 is TRUE if channel1 input signal is over range i.e. above 20.04 mA in this case.
0001
Input image bit7 provides status of module supply
%IX0.7 ModuleSupply_OK
0002
Input image bit2 is TRUE if output channel0 is enabled and healthy.
%IX0.2 OutCh0_OK
0003
Input image bit 3 is TRUE if output channel1 is enabled and healthy.
%IX0.3 OutCh1_OK
0004
Output Channel0 data (-32000 to 32000) is written to module memory 6100 to generate proportional
±10 V output. Successful execution of function IM_Write returns TRUE. (Wr_Done1 becomes TRUE).
OutCh0_OK IM_Write
EN
0 Slot Wr_Done1
ADR(A01_Data) Data_Adr
6100 MMW
2 Len
OutCh1_OK IM_Write
EN
0 Slot Wr_Done2
ADR(A02_Data) Data_Adr
6102 MMW
2 Len