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    16by1MUX Day3

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    shresthanagesh
    The document summarizes learning Verilog modelling by implementing a 16-to-1 multiplexer (MUX) using different approaches: 1) Pure behavioral modelling of a 16-to-1 MUX 2) Behavioral modelling of a 4-to-1 MUX and structurally implementing a 16-to-1 MUX using 4-to-1 MUXes 3) Fully structural implementation of a 16-to-1 MUX using 2-to-1 MUXes as primitives In all cases, the Verilog code was synthesized to match the expected structural design.

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    16by1MUX Day3

    Uploaded by

    shresthanagesh
    61 views6 pages
    The document summarizes learning Verilog modelling by implementing a 16-to-1 multiplexer (MUX) using different approaches: 1) Pure behavioral modelling of a 16-to-1 MUX 2) Behavioral modelling of a 4-to-1 MUX and structurally implementing a 16-to-1 MUX using 4-to-1 MUXes 3) Fully structural implementation of a 16-to-1 MUX using 2-to-1 MUXes as primitives In all cases, the Verilog code was synthesized to match the expected structural design.

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    16by1MUX-Day3

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    The document summarizes learning Verilog modelling by implementing a 16-to-1 multiplexer (MUX) using different approaches: 1) Pure behavioral modelling of a 16-to-1 MUX 2) Behavioral modelling of a 4-to-1 MUX and structurally implementing a 16-to-1 MUX using 4-to-1 MUXes 3) Fully structural implementation of a 16-to-1 MUX using 2-to-1 MUXes as primitives In all cases, the Verilog code was synthesized to match the expected structural design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    61 views6 pages

    16by1MUX Day3

    Uploaded by

    shresthanagesh
    The document summarizes learning Verilog modelling by implementing a 16-to-1 multiplexer (MUX) using different approaches: 1) Pure behavioral modelling of a 16-to-1 MUX 2) Behavioral modelling of a 4-to-1 MUX and structurally implementing a 16-to-1 MUX using 4-to-1 MUXes 3) Fully structural implementation of a 16-to-1 MUX using 2-to-1 MUXes as primitives In all cases, the Verilog code was synthesized to match the expected structural design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 6

    #evolvestreak Day 3: Learning Verilog Modelling

    Learnt Verilog Modelling (Behavioral and Structural models) using the 16to1 MUX example.
    Experimented to see how it will get synthesized. In all the cases, the tool synthesized to the
    ultimate structural design. (low level implementation)

    1. Pure Behavioral Modelling of 16to1 MUX

    module mux16to1( in, sel, out );


    input [15:0] in;
    input [3:0] sel;
    output out;

    assign out = in[sel];


    endmodule

    Testbench: (common) to all designs

    module muxtest;
    reg [15:0] A;
    reg [3:0] S;
    wire F;

    mux16to1 M (.in(A), .sel(S), .out(F));


    initial begin
    $monitor($time, " A = %h, S = %h, F = %b",A,S,F);
    #5 A = 16'h3f0a; S = 4'h0;
    #5 S = 4'h1;
    #5 S = 4'h6;
    #5 S = 4'hc;
    #5 $finish;
    end

    endmodule

    RTL representation of the above code.

    Post synthesis schematic is same as expected.


    2. Behavioral Modelling of 4:1 MUX, Implementing 16to1 MUX from 4:1 MUX using structural
    modelling

    Behavioral Modelling of 4:1 MUX (below code).

    module mux4to1( in, sel, out );


    input [3:0] in;
    input [1:0] sel;
    output out;

    assign out = in[sel];


    endmodule

    Structural model of 16to1 MUX as shown in figure.


    module mux16to1 (in, sel, out);
    input [15:0] in;
    input [3:0] sel;
    output out;
    wire [3:0] t;

    mux4to1 M0 (in[3:0], sel[1:0], t[0]);


    mux4to1 M1 (in[7:4], sel[1:0], t[1]);
    mux4to1 M2 (in[11:8], sel[1:0],t[2]);
    mux4to1 M3 (in[15:12], sel[1:0],t[3]);
    mux4to1 M4 (t,sel[3:2], out);
    endmodule

    RTL representation of the above code:


    3. Fully structural implementation of 16to1 MUX.

    2:1 MUX in structural:

    module mux2to1( in, sel, out );


    input [1:0] in;
    input sel;
    output out;
    wire t1, t2, t3;

    assign t1 = ~sel;
    assign t2 = in[0] & t1;
    assign t3 = in[1] & sel;
    assign out = t2 | t3;

    endmodule
    module mux4to1(in, sel, out);
    input [3:0] in;
    input [1:0] sel;
    output out;
    wire [1:0] t;

    mux2to1 M0 (in[1:0], sel[0], t[0]);


    mux2to1 M1 (in[3:2], sel[0], t[1]);
    mux2to1 M2 (t, sel[1], out);
    endmodule
    Fig: Post - Synthesis done in Vivado. Similar to structural design in all cases. (ultimate aim).

    Simulation waveform of 16:1 MUX.

    0 A = xxxx, S = x, F = x
    5 A = 3f0a, S = 0, F = 0
    10 A = 3f0a, S = 1, F = 1
    15 A = 3f0a, S = 6, F = 0
    20 A = 3f0a, S = c, F = 1
    Reference:
    NPTEL Video on Hardware Modelling using Verilog by Indranil Sengupta sir.

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