Ex.

No: 1 Synthesize and implement Combinational and

Sequential Circuits in VERILOG HDL

Aim:

To Synthesize and implement Combinational and Sequential Circuits in VERILOG / VHDL

SOFTWARE REQUIRED:

 Xilinx ISE Design Suite 6.1

Theory:
COMBINATIONAL CIRCUIT:
 The output of a Combinational Circuit depends entirely on the present input.
 It exhibits a faster speed.
 It is comparatively easier to design.
 No feedback is present between the input and output.
 The combinational circuit depends on time.
 Logic gates form the building blocks of such circuits.
 One can make use of it for both boolean and arithmetic operations.
 They don’t hold the capacity of storing any state.
 These circuits do not have a clock- thus, they don’t require triggering.
 They do not possess any memory element.
 Users can feasibly use as well as handle them
 Example – Demultiplexer, Multiplexer, Decoder, Encoder, etc.
 SEQUENTIAL CIRCUIT :
 The output of a Sequential Circuit depends on both- past as well as present inputs.
 It works at a comparatively slower speed.
 The design of these circuits is comparatively much tougher than the Combinational
 Circuit.
 A feedback path exists between the output and the input.
 The circuit is time-dependent.
 Flip-flops constitute the building blocks of such a circuit.
 People mainly use them for storing data and information.
 They possess the capability of storing any data state or retaining an earlier state at
any givenpoint. Because a Sequential circuit depends on a clock, it usually requires
triggering
 They always possess a memory element.
 A user may not be able to handle and use these circuits easily.
 For Example – Counters, Flip-flops, etc
Procedure:
1. Start theXilinxISE by using Start>Program files> XilinxISE> project navigator
2. Click File>New Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbolof FPGAdevice and then right click>click on new source.
6. Select the Verilog Module and give the filename>click next and define ports >click next and
finish.
7. Type the Verilog Code in Verilog Editor.
8. Run theCheck syntax>Process window >synthesize>double click check syntax.If any errors
found then remove the errors with proper syntax &coding.
9. Click on the symbol of FPGA device and then right click>click on new source.
10. Select the Test Bench Waveform and give the filename>select entity click next and finish.
11. Select the desired parameters for simulating your design.In this case combinational circuit and
simulation time click finish.
12. Assign all input signal using just click on graph and save file.
13. From the source process window. Click Behavioral simulation from drop-down menu 14. Select
the test bench file (.tbw) and click process button>double click the Simulation Behavioral Model
15. Verify your design in wave window by seeing behavior of output signal with respect to input
signal
CODE:

To synthesis and implement the following combinational circuit and sequential circuits
using data flow or gate levelmodelling along with their test bench.

a. ADDER and SUBTRACTOR

b. Multiplexer & De-multiplexer

c. Decoder & Encoder

d. Code converter

e. Flipflop

f. Asynchronous ripple counter

g.RANDOM NUMBER GENERATOR

 Ex No 1 (a) ADDER and SUBTRACTOR REALISATION
Aim:

Realize the adder and subtractor using VHDL and Verilog.

Apparatus Required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator

Theory:
Half Adder A combinational circuit that performs the addition of two bits is called a
half-adder. This circuit needs two binary inputs and produces two binary outputs. One of the
input variables designates the augend and other designates the addend. The output variables
producethe sum and the carry.

The simplified Boolean functions of the two outputs can be obtained as below:
Sum S = x’y + xy’
Carry C = xy
Where x and y are the two input variables.

Full Adder A combinational circuit that performs the addition of three bits is called a
half- adder. This circuit needs three binary inputs and produces two binary outputs. One
of the input variables designates the augend and other designates the addend. Mostly, the
third input represents the carry from the previous lower significant position. The output
variables produce the sum and the carry.

The simplified Boolean functions of the two outputs can be obtained as below:
Sum S = x xor y xor z
Carry C = xy + xz + yz
Where x, y & z are the two input variables.
A half subtractor is a combinational circuit that subtracts two binary inputs and produces
their difference. It also has an output to specify if a 1 has been borrowed. The circuit has
two inputs, one representing the Minuend bit and the other Subtrahend bit. The circuit
produces two outputs, the difference and borrow. The Boolean functions for the tow
outputs can be written as

D = x’y + xy’

B = x’y
Truth Table for HALF ADDER:

INPUT OUTPUT
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Logic Diagram for Half Adder:

Waveform for Half Adder:

Truth Table for Full Adder:

INPUT OUTPUT
A B CIN SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Logic Diagram:
Full subtractor is a combinational circuit that subtraction between two binary inputs, taking into
account that a 1 may have been borrowed by a lower significant sage. The circuit has three inputs,
representing the minuend bit, the Subtrahend bit and the previous borrow bit respectively. The two
outputs, d and b represent the difference and output borrows. The Boolean functions for the tow
outputs can be written as

D = x’yz + xy’z+xy’z’+xyz

B = x’y+x’z+yz

Program

Half Adder Design in Verilog

module my_halfadrvlog (s,c,x,y);

output s,c;

input x,y;

xor (s,x,y);

and (c,x,y);

endmodule

Full Adder Design in Verilog

module my_fuladrvlog (s,c,x,y,z);

output s,c;

input x,y,z;

xor (s,x,y,z);

assign c = ((x & y) | (y & z) | (z & x));

endmodule

Half Subtractor Design in Verilog

module my_halfsubvlog (d,b,x,y);

output d,b;

input x,y;

xor (d,x,y);

and (b,~(x),y);

endmodule
Waveform:

Truth Table for HALF SUBTRACTOR :

INPUT OUTPUT
A B SUM CARRY
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Logic Diagram for HALF SUBTRACTOR:

Waveform:
Full Subtractor Design in Verilog

module my_fulsubvlog (d,b,x,y,z);

output d,b;

input x,y,z;

xor (d,x,y,z);

assign b = ( ( (~(x))&y) | (y & z) | ((~(x)) & z));

endmodule

Truth Table for FULL SUBTRACTOR:

INPUT OUTPUT
A B CIN SUM CARRY
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Logic Diagram:

Waveform:

Result : Thus the Adder Circuits are designed in Verilog HDL and the output are verified.
 1. b) MULTIPLEXER REALISATION IN VERILOG

Aim:
Design a 4 to 1 multiplexer and 1 to 4 De multiplexer circuit in Verilog.

Apparatus Required:

Simulation Tools: Verilog – Xilinx Model Sim;

Theory:
A digital multiplexer is a combinational circuit that selects binary information from one
of many input lines and directs it to a single output line. Multiplexing means transmitting a
large number of information units over a smaller number of channels or lines. The selection of
a particular input line is controlled by a set of selection lines. Normally, there are 2n input
lines and n selection lines whose bit combinations determine which input is selected. A
multiplexer is also called a data selector, since it selects one of many inputs and steers the
binary information to the output lines.

The de-multiplexer performs the reverse operation of a multiplexer. It is a

combinational circuit which accepts a single input and distributes it over several outputs. The
number of output lines is ‘n’ and the number of select lines is 2n lines. De-multiplexer ICs may
have an enable input to control the operation of the unit. When the enable input is in a given
binary state (the disable state), the outputs are disabled, and when it is in the other state (the
enable state), the circuit functions as normal de-multiplexer. The size of the de-multiplexer is
specified by the single input line and the number 2n of its output lines.

4 – to – 1 Multiplexer Design in Verilog

module my_4to1muxbehavirvlog (y,i,en,sel);
output y;
input [0 : 3] i;
input [0 : 1] sel;
input en;
reg y;
always @ (i or en or sel)
begin
if (en === 0)
begin
case (sel)
2'b00 : y = i[0];
2'b01 : y = i[1];
2'b10 : y = i[2];
2'b11 : y = i[3];
default : y = 1'bX;
endcase
end
else
y = 1'bZ;
end
endmodule

1 – to – 4 De-multiplexer Design in Verilog

module my_1to4demuxgatevlog(y,i,en,s);
output [0 :3] y;
input i,en;
input [0 : 1] s;
and (y[0],~en,~s[1],~s[0],i);
and (y[1],~en,~s[1],s[0],i);
and (y[2],~en,s[1],~s[0],i);
and (y[3],~en,s[1],s[0],i);
endmodule

Logic Diagram:

Waveform:
Logic Diagram for Demultiplexer :

Waveform:

Conclusion:

Thus the logic circuit for the 4 to 1 multiplexer and 1 to 4 Demultiplexer are designed in
Verilog HDL and the output are verified.
 Ex No 1.(c) Encoder and Decoder
Aim:

Realize Encoder and Decoder in Verilog .

Apparatus Required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator;

Theory:

An encoder has 2n (or fewer) input lines and ‘n’ output lines. The output lines generate
the binary code corresponding to the input value. In encoders, it is assumed that only one
input has a value of 1 at any given time. The encoders are specified as m-to-n encoders
where m ≤ 2n.

A decoder is a combinational circuit that converts binary information from ‘n’ input lines
to a maximum of 2n unique output lines. It performs the reverse operation of the encoder. If
the n- bit decoded information has unused or don’t-care combinations, the decoder output
will have fewer than 2n outputs. The decoders are represented as n-to-m line decoders,
where m ≤ 2n. Their purpose is to generate the 2n (or fewer) minterms of n input variables.
The name decoder is also used in conjunction with some code converters such as BCD-to-
seven-segment decoders. Most, if not all, IC decoders include one or more enable inputs to
control the circuit operation. A decoder with an enable input can function as a de-
multiplexer.
Program

4 – to – 2 Encoder Design in Verilog

module my_encodr2 (y,x);

output [0:3] y;

input [0:3] x;

reg [0:1] y;

always @ (x)

case (x)

4'b0001: y = 11;

4'b0010: y = 10;

4'b0100: y = 01;

4'b1000: y = 00;
 default : $display ("Invalid Input");

endcase

endmodule

2 – to – 4 Decoder Design in Verilog:

module my_decodr(d,x);

output [0:3] d;

input [0:1] x;

wire [0:1] temp;

not n1(temp[0],x[0]);

not n2(temp[1],x[1]);

and a0(d[0],temp[0],temp[1);

and a1(d[1],temp[0],,x[1]);

and a2(d[2],x[0], temp[1]);

and a3(d[3], x[0],x[1]);

endmodule

Logic Diagram for Encoder:

Truth Table:

i/p 0 i/p1 i/p 2 i/p3 o/p0 o/p1

1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1
Waveform:

Logic diagram for Decoder :

Truth Table:

INPUTS OUTPUTS
DIN X Y D0 D1 D2 D3

1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

Result :

Thus the logic circuit for the Encoder and decoder are designed in Verilog HDL and the output are verified.
 Ex No 1.(d) Code Converter
Aim:
Realize the code converter in Verilog

Apparatus Required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator.

Theory:

The availability of a large variety of codes for the same discrete elements of information
results in the use of different codes by different digital system. It is sometimes necessary to use
the output of one system as the input to another. A conversion circuit must be inserted between
the two systems if each uses different codes for the same information. Thus, a code converter is
a circuit that makes the two systems compatible even though each uses a different binary code.
To convert from binary code A to binary code B, the input lines must supply the bit
combination of elements as specified by code A and the output lines must generate the
corresponding bit combination of code B. A combinational circuit which performs this
transformation by means of logic gates, is known to be Code Converter.

Code Converters Design in Verilog:

module my_codeconvertrvlog (op,ip);

output [4 : 0] op;
input [1 : 0] ip;
reg [4 : 0] op;
integer choice;
initial
choice = 1'd0;
always @ (choice or ip)
begin
case (choice)
0:
begin
$display ("Enter UR Choice ");
$display (" 1'd1 For Binary to Gray");
$display (" 1'd2 For Gray to Binary");
end
1:
begin
op[0] = (ip[1] ^ ip[0]);
op[1] = (ip[2] ^ ip[1]);
op[2] = (ip[3] ^ ip[2]);
op[3] = ip[3];
 op[4] = 1'b 0;
end
2:
begin
op[0] = ((ip[3]^ip[2])^(ip[1]^ip[0]));
op[1] = ip[3]^ip[2]^ip[1];
op[2] = ip[3]^ip[2];
op[3] = ip[3];
op[4] = 1'b 0;
end
default :
begin
$display ("Entered a Wrong Option");
$display ("To Know the choices Enter 1'd0");
end
endcase end endmodule
Binary to Gray Code Converter

Binary to Gray Converter

BINARY CODE GRAY CODE

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
 1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Binary to Gray Converter

Gray to Binary Converter

Gray to Binary Converter

GRAY CODE BINARY CODE

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Waveform:

Result :

Thus the code Converter is designed using Verilog HDL and the outputs also verified.
 Ex No 1.(e) Flipflop Realization
Aim:

Realize the S-R Flip-Flop in Verilog HDL.

Apparatus required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator

Theory:

A flip-flop circuit can maintain a binary state indefinitely (as long as power is delivered
to the circuit) until directed by an input signal to switch states. The basic flip-flop has two
outputs Q and Q’. The outputs Q and Q’ are always complementary. The flip-flop has two
stable states which are known as the 1 state and 0 state. In the 1 state, the output Q = 1 and
hence called Set state. In the 0 state, the output Q’ = 0 and also called as Reset or Clear state.
The basic flip-flop can be obtained by using NAND or NOR gates. The basic flip-flop circuit is
also called latch, since the information is latched or locked in this circuit. The basic flip-flop
is also called the basic binary memory cell, since it maintains a binary state as long as power
is available. It is often required to set or reset the basic memory cell in synchronism with a
train of pulses known as clock. Such a circuit is referred to as clocked set-reset (S-R) Flip-Flop.
In the S-R flip-flop, when the power is switched on, the state of the circuit is uncertain. It is
desired to initially set or reset the flip-flop, i.e. the initial state of the flip-flop is to be
assigned. This is accomplished by using the direct or asynchronous inputs, referred to as
preset and clear inputs. These inputs may be applied at any time between clock pulses and
are not in synchronism with the clock.

SR Flip Flop Gate Level Design in Verilog

module my_srffgatevlog (q,qbar,s,r,clk,clr);
output q,qbar;
input s,r,clk,clr;
wire a,b,c,d,high;
assign high = 1'b1;
nand na0(a,s,clk);
nand na1(b,r,clk);
nand na2(c,qbar,a);
nand na3(d,q,b);
and a0 (q,c,clr);
and a1 (qbar,d,high);
endmodule
Truth Table:

INPUTS OUTPUTS
CLK S R QN QN+1 STATE
↑ 0 0 0 0 NO CHANGE
↑ 0 0 1 1 NO CHANGE
↑ 0 1 0 0 RESET
↑ 0 1 1 0 RESET
↑ 1 0 0 1 SET
↑ 1 0 1 1 SET
↑ 1 1 0 X INDETERMINATE
↑ 1 1 1 X INDETERMINATE.
0 X X 0 0 NO CHANGE
0 X X 1 1 NO CHANGE
Logic Diagram:

Waveforms:

Conclusion:

Thus the S-R flip-flop is realized in Verilog HDL and the output is verified.
 Ex No 1.(f) Asynchronous ripple counter
Aim:

To realize an asynchronous ripple counter in Verilog

Apparatus required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator

Theory:

In a ripple counter, the flip-flop output transition serves as a source for triggering other flip-
flops. In other words, the Clock Pulse inputs of all flip-flops (except the first) are triggered
not by the incoming pulses, but rather by the transition that occurs in other flip-flops. A
binary ripple counter consists of a series connection of complementing flip-flops (JK or T
type), with the output of each flip-flop connected to the Clock Pulse input of the next
higher-order flip-flop. The flip-flop holding the LSB receives the incoming count pulses. All
J and K inputs are equal to
1. The small circle in the Clock Pulse /Count Pulse indicates that the flip-flop
complements during a negative-going transition or when the output to which it is
connected goes from 1 to 0. The flip-flops change one at a time in rapid succession, and
the signal propagates through the counter in a ripple fashion. A binary counter with
reverse count is called a binary down-counter. In binary down-counter, the binary count
is decremented by 1 with every input count pulse.

4- Bit Asynchronous Ripple Counter Design in Verilog

module my_asyncbincnt (q,qbar,clk,reset);

output [0 : 3] q;
output [0 : 3] qbar;
input clk,reset;
wire [0 : 1] temp;
reg high;
initial
high = 1'b1;
my_jkffbehaviorvlog ff1 (q[0],qbar[0],high,high,clk,reset);
my_jkffbehaviorvlog ff2 (q[1],qbar[1],high,high,q[0],reset);
my_jkffbehaviorvlog ff3 (q[2],qbar[2],high,high,q[1],reset);
my_jkffbehaviorvlog ff4 (q[3],qbar[3],high,high,q[2],reset);
endmodule
 module my_jkffbehaviorvlog (q,qbar,j,k,clk,reset);
output q,qbar;
input j,k,clk,reset;
reg q,qbar;
always @ (negedge clk or reset)
if (~reset)
begin
q = 1'b0;
qbar = 1'b1;
end
else if (reset)
begin
if (j==0 && k ==0)
begin
q = q;
qbar = qbar;
end
else if ( j== 0 && k ==1)
begin
q = 1'b0;
qbar = 1'b1;
end
else if (j==1 && k == 0)
begin
q = 1'b1;
qbar = 1'b0;
end
else if (j ==1 && k ==1)
begin
q = ~q;
qbar = ~qbar;
end
else
begin
q = 1'bz;
qbar = 1'bz;
end
end
endmodule;
Logic Diagram:
State Table:

Truth Table for JK flip-flop:

J K Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 Qn

Waveforms In Binary

Conclusion:

Thus the asynchronous ripple counter is designed in Verilog HDL and the output is verified.
 Ex No 1.(g) RANDOM NUMBER GENERATOR REALIZATION IN
VERILOG.

Aim:

Realize the Random Number generator in Verilog.

Apparatus Required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator;

Theory:

Random numbers for polynomial equations are generated by using the shift
register circuit. The random number generator is nothing but the Linear Feedback Shift
Register(LFSR). The shift registers are very helpful and versatile modules that facilitate the
design of many sequential circuits whose design may otherwise appear very complex. In its
simplest form, a shift register consists of a series of flip-flops having identical
interconnection between two adjacent flip-flops. Two such registers are shift right
registers and the shift left registers. In the shift right register, the bits stored in the flip-
flops shift to the right when shift pulse is active. Like that, for a shift left register, the bits
stored in the flip-flops shift left when shift pulse is active. In the shift registers, specific
patterns are shifted through the register. There are applications where instead of specific
patterns, random patterns are more important. Shioft registers can also built to generate
such patterns , which are pseudorandom in nature. Called Linear Feedback Shift Registers
(LFSR’s), these are very useful for encoding and decoding the error control codes.

Main Module:
module main(q,qbar,clk,reset);
inout [0:3]q;
inout [0:3]qbar;
input clk,reset;

wire a,b;
xor (a,q[3],qbar[2]);
not (b,a);
jk ff0(q[0],qbar[0],a,b,clk,reset);
jk ff1(q[1],qbar[1],q[0],qbar[0],clk,reset);
jk ff2(q[2],qbar[2],q[1],qbar[1],clk,reset);
jk ff3(q[3],qbar[3],q[2],qbar[2],clk,reset);
endmodule

JK Flip-flop:

module jk(q,qbar,j,k,clk,reset);
output q,qbar;
input j,k,clk,reset;
 reg q,qbar;
always @(posedge clk or posedge reset)
if (reset)
begin
q=1'b0;
qbar=1'b1;
end
else
begin
if (j==0 && k==0)
begin
q=q;
qbar=qbar;
end
else if (j==0 && k==1)
begin
q=1'b0;
qbar=1'b1;
end
else if (j==1 && k==0)
begin
q=1'b1;
qbar=1'b0;
end
else if (j==1 && k==1)
begin
q=~q;
qbar=~qbar;
end
else
begin
q=1'bz;
qbar=1'bz;
end
end
endmodule

Logic Diagram:
Waveforms:

Conclusion:

Thus the Random number Generator is designed and simulated in Verilog HDL
 EX NO. 5 DESIGN of 8 bit processor
AIM:

To design a general purpose processor using Verilog HDL.

APPARATUS REQUIRED:

Software: Xilinx Project navigator,Modelsim

Theory :
A single cycle processor is a processor that carries out one instruction in a single clock cycle.

Single Datapaths is equivalent to the original single-cycle datapath The data memory has only
one Address input. The actual memory operation can be determined from the MemRead and
MemWrite control signals. There are separate memories for instructions and data. There are 2
adders for PC-based computations and one ALU. The control signals are the same. Below we
have the block diagram for the processor architecture.
ProgramCounter VERILOG CODE

module ProgramCounter
(
input [4:0]d_in,
input reset, clk,
output reg [4:0] d_out
);
always @(posedge clk)
if (reset)
d_out <= 5'b00000;
else
d_out <= d_in;
endmodule

AC VERILOG CODE

module Accumulator
(input [7:0] d_in,
input load, clk,
output reg [7:0] d_out
);
always @(posedge clk)
if (load)
d_out <= d_in;
initial
d_out=8'h00;
endmodule

ALU VERILOG CODE

module ALU
(
input [7:0]a, input [7:0]b,input [2:0]opcode,
output reg [7:0]alu_out
);
always @(opcode,a,b)
case(opcode)
3'b000:alu_out = a + b;
3'b001:alu_out = a - b;
3'b010:alu_out = a&b;
3'b011:alu_out = a|b;
3'b100:alu_out = ~b;
3'b101:alu_out = a^b;
3'b110:alu_out = a~^b;
default:alu_out = 0;
 endcase
endmodule

ADDER VERILOG CODE

module CounterIncrement
(
input [4:0]a, input [4:0]b,
output[4:0] adder_out
);
assign adder_out = a + b;
endmodule
-

MUX-1 VERILOG CODE

module Mux2to1_6Bit
(
input [4:0] i0, i1,input sel,
output[4:0] mux_out
);
assign mux_out = sel ? i1 : i0;
endmodule

MUX-2 VERILOG CODE

module Mux2to1_8Bit
(
input [7:0]i0,i1,input sel,
output [7:0]mux_out
);
assign mux_out =sel?i1:i0;
endmodule

CONTROLLER VERILOG CODE

module Controller(
input [2:0] opcode,
output reg rd_mem,wr_mem,ac_src,ld_ac,pc_src,jmp_uncond);
always @(opcode)
begin
rd_mem = 1'b0;
wr_mem = 1'b0;
ac_src = 1'b0;
pc_src = 1'b0;
ld_ac = 1'b0;
jmp_uncond=1'b0;
case (opcode)
3'b000: //load accumulator from memory
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;
end
-
3'b001:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//SUBTRACT
end
3'b010:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//AND
end
3'b011:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//OR
end
3'b100:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//NOT
end
3'b101:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//XOR
end
3'b110:
 begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//XNOR
end
3'b111:
begin
rd_mem = 1'b0;
wr_mem = 1'b0;
ld_ac = 1'b0;
ac_src = 1'b0;
pc_src=1'b1;
jmp_uncond=1'b1;//JUMP
end
default:
begin
rd_mem = 1'b0;
wr_mem = 1'b0;
ac_src = 1'b0;
pc_src = 1'b0;
ld_ac = 1'b0;
end
endcase //end case
end //end always
endmodule

DATA MEMORY VERILOG CODE

module DataMemory (
input rd, wr,
input [4:0] abus,
input [7:0] in_dbus,
output reg [7:0] out_dbus);
reg [7:0] dm_array [0:31];
always @(rd,abus)
begin
if (rd)
out_dbus = dm_array [abus];
end
always @(wr,in_dbus) //always @(wr or abus or in_dbus)
begin
if (wr)
dm_array [abus] = in_dbus;
end
-
initial
begin
dm_array[0] = 8'h01;
dm_array[1] = 8'h02;
dm_array[2] = 8'h03;
dm_array[3] = 8'h04;
dm_array[4] = 8'h05;
end
endmodule

INSTRUCTION MEMORY VERILOG CODE

module InstructionMemory (input [4:0] abus, output reg [7:0] dbus);

reg [7:0] im_array [0:12];
always @(abus)
dbus = im_array [abus];
initial
begin
im_array[0]= 8'h00; // Initialize Accumulator with 0 and do addition with content of
DataMemory at address 0.
im_array[1]= 8'h21; // Subtract content of accumulator with content of DataMemory at
address 1.
im_array[2]= 8'h42; // Logical AND of accumulator with content of DataMemory at address
2.
im_array[3]= 8'h63; // Logical OR of accumulator with content of DataMemory at address 3.
im_array[4]= 8'h84; // Logical NOT of accumulator with content of DataMemory at address
4.
im_array[5]= 8'hA4; // Logical XOR of accumulator with content of DataMemory at address
4.
im_array[6]= 8'hC4; // Logical XNOR of accumulator with content of DataMemory at
address 4.
im_array[7]= 8'hEA; // Unconditional Jump to 01010 address of Instruction memory.
im_array[10]= 8'h00; // Addition with content of DataMemory at address 0.
im_array[11]= 8'hE0; // Unconditional Jump to 00000 address of Instruction memory.
end
endmodule
-
DATAPATH MEMORY VERILOG CODE

module DataPath (
input reset,ld_ac, ac_src, pc_src, clk,
output [2:0] opcode,
output [4:0] im_abus,
input [7:0] im_dbus,
output [4:0] dm_abus,
output [7:0] dm_in_dbus,
input [7:0] dm_out_dbus,
output [7:0] ac_out,alu_out);
//wire [7:0] ac_out,alu_out,mux2_out;
wire [7:0]mux2_out;
wire [4:0] pc_out, adder_out,mux1_out;
ProgramCounter pc(.d_in(mux1_out),.reset(reset),.clk(clk),.d_out(pc_out)); //instantiation
of all module
CounterIncrement adder(.a(pc_out),.b(5'b00001),.adder_out(adder_out));
Mux2to1_6Bit mux1(.i0(adder_out),.i1(im_dbus[4:0]),.sel(pc_src),.mux_out(mux1_out));
Accumulator ac(.d_in(mux2_out),.load(ld_ac),.clk(clk),.d_out(ac_out));
ALU alu(.a(ac_out),.b(dm_out_dbus),.opcode(opcode),.alu_out(alu_out));
Mux2to1_8Bit mux2(.i0(alu_out),.i1(dm_out_dbus),.sel(ac_src),.mux_out(mux2_out));
assign im_abus = pc_out; //assign im_abus = 6'b000000;
assign opcode = im_dbus [7:5];
assign dm_abus = im_dbus [4:0]; //abus for DataMemory.
assign dm_in_dbus=ac_out;
endmodule

CPU MEMORY VERILOG CODE

module CPU( //The CPU

input clk,reset,
output rd_mem,wr_mem,
output [4:0] im_abus, input [7:0] im_dbus,
output [4:0] dm_abus, output [7:0] dm_in_dbus,
input [7:0] dm_out_dbus,
output [7:0] ac_out,alu_out,
output [2:0] opcode);
//wire [2:0] opcode;
-
wire ac_src,ld_ac, pc_src,jmp_uncond;
DataPath dpu
(.reset(reset),.ld_ac(ld_ac),.ac_src(ac_src),.pc_src(pc_src),.clk(clk),.opcode(opcode)
,.im_abus(im_abus),.im_dbus(im_dbus),.dm_abus(dm_abus),.dm_in_dbus(dm_in_dbus),.dm
_out_dbus(dm_out_dbus),.ac_out(ac_out),.alu_out(alu_out));//dj
Controller cu
(.opcode(opcode),.rd_mem(rd_mem),.wr_mem(wr_mem),.ac_src(ac_src),.ld_ac(ld_ac),
.pc_src(pc_src),.jmp_uncond(jmp_uncond));
endmodule

TEST BENCH CPU MEMORY VERILOG CODE

module testBench;
reg clk;
reg reset;
wire [7:0] im_dbus;
 wire [7:0] dm_out_dbus;
wire rd_mem;
wire wr_mem;
wire [4:0] im_abus;
wire [4:0] dm_abus;
wire [7:0] dm_in_dbus;
wire [7:0] ac_out,alu_out;
wire [2:0] opcode;
CPU uut (
.clk(clk),.reset(reset),.rd_mem(rd_mem),.wr_mem(wr_mem),
.im_abus(im_abus),.im_dbus(im_dbus),.dm_abus(dm_abus),
.dm_in_dbus(dm_in_dbus),.dm_out_dbus(dm_out_dbus),.ac_out(ac_out),.alu_out(alu
_out),.opcode(opcode));
InstructionMemory IM (.abus(im_abus),.dbus(im_dbus));
-
DataMemory DM
(.rd(rd_mem),.wr(wr_mem),.abus(dm_abus),.in_dbus(dm_in_dbus),.out_dbus(dm_out_dbus)
);
initial
begin
clk = 0; reset = 1;//im_dbus =8'hxx;dm_out_dbus = 8'b00000000;
#20 reset = 1'b0;
#500 $finish;
end
always
#10 clk = ~clk;
Endmodule
RTL DIAGRAM
TEST BENCH WAVE FORM :

Data memory :
Location 00 01 02 03 04
Data 01 02 03 04 05
Instruction memory :
Location 0 1 2 3 4 5 6 7 8 9
Instruction 00 21 42 63 84 A4 C4 EA 00 E0
(* operation with accumulator with location in last 5 bit)

Ans (in acc in hex) 00 01 FF 03 07 FA FF 05 06 07

Conclusion:

Thus the 8-bit general purpose processor is designed and simulated in Verilog HDL

EX NO. 6 SIMULATION AND ANALYSIS OF CMOS

COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS
USING CAD TOOLS
AIM:
To Simulate and Analyze the CMOS combinational and sequential logic circuits using CAD tools

SOFTWARE REQUIRED: