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Swastik Gupta - 23.

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CIASSMAte

Date
Page: 4
Suuaaliklpkla Rallo.2.3
Expanimun-1

Am-Naicaliom and inlunsalalion o taulh taul hor AND, OR, MOT,


NANDNo R Ex- oR, EX- NoR galua

1 AND Gli

Y: A.b

O O

1 1

y-A
IASSMAte
Dato
Pge 6
23

NoRCnndL

Ih luulu Aull glaw th tha uAltea a elt O f f s t uom

vi Ex- OR nd

h Julla glsun_oma a th uthig b0N and eni a slcho


OFE e went u

Vi EX- NOR Cnat)

1h Jull alousa t h ks Atchn 0 ON 6 beth Ahe

Cenclusiem

Aua Anelianalhaul all Aahua o


uL aeloau Am thiin nlald sut ao thuin
aruntiultaa thua AmnnUBakn ul ale modd
aulh all an all th qaua on allhamui outcom
X
viabs.itb.acin/vMiabs- dev/labs/dlie
L A Not secure vlabs.iitb.ac.in/vlabs-dev/tabs/digtal electronics/experiments/verificatbior-and-interpretation-truth-table gates itr/round-tefmplate/experime
NSTROCTONS

Verification of truth table for AND gate

A -out
1
B- Check

TRUTH TABLE Print

SerialNo. AB Output Remarks


Correct
COteet
COLeet
COrect

Reset
Virtuial Labs viabsitp.acimyviabs-devyabsy dig
N o t Secure 1 Vlabs.intb.ac.an/vlabs-dev/kabs/dIgital electronics/expefimernts/verihcation- and interpretation-truthtabie gates il/round-letmplate/experime|

INSTRUCTIONS

Experiment to perform AND gate on kit

AND gate using Resis tor Transistor Logie (RTL)


Swinch 1

Resistar 3

Switch2
Resster

Connected!!

p i irantar Q Kesister 4

Switch 3
Virtuial Labs Ca vlabs.itb.ac.in/vlabs-dev/tabs/dig x

DC L A Not secure | vlabs.itb.acin/vlabs-dev/tabs/digital electronicsexperiments/verificatiorn-and-interpretation-truth-table gates-itr/round-template/experimeI

Verification of truth table for OR gate

1 A -out
1
B Check

TRUTH TABLE Print

SerfalNo.A B Output Remarks


Corect
Correct
COec

Cotec

Reset
Virtuial Labs vlabs.itb.acin/viab5 -dev/iabs/diy x X

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INSTRUCTIONS

Experiment to perform OR gate on kit


OR 1ogic implenentation using DRL (Diode
ResistEanoe L4ogLa)

Switch I
Diode 1

Kesbter

Swirch2

Connected!!
vlabsitb.ac.in/viabs -dev/labsydig X F
Vwtal Labs
A Not secure | vlabs.itb.acin/vlabs-dev/labs/digital-electrornics/experiments/verification and interpretation-truth table gates it/round-template/experime

Verification of truth table for NOT gate

A out ChaCkK

TRUTH TABLE t

Serial No. A Output Remarks


Correet

Correct

Reset
Virtal Labs viabs itb.acin/viabs- dev/labs/die X

ANot secure vlabs.itb.acin/vlabs-dev/labs/digital electronics/experiments/verification-and-interpretation-truth table gatesitr/round-template/experime..

INSTRUCTIONS

Experiment to perform NOT gate on kit


ransistor as a NOT gate

Resbtur Bathery

Switch

Resistor

Connected!!

pa transbtor
Virtual Labs iabsitb.ac.inviabs-dev/labs/dig X
A N o t secure | vlabs.intb.acin/viabs dev/tabs/digital -electronics/experments/verification-and-interpretation- truth-table-gates lir/round-termplate/experime.

Verification of truth table for NAND gate

1
AT
-out
B Check

TRUTH TABLE Print

SerialSo. A B Output Remarks


0
correct
Correet
Corect
Correct

Resel
viabsitbacin/viabs-dev/labs/dig XX
Virtual Latbs
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INSTRUCTIONS

Experiment to perform NAND gate on kit

NAND gate uslng Reslstor Translstor Loglo ( T )

Resstnr

Switch 2
Resbtar
Du onnected!!

p tasntar 9

Smitch 3
Resistor 2

mpa transhdar
viabsitb.acin/vlabs- dev/labs/dig X
Vitual Labs
PC ANot secure | Vlabs.itb.acin/vlabs-dev/labs/digital -electronics/experiments/verification-and-interpretation-truth-table gates tt/round-template/experime.

Verification of truth table for NOR gate

1 A
1
B -Q Gneck

TRUTH TABLE Prnt

SerialNo. A B Output Remark

Corect
0 0 Correct
Lorrect
Cofrect

Reset
irtual Lat Mlabs.itb.acinvlabs dev/Aabs/dig X +

A Not secure| vlabs.itb.acin/vlabsdev/labs/digital electronics/experiments/verification and-interpretation truth table gates it/round template/experime...|

INSTRUCTIONS

Experiment to perform NOR gate on kit

gate usingReniator-Tranaintor Logic (RTL)


h1

Resistor 3

Smitch
Kettor

Mt Balb Connected!!
pa traster
Switch 3

p n transalor
Virtual Labs viabsitD.acinyviabs-dev/labsydigX abs.intb.acinviabs-devlatrogia
L A Not secure vlabs.iitb.ac.invlabs-dev/tabs/digtal electronics/experiments/verificatior-and-interpretation-truth-table gatesitr/round-tefmplate/experime

Verification of truth table for XNOR gate

A out
B Check

TRUTH TABLE PInt

Serial No.A B Output Remarks


corect
COrec
COrreCt

Corect

Reset
viabsitbacin/viabs-dev/labs/dig XX
Virtual Labs
Not secure vlabs.intb.ac.in/vlatbs-dev/tabs/digital -electronics/experiments/verificatior-and-interpretation-truth-table gates-itr/round-letmplate/experime.

Experiment to perform XNOR gate on kit

Power
XNOR gate using Resistor-
Transistor Logio (RTL)
Keshtor Resstor 5
Resistor 1

5V =
or Q3
Resintor

Reshar Resistor 1

p aasstor Q
5V
Switch 2

Bulb

npn tramsistor Q2

pa trsair

pa ta
Resintor

R1,2,5,6,7,8,11,12- 10 kilo-oln

Kesntor 1
t3,4,9,10,13 -
5
kilo -obm
Virtual Labs viabsitbacin/viabs-dev/labs/dig X X

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INSTRUCTIONS

Verification of truth table for XOR gate

A -out
1
B
TRUTH TABLE PTInt

SerialNo.A B Output Remarks


0 cofrect
ect

comecr

Reset
Virtuial Labs viab.tt.ac.inyviatn- devlabsy digital viabs.itb.acinyviabs-dev/iabsydr X

A Not secure Viab5.ntb.ac.inVlabs-de/tatos/digirtal -electronicsyexpefments/yverilicatior-and -inter pretation-truth- tatDe gates /roundlefmplate/experime.

INSTRUCTIONS

Experiment to perform XOR gate on kit

Fower
Resistor 3 xOR gate
Reshtor 11 using Resistor
Transistor Logic (R
Reststor 2 p a tranitor Q

Switch 1

a o r Q2
Resator7
5 V

wansster Q
Restor
Swich2

5V Reskstor4

Resistor 9 a

eshterS

pa traasstor Q4

R1,2,4,5,7,8 - 10 kilo-om

R 3 , 6 , 9 - 5 kilo-obm

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