MSCTS, Classic and CCD CTS Reports

MSCTS REPORTS
icc2_shell> report_global_timing
Information: The stitching and editing of coupling caps is turned OFF for design
'chiptop_lib:powerplane_no_drc.design'. (TIM-125)
Information: Design Average RC for design powerplane_no_drc (NEX-011)
Information: r = 1.980745 ohm/um, via_r = 0.906069 ohm/cut, c = 0.160584 ff/um, cc = 0.000000 ff/um
(X dir) (NEX-017)
Information: r = 2.596739 ohm/um, via_r = 0.587850 ohm/cut, c = 0.184656 ff/um, cc = 0.000000 ff/um
(Y dir) (NEX-017)
Information: Update timing completed net estimation for all the timing graph nets (TIM-111)
Information: Net estimation statistics: timing graph nets = 5878, routed nets = 122, across physical
hierarchy nets = 0, parasitics cached nets = 5878, delay annotated nets = 0, parasitics annotated nets =
0, multi-voltage nets = 0. (TIM-112)
****************************************
Report : global timing
-format { narrow }
Design : ChipTop
Version: S-2021.06-SP4
Date : Wed Sep 28 19:12:16 2022
****************************************
Setup violations
--------------------------------------------------------------
Total reg->reg in->reg reg->out in->out
--------------------------------------------------------------
WNS -0.41 0.00 0.00 -0.41 0.00
TNS -3.43 0.00 0.00 -3.43 0.00
NUM 17 0 0 17 0
--------------------------------------------------------------
Hold violations
--------------------------------------------------------------
--------------------------------------------------------------
WNS -0.17 -0.17 0.00 0.00 0.00
TNS -56.78 -56.78 0.00 0.00 0.00
NUM 727 727 0 0 0
--------------------------------------------------------------
icc2_shell> report_utilization
****************************************
Report : report_utilization
Design : ChipTop
Date : Wed Sep 28 19:13:31 2022
****************************************
Utilization Ratio: 0.1755
Utilization options:
- Area calculation based on: site_row of block powerplane_no_drc

- Categories of objects excluded: hard_macros macro_keepouts soft_macros io_cells
hard_blockages
Total Area: 62393.0112
Total Capacity Area: 15298.2864
Total Area of cells: 2684.7792
Area of excluded objects:
- hard_macros : 26888.3275
- macro_keepouts : 20362.0620
- soft_macros : 0.0000
- io_cells : 0.0000
- hard_blockages : 0.0000
Utilization of site-rows with:
- Site 'unit': 0.1755
0.1755
icc2_shell> report_clock_qor
Info: Initializing timer in CLOCK_SYN_REPORT_MODE
****************************************
Report : clock qor
-type summary
Design : ChipTop
Date : Wed Sep 28 19:14:12 2022
****************************************
Attributes
===========
M Master Clock
G Generated Clock
& Internal Generated Clock
U User Defined Skew Group
D Default Skew Group
* Generated Clock Balanced Separately
===========================================
==== Summary Reporting for Corner fast ====
===========================================
======================================================= Summary Table for Corner fast

========================================================
Clock / Attrs Sinks Levels Clock Clock Clock Max Global Trans DRC Cap
DRC Wire
Skew Group Repeater Repeater Stdcell Latency Skew Count Count

Length
Count Area Area
------------------------------------------------------------------------------------------------------------------------------------------
----
### Mode: func, Scenario: func_fast
clock M,D 714 8 246 316.75 316.75 0.33 0.00 0 0 11602.91
------------------------------------------------------------------------------------------------------------------------------------------
----
All Clocks 714 8 246 316.75 316.75 0.33 0.00 0 0 11602.91
Warning: Please use -largest / -smallest / -all switches with -show_verbose_paths / -show_paths to
report the clock paths. (CTS-956)
===========================================
==== Summary Reporting for Corner slow ====
===========================================
======================================================= Summary Table for Corner slow

========================================================
DRC Wire

Length
Count Area Area
------------------------------------------------------------------------------------------------------------------------------------------
----
### Mode: func, Scenario: func_slow
clock M,D 714 8 246 316.75 316.75 0.00 0.00 0 0 11602.91
------------------------------------------------------------------------------------------------------------------------------------------
----
All Clocks 714 8 246 316.75 316.75 0.00 0.00 0 0 11602.91
1
icc2_shell> report_power
****************************************
Report : power
-significant_digits 2
Design : ChipTop
Date : Wed Sep 28 19:15:30 2022
****************************************
Information: Activity propagation will be performed for scenario func_slow.
Note - message 'POW-024' limit (10) exceeded. Remainder will be suppressed.
Infomation: Fast mode activity propagation power.rtl_activity_annotation setup is ignored. Always use
accurate mode.
**** Information : No. of simulation cycles = 8 ****
Mode: func
Corner: slow
Scenario: func_slow
Voltage: 0.72
Temperature: 125.00
Voltage Unit : 1V
icc2_shell> report_qor
****************************************
Report : qor
Design : ChipTop
Date : Wed Sep 28 19:17:11 2022
****************************************
Scenario 'func_fast'
Timing Path Group 'in2reg'
----------------------------------------
Levels of Logic: 4
Critical Path Length: 2.07
Critical Path Slack: 1.28
Critical Path Clk Period: 3.30
Total Negative Slack: 0.00
No. of Violating Paths: 0
Worst Hold Violation: 0.00
Total Hold Violation: 0.00
No. of Hold Violations: 0
----------------------------------------
Timing Path Group 'reg2out'
----------------------------------------
Levels of Logic: 64

Critical Path Slack: -0.41
Total Negative Slack: -3.43
----------------------------------------
Timing Path Group 'reg2reg'
----------------------------------------
Levels of Logic: 43
Worst Hold Violation: -0.17
Total Hold Violation: -56.78
----------------------------------------
Scenario 'func_slow'

----------------------------------------
Levels of Logic: 43
----------------------------------------
Cell Count
----------------------------------------
Hierarchical Cell Count: 2
Hierarchical Port Count: 216
Leaf Cell Count: 5604
Buf/Inv Cell Count: 1278
Buf Cell Count: 339
Inv Cell Count: 939
CT Buf/Inv Cell Count: 0
Combinational Cell Count: 4890
Single-bit Isolation Cell Count: 0
Multi-bit Isolation Cell Count: 0

Isolation Cell Banking Ratio: 0.00%
Single-bit Level Shifter Cell Count: 0
Multi-bit Level Shifter Cell Count: 0
Level Shifter Cell Banking Ratio: 0.00%
Single-bit ELS Cell Count: 0
Multi-bit ELS Cell Count: 0
ELS Cell Banking Ratio: 0.00%
Sequential Cell Count: 714
Integrated Clock-Gating Cell Count: 0
Sequential Macro Cell Count: 4
Single-bit Sequential Cell Count: 710
Multi-bit Sequential Cell Count: 0
Sequential Cell Banking Ratio: 0.00%
BitsPerflop: 1.00
Macro Count: 4
----------------------------------------
Area
----------------------------------------
Combinational Area: 1927.23
Noncombinational Area: 757.55
Buf/Inv Area: 510.07
Total Buffer Area: 343.30
Total Inverter Area: 166.77

Macro/Black Box Area: 26672.12
Net Area: 0
Net XLength: 65424.07
Net YLength: 47903.47
----------------------------------------
Cell Area (netlist): 29356.90
Cell Area (netlist and physical only): 29963.93
Net Length: 113327.54
Design Rules
----------------------------------------
Total Number of Nets: 5921
Nets with Violations: 419
Max Trans Violations: 5
Max Cap Violations: 419
----------------------------------------
Capacitance Unit : 1fF
Time Unit : 1ns
Temperature Unit : 1C
Dynamic Power Unit : 1pW
Leakage Power Unit : 1pW
Switched supply net power scaling:

scaling for leakage power
Supply nets:
VDD (power) probability 1.00 (default)
VSS (ground) probability 1.00 (default)
Cell Internal Power = 2.99e+08 pW ( 42.1%)
Net Switching Power = 4.11e+08 pW ( 57.9%)
Total Dynamic Power = 7.10e+08 pW (100.0%)
Cell Leakage Power = 3.23e+07 pW
Attributes
----------
u - User defined power group
Power Group Internal Power Switching Power Leakage Power Total Power ( % )
Attrs
-----------------------------------------------------------------------------------------------------------------------------
io_pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 ( 0.0%)
memory -5.77e+07 1.34e+07 1.99e+07 -2.44e+07 ( -3.3%)
black_box 0.00e+00 0.00e+00 0.00e+00 0.00e+00 ( 0.0%)
clock_network 3.49e+08 3.43e+08 8.17e+06 7.00e+08 ( 94.3%)
register 7.12e+05 9.52e+05 1.31e+06 2.97e+06 ( 0.4%)
sequential 0.00e+00 0.00e+00 0.00e+00 0.00e+00 ( 0.0%)

combinational 6.87e+06 5.36e+07 2.96e+06 6.34e+07 ( 8.5%)
-----------------------------------------------------------------------------------------------------------------------------
Total 2.99e+08 pW 4.11e+08 pW 3.23e+07 pW 7.42e+08 pW
CCD cts Report

****************************************
-format { narrow }
Design : ChipTop
Date : Wed Sep 28 16:27:53 2022
****************************************
Setup violations
--------------------------------------------------------------
--------------------------------------------------------------
WNS -0.20 0.00 0.00 -0.20 0.00
TNS -0.75 0.00 0.00 -0.75 0.00
NUM 8 0 0 8 0
--------------------------------------------------------------
Hold violations
--------------------------------------------------------------

--------------------------------------------------------------
WNS -0.17 -0.17 0.00 0.00 0.00
TNS -52.36 -52.36 0.00 0.00 0.00
NUM 702 702 0 0 0
--------------------------------------------------------------
icc2_shell> report_clock_qor -smallest 2
****************************************
Report : clock qor
-type summary
Design : ChipTop
Date : Wed Sep 28 16:28:42 2022
****************************************
Attributes
===========
M Master Clock
G Generated Clock

===========================================
===========================================

========================================================
DRC Wire

Length
Count Area Area
------------------------------------------------------------------------------------------------------------------------------------------
----
clock M,D 714 5 91 25.84 25.84 0.17 0.07 0 0 2105.19
------------------------------------------------------------------------------------------------------------------------------------------
----
All Clocks 714 5 91 25.84 25.84 0.17 0.07 0 0 2105.19
& = Offset derived from max_clock_tree_path / min_clock_tree_path
r = latency reported is for a rising edge triggered event at the sink
f = latency reported is for a falling edge triggered event at the sink
Showing 2 smallest datapoints per clock / skew group (L=largest, S=smallest)

=========================================== Details Table for Corner fast
============================================
Clock / Sink Launch Capture Late Early
Skew Group Name Latency Latency Offset Offset
----------------------------------------------------------------------------------------------------------------------
clock
S GPRs/GPR3_reg_reg_0_/CK 0.10 r 0.10 r -- --
===========================================
===========================================

========================================================
DRC Wire

Length
Count Area Area
------------------------------------------------------------------------------------------------------------------------------------------
----
clock M,D 714 5 91 25.84 25.84 0.09 0.07 0 0 2105.19
------------------------------------------------------------------------------------------------------------------------------------------
----
All Clocks 714 5 91 25.84 25.84 0.09 0.07 0 0 2105.19
& = Offset derived from max_clock_tree_path / min_clock_tree_path
r = latency reported is for a rising edge triggered event at the sink
f = latency reported is for a falling edge triggered event at the sink
Showing 2 smallest datapoints per clock / skew group (L=largest, S=smallest)
=========================================== Details Table for Corner slow

============================================
Clock / Sink Launch Capture Late Early
Skew Group Name Latency Latency Offset Offset
----------------------------------------------------------------------------------------------------------------------
clock
icc2_shell>
****************************************
Report : power
Design : ChipTop
Date : Wed Sep 28 16:30:08 2022
****************************************
Information: Doing activity propagation for mode 'func' and corner 'slow' with effort level 'medium'.
(POW-024)
Information: Timer-derived activity data is cached on scenario func_slow (POW-052)
accurate mode.
Mode: func
Corner: slow
Scenario: func_slow
Voltage: 0.72
Temperature: 125.00
Voltage Unit : 1V
Time Unit : 1ns

Supply nets:
Attributes
----------
Attrs
-----------------------------------------------------------------------------------------------------------------------------
io_pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 ( 0.0%)
memory -5.77e+07 1.33e+07 1.99e+07 -2.45e+07 ( -7.9%)
black_box 0.00e+00 0.00e+00 0.00e+00 0.00e+00 ( 0.0%)

register 7.06e+05 9.86e+05 1.31e+06 3.00e+06 ( 1.0%)
sequential 0.00e+00 0.00e+00 0.00e+00 0.00e+00 ( 0.0%)
-----------------------------------------------------------------------------------------------------------------------------
****************************************
Design : ChipTop
Date : Wed Sep 28 16:30:44 2022
****************************************
- Area calculation based on: site_row of block placement_design

hard_blockages
- hard_macros : 26888.3275
- io_cells : 0.0000
- Site 'unit': 0.1565
0.1565
icc2_shell> report_qor
****************************************
Report : qor
Design : ChipTop
Date : Wed Sep 28 16:32:55 2022
****************************************
Timing Path Group 'in2reg'
----------------------------------------
Levels of Logic: 4

----------------------------------------
Timing Path Group 'reg2out'
----------------------------------------
Levels of Logic: 64
Critical Path Slack: -0.20
Total Negative Slack: -0.75
----------------------------------------
----------------------------------------
Levels of Logic: 43
Worst Hold Violation: -0.17
Total Hold Violation: -52.36
----------------------------------------
Scenario 'func_slow'
----------------------------------------
Levels of Logic: 43
----------------------------------------
Cell Count
----------------------------------------
Hierarchical Cell Count: 2
Hierarchical Port Count: 254
Leaf Cell Count: 5449
Buf/Inv Cell Count: 1123
Buf Cell Count: 184
Inv Cell Count: 939
CT Buf/Inv Cell Count: 0
Combinational Cell Count: 4735
Single-bit Isolation Cell Count: 0
Multi-bit Isolation Cell Count: 0
Isolation Cell Banking Ratio: 0.00%
Single-bit Level Shifter Cell Count: 0
Multi-bit Level Shifter Cell Count: 0
Level Shifter Cell Banking Ratio: 0.00%
Single-bit ELS Cell Count: 0
Multi-bit ELS Cell Count: 0
ELS Cell Banking Ratio: 0.00%
Sequential Cell Count: 714
Integrated Clock-Gating Cell Count: 0
Sequential Macro Cell Count: 4
Single-bit Sequential Cell Count: 710
Multi-bit Sequential Cell Count: 0
Sequential Cell Banking Ratio: 0.00%

BitsPerflop: 1.00
Macro Count: 4
----------------------------------------
Area
----------------------------------------
Combinational Area: 1636.32
Noncombinational Area: 757.55
Buf/Inv Area: 219.16
Total Buffer Area: 52.39
Total Inverter Area: 166.77
Macro/Black Box Area: 26672.12
Net Area: 0
Net XLength: 64317.99
Net YLength: 44582.98
----------------------------------------
Net Length: 108900.97
Design Rules
----------------------------------------
Total Number of Nets: 5865

Nets with Violations: 438
Max Trans Violations: 5
Max Cap Violations: 438
----------------------------------------
Classic CTS Reports
icc2_shell> check_pg_drc
Command check_pg_drc started at Wed Sep 28 15:25:11 2022
Command check_pg_drc finished at Wed Sep 28 15:25:14 2022
CPU usage for check_pg_drc: 1.45 seconds ( 0.00 hours)
Elapsed time for check_pg_drc: 3.10 seconds ( 0.00 hours)
Total number of errors found: 4
4 insufficient spacings on M5
------------
Description of the errors can be seen in gui error set "DRC_report_by_check_pg_drc"
------------
icc2_shell>
icc2_shell> check_pg_connectivity
Loading cell instances...
Number of Standard Cells: 7848
Number of Macro Cells: 4
Number of IO Pad Cells: 0
Number of Blocks: 0
Loading P/G wires and vias...
Number of VDD Wires: 161
Number of VDD Vias: 1742
Number of VDD Terminals: 83
**************Verify net VDD connectivity*****************
Number of floating wires: 0
Number of floating vias: 0
Number of floating std cells: 0
Number of floating hard macros: 0
Number of floating I/O pads: 0
Number of floating terminals: 0
Number of floating hierarchical blocks: 0
************************************************************
Loading cell instances...
Loading P/G wires and vias...
Number of VSS Wires: 124
Number of VSS Vias: 1612
Number of VSS Terminals: 80
**************Verify net VSS connectivity*****************
Number of floating wires: 0
Number of floating vias: 0
Number of floating std cells: 0
Number of floating hard macros: 0
Number of floating I/O pads: 0
Number of floating terminals: 0

Number of floating hierarchical blocks: 0
************************************************************
Overall runtime: 0 seconds.
icc2_shell> check_pg_missing_vias
Check net VDD vias...
Number of missing vias: 0
Checking net VDD vias took 0 seconds.
Check net VSS vias...
Number of missing vias: 0
Checking net VSS vias took 0 seconds.
Overall runtime: 0 seconds.
****************************************
-format { narrow }
Design : ChipTop
Date : Wed Sep 28 15:10:36 2022
****************************************
Setup violations
--------------------------------------------------------------
--------------------------------------------------------------
WNS -0.13 0.00 0.00 -0.13 0.00
TNS -0.28 0.00 0.00 -0.28 0.00
NUM 4 0 0 4 0
--------------------------------------------------------------
Hold violations
--------------------------------------------------------------
--------------------------------------------------------------
WNS -0.17 -0.17 0.00 0.00 0.00
TNS -52.63 -52.63 0.00 0.00 0.00
NUM 743 743 0 0 0
--------------------------------------------------------------
icc2_shell>
icc2_shell> report_qor -summary
****************************************
Report : qor
-summary
Design : ChipTop
Date : Wed Sep 28 15:19:24 2022

****************************************
Timing
---------------------------------------------------------------------------
Context WNS TNS NVE
---------------------------------------------------------------------------
func_fast (Setup) -0.13 -0.28 4
func_slow (Setup) 0.76 0.00 0
Design (Setup) -0.13 -0.28 4
func_fast (Hold) -0.17 -52.63 743
func_slow (Hold) 0.03 0.00 0
Design (Hold) -0.17 -52.63 743
---------------------------------------------------------------------------
Miscellaneous
---------------------------------------------------------------------------
Nets with DRC Violations: 439
icc2_shell> report_clock_qor
****************************************
Report : clock qor
-type summary
Design : ChipTop
Date : Wed Sep 28 15:21:19 2022
****************************************
Attributes
===========
M Master Clock
G Generated Clock
===========================================
===========================================

========================================================
DRC Wire

Length
Count Area Area

------------------------------------------------------------------------------------------------------------------------------------------
----
clock M,D 714 6 96 35.56 35.56 0.11 0.06 0 0 2860.95
------------------------------------------------------------------------------------------------------------------------------------------
----
All Clocks 714 6 96 35.56 35.56 0.11 0.06 0 0 2860.95
===========================================
===========================================

========================================================
DRC Wire

Length
Count Area Area
------------------------------------------------------------------------------------------------------------------------------------------
----
clock M,D 714 6 96 35.56 35.56 0.06 0.05 0 0 2860.95
------------------------------------------------------------------------------------------------------------------------------------------
----
All Clocks 714 6 96 35.56 35.56 0.06 0.05 0 0 2860.95

icc2_shell>
****************************************
Report : power
Design : ChipTop
Date : Wed Sep 28 15:22:54 2022
****************************************
Information: Doing activity propagation for mode 'func' and corner 'slow' with effort level 'medium'.
(POW-024)
Information: Timer-derived activity data is cached on scenario func_slow (POW-052)
accurate mode.
Mode: func
Corner: slow
Scenario: func_slow
Voltage: 0.72
Temperature: 125.00
Voltage Unit : 1V
Time Unit : 1ns
Supply nets:
Warning: Power table extrapolation (extrapolation mode) for port D on cell GPRs/C_reg_reg_31_ for
parameter Tinp. Lowest table value = 0.003000, highest table value = 0.133000, value = 0.137653 (POW-
046)
Warning: Power table extrapolation (extrapolation mode) for port CK on cell GPRs/C_reg_reg_31_ for
parameter Tinp. Lowest table value = inf, highest table value = inf, value = 0.003376 (POW-046)
Warning: Power table extrapolation (extrapolation mode) for port D on cell GPRs/B_reg_reg_31_ for
046)
Warning: Power table extrapolation (extrapolation mode) for port CK on cell GPRs/B_reg_reg_31_ for
Warning: Power table extrapolation (extrapolation mode) for port D on cell GPRs/GPRF_reg_reg_30_ for
046)
Warning: Power table extrapolation (extrapolation mode) for port CK on cell GPRs/GPRF_reg_reg_30_
for parameter Tinp. Lowest table value = inf, highest table value = inf, value = 0.009823 (POW-046)
Warning: Power table extrapolation (extrapolation mode) for port D on cell GPRs/C_reg_reg_30_ for
046)
Warning: Power table extrapolation (extrapolation mode) for port CK on cell GPRs/C_reg_reg_30_ for
Warning: Power table extrapolation (extrapolation mode) for port D on cell GPRs/B_reg_reg_30_ for
046)
Warning: Power table extrapolation (extrapolation mode) for port CK on cell GPRs/B_reg_reg_30_ for
Warning: Rise-Fall toggles on pin MemXHier_MemXb/O[0] are impossible given input states; converted
to zero toggles. (POW-069)
Warning: Rise-Fall toggles on pin MemXHier_MemXa/O[0] are impossible given input states; converted
Warning: Rise-Fall toggles on pin MemYHier_MemXb/O[0] are impossible given input states; converted
Warning: Rise-Fall toggles on pin MemYHier_MemXb/O[1] are impossible given input states; converted
Attributes
----------
Attrs
-----------------------------------------------------------------------------------------------------------------------------
io_pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 ( 0.0%)
memory -5.77e+07 1.33e+07 1.99e+07 -2.46e+07 ( -7.5%)
black_box 0.00e+00 0.00e+00 0.00e+00 0.00e+00 ( 0.0%)
register 7.06e+05 9.80e+05 1.31e+06 2.99e+06 ( 0.9%)
sequential 0.00e+00 0.00e+00 0.00e+00 0.00e+00 ( 0.0%)

-----------------------------------------------------------------------------------------------------------------------------
****************************************
Design : ChipTop
Date : Wed Sep 28 15:24:15 2022
****************************************
- Area calculation based on: site_row of block placement_design

hard_blockages
- hard_macros : 26888.3275
- io_cells : 0.0000
- Site 'unit': 0.1571
0.1571
icc2_shell>

MSCTS, Classic and CCD CTS Reports

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MSCTS REPORTS

Information: Design Average RC for design powerplane_no_drc (NEX-011)

Report : global timing

Date : Wed Sep 28 19:12:16 2022

Total reg->reg in->reg reg->out in->out

TNS -3.43 0.00 0.00 -3.43 0.00

Total reg->reg in->reg reg->out in->out

WNS -0.17 -0.17 0.00 0.00 0.00

TNS -56.78 -56.78 0.00 0.00 0.00

NUM 727 727 0 0 0

Date : Wed Sep 28 19:13:31 2022

Utilization Ratio: 0.1755

- Area calculation based on: site_row of block powerplane_no_drc

Total Area: 62393.0112

Total Capacity Area: 15298.2864

Total Area of cells: 2684.7792

Area of excluded objects:

Utilization of site-rows with:

- Site 'unit': 0.1755

Info: Initializing timer in CLOCK_SYN_REPORT_MODE

Report : clock qor

Date : Wed Sep 28 19:14:12 2022

& Internal Generated Clock

U User Defined Skew Group

D Default Skew Group

* Generated Clock Balanced Separately

==== Summary Reporting for Corner fast ====

======================================================= Summary Table for Corner fast

Skew Group Repeater Repeater Stdcell Latency Skew Count Count

Count Area Area

### Mode: func, Scenario: func_fast

clock M,D 714 8 246 316.75 316.75 0.33 0.00 0 0 11602.91

==== Summary Reporting for Corner slow ====

======================================================= Summary Table for Corner slow

Skew Group Repeater Repeater Stdcell Latency Skew Count Count

Count Area Area

### Mode: func, Scenario: func_slow

clock M,D 714 8 246 316.75 316.75 0.00 0.00 0 0 11602.91

All Clocks 714 8 246 316.75 316.75 0.00 0.00 0 0 11602.91

Date : Wed Sep 28 19:15:30 2022

Information: Activity propagation will be performed for scenario func_slow.

Note - message 'POW-024' limit (10) exceeded. Remainder will be suppressed.

Note - message 'POW-052' limit (10) exceeded. Remainder will be suppressed.

**** Information : No. of simulation cycles = 8 ****

Date : Wed Sep 28 19:17:11 2022

Timing Path Group 'in2reg'

Critical Path Length: 2.07

Critical Path Slack: 1.28

Critical Path Clk Period: 3.30

Total Negative Slack: 0.00

No. of Violating Paths: 0

Worst Hold Violation: 0.00

Total Hold Violation: 0.00

No. of Hold Violations: 0

Timing Path Group 'reg2out'

Critical Path Length: 2.18

Critical Path Clk Period: 3.30

Total Negative Slack: -3.43

Information : No. of simulation cycles = 8