Preprints201808 0288 v1
Preprints201808 0288 v1
Preprints201808 0288 v1
v1
Article
Abstract: In this paper, we discuss voltage control method for buck converter operating in
continuous conduction mode (CCM) using analog feedback system. The aim of this work is to
control the output voltage of a buck converter during the variation in load current. This is obtained
using analog feedback made with operational amplifier (Opamp). However, the same technique
can be applied to other DC-DC converters (e.g boost, buck-boost, cuk converter, etc) in CCM mode,
but for the purpose of analysis buck converter is chosen as an example.
1. Introduction
The issue of voltage regulation cannot be neglected in power electronics circuits. The load
requires a controlled and regulated output voltage to operate. However the non-linear and abrupt
current drawing nature of the load causes the output voltage of the converter to deviate from the
desired level. This could result in failure of the load operation. The main role of a power electronics
circuit is to convert one form of electric power to the other form of electric power by changing either
voltage, frequency or both. In DC-DC converters the level of voltage is either shifted up or down
depending upon the application. In this work the output voltage of a buck converter is controlled.
Buck converter converts its input voltage to a lower dc output level. This work is primarily focused
on voltage control of DC-DC converter (buck converter as an example). The converter is basically
non-linear and time variant in nature. The principles of state space averaging [1]–[6] and circuit
averaging [1], [7], [8] can be applied to obtain linear time invariant (LTI) model. Moreover, this
paper focuses the continuous conduction mode (CCM) operation. During CCM the inductor current
is always positive and never drops to zero. In CCM mode the converter has two states. In general a
DC-DC converter can operate in either continuous conduction mode (CCM) or discontinuous
conduction mode (DCM).
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The simulation model is setup in LTspice where the buck converter along with its controller is
simulated. The simulation model is explained in detail below:
The simulation setup from LTspice in fig1 is discussed where the main objective is to regulate the
output voltage irrespective of output load current. The pulse source is used to model the varying
load.
The converter designed has considerably high end specifications which are hard to achieve. The
details are given:
• Input Voltage vg=5V. The input voltage is 5V.
• Output Voltage v=1.5V. The objective is to regulate the output voltage at 1.5V.
• Output Current iload range= 0-10A. The output current can vary between 0 and 10A.
• Power Stage Switching Frequency=2MHz.
• Bandwidth of the feedback loop/Crossover Frequency = 200KHz, implies Settling Time = 5us.
• Phase Margin (P.M) =50 degrees
The PWM block can generate a duty cycle value ranging [Dmin = 0:05- Dmax = 0:9]. Some important
blocks of the simulation model are:
• Feedback Circuit
This block has operational amplifier with resistors and capacitors making up the proportional
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• Sources
Input Voltage Source = 5V
Output Current Pulse Source = 0-10A
In fig1, for setting the reference level a soft start switching technique is realized. The voltage at
reference node increases in a linear fashion from 0 to 1.5V in 50us. The 1.5V is not applied
upfront as initially the output voltage will be zero. This will produce high error signal pushing the
opamp to its limits to achieve the low error state. In doing so the feedback system may damage the
power MOSFETs.
1) The fig2 shows the output voltage follows a reference value Vref in a linear fashion and the gets
stable when reaches to steady state condition.
2) At 150us there is a step change in the output load current and it jumps from 0 to 10A. The value of
output current pulse source remains high for 30us and then at 180us there is another step change but
this time from 10 to 0A. It is important to observe that the output voltage in such an enormous step
change of load current remains close to 1.5V with good accuracy.
3) During the rising edge of load current, the inductor current rises, output voltage dips and
stabilizes. While during the falling edge of load current, the inductor current drops, output voltage
overshoots and stabilizes.
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4) It is important to note that when the load current takes a positive step, there is an output voltage
dip. The deviation in the output voltage from its reference value is used as an error signal to drive
the opamp. Similarly, during the negative step, the output voltage overshoots the reference value
and the error is used to drive the opamp.
As mentioned that during the positive step of load current from 0 to 10A, there is a voltage dip in the
output voltage. This is verified in fig3 through LTspice where the voltage dip of -78mV is shown. It
should be noted that the control signal in fig2 gets saturated for some time, otherwise the dip would
have been further lower than -78mV .
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2. 𝑉 1.5V
As mentioned that during the negative step of load current from 10 to 0A, there is a voltage
overshoot in the output voltage. This is verified in fig5 through LTspice where the voltage overshoot
of 91.92mV is shown. It should be noted that the control signal in fig2 gets saturated for longer time,
otherwise the dip would have been further lower than 91.92mV .
The same arguments hold true in this case for the settling time which we can see in fig6. There is a
considerable deviation found in the output voltage after 5us of the settling time. This is because the
control signal in fig2 gets saturated for a longer period of time in the case of falling edge.
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5. Conclusions
In this paper a simulation model was setup in LTspice to regulate the output voltage of the buck
converter to 1.5V in the presence of disturbances in the output load current. It was seen that the
output current was varied in step change of 10A. The output current was a pulse source which was
used to trigger a positive edge of 0 to 10A, and negative edge of 10 to 0A at the load side. In both the
cases the output voltage was well regulated near 1.5V. The control signal was saturated for
negligible time because the load current variation was very abrupt and fast, due to which the
controller faced some issues to meet the exact settling time requirements.
Author Contributions: Conceptualization, U.R..; Methodology, U.R.; Software, U.R.; Validation, M.S. and U.R.;
Investigation, A.B and M.S.; Resources, M.S.; Data Curation, A.B and M.S.; Writing-Original Draft Preparation,
U.R.; Writing-Review & Editing, A.B and M.S.; Visualization, U.R.; Supervision, A.B.; Project Administration,
A.B.
References
1. R. W. Erickson and D. Maksimovic, Fundamentals of power electronics. Springer Science & Business Media,
2007.
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2. R. Middlebrook and S. Cuk, “A general unified approach to modeling switching-converter power stages,”
in Power Electronics Specialists Conference, 1976 IEEE. IEEE, 1976, pp. 18–34.
3. J. Mahdavi, A. Emaadi, M. Bellar, and M. Ehsani, “Analysis of power electronic converters using the
generalized state-space averaging approach,” IEEE Transactions on Circuits and Systems I: Fundamental
Theory and Applications, vol. 44, no. 8, pp. 767–770, 1997.
4. R. Middlebrook, “Small-signal modeling of pulse-width modulated switched-mode power converters,”
Proceedings of the IEEE, vol. 76, no. 4, pp. 343–354, 1988.
5. W. Polivka, P. Chetty, and R. Middlebrook, “State-space average modelling of converters with parasitics
and storage-time modulation,” in Power Electronics Specialists Conference, 1980. PESC. IEEE. IEEE, 1980, pp.
119–143.
6. R. Erickson, “Dc-dc power converters department of electrical and computer engineering university of
colorado boulder, co 80309-0425,” Article in Wiley Encyclopedia of Electrical and Electronics Engineering, 1999.
7. E. Van Dijk, J. Spruijt, D. M. O’sullivan, and J. B. Klaassens, “Pwmswitch modeling of dc-dc converters,”
IEEE Transactions on Power Electronics, vol. 10, no. 6, pp. 659–665, 1995.
8. A. Ayachit, A. Reatti, and M. K. Kazimierczuk, “Small-signal modeling of pwm dual-sepic dc-dc converter
by circuit averaging technique,” in Industrial Electronics Society, IECON 2016-42nd Annual Conference of the
IEEE. IEEE, 2016, pp. 3606–3611.