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Plate 3

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Kwon Jiralll

The document describes designing a BCD to seven-segment decoder circuit using logic gates. It includes a truth table that maps BCD input values (0-9, 10-15) to the appropriate segment outputs (a-g) for a 7-segment display. The circuit is designed using AND, OR, and NOT gates based on simplifying the truth table with a Karnaugh map. Components include 6 AND gates, 5 OR gates, 2 NOT gates, a 7-segment display, wires, and a breadboard.

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Plate 3

Uploaded by

Kwon Jiralll
23 views7 pages
The document describes designing a BCD to seven-segment decoder circuit using logic gates. It includes a truth table that maps BCD input values (0-9, 10-15) to the appropriate segment outputs (a-g) for a 7-segment display. The circuit is designed using AND, OR, and NOT gates based on simplifying the truth table with a Karnaugh map. Components include 6 AND gates, 5 OR gates, 2 NOT gates, a 7-segment display, wires, and a breadboard.

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The document describes designing a BCD to seven-segment decoder circuit using logic gates. It includes a truth table that maps BCD input values (0-9, 10-15) to the appropriate segment outputs (a-g) for a 7-segment display. The circuit is designed using AND, OR, and NOT gates based on simplifying the truth table with a Karnaugh map. Components include 6 AND gates, 5 OR gates, 2 NOT gates, a 7-segment display, wires, and a breadboard.

Copyright:

© All Rights Reserved
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23 views7 pages

Plate 3

Uploaded by

Kwon Jiralll
The document describes designing a BCD to seven-segment decoder circuit using logic gates. It includes a truth table that maps BCD input values (0-9, 10-15) to the appropriate segment outputs (a-g) for a 7-segment display. The circuit is designed using AND, OR, and NOT gates based on simplifying the truth table with a Karnaugh map. Components include 6 AND gates, 5 OR gates, 2 NOT gates, a 7-segment display, wires, and a breadboard.

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PROBLEM

A seven-segment display is a form of electronic display device for displaying


decimal numerals that is an alternative to the more complex dot matrix displays. These
are widely used in digital clocks, electronic meters, basic calculators, and other electronic
devices that display numerical information.
A BCD to seven-segment decoder is a combinational circuit that accepts BCD and
generates the appropriate outputs for selection of segments in a display indicator used in
displaying decimal digits.
Design a BCD to seven-segment decoder circuit using the basic gates and
appropriate 7-segment display. A DIP switch may be used as a transducer.

Analysis

1. Discussion

Seven LEDs are grouped in a rectangle to create a seven-segment display. Each of


the seven LEDs is referred to as a segment because, when illuminated, each segment
creates to the display of a number digit (both decimal and hexadecimal). I used six
74LS08 or AND gate, two 74LS04(NOT gate), and five 74LS32(OR gate), to have the
seven-segment displayed the output from 0 to 9.
The first thing that I did was create a truth table in order to generate the output
required to simplify the function. I simplified using the Karnaugh Map after obtaining the
Truth table. I used LTSpice to create a diagram to guide my breadboard implementation. I
also did a lot of troubleshooting before finally getting the right output.
4. Materials

 6 of 74LS08 or AND Gate


 5 of 74LS32 or OR Gate
 2 of 74LS04 NOT Gate (inverter)
 1 seven-segment display
 Wires
 Power Supply
 Breadboard
2. TRUTH TABLE:

# w x y z a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 0 1 1 0 0 0 0

2 0 0 1 0 1 1 0 1 1 0 1

3 0 0 1 1 1 1 1 1 0 0 1

4 0 1 0 0 0 1 1 0 0 1 1

5 0 1 0 1 1 0 1 1 0 1 1

6 0 1 1 0 1 0 1 1 1 1 1

7 0 1 1 1 1 1 1 0 0 0 0

8 1 0 0 0 1 1 1 1 1 1 1

9 1 0 0 1 1 1 1 1 0 1 1

10 1 0 1 0 0 0 0 0 0 0 0

11 1 0 1 1 0 0 0 0 0 0 0

12 1 1 0 0 0 0 0 0 0 0 0

13 1 1 0 1 0 0 0 0 0 0 0

14 1 1 1 0 0 0 0 0 0 0 0

15 1 1 1 1 0 0 0 0 0 0 0
3. Simplification using K-Map Method

a. w’y + w’xz + wx’y’ + x’y’z’


= w’(y+xz) + x’y’(w+z’)
wx
yz
1 1
1 1
1 1
1 1

b. w’x’ + x’y’ + w’y’z’ + w’yz


= w’(x’+y’z’+yz) + x’y’

1 1 1
1 1
1 1
1

c. w’x + w’z + x’y’


= w’(x+z) + x’y’

1 1 1
1 1 1
1 1
1

d. x’y’z’ + wx’y’ + w’x’y + w’yz’ + w’xy’z


= x’y’(z’+w) + w’(y(x’+z’) + xy’z)

1 1
1 1
1
1 1
e. w’yz’ + x’y’z’
= z’(w’y + x’y’)

1 1

1 1

f. wx’y’ + w’xy’ + w’xz’ + w’y’z’


= wx’y’ + w’(y’(x+z’) + xz’)

1 1 1
1 1

g. w’x’y + wx’y’+ w’xy’ + w’xz’


= x’(w’y + wy’) + w’x(y’+z’)

1 1
1 1
1
1 1
4. LOGIC DIAGRAM

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