Translinear Signal Processing Circuits in Standard Cmos Fpaa

Translinear Signal Processing Circuits in Standard CMOS FPAA
Luis Martnez-Alvarado, Jordi Madrenas and Daniel Fernndez

lmartinez@eel.upc.edu
Universitat Politcnica de Catalunya Electronic Engineering Department
L. Martinez-Alvarado
ICECS'09
Outline
Introduction Recongurable Translinear Cell Architecture Application Examples Mapping Application Examples Results
Fourt-Quadrant Multiplier Fourth-Order Low-Pass Filter
Conclusion
ICECS'09
Introduction
Field Programmable Analog Arrays (FPAAs) are highly attractive for prototyping. FPAAs can be classied depending on their operation mode, continuous time or discrete time, and can be implemented by means of: Switched capacitor topologies. Transconductors. Current conveyors. Current integrators. Translinear elements.
ICECS'09
Introduction
Some typical applications of FPAAs are: Filtering. Neuronal networks. Signal processing. V-F converters. Aerospace communication. ...
ICECS'09
Introduction
Pre-distortion circuit The Proposed implementation circuit
M5
M4
M3
M11
IB1
M6 M10
C
M1 M7 M2
Symbol
C
G IB1 IB2
I B2
M8 M12
M9
M13
D.Fernandez and J Madrenas, "A MOSFET-Based Wide-Dynamic Range Translinear Element", Circuits and Systems II , IEEE Transactions on, col. 55, no. 11, pp. 1124-1128, Nov. 2008.
ICECS'09
Introduction
10
-3
10-4 10-5 10-6
HPTE MOS ID=I0egmVGS
I0=1.92e-25 gm=28.6
I0=1.92e-13 gm=27.5
IC or ID [A]
10-7 10-8 10
-9
10-10 10-11 10-12
0.5
1.5
VBE or VGS [V]
Measured I-V characteristic of the wide dynamic range translinear element compared to the transfer characteristic of a MOS transistor of the same size of the output transistor M1 of the translinear element.
ICECS'09
Recongurable Translinear Cell Architecture
in_west
in_north
SM COL
CTL
CAL_C
out
C_BUS DIODE
TE
in_west
in_north
REG PCS 7
CTL out
PCM
in
C TE B IB1 IB2
TE CTL EN in_north
CAL_B
SM GATE
out
G_BUS
TE
E EP /EP 8
in_west
CTL calib out
CTL
PCAP
EN
PCS 7-bit
MODE
PCAP
CTL CAL
TE
REG COL
data bus 8
REG GATE
REG EMI
REG PCS
CAL_C
SM EMI
out
E_BUS
TE
PCS 6-bit
CTL
out
M EP
REG CAL
Block Diagram of the Recongurable Translinear Cell

ICECS'09

The RTC has 7 dierent forms to be congured:
C C
G G
E E
Translinear element
TE with Enz Punzenberger connection
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The RTC has 7 dierent forms to be congured:
Bias current Bias current source source with PC
Current mirror
Current mirror with PC
Programmable Capacitor
ICECS'09
Application Examples Mapping
Io+
Io
Iy +
C
Iu
C
B B
Ix +
C
Iz 1+
C
B B
Iz 1C C
B B
Ix C
Iy -
Iu
C
B B
Ix +
C
Iz 2+
C
B B
Iz 2C
B B
Ix C
TE1
E
TE2
E
TE3
E
TE4
E
TE5
E
TE6
E
TE7
E
TE8
E
TE9
E
TE10 TE11
E E
TE12
E
Vref
Vref
Vref
Io+ Io =
(Ix + Ix ) (Iy + Iy )
Iu
(1)
Four-quadrant multiplier schematic
ICECS'09

Io Iy+
C
B
-
Io+ Iz 1+
C
TE1
E
TE4
E
Vref
RTC[0][0] RTC[0][1] RTC[0][2] RTC[0][3] RTC[0][4]
Iu
C
B
Ix C
C Iz 1
-
Ix+
C
TE2
E
TE6
E
TE5
E
TE3
E
Vref
RTC[1][0] RTC[1][1] RTC[1[2] RTC[1][3]
PCS1
RTC[1][4]
Iy C
B
B
+ C Iz 2
TE7
E
TE10
E
Vref
RTC[2][1] RTC[2][2] RTC[2][3] RTC[2][4]
RTC[2][0]
Iu
C
B
Ix C
C
Ix+ Iz 2- C
TE8
E
TE12
E
TE9
E
TE11
E
Vref
RTC[3][0] RTC[3][1] RTC[3][2] RTC[3][3]
PCS2
RTC[3][4]
Four-quadrant multiplier mapping

ICECS'09
Iin
C C
Ib
C
B B
Ib Iout
C C
B B
C
B Vref
Vref B
TE1
E
TE2
E
TE3
E
TE2n
C1
...
TE2n+1 E
Cn
TE2n+2
Input Stage
1st Stage
nth stage
Output Stage
fci
gm2i 2 Ci
(2)
nth-order low-pass lter schematic
ICECS'09
Application Examples Results
Four-quadrant translinear multiplier DC response at dierent tuning currents Ix = Ix+ Ix : 10 A, 6 A, 2 A, 2 A, 6 A and 10 A

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Four-quadrant translinear multiplier log-scale DC response simulation at dierent tuning currents Ix = Ix+ Ix : 10 A, 1 A, 100 nA, 10 nA, 1 nA
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Transient response of the four-quadrant translinear multiplier

ICECS'09
Fourth-order low-pass lter. Frequency Response at dierent tuning currents. From left to right tuning current Ib is: 1 nA, 10 nA, 100 nA, 1 A and 10 A, with a capacitance of 2.5 pF .
ICECS'09
RTC Layout
ICECS'09
Experimental Results
ICECS'09
Conclusion
Two typical signal-processing application circuits (four-quadrant multiplier and fourth-order low-pass lter) were presented. The simulation results validated the recongurability and the functionality of the 25-cell eld programmable analog array. For the four-quadrant multiplier the dynamic range reaches ve decades. For the low-pass lter a cut-o frequency can be tuned by means of a bias current source. The successful presented results, demonstrate a high potential of translinear element based FPAAs.
ICECS'09

Translinear Signal Processing Circuits in Standard Cmos Fpaa

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Translinear Signal Processing Circuits in Standard CMOS FPAA

Luis Martnez-Alvarado, Jordi Madrenas and Daniel Fernndez

10-4 10-5 10-6

HPTE MOS ID=I0egmVGS

10-10 10-11 10-12

VBE or VGS [V]

Recongurable Translinear Cell Architecture

CTL calib out

Block Diagram of the Recongurable Translinear Cell

Recongurable Translinear Cell Architecture

TE with Enz Punzenberger connection

Recongurable Translinear Cell Architecture

Bias current Bias current source source with PC

Current mirror with PC

Application Examples Mapping

Four-quadrant multiplier schematic

Application Examples Mapping

Four-quadrant multiplier mapping

Application Examples Mapping

nth-order low-pass lter schematic

Application Examples Results

Four-quadrant translinear multiplier DC response at dierent tuning currents Ix = Ix+ Ix : 10 A, 6 A, 2 A, 2 A, 6 A and 10 A

Application Examples Results

Application Examples Results

Transient response of the four-quadrant translinear multiplier

Application Examples Results

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Recongurable Translinear Cell Architecture

Block Diagram of the Recongurable Translinear Cell

Recongurable Translinear Cell Architecture

Recongurable Translinear Cell Architecture

nth-order low-pass lter schematic

Four-quadrant translinear multiplier DC response at dierent tuning currents Ix = Ix+ Ix : 10 A, 6 A, 2 A, 2 A, 6 A and 10 A