EE8351

DIGITAL LOGIC CIRCUITS

S.S.Harish
Department of EEE
UNIT II COMBINATIONAL CIRCUITS
Objective
To study various number systems and simplify the logical expressions
using Boolean functions
To study combinational circuits

• Combinational logic
• representation of logic functions-SOP and POS forms
• K-map representations - minimization using K maps
• simplification and implementation of combinational logic
• multiplexers and de multiplexers - code converters, adders, subtractors, Encoders
and Decoders.
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 Combinational logic

• Interconnection of logic gates

• Output of gates is combination of present values
• Specified logically by Boolean or logic functions
• For each possible input combination one possible value for each output
• List of the output values for each combination of input variables truth table
• tasks:
(1) Analyze the behavior of a given logic circuit
(2) Synthesize a circuit that will have a given behavior

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 Boolean law, theorem and postulates
• Associative law
• (X + Y) + Z = X + (Y + Z) X+X=X
• Commutative law X+1=1
• X+Y= Y+X X+0=X
• Distributive law
• X(Y+Z)=XY + YZ X.X=X
• X+ YZ = (X+Y) (X+Z) X.1=X
• Demorgan’s Theorem X.0=0
• (X+Y)’= X’ Y’
• (XY)’= X’+Y’ X+X’=1
• Absorption law X.X’=0
• X+XY= X
• X(X+Y)=X
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 Function Representation
• Truth table- all possible combination of input and output
• More inputs and outputs- Large table
• Algebric Expression- with variables and operators
• F= X + Y’.Z
X Y Y’ Z F
• F=1, Only when X=1 OR y’z =1 0 0 1 0 0
• Circuit diagram-gate implementation 0 0 1 1 1
0 1 0 0 0
1) Paranthesis 0 1 0 1 0
2) NOT 1 0 1 0 1
3) AND 1 0 1 1 1
4) OR 1 1 0 0 1
1 1 0 1 1
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 Minimization
• Boolean function F(A,B,C)= AB+BC’+A’B
X.X’=0
• Inputs- literals; product- terms X+X’=1
• Minimization- reduction of literals or terms or both
X+1=1

F(x,y) =x (x’ +y) F(x,y,z)=xy+x’z+yz

3-literals, 2-term (3 terms, 6 literals)
=xx’ + xy =xy+x’z+yz(x+x’)
=xy+x’z+xyz+ x’yz
=0+xy;
=xy(1+z) + x’z (1+y)
F=xy (2-literals, 1 term) =xy+x’z (2 terms, 4-literals)
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 Minimization

• Expression types
• Minterms and maxterms
• Product of variables- minterm (m)
• Sum of variables – maxterms (M) X Y Z F
• F=x’y’z+xy’z’+xy’z+xyz’+xyz 0 0 0 0
=m1+m4+m5+m6+m7 0 0 1 1
0 1 0 0
• Sum of minterms
0 1 1 0
• F=M0.M2.M3 1 0 0 1
• Product of maxterms 1 0 1 1

• Canonical forms 1 1 0 1
1 1 1 1 7
 Minimization

• Canonical form- each term- with all variables

• Standard form
• With any number of literals
• Sum of products (SOP) form
• F=x’+xy+xyz’
• Product of Sum (POS) form
• F=x(y’+z)(x+z)

• Standard forms two level gate structure

• F=Σ(1,3,5)
• F=π(0,2,7)

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 Minimization

• Need to remember Boolean laws, theorem and postulates

• More terms may miss
• Don’t care conditions  x
• Systematic method upto Function with 5 variables
• Karnaugh map or K-map

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 Minimization using K-map
Adjacent row / column vary by one bit
Two variable K-map Cover adjacent ones – size-1,2,4

A B 0 1
Covering adjacent ones in first row {size-2}
0
A’(B+B’)=A’
1

Second row A

First column B’

Second column B

Note: adjacent ons in all four places “1” 10

 Minimization using K-map
Three variable K-map
Adjacent row / column vary by one bit
1st column C’
AB C 0 1 Cover adjacent ones – size-1,2,4,8
2nd column C
00
01 Covering adjacent one in first row {size-2}
All eight one
A’B’(C’+C)=A’B’ {x+x’=1}
11 {size-8}
10  output is “1”
Covering adjacent ones in first 2 rows {size 4}
A’(B+B’)(C’+C)= A’

A BC IIIlar Covering adjacent ones in 2nd and 3rd rows

00 01 11 10
B(A+A’)(C’+C)= B
0

1
3rd and 4th row A
4th and 1st row B’
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 Minimization using K-map
Four variable K-map Adjacent row / column vary by one bit
Cover adjacent ones – size-1,2,4,8,16 1st and 2nd column C’D’
AB CD 00 01 11 10 2nd and 3rd column C’D
00 Covering adjacent ones in first row {size-4}
01 A’B’(C’+C)(D+D’)=A’B’ {x+x’=1} First 2 columns
11  C’
10 Covering adjacent ones in first 2 rows {size 8}
A’(B+B’)(C’+C)(D+D’)= A’ Corner elements{size-4}
B’D’
IIIlar Covering adjacent ones in
2nd and 3rd rows B All sixteen ones
{size-16}
3rd and 4th row A  output is “1”
4th and 1st row B’

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 Minimization using K-map

• F(A,B,C)= Σm(0,2,4,6)

AB C 0 1 A BC
00 1 00 01 11 10
01 1 0 1 1

11 1
1 1 1
10 1

F=C’
F=C’

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 Minimization using K-map
F(A,B,C)= π M(1,3,5,7)

AB C 0 1
Minterms function of place of one
00 0 Maxterms function of place of zero
01 0
11 0 F(Minterms)= [F(Maxterms)]’
10 0

F’(A,B,C)= C
F(A,B,C)=C’

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 Minimization using K-map
F(A,B,C,D)=Σm(0,1,3,4,8,9,15)
AB CD 00 01 11 10
00 1 1 1 Square of size 4:
01 1 B’C’
11 1
10 1 1 Square of size 2:
A’C’D’+A’B’D All ones covered atleast by one square

Square of size 1:
ABCD

F(A,B,C,D)=B’C’+A’C’D’+A’B’D+ABCD

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 Minimization using K-map
F(A,B,C,D)=Σm(0,1,3,4,8,9,15)+Σd(2,13)
AB CD 00 01 11 10
00 1 1 1 X Square of size 4:
01 1 B’C’+ A’B’
11 X 1
10 1 1 Square of size 2:
A’C’D’+ABC

F(A,B,C,D)=B’C’ +A’B’+ABC+A’C’D’--------- with don’t care terms

F(A,B,C,D)=B’C’+A’C’D’+A’B’D+ABCD-------without don’t care terms

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 Minimization using K-map
F(a,b,c,d)=Σm(0,1,3,5,6,7,8,12,14)+Σd(9,15)
ab cd 00 01 11 10
00 1 1 1
01 1 1 1
11 1 X 1
10 1 x

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 Implementation
SOP and POS form- circuits with AND, OR, NOT gates
F(A,B,C,D)=B’C’+A’C’D’+A’B’D+ABCD
A B C D

A D
B C

F F

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 Implementation
• Using Universal gates, NAND, NOR
NOT gate AND gate OR gate
X Y O/P X O/P X Y O/P
X Y O/P
0 0 1 0 1 0 0 0
0 0 0
0 1 1 1 0 0 1 1
0 1 0
NAND = (X.Y)’ 1 0 1 1 0 1
1 0 0
1 1 0 1 1 1 1 1 1

X Y O/P
0 0 1
0 1 0
1 0 0
NOR = (X+Y)’ 1 1 0
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 Implementation
• Using only NAND
• Step 1: Obtain minimum SOP form
• Step 2: Implement using AND – OR gates
• Step 3: Replace AND,OR gates with NAND gate. No change in
interconnection of gates. Single literal if any is complimented.
• F(a,b,c)= ab+b’c+c
• ={(ab+b’c+c)’}‘
• ={(ab)’.(b’c)’.c’}’ NAND = (X.Y.Z)’

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 Implementation
• Using only NOR
• Step 1: Obtain minimum POS form
• Step 2: Implement using AND – OR gates
• Step 3: Replace AND,OR gates with NOR gate. No change in
interconnection of gates. Single literal if any is complimented.
• F(a,b,c)= (a+b).(b’+c).c
• ={((a+b).(b’+c).c)’}‘
• ={(a+b)’+(b’+c)’ +c’}’ NOR = (X+Y+Z)’

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 Implementation

• F(A,B,C,D)= π M(2,3,6,7,8,9,12,13), implement using NOR only

AB CD 00 01 11 10 A
00 0 0 C’
F
01 0 0
11 0 0 A’

10 0 0 C

A
F’=(A’C+AC’)’ C’ F
F=(A+C’).(A’+C) POS form
A’
C
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 Implementation
• F(A,B,C,D)= Σm(1,3,5,7,9,11,13,15)+Σd(0,2,4,6,8), implement using
NAND only
AB CD 00 01 11 10
00 x 1 1 x
01 x 1 1 x
11 1 1
10 x 1 1

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 Combinational Circuits
ADDER
• Combinational circuit to perform arithmetic add- Adder
• 2 bits added- half adder- i.e carry not used

Truth Table
x y sum carry x 0 0 1 1
0 0 0 0 y 0 1 0 1
0 1 1 0 Sum 0 1 1 0
1 0 1 0 carry (1)
1 1 0 1

Sum Carry
x y 0 1 x y 0 1 Boolean Function
0 0 1 0 0 0 Sum=x’y+xy’
1 1 0 1 0 1 Carry=xy 24
 Combinational Circuits
ADDER
• 2 bits added with carry  full adder
Truth Table Sum Carry
C1 0
x 0 x y z sum carry x yz x yz
00 01 11 10 00 01 11 10
y 0 0 0 0 0 0
0 1 1 0 1
Sum 0 0 0 1 1 0 0
carry 0 0 1 0 1 0 1 1 1 1 1
1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1 Boolean Function
1 1 0 0 1 Sum=x’y’z+xy’z’+x’yz’+xyz
1 1 1 1 1 Carry=xy+xz+yz

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 Combinational Circuits
ADDER Boolean Function
Sum=x’y’z+xy’z’+x’yz’+xyz=x(+)y(+)z
Carry=xy+xz+yz
x yz
00 01 11 10 Carry=xy+x’yz+xy’z
0 1 =xy+z(x’y+xy’)
=xy+z(x(+)y)
1 1 1 1

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 Combinational Circuits
Subractor

Truth Table
Diff
x y diff Borr a 0 0 1 1
0 0 0 0 b 0 1 0 1
0 1 1 1 Diff 0 1 1 0 x’
Bor
1 0 1 0 Borr 0 1 0 0
1 1 0 0
Diff
Diff Borrow
x y 0 1 x y 0 1 Boolean Function
Borr
0 0 1 0 0 1 Diff=x’y+xy’
1 1 0 1 0 0 Borrow=x’y 27
 Combinational Circuits
Subractor
• 2 bits with carry  full Subractor
Truth Table Diff Borr
C1 0
a 0 x y z diff borr x yz x yz
00 01 11 10 00 01 11 10
b 0 0 0 0 0 0
0 1 1 0 1
Diff 0 0 0 1 1 0 0
borr 0 0 1 0 1 0 1 1 1 1 1
1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1 Boolean Function
1 1 0 0 1 Diff=x’y’z+xy’z’+x’yz’+xyz
1 1 1 1 1 Borr =xy+xz+yz

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 Combinational Circuits
Subractor

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 Combinational Circuits
Adder/Subractor
• Using 2’s compliment
• 1’s compliment using inverter
• Add 1 –from carry
• Instead of 2 circuit –using in 2’s compliment form
• M=0A+B
• M=1A-B
• Next higher bit, so on for n bits

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 Combinational Circuits
Multiplexer
• Many line to one line
• Select- to connect one input to output
• 2:1 Multiplexer O=S’D0+SD1
• 4:1 Multiplexer O=S0’ S1’ D0 + S0’ S1 D1 + S0 S1’ D2 + S0 S1 D3

Application
Boolean function implementation
Pulse train generator
Register to register transfer

O=Σmk Dk; k=0 to 2n-1; n- number of select lines 31

 Combinational Circuits
Multiplexer
Implement F=Σm(1,2,6,7) using 4:1 multiplexer
X’Y’ X’Y XY’ X’Y’
Z’ 0 2 4 6 X Y Z Out
Z
req D0
Z 1 3 5 7
0 0 0 0 Z’ D1
out Z Z’ 0 Z 0 D2 4:1 Mux
0 0 1 1 F
1 D3
0 1 0 1 S0 S1
0 1 1 0
1 0 0 0 X Y
1 0 1 0
1 1 0 1
1 1 1 1

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 Combinational Circuits
Multiplexer
Implement F=Σm(1,3,4,11,12,13,14,15) using 8:1 multiplexer

0 D0
X’Y’Z’ X’Y’Z X’YZ’ X’YZ XY’Z’ XY’Z XYZ’ XYZ
W’ D1
W’ 0 1 2 3 4 5 6 7 0 D2
W 8 9 10 11 12 13 14 15 1 D3
out 0 W’ 0 1 1 W W W D4 8:1 Mux
F
W D5
D6
D7
S0 S1 S3

X Y Z

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 Combinational Circuits
Demultiplexer
• One to Many
• Select- to connect input to one output
• 1:2 Demultiplexer
• D0=S’ E
• D1=S E
• 1:4 Demultiplexer
• D0=S1’ S0‘ E
• D1=S1’ S0 E
Application
• D2=S1 S0‘ E • Multiple Boolean function
• D3=S1 S0 E implementation
• Data transmission
Dk= mk F; k=0 to 2n-1; n- number of select lines • Enable in Microprocessor 34
 Combinational Circuits
Demultiplexer
Boolean Function
F1=Σm(1,2,4,7)
D0
F2=Σm(3,5,6,7) D1
A 1:8 Mux D2
D3 F1
1: 8 Demultiplexer
D4
D5
D6 F2
D7
S0 S1 S2

B C D

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