VS-P400 Series

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Vishay Semiconductors
Power Modules,
Passivated Assembled Circuit Elements, 40 A
FEATURES
• Glass passivated junctions for greater reliability
• Electrically isolated base plate
• Available up to 1200 VRRM/VDRM
• High dynamic characteristics
• Wide choice of circuit configurations
• Simplified mechanical design and assembly
• UL E78996 approved
PACE-PAK (D-19) • Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912

PRIMARY CHARACTERISTICS DESCRIPTION

IO 40 A The VS-P400 series of integrated power circuits consists of
Type Modules - thyristor, standard power thyristors and power diodes configured in a single
Package PACE-PAK (D-19) package. With its isolating base plate, mechanical designs
are greatly simplified giving advantages of cost reduction
and reduced size.
Applications include power supplies, control circuits and
battery chargers.

MAJOR RATINGS AND CHARACTERISTICS

SYMBOL CHARACTERISTICS VALUES UNITS
IO 80 °C 40 A
ITSM, 50 Hz 385
A
IFSM 60 Hz 400
50 Hz 745
I2t A2s
60 Hz 680
I2t 7450 A2s
VRRM Range 400 to 1200 V
VISOL 2500 V
TJ
-40 to +125 °C
TStg

ELECTRICAL SPECIFICATIONS
VOLTAGE RATINGS
VRRM/VDRM, MAXIMUM VRSM, MAXIMUM
IRRM MAXIMUM
REPETITIVE PEAK REVERSE AND NON-REPETITIVE PEAK
TYPE NUMBER AT TJ MAXIMUM
PEAK OFF-STATE VOLTAGE REVERSE VOLTAGE
mA
V V
VS-P401, VS-P421, VS-P431 400 500
VS-P402, VS-P422, VS-P432 600 700
VS-P403, VS-P423, VS-P433 800 900 10
VS-P404, VS-P424, VS-P434 1000 1100
VS-P405, VS-P425, VS-P435 1200 1300

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ON-STATE CONDUCTION
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum DC output current 40 A
IO Full bridge circuits
at case temperature 80 °C
t = 10 ms No voltage 385
Maximum peak, one-cycle t = 8.3 ms reapplied 400
ITSM,
non-repetitive on-state or A
IFSM t = 10 ms 100 % VRRM 325
forward current
t = 8.3 ms reapplied Sinusoidal half wave, 340
t = 10 ms No voltage initial TJ = TJ maximum 745
t = 8.3 ms reapplied 680
Maximum I2t for fusing I2t A2s
t = 10 ms 100 % VRRM 530
t = 8.3 ms reapplied 480
t = 0.1 ms to 10 ms, no voltage reapplied
Maximum I2t for fusing I2t 7450 A2s
I2t for time tx = I2t · tx
Low level value of threshold voltage VT(TO)1 (16.7 % x  x IT(AV) < I <  x IT(AV)), TJ = TJ maximum 0.83
V
High level value of threshold voltage VT(TO)2 (I >  x IT(AV)), TJ = TJ maximum 1.03
Low level value of on-state slope resistance rt1 (16.7 % x  x IT(AV) < I <  x IT(AV)), TJ = TJ maximum 9.61
m
High level value of on-state slope resistance rt2 (I >  x IT(AV)), TJ = TJ maximum 7.01
Maximum on-state voltage drop VTM ITM =  x IT(AV) TJ = 25 °C 1.4 V
Maximum forward voltage drop VFM IFM =  x IF(AV) TJ = 25 °C 1.4 V
Maximum non-repetitive rate of rise of TJ = 125 °C from 0.67 VDRM
dI/dt 200 A/μs
turned-on current ITM =  x IT(AV), Ig = 500 mA, tr < 0.5 μs, tp > 6 μs
Maximum holding current IH 130
TJ = 25 °C anode supply = 6 V, resistive load mA
Maximum latching current IL 250

BLOCKING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum critical rate of rise of
dV/dt TJ = 125 °C, exponential to 0.67 VDRM gate open 200 V/μs
off-state voltage
Maximum peak reverse and off-state IRRM,
TJ = 125 °C, gate open circuit 10 mA
leakage current at VRRM, VDRM IDRM
Maximum peak reverse leakage current IRRM TJ = 25 °C 100 μA
50 Hz, circuit to base, all terminals shorted,
RMS isolation voltage VISOL 2500 V
TJ = 25 °C, t = 1 s

TRIGGERING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum peak gate power PGM 8
W
Maximum average gate power PG(AV) 2
Maximum peak gate current IGM 2 A
Maximum peak negative gate voltage -VGM 10 V
TJ = - 40 °C 3
Maximum gate voltage required to trigger VGT TJ = 25 °C 2 V
TJ = 125 °C Anode supply = 1
TJ = - 40 °C 6 V resistive load 90
Maximum gate current required to trigger IGT TJ = 25 °C 60 mA
TJ = 125 °C 35
Maximum gate voltage that will not trigger VGD 0.2 V
TJ = 125 °C, rated VDRM applied
Maximum gate current that will not trigger IGD 2 mA

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THERMAL AND MECHANICAL SPECIFICATIONS

PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum junction operating
TJ, TStg -40 to +125 °C
and storage temperature range
Maximum thermal resistance,
RthJC DC operation 1.05
junction to case per junction
K/W
Maximum thermal resistance,
RthCS Mounting surface, smooth and greased 0.10
case to heatsink
Mounting torque, base to heatsink (1) 4 Nm
58 g
Approximate weight
2.0 oz.
Case style PACE-PAK (D-19)
Note
(1) A mounting compound is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound

120 120
+

Maximum Total Power Loss (W)

Maximum Total Power Loss (W)

~
100 100 R
th
- SA
=
1K 0.
80 80 /W 7
K/
W
1.5 -Δ
180° K/W R
60 60
(sine) 2K
/W
40 40 3 K/W
5 K/W
20 TJ = 125 °C 20
10 K/W

0 0
0 5 10 15 20 25 30 35 40 0 25 50 75 100 125

93755_01a Total Output Current (A) 93755_01b Maximum Allowable

Ambient Temperature (°C)
Fig. 1 - Current Ratings Nomogram (1 Module Per Heatsink)

30 40
Maximum Average On-State

Maximum Average On-State

35 DC
25
180° 180°
120° 30 120°
Power Loss (W)

Power Loss (W)

20 90° 90°
60° 25 60°
30° RMS limit 30° RMS limit
15 20

15
10
Ø Ø
Conduction angle 10 Conduction period
5 TJ = 125 °C TJ = 125 °C
Per junction 5 Per junction

0 0
0 5 10 15 20 0 5 10 15 20 25 30 35

93755_02 Average On-State Current (A) 93755_03 Average On-State Current (A)

Fig. 2 - On-State Power Loss Characteristics Fig. 3 - On-State Power Loss Characteristics

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130 350
Fully turned-on At any rated load condition and with
325 rated VRRM applied following surge.
Maximum Allowable Case

120 Initial TJ = 125 °C

Peak Half Sine Wave

On-State Current (A)
300 at 60 Hz 0.0083 s
Temperature (°C)

110 180° at 50 Hz 0.0100 s

(Rect.) 275

100 180° 250

(Sine)
225
90
200
80
175 Per junction
Per module
70 150
0 5 10 15 20 25 30 35 40 45 1 10 100

93755_04 Total Output Current (A) 93755_06 Number of Equal Amplitude Half
Cycle Current Pulses (N)
Fig. 4 - Current Ratings Characteristics
Fig. 6 - Maximum Non-Repetitive Surge Current

1000 400
Instantaneous On-State Current (A)

Maximum non-repetitive surge current

TJ = 25 °C versus pulse train duration. Control of
On-State Current (A)
350 conduction may not be maintained.
Peak Half Sine Wave

Initial TJ = 125 °C
100 TJ = 125 °C No voltage reapplied
Rated VRRM reapplied
300

250
10

200
Per junction Per junction
1 150
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.01 0.1 1
93755_05 Instantaneous On-State Voltage (V) 93755_07 Pulse Train Duration (s)

Fig. 5 - On-State Voltage Drop Characteristics Fig. 7 - Maximum Non-Repetitive Surge Current

10
Steady state value
RthJC = 1.05 K/W
ZthJC - Transient Thermal

(DC operation)
Impedance (K/W)

Per junction
0.1

0.01
0.0001 0.001 0.01 0.1 1

93755_08 Square Wave Pulse Duration (s)

Fig. 8 - Thermal Impedance ZthJC Characteristics

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100
Rectangular gate pulse (1) PGM = 10 W, tp = 5 ms
Instantaneous Gate Voltage (V)

(a) Recommended load line for (2) PGM = 20 W, tp = 25 ms

rated dI/dt: 10 V, 20 Ω, tr ≤ 1 μs (3) PGM = 50 W, tp = 1 ms
(b) Recommended load line for (4) PGM = 100 W, tp = 500 μs
10 rated dI/dt: 10 V, 65 Ω, tr ≤ 1 μs (a)

(b)

TJ = 25 °C
TJ = 125 °C

TJ = 40 °C
1
(1) (2) (3) (4)
VGD

Frequency limited by PG(AV)

IGD
0.1
0.001 0.01 0.1 1 10 100

93755_09 Instantaneous Gate Current (A)

Fig. 9 - Gate Characteristics

ORDERING INFORMATION TABLE

Device code VS- P 4 0 2 K W

1 2 3 4 5 6 7

1 - Vishay Semiconductors product

2 - Module type
3 - Current rating
1 = 25 A DC (P100 series)
4 = 40 A DC (P400 series)
4 - Circuit configuration
0 = single phase, hybrid bridge common cathode
2 = single phase, hybrid bridge doubler connection
3 = single phase, all SCR bridge
5 - Voltage code
1 = 400 V
2 = 600 V
3 = 800 V
4 = 1000 V
5 = 1200 V
6 - K = optional voltage suppression
7 - W = optional freewheeling diode

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CIRCUIT CONFIGURATION
CIRCUIT
CIRCUIT DESCRIPTION CONFIGURATION SCHEMATIC DIAGRAM TERMINAL POSITIONS
CODE
G1

AC1
Single phase, hybrid bridge AC1 G1 -
0 AC2
common cathode
AC2 G2 +
G2
(-) (+)

G1 G2

AC2
Single phase, hybrid bridge AC1 G1 -
2 AC1
doubler connection
AC2 G2 +

(-) (+)

G3 G1

AC1
AC2 G2 -
Single phase, all SCR bridge 3 AC2
G1 G4
AC1 G3 +
G4 G2
(-) (+)

CODING (1)

WITH BOTH
CIRCUIT WITH
BASIC WITH VOLTAGE VOLTAGE SUPPRESSION
CIRCUIT DESCRIPTION CONFIGURATION FREEWHEELING
SERIES SUPPRESSION AND FREEWHEELING
CODE DIODE
DIODE
Single phase, hybrid bridge
0 P40. P40.K P40.W P40.KW
common cathode
Single phase, hybrid bridge
2 P42. P42.K - -
doubler connection
Single phase, all SCR bridge 3 P43. P43.K - -
Note
(1) To complete code refer to Voltage Ratings table, i.e.: for 600 V P40.W complete code is P402W

LINKS TO RELATED DOCUMENTS

Dimensions www.vishay.com/doc?95335

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 Outline Dimensions
Vishay Semiconductors

D-19 PACE-PAK

DIMENSIONS in millimeters (inches)

0.9 x 45°
(0.035 x 45°)
12.7 (0.50) 12.7 (0.50) Ø 1.65 (0.06)

4.6 (0.18)

25 (0.98) MAX.
15.5 (0.61)
MAX.
2.5 (0.10)
MAX.
63.5 (2.50)

Fast-on 6.35 x 0.8 (0.25 x 0.03)

45 (1.77)

23.2 (0.91) 5.2 (0.20) 32.5 (1.28) MAX.

33.8 (1.33)

48.7 (1.91)

Document Number: 95335 For technical questions, contact: indmodules@vishay.com www.vishay.com

Revision: 24-Jul-08 1
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