PHYSICAL DESIGN

TABLE OF CONTENTS
S.NO TITLE
1 APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC) FLOW
2 PHYSICAL DESIGN (PD) FLOW
3 TOOLS USED
4 INPUTS AND OUTPUTS OF PD FLOW AND EXPLANATION
5 CREATING PROJECT FOLDER
6 INVOKING OF SHELL
7 IMPORT DESIGN
8 FLOORPLAN
9 POWERPLAN
10 PLACEMENT
11 CLOCK TREE SYNTHESIS (CTS)
12 ROUTING
13 SPEF FILE GENERATION
14 STATIC TIMING ANALYSIS (STA)
15 PHYSICAL VERIFICATION (PV)

1) What is ASIC flow?

2) What is PD flow?
3) What are the tools used for?
a. Synthesis
b. Physical Design
c. Timing Closure
d. Physical Verification
e. Power
4) INPUTS and OUTPUTS of PD flow
a. What are the different Inputs files we use in PD flow?
b. What are the different output files?
c. Explanation of PD Flow with stage wise input and outputs?
d. Showing the path of the Input Files we use in our design?
e. Explanation of Input files and compared it with the file?
f. Explanation of Output files and compared it with the file?
5) CREATING PROJECT FOLDER
a. Inputs Folder and copying required input files
b. Outputs Folder
i. Reports it is used to store all the reports generated stage wise
ii. Logs to store the log file generated
iii. Work to store the project libraries
c. Scripts Folder
6) INVOKING OF SHELL
7) IMPORT DESIGN
a. Creating Project library and what are its requirements?
b. Setting up required libraries (i.e. target and link libraries)
c. Importing your design? By reading which file?
d. Importing your timing constraints? By reading which file?
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e. Reading your parasitic values (R &C)? By reading which file?
f. To know the count of Macros, Standard cells and Ports?
g. Showing the Hierarchy Browser
h. Sanity Checks
i. To check whether the netlist/design is proper or not.
ii. To check whether the libraries are correct or not
iii. Zero-Interconnect Delay Model
i. Save Block and Library
PURPOSE ICC1 COMMAND/VARIABLE ICC2 COMMAND/VARIABLE
To set LINK LIBRARIES link_library link_library
To set TARGET target_library -
LIBRARIES
To create PROJECT create_mw_lib create_lib
LIBRARY
IMPORT DESIGN import_designs read_verilog
To read PARASATIC set_tlu_plus_files read_parasitic_tech
INFORMATION
To read TIMING read_sdc read_sdc
CONSTRAINTS
To get the count of a) sizeof_collection [get_ports *] a) sizeof_collection [get_ports *]
a) Ports b) sizeof_collection [all_macro_cells] b) sizeof_collection [get_flat_cells -
b) Macros c) sizeof_collection [get_flat_cells -filter filter “is_hard_macro”]
c) Standard cells “is_hard_macro==false”] c) sizeof_collection [get_flat_cells -
filter “is_hard_macro==false”]
SANITY CHECKS a) check_design a) check_design -checks netlist
a) to check the design b) check_timing b) check_timing
b) to check timing c) check_library c)
c) to check libraries d) set_zero_interconnect_delay_mode true d) report_timing
d) Zero Interconnect report_timing
Delay set_zero_interconnect_delay_mode false
To save the design a) save_mw_lib a) save_lib
a) Library b) save_mw_cel -as design_imported b) save_block -as block_imported
b) Block/CEL

8) FLOORPLAN
a. MANUAL
i. Procedure to open the block through command and tool wise
ii. Check the routing direction of the metal layers? If it is not defined, how to
define it? What happens if the metal layers routing directions are not
mentioned?
iii. Define
1. Utilization
a. Standard cell utilization
b. Macro utilization
2. I/O Clearance
3. Core area
4. Die area
iv. How core utilization and core area are related
v. Creating Core Area and Die Area. And its requirements?
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vi. What is double back? Advantages and disadvantages?
vii. Placement of Ports
1. Setting the constraints for the ports
2. Placing the ports
viii. Where the ports will be placed?
ix. Difference between PADS, PORTS, PINS and TERMINAL?
x. Creating Voltage Area (For a Multi-Voltage Design)
xi. Macro Placement
1. Enabling Different colours for different families
2. Enabling Fly Lines
3. Moving macro’s to inside of core area
4. Explanation of offset
5. Align and Distribute tool
xii. Fixing of Macro’s and Ports
xiii. Different Physical Cells and explain
1. END-CAP Cells
2. TAP-CELLS
3. DECAP CELLS
4. TIE CELLS
What are the physical cells we insert in the floorplan stage?
xiv. Different Special Cells and explain
1. SPARE CELLS
2. FILLER CELLS
xv. Inserting I/O Buffers
xvi. Placing Blockages, Bounds and applying Keepout margin to the MACRO’s
xvii. Sanity Checks
1. Ports are fixed or not.
2. Macro’s are fixed or not.
3. Notches
b. AUTOMATIC
i. What is the command to place the macros inside core area by the tool?
c. Save Design
d. Create DEF File
PURPOSE ICC1 ICC2
To OPEN BLOCK open_mw_lib lib_name open_lib lib_name
open_mw_cel cel_name open_block block_name
To check ROUTING get_attribute [get_layers M*] get_attribute [get_layers M*]
DIRECTION preferred_direction -quiet routing_direction
To SET the - set_attribute [get_layers {M1 M3 M5
DIRECTION of M7 M9}] routing_direction horizontal
ROUTING LAYERS
To create CORE area a) create_floorplan a) & b) initialize_floorplan
and DIE area b) initialize_rectilinear_block
a) Rectangular shapes
b) Rectilinear shapes
PLACING PORTS a) set_fp_pin_constraints a) set_individual_pin_constraints
a) Setting constraints b) place_fp_pins b) place_pins
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b) Placing ports
To create VOLTAGE create_voltage_area create_voltage_area
AREA
To SEPARATE set_hierarchy_color -cycle_color set_colors -cycle_color
MACRO’s based on
family
To Fix a) set_attribute [all_macro_cells] a) set_attribute [get_flat_cells -filter
a) MACROS is_fixed true "is_hard_macro"] physical_status fixed
b) PORTS b) set_attribute [get_ports *] is_fixed b) set_attribute [get_ports *]
true physical_status fixed
To Insert a) add_end_cap a) create_boundary_cells
a) END-CAP cells b) add_tap_cell_array
b) WELL-TAP
cells
MACRO placement create_fp_placement create_placement -floorplan
done by tool
To apply KEEPOUT set_keepout_margin create_keepout_margin
marjin
To save the design a) save_mw_lib a) save_lib
a) Library b) save_mw_cel -as floorplan_done b) save_block -as floorplan_done
b) Block/CEL
Sanity Checks a) get_attribute [get_ports *] is_fixed a) get_attribute [get_ports *]
a) Ports are fixed or not b) get_attribute [all_macro_cells] is_fixed physical_status
b) Macro’s are fixed or b) get_attribute [get_flat_cells -filter
not "is_hard_macro"] physical_status

9) POWERPLAN
a. Opening of the block through command and tool
b. Opening the design through reading the DEF file
c. What are the different structures we form in power plan and in which layers it is
formed and why it is formed in that layer only? And where it is formed?
d. Why stripes are created in MESH type structure?
e. Creating of rings
f. Creating of Stripes
g. Creating of Rails
h. Which Physical Cells will be inserted in this stage? How to see in the design?
i. Sanity Checks
i. Check whether stripes are formed all over the design
ii. Rings, Stripes and Rails are connected properly or not
iii. If any routing is done over macros? Check whether that routing is allowed or
not? If it is not allowed how to remove the routed metal layers above the
macro’s? What will be the issues you’ll face if it is not removed?
iv. Utilization.
j. Save Design
k. Create Def
10) PLACEMENT
a. Opening of the block through command and tool
b. Opening the design through reading the DEF file
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c. Can we proceed to placement without having timing constraints? If no, what is the
problems you’ll face if you don’t have timing constraints?
d. Types of placement
i. Coarse Placement
ii. Legalize Placement
iii. Detail Placement
e. Types of Blockages
i. Soft Blockage
ii. Partial Blockage
iii. Hard Blockage
f. Explain keepout marjin and cell padding?
g. Difference between keepout marjin and blockage?
h. Explanation of various Timing path
i. In to Reg
ii. Reg to Reg
iii. Reg to Out
iv. In to Out
i. Explanation of Setup time, Setup Slack and Hold time, Hold Slack?
j. Define
i. Uncertainity
ii. Skew
iii. Jitter
iv. Marjin
k. How to calculate Cell Delay and Net delay
l. Define derate? How does it impact on setup slack and hold slack?
m. Explanation of Timing Exceptions?
i. False Path
ii. Multi-cycle path
iii. Half Cycle path
n. Write the setup and hold slack formula with derate and uncertainity
i. Multi cycle path
ii. Half Cycle path
o. Sanity Checks
i. Congestion
1. Global Routing Congestion
2. Cell Density
3. Pin Density
ii. Logical DRC
1. Maximum transition
2. Maximum Capacitance
3. Maximum Fanout
iii. Timing Checks
1. Setup
p. Fixes
i. Swapping of cells (HVT to LVT/LVT to HVT)
ii. Upsizing/ Downsizing of cells
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iii. Inserting Buffer
iv. Cloning
v. Path Group
q.