Chapter 3

Chapter 3
Expedition PCB Design Process
Expedition PCB gives you exceptional placement manipulation, dynamic Online DRC,
extensive Batch DRC, Rules by Area, dynamic area fills, and powerful routing by high-speed
rules. The Automatic Routing commands provide you with access to the most powerful shape-
based automatic routing tools available. These commands allow you to automatically
manipulate individual traces or groups of traces, or to automatically route the entire design
based on a user-defined routing scheme. The ability to define routing schemes allows you to
make adjustments in how the automatic router tackles your toughest designs.
The Placement manipulation routines allow parts to be moved, rotated and pushed using
automatic part shove and shove-back along with automatic re-route. Parts can be moved
individually or as groups. If you would like to retain the routing within a group of parts, the
move circuit option will automatically make adjustments to the design with minimal effect to
the connectivity within the circuit.
If you have groups of like circuitry or reusable blocks in your design, copy circuit will
automatically scan your design for equivalent parts and connectivity and allow you to
automatically build new circuits based on an existing master circuit.
Expedition PCB has a built-in dynamic Online DRC engine. This keeps track of any existing
hazards created within your design. Hazards such as Open nets, pad entry, layer restriction,
trace length and delay are shown based on the current state of the design. As you make changes
to your design, these and other online hazards are added and removed from the Review Hazards
dialog.
By default, Expedition PCB does not allow clearance violations to be created. However if
clearances or rules are changed while the design is in progress, these changes could create
hazards for the existing objects placed in your design. Batch DRC allows for the checking of
Proximity, Connectivity and manufacturing rule hazards.
Batch DRC can have sets of verification settings defined as a scheme that can be used to check
for hazards during the design process. Schemes allow you to define which verification options
you would like to run grouped as a scheme name. So you can define specific verification
routines to be run after placement, routing, planes and a final routine that can be selected by a
single name. Any hazards, found by Batch DRC, are listed in the Review hazards dialog in the
Batch pulldown.
Expedition PCB has the ability to define areas within your design that have different clearance
rules. These rule areas give you the ability to define areas within your design where the
clearance must be smaller in order to complete routing to BGAs, large QFPs, or other more
difficult parts. Dynamic Area fills are areas of plane metal that dynamically change when
Expedition PCB User’s Guide, EE2007.1 75

Verifying Parameters
objects are placed within or when traces are routed through the area. This gives visualization of
the impact of changes made within plane areas.
Expedition PCB has extensive high-speed rules that can be defined to aid in routing correctly by
construction. These rules, like pin order, maximum length, minimum length, delay formulas,
differential pairs, routing trace groups to tolerance, parallelism, and cross-talk, aid in the
construction of your design.
The ability to split a PCB design into multiple partitions and have different designers working
on those simultaneously is available in Expedition PCB. After the work on the partitions is
complete, the partitions may be joined back into the original design.
Verifying Parameters
Prior to editing your design file, you must verify the parameters that determine how you want
Expedition PCB to work. Some general utilities are available with Expedition PCB to make
working in graphics easier:
If you want to:

Learn about Setup Parameters Information on page 76
Learn about Editor Control Information on page 89
Learn about Net Class and Clearances Information on page 101
Learn about Net Properties Information on page 104
Learn about Plane Shapes Information on page 109
Learn about Actual Plane Shapes Information on page 110
Learn about Plane Obstructs Information on page 111
Learn about Rule Areas Information on page 303
Learn about Fixing Parts Information on page 125
Setup Parameters
Setup Parameters defines the layers, planes, vias, clearances, layer stackup and graphic levels
that are used in the design. It also specifies whether or not options such as buried parts are
utilized in the design process. Due to the significance of the information in Setup Parameters, it
should be defined at the beginning of the design process.
General Tab in Setup Parameters

Defines the number of physical layers, user-defined layers, padstack technology, display units
and test point settings.
76 Expedition PCB User’s Guide, EE2007.1

Setup Parameters
To set general parameters

1. Define the number of physical layers; the maximum number of physical route layers is
120. The number for the design displays in this entry, and is editable. If you change the
number, you must select the Remap Layers button.
2. Set the user-defined layers; all the user-defined layers found in the design and Cell
Editor display in this field. The maximum number of user-layers is 250. You can add,
delete, undo deletions and rename user-defined layers.
Caution
Renaming user-defined layers in Setup Parameters does not automatically rename the
layers used in cells or designs. Some layer names are reserved and cannot be used.
3. Define the padstack technology name to be used in the design process. Use the drop-
down to view all the defined padstack technology names. New padstack technology files
are created in the File > New Technology dialog within the Padstack Editor.
4. Select the Design Units. The options are: Inches, Millimeters, Microns or Thousands.
5. Select the Velocity of Propagation units. The options are: Inches/ns,Meters/s or %C.
6. Select a Test Point Cell Name from the drop-down list. This list contains all the cell
names for the test points prefixed by Local: for cell names in the local central library and
Central: for cell names in the Central Libraries database. (None) is the default.
7. Select the placement grid for test points. This is a user-defined number displayed in (th)
units.
8. Select the test side for test points. Options are: Top, Bottom or Both.
9. Define the prefix to be used by the reference designator.
10. Check to use closed polygon assembly outlines as test point obstructs.
Remap Layers
This dialog allows you to remap current net class layer assignments to new layers. The
maximum number of physical route layers is 120. This command should be used when the net
class information is setup with a number of layers that differ from the current number of layers.
This situation arises when:
1. Net classes and the number of layers used during the setup differ from the actual number
of layers used to design the board using PCB.
2. Net classes and the number of layers used during the initial setup must be changed.

Setup Parameters
3. Within PCB the number of layers in Setup Parameters changes. This happens when a
seed job with net class data is assigned a number of layers and more or less layers are
required for the actual design.
Note
You cannot remap the top and bottom layers.
The Current Layer column displays the number of layers assigned in Setup Parameters and for
each current layer (apart from the top and bottom) you can use the drop-down list to select the
layer to which the Net Class Layer Assignments are to be mapped.
Caution
A layer can appear in this column only once, therefore, when a new layer is selected,
make sure that any existing entries for that layer are also remapped.
Via Definitions Tab in Setup Parameters

The vias that are defined in Setup Parameters are the defaults for use by Interactive Routing or
Autorouting. When the router needs a via, it uses a via defined in Setup Parameters based on the
span that is needed. However, if a net class is defined for the net being processed, the vias are
based off the net class definition which, by default, is the same as is defined in Setup
Parameters.
If the design uses through vias, then only one via that spans all layers needs to be defined. If the
design uses multiple via spans, Blind or Buried, each span must also be defined with a default
via padstack.
Although through vias and blind/buried vias have a different span when placed in a design, a
through via and blind/buried via can use the same via padstack because the span is a property of
each via. For each via span defined, a default via padstack must also be assigned. A net class
assigned to specific nets, in the Via Assignment section of the Net Classes and Clearances, can
override this via padstack. The vias that are defined in Setup Parameters are the defaults for use
by Interactive Routing or Autorouting. When the router needs a via, it uses a via defined in
Setup Parameters based on the span that is needed.
If a net class is defined for the net being processed, the vias are based off the net class definition
that, by default, is the same as is defined in Setup Parameters. Certain padstack / via range
combinations can be created that cannot be manufactured. The Allowed Via Padstacks dialog
accessed by clicking in the Padstacks field (in the diagram above marked by a red rectangle)
contains a list of padstacks with a check box beside each one that lets you define the padstacks
that will be allowed for the selected layer range.

Setup Parameters
Figure 3-1. Allowed Via Padstacks
Only checked padstacks are allowed. Check the appropriate padstacks and click OK to display
only these selected padstacks in the dropdown list in the Padstack dropdown. The Allowed Via
Padstacks dialog affects the contents of the net class via list, found in the Via Assignments
section of the Net Classes and Clearances dialog, and the contents of the via padstacks, found in
the right-mouse click popup menu during Plow.
To create and define via definitions

1. Select the New icon if you want to add a new via span definition. A new column appears
with the "Undefined Range" heading. If one of the layer ranges is highlighted, the new
column appears to the right; if no layer ranges are selected, the new column appears at
the end of the layer ranges.
2. Define the layer range that represents the span of a via. Via spans are created by clicking
on the green column between the layers where you want to place a via span. If you press
and hold the right mouse button and move over each row in the stack, its selection state
toggles. A via span may only be defined once for a job. If a duplicate span is defined, the
Layer Range field displays "Duplicate Range".
For example, if the span 1-2 already has a via assigned to it, you cannot assign a
different via to the same layer span in another column. If multiple via sizes are to be
defined for a single span, these must be defined by net class. The Padstack entry
displays (Not Defined), the Capacitance and Delay Entry fields display 0, the Grid entry
displays (Default) and the via span accepts the defined layer type for those layers.
3. Select the Padstack by clicking (Not Defined). A drop-down displays that contains all
the via padstacks that are defined in either of the libraries. The via name appears as
L:<via name> or C:<via name> to distinguish between Central and Local libraries. The
Allowed option displays the Allowed Padstack dialog where you can define the
padstacks that are allowed for the selected layer range.
4. Enter a capacitance value for the selected via; by default, the capacitance values are set
to 0pF. If Signal Vision cannot determine the correct via span for the transmission line

Setup Parameters
symbols that transition between layers, the via capacitance for that layer transition,
defaults to the through-hole span capacitance value.
5. Enter an Inductance value for the selected via; by default, the inductance values are set
to 0pF.
6. Enter a delay; by default, the capacitance values are set to 0ns. PCB routes to a value
less then the maximum specified. If a delay is not entered into this files, the delay
entered in Net Properties is used.
7. Define the grid setting by either entering a new value in this field or selecting form the
drop-down list. The Grid allows you to change the via grid for each span overriding the
Editor Control default via grid setting. If [Default] is selected, the via grid value in the
Editor Control Grids tab is used. If [None] is selected for a via span, no grid is used
when this span is placed in the design.
8. Check the Skip via box for each via layer span if you want to only allow trace
connections to the top and bottom of the via span. If checked, all pads on internal layers
will be removed and will not exist in any of the output files.
9. You can define the layer type between routing layers as either Buildup (Blue) or
Laminate (Red). This layer type is used to aid in defining the via spans correctly for your
design. In Buildup areas only standard technology vias can be used. Photo -vias or
internal vias (cutouts in dielectric switches) are allowed.
10. Select the Sort Via Spans icon, if you have added new via spans that are out of sequence.
11. Select the Use mount and opposite side pads for start and end layers of blind and buried
vias checkbox.
Skip Vias
A skip via is a via (hole) with pads only on the top/start and bottom/stop layers of its rule, span
and/or layer. This method minimizes the amount of metal to produce a board and increases the
routable area through adherence to hole clearances rather than pad clearances on the
unconnected inner layers. All layers between these top and bottom layers have the pads
removed. For example; for a rule span of 1-3 layers, 1 and 3 have pads, layer 2 does not.
Note
You can only select the Skip Via check box if more than two layers are in the span. You
cannot mix skip vias and non-skip vias on a specific via layer range, for example, if you
have a via range of 1-4, the vias are either all normal vias or all skip vias based on the
settings on the current settings in Setup Parameters.
If the rules have been violated, design rule checking is available and highlights any errors.

Setup Parameters
Routing
If you had previously routed a net with a via that is marked as a skip via and then disable the
skip via (uncheck the option in Setup Parameters) all existing vias of that range lose the skip via
setting and are no longer classed as skip vias.
It is quite possible to change your skip via settings after some or all of the design has been
routed. After the changes are done, the design is reloaded. The result of this reload could be
numerous skip via violations as the reload does not automatically remove any illegal
connections. In this case, a warning displays stating:
Skip Via design rule changes have resulted in numerous skip via
violations. Please run Batch DRC to highlight these violations.
Plow
Plow will only allow traces to exit or enter a skip via on the top or bottom layer of the via's span.
Push
When traces are pushed, illegal skip via connections will be prevented. The illegal connections
are prevented during Push Trace and Push Part commands.
Re-Route
When traces are re-routed with the Re-Route command or during Push & Shove the skip via
rules are respected.
When the via/range being shoved is a skip via, push and shove re-uses the skip via's hole
and does not re-connect to an inner layer of the skip via's span.
Via optimization/minimization/merge routines do not merge a skip via with a samenet
via having a different range.
Drag - Move Function

When a skip via is moved by dragging the via, the hole range is retained. If the range cannot be
maintained, Move fails and a warning message is displayed.
Batch DRC
If skip vias are present in the design, Batch DRC always checks for any illegal skip via
connections:
Trace connected on an internal range layer

Connection to a plane on an internal range layer

Setup Parameters
Hazards
Illegal Skip Via Connections are reported as Proximity Hazards.
Display Control
The Internal Skip Via Pads option on the Pads Section in the Layer Tab of the Display Control
Dialog allows to easily distinguish skip via pads from other via pads. Visibility is always on but
you can change the color and fill pattern of the skip vias.
Plane Engine
The plane engine follows the same connection rules as the router:
1. No connections are allowed to a skip via unless the connection occurs on the start or end
layer of the via range.
2. If a skip via on a plane net passes through that plane net, the plane net uses the
appropriate clearances for that plane net to clear out the plane to ensure that no
connection exists on the plane on that layer. The clearance used in this case is the pad to
plane clearance that is normally used on this layer.
Until the pads are removed from the layer with the Padstack Processor, the clearance on
the layer is based on the pad size.
Once the pads are removed from the layer, the clearance is calculated based on the hole
size.
3. Conversely, if the skip via range ends or begins on the plane net matching the net of the
skip via, the proper thermal connection must be made.
With the Unified Plane Generation enabled, the positive plane clearances automatically are
regenerated when the pads are removed with the Padstack Processor. When negative planes are
used, the planes are processed after removing the skip via pads to allow the correct clearance
around the skip holes in the Gerber files.
Padstack Processor
In order to prepare a design for artwork generation, the Padstack Processor allows for easy
removal of internal skip via pads. On the Pads tab, the Skip Vias Only checkbox is only enabled
when the Action is set to Delete and when checked only the skip vias are processed from the
chosen selection parameter:
If the Apply to: option is set to All Padstacks, all the Skip Vias in the design are
processed.
f the Apply to: option is set to Selected Padstacks, only the skip vias in the selected set
of padstacks are processed.
f the Skip Vias Only option is unchecked, then no skip vias will be processed.

Setup Parameters
By removing the pads in the Padstack Processor, no changes are necessary when generating the
various PCB fabrication outputs.
Via Clearances Tab

The Via Clearances tab allows you to define via clearances used in the design process. The
default this clearance is set to [Net Class] which means; use the electrical rules defined in the
Net Classes and Clearances dialog for the Trace to Via clearance. If one of these options is not
checked, then the Net Class rules are applied for all via clearances. If stacked vias are desired,
you must use the Same Net Clearances option.
When accessed from Library Manager, this tab allows you to define via clearances that can be
used when adding vias within the Cell Editor.
The Trace to Via clearance should be defined as the smallest clearance between all traces and
this specific via span. This clearance can be over-ridden by larger clearances defined as
electrical rules in the Net Classes and Clearances dialog. If the trace or via have no other
electrical rules that are larger than this clearance, this Setup Parameters clearance is used. Via to
via clearances can also be defined in this matrix.
By default, this clearance is set to [Net Class] which means use the electrical rules defined in the
Net Classes and Clearances dialog for the via to via clearance. The via to via clearance defines
the smallest clearance between spans that is allowed and can be over-ridden by larger electrical
rules defined in the Net Classes and Clearances dialog. If the via's nets have no other electrical
rules, this Setup Parameters clearance is used.
Via Clearance Definitions

Selecting this check box implies that the general trace-via and via-via rules may be set in such a
way that they override the Net Classes and Clearances trace-via and via-via clearances. When
this checkbox is selected, the via names are put in the same row to make them more visible. The
default for each field is {Net Class}.
Figure 3-2. Net Class General Clearances

Setup Parameters
The Plane to Via clearance should be defined as the smallest clearance between all traces and
this specific via span. This clearance can be overridden by larger clearances defined in the
Clearances tab of the Net Class dialog. If the trace or via have no other electrical rules larger
than this clearance, then the Setup Parameters clearance is used.
The Via to Via clearance defines the smallest clearance between spans that is allowed and can
be overridden by larger clearances defined in the Net Class dialog. If the vias’ nets have no
other electrical rules, then the Setup Parameters clearance is used. Set the Net Class via to via
clearance value to be equal to the minimum clearance you want for the microvias. Then, for
these general clearances in the via span dialog, specify {Net Class} for these microvias, and
enter a value larger than the Net Class clearance for all the other via-via clearances.
Used if > Net Class - In the case of different net clearances for vias, both trace to trace and via to
via, the value entered into the matrix is only applied if it is greater than the Net Classes and
Clearances rule.
We recommend that you set the Net Class via to via clearance value to be equal to the minimum
clearance you want for the microvias. Then, for these general clearances in the via span dialog,
specify {Net Class} for these microvias, and enter a value larger than the Net Class clearance
for all the other via-via clearances.
(Not Applicable) - If the vias do not share layers, this field is not selectable and the clearance
rule does not apply.
Use the Same Net Via Span to Via Span Clearances

This matrix refers to via spans that are connected together by a single trace path on the same net.
The default for each field is {Net Class}. The values entered in the matrix are used only if they
are less than (<) the values in the Net Classes and Clearances dialog.
Figure 3-3. Same Net Clearances in Setup Parameters
Online DRC supports and enforces the Same Net Via Clearance and Coincident Vias, if the
variable is set. If Coincident Vias are not indicated, then online DRC do not allow Coincident
Vias.
P (Pitch (padstack origin to padstack origin)) = The router and DRC uses the value from
the via to via clearance found in default Net Class Clearances.

Setup Parameters
PE (Pad Edge to Pad Edge (Default)) = Pad edge to pad edge.

HE (Hole Edge to Hole Edge (Default)) = This is used for clearances of vias with the
same layer range (Row; Via-Via 1-2 and Column; Layer 1-2). All clearance options are
legal except Coincident or any combination that includes Coincident in this match of
layer ranges.
C (Coincident (Exact center over center stack)) = If this is selected, the option to enter a
value is disallowed through a grayed-out Distance field. Coincident or any combination
that includes Coincident is not allowed if the via layer ranges share two or more of the
same layers. For example if there is a layer range 1 - 2 and another 1 - 3, then Types; C,
PC, PEC nor HEC are not valid and do not display in the pulldown.
PC (Padstack Origin and Coincident), PEC (Pad Edge + Coincident), HEC (Hole edge +
Coincident) - are combinations of via to via clearances and coincident.
If you check General or Same Net, the dialog expands, allowing you to specify the clearances.
By default this clearance is set to [Net Class] which means use the electrical rules defined in the
Net Class dialog for the Trace to Via and Via to Via clearances. If one of these options is not
checked, then the Net Class rules are applied for all via clearances. You must use the Same Net
Clearances option if stacked vias are desired.
Multiple Via Objects

The creation of multiple via objects are dependent on the Same Net, Via to Via clearance for
their layer range. This value is used to locate single vias in relationship to each other within the
multiple via object pattern.
For staggering multiple via objects through different layer ranges, the Same Net values are used
to stagger multiple via objects to other multiple via objects or single vias on different layer
ranges. Via patterns supporting buildup layers and microvias use the efficient pattern to span
several layer sets.
To define vias so they can be stacked

1. Define your vias in Setup Parameters.
2. Use the same net selection in the bottom of the same page.
3. Select via center to via center and set all the layers that have a layer in the table in
common to clearance of 0. When you route you will now get stacked vias.
(Net Class) - Choosing this option means that there are no Same Net via-via clearance rules
between those via spans and the General clearances are applied.
(Not Applicable) - If the vias do not share layers, this field is not selectable and the clearance
rule does not apply. (Not Applicable) is also used when the matrix references the same via span.

Setup Parameters
Layer Stackup
This dialog defines the conductive and dielectric materials that make up the design's layer
structure. The Layer Stackup is only used by signal integrity tools. The Conductive Layer
Number displays the number of signal/plane layer numbers corresponding to the dielectric layer
stack in the design.
Note
This tab is not available if Setup Parameters is accessed through Library Manager.
Layer Type The type of each material in the stack. The Dielectric Material is used for
signal or plane layers.
The Metal material is used for signal flooded layers.
Thickness The thickness of each material layer in the stack in the units of the design.
Resistivity The resistivity (in ohm-meters) of each material layer in the stack. The trace
resistance is calculated using the following formula and it retrieves the
resistivity and the thickness of the trace from the field solver:
Resistance=resistivity x Length of trace / cross section Area of trace.
Dielectric Constant The dielectric constant (er) of each dielectric material layer in the stack. This
value can only be defined for a dielectric and solder mask material type. If
you do not want a dielectric layer to have any effect, set its dielectric
constant to 1 (dielectric between conductive layers must have a dielectric
constant greater than 1).
Description A user-defined description for each material layer
Keep Layer When checked, the signal and plane layer definitions in the Planes tab are
Stackup in Sync maintained. If any of the definitions have changed and this option is
with Layer checked, a warning message appears informing you that this action will
Definitions in change one or more of the material types defined in the layer stackup and
Planes tab asks if you want to continue.
Restriction: The previous option is not available if the Layer Stackup dialog
is accessed from within Signal Vision.
Options Displays a dialog allowing you to calculate or define a trace’s characteristic
impedance (Z0) and velocity of propagation (Vp)
OK Updates the other databases so that signal integrity checks can be performed
on the design using the new data and then exits the dialog.
Apply Updates the other databases so that signal integrity checks can be performed
on the design using the new data and leaves the dialog open.
Cancel Rejects the changes and exits the dialog. Any database changes enacted by
the Apply button are undone. If OK or Apply were selected in the Layer
Stackup Options dialog, the changes are also undone.

Setup Parameters
Buried Resistors and Rise Time

This dialog allows you to define buried resistors, and also to define new technology rise times.
Buried Resistors
When the Allow buried resistors checkbox is selected, SMD parts built with a resistor shape can
be placed on, or pushed to, internal board layers with the Place Part and Push commands. The
pads of the SMD part must overlap the resistor shape area. If the Allow Buried Resistors
checkbox is not selected, SMD parts can only be placed on the top or bottom of the board or be
pushed between the top and bottom.
The graphic displays the number of layers for the design. The word Plane appears next to any
layers that allow plane shapes and do not allow routing.
The Layer Stack Center determines the layer at which parts are mirrored and placed in a
different display class with the Push or Place Part commands.
Example
If the center of the layer stack is between layers 4 and 5 on an 8 layer design, parts placed on
layer 1 through 4 are considered topside parts and on layers 5 through 8 are considered bottom
side parts.
Rise time by Technology

A new technology is added by defining the "tech" field in the Part Editor. If the technology is
not in the default list, that entry is added to the list of available technologies and is assigned the
Default Tech values. These values can be edited by clicking on the appropriate field in the table.
The system is delivered with the set of technologies shown in the System Set of Technologies
table.
Use the Rise Time text field to edit the rise time values for the corresponding device
technology. If there are multiple drivers in a net, the smallest rise time is used for crosstalk
estimations.
Use the Voltage Swing text field to edit the voltage swing for the corresponding device
technology. If there are multiple drivers in a net, the largest voltage swing is used for crosstalk
estimations.
Default Values
The entered values for Rise Time and Voltage Swing are applied to all new technologies in your
design (through the Part Editor "tech" entry). The initial values are set to 0.6 nanosecond for
Rise Time and 5 volts for Voltage Swing. These values are used for crosstalk estimations on all
nets containing at lease one source pin. For example:

Setup Parameters
Nets with I/O's and loads

Nets with only I/O's
Analog nets that have no drivers or loads
Nets that have incomplete or no part information on their pins.
Reserved Layer Names

When opening a cell for edit, you may receive the following error:
Cannot open Cell lib. Unable to create scratch jobprefs.
One cause for this error is that the Central Library contains a reserved layer name. The layer
names must be renamed and any cells containing these layer names can then be changed.
Reserved User Layer Names

(All)
Assembly, Top and Bottom
Drill Drawing (Through)
Redline
Silkscreen Top, Bottom, Mount and Opposite
Soldermask Top, Bottom, Mount and Opposite
Solderpaste Top and Bottom
Documentation
The workarounds use the Documentation reserved layer. The same procedures may be followed
for all the other Reserved layers.
Workaround 1
1. Run the FixCellLayers utility to rename the conflicting user-defined layer and update
the cells in the Central Library
<$SDD_HOME>\wg\win32\bin>FixCellLayers.exe -CentralLibrary=<specify_full
_path_to_CL>.lmc
This renames the user layer and moves all draw data that was on the Documentation
layer to Documentation Temp for all cells in the Central Library.
If the Documentation Temp name is not acceptable for the new user layer name, then
use the following workaround.

Setup Parameters
Workaround 2
1. Open the Central Library, invoke Setup > Setup Parameters and rename the
Documentation user layer.
2. Use Library Services > Export ASCII to export all cells that contain draw data on the
Documentation layer to HKP.
3. Edit the HKP file(s) to replace all instances of USER_LYR Documentation to the new
user layer name. Text and Graphics definition in the HKP file is slightly different (text
has 4 dots preceding USER_LYR and graphics has 3 dots).
4. Remove or update the ..TIMESTAMP entry in the HKP file to ensure that the cell(s)
overwrite correctly when re-imported.
5. Use Library Services > Import ASCII to replace the affected cell(s) in the Central
Library.
6. Verify the LibraryServices.txt log file to ensure the operation completed successfully.
The Verification Status of cells imported from ASCII defaults back to Unverified;
therefore, cells that were previously Verified should be re-Verified as required.
Editor Control
The Setup - Editor Control dialog defines the parameters for interactive routing as well as some
of the parameters used by the Auto Router. This dialog allows you to customize which layers
routing can be on, layer bias, pad entry, grids, tuning, etc.
It also allows you to turn rules on or off when trying to route a complex design. Each of the tabs
of this dialog are discussed below.
Note
Within FabLink XE, Xtreme PCB and ICX Pro HSR, some of the tabs and options in
Editor Control may not be available.
General Setup Rules

The General tab of the Editor Control dialog allows you to define the database and checkpoint
automatic save intervals. You can also define the algorithmic expense or "cost", associated with
placing a via, or whether to go against the layer bias, when using the interactive routing tools.
In this tab, you can define which routing layers are enabled for interactive or automatic routing,
what the preferred layer bias is for each layer, and which layers are paired together when vias
are placed. Be careful about changing this control from its default setting, High. If you select
Medium or Low too early in the routing process, routing channels may quickly become
blocked, making routing very difficult.

Setup Parameters
The radius of any curved traces can be defined. Any radius can be defined and the value is based
on the units defined for the design. New entries are added to the list and are selectable from
either the drop-down or the pop-up menu. If you want to override the selected default curve
radius (Variable) you can choose a new radius from the list.
The value entered for the minimum arc radius of a curved trace affects the Modify Corners
command. If a value for the minimum radius is set in the General tab of Editor Control, the
value entered in Modify corners must be larger. If not, an error dialog appears stating the
allowed smallest minimum radius.
Figure 3-4. Editor Control General Tab
Differential pairs are composed of two nets, carrying a signal and its inverse, generally derived
from the outputs of a single gate. These nets are active at the same time, and have the same
number of inputs and terminators. Differential pairs are defined in this tab so that the signal and
its inverse arrive at the differential inputs with identical characteristics. To achieve this, these
nets are routed with adjacent traces and paired vias. If no adjacent layer pairs are defined, then
differential pairs are routed on the same layer.
Options are available, during interactive routing, to allow trace and via shoving of existing
traces and vias, to add vias using the mouse and to allow pad and via jumping over traces and
vias during interactive routing.

Setup Parameters
Curve trace radius provides the ability to create concentric arc's using curved traces. Values
entered into this field can be selected when using the command from the popup that displays
with a mouse right-click when in the route environment while in Forced or Angle Plow. If
"Variable" is selected, the methodology reverts back to a defined curve using the cursor. Values
are only stored for the current design session. When the design is exited the input values are
discarded.
The Interactive DRC option allows you to turn DRC off while in the layout environment. This
option is not available in Team PCB or Cell Editor and Backward and Forward Annotation
remain enabled. If you use DRC OFF to circumvent system limitations, any resulting hazards
will persist through to generation of manufacturing data. Certain commands are affected by
turning Interactive DRC off:
Teardrop Dialog - The following "Process" options of the "Pad Teardrops" tab of the Teardrop
generator dialog are disabled:
All Pads
Pads Without Teardrops
The following "Process" options of the "Trace Teardrops" tab of the Teardrop generator dialog
are disabled:
All Traces
Traces Without Teardrops
Breakout Traces Dialog - The following options in the "Items to process" options list of the
Breakout Traces dialog are disabled:
All Traces
Pads Without Breakout Traces
Auto Route - All Auto Route functions and entry points to the Auto Router are disabled.
Closing and Saving Commands - Before Closing or Saving a design (and after opening), you
are warned and advised to run Batch DRC if the session or previous sessions had turned off
Interactive DRC and not yet run Batch DRC.
The current state of Interactive DRC is saved and applied to next invocation.
Modify Corners - The following option in the "Action" options list is disabled:
All Corners
Team PCB Reserved Areas - When DRC OFF is active on a TeamPCB split design, it only
applies to actions taken within the split design's reserved area. The remaining areas of the
design (outside of the reserved area) always maintain DRC ON.

Setup Parameters
Xtreme PCB - DRC Off is disabled within Xtreme PCB. If a design is opened in Xtreme PCB
that had not had Batch DRC run, a dialog prompting you to run Batch DRC is presented.
Reusable Blocks - If DRC OFF is enabled in a design containing placed Reusable Blocks, the
current limitations (DRCs) imposed on all un-flattened reuse blocks are maintained (Reuse
Block property is still assigned) as defined below.
Modification to the block's elements, move, edit, etc. is not permitted.

Reference designators are placed with the reusable block and are edited by Forward
Annotate.
Part entries are locked.
Plane shape information is locked. Plane data is created on demand.
Gate and pin swap is not permitted.
Existing routing is not editable.
The rules as set by each un-flattened reusable block's DRC Region are maintained.
When a reusable block is flattened, Interactive DRC is allowed.
Automatic and Interactive Tuning - On the Tuning Tab of Editor Control, automatic and
interactive Tuning are turned off and all command access, including key-ins is disabled.
Gloss - All Gloss functions and entry points are disabled.
Auto Swap/Rotate By Cell Name and Part Number - All Auto Swap/Rotate By Cell Name
and Part Number functions and entry points are disabled.
Copper Balancing - All Copper Balancing functions and entry points are disabled.
Parts Tab
The Parts tab allows you to define whether the Online Design Rules Checker (DRC) provides a
warning when part violations are created, or prevents you from creating these violations.

Setup Parameters
Figure 3-5. Editor Control Parts Tab
The preferred rotation and placement of reference designators, how netlines are to be displayed
while parts are moving, the snap anchor and the alignment method to be used for parts are also
defined on this tab.
The Display local netlines only option limits the display to those netlines directly attached to the
part. This option is to be used when the netlines have been turned off within Display Control.
The default setting for this option, Dynamic netline ordering, orders the netlines while the part
is moving. If the option to Apply filter to Netlines is selected on the Editor Control Filter tab,
these nets do not have their netlines displayed when a part is being moved.
You can set the maximum number of pins to display netlines when moving parts or groups of
parts attached to the cursor by adding a number into the text entry field. If you entered 500, any
part that has greater than 500 pins would not generate dynamic netlines during part movement.
The default is empty; this means that all netlines are shown during part movement

Setup Parameters
Cells Tab
The Cells tab contains general information about selecting parts and defining valid placement
layers and rotation angles. These defined placement layers and rotation angles are used by
Online DRC. The Online DRC options; Off, Warning or Preventative are controlled on the Parts
tab. If the Online DRC option is set to warning, placement layers and rotation angles hazards
are listed as Review Hazards Online Component hazards.
Figure 3-6. Editor Control Cells Tab
Clusters and Rooms Tab

Cluster and room configurations can be defined for your design. These are optional part
attributes used to aid in placing parts that should be clustered together (bypass capacitors or
parts that should be grouped together in a specific location on the board). A cluster has no
physical representation on the board while a room is defined using a shape. A room shape must
be defined as a polygon, circle or rectangle.
Place Part allows you to list parts based on Cluster and Room names. Once Rooms are defined,
parts that are not placed in the defined room will become an Online DRC hazard that can be
reviewed using Review Hazards component hazards.

Setup Parameters
Figure 3-7. Editor Control Clusters and Rooms Tab
Clusters and Rooms can also be defined in the Design Capture schematic using the Cluster and
Room symbol properties. Forward Annotation reads these properties and populates the Editor
Control tab with changes made in the schematic.
Any changes made to the Cluster and Room definitions must be Back Annotated so the data is
not lost during the next Forward Annotation. Back Annotation will be run when save is done.
Routes Tab
The Routes tab contains general information about routing preferences.
Options are available to allow 45 degree angles to be used in routing and to prevent loops. Via
options allow you to put restrictions on whether vias can be placed under components or how
many vias should be used when fanning out pins. Optional net rules restrictions that should be
respected during interactive routing commands and differential pair routing parameters.

Setup Parameters
Figure 3-8. Editor Control Routes Tab
The redlined options are not displayed if CES has been used on the design as these values are
entered on a net basis within the CES interface.
Convergence and separation values can be entered into this dialog if you have not used CES.
The convergence distance is calculated from the pad edge and not the pad origin. The tolerance
value entered into this field is used to ensure that the legs of the convergence point are matched
to the user-defined tolerance. A convergence point is where the traces of a differential pair come
together from the component pins.
The separation distance is measured from the pad origin. If you set the max separation distance
to a very small value, you will see numerous hazards at the pad entry points. A maximum
separation distance keyin (xmsd value) is available. However, if this keyin is used, the entered
value is set for every net on the board.
Differential Pair Convergence, Convergence Tolerance and Separation hazards are listed under
the Online pulldown in Review Hazards.
Gloss Tab
The Gloss tab contains options that allow you to improve glossing performance and applies
only to the interactive routing tools and for the Auto Route Smooth pass for Efforts 2 and 3.

Setup Parameters
You can select to move a trace over the obstacle to remove excessive vertices, remove excessive
meanders, gloss around deleted traces or vias and move vias to reduce trace segments. Dyna-
move continues to jump over pads/vias regardless of the Advanced Glossing Options being
enabled or disabled. Advanced Glossing only affects Gloss and the Push/Shove of traces and if
you dynamove a trace, the segments being dragged will hop across pads/vias.
Figure 3-9. Editor Control Gloss Tab
Pad Entry Tab

The Pad Entry tab allows you to define the preferred route entry for a particular shaped pad(s).
You can also define if vias are allowed under the pad, where they are allowed, and which via
spans are allowed. These design rules can be defined based on the selection of rectangular,
oblong/octagon, round/octagonal, square and custom pad geometries.
Figure 3-10. Editor Control Pad Entry Tab

Setup Parameters
Round / octagonal and custom pads only allow via under pad rules to be defined within Editor
Control. Trace entry for custom pads can be controlled by defining trace obstructs when the
custom pad is being created within the Padstack Editor. Round pads have system-defined pad
entry rules (a trace may enter round pads at 45 degrees increments) and this can not be adjusted.
Expedition PCB uses the pad entry as preferred rules. These rules do not stop the router from
making a connection within a pad. Pad entry hazards can be reviewed and fixed using Review
Hazards. If a Route grid is set in the Grids tab, you can select the Gridless pad entry for all pads
option to allow traces to follow the set grid to the pad and then "jump" off the grid to connect to
the pad regardless of the grid setting.
Grids Tab
The Grids tab contains parameters that define the placement, route, via and drawing grid for the
design. The dropdown list accompanying all of the grid fields can be used to select either a
previously entered setting, or none. New grid values can be entered by selecting the field and
keying in the desired value. Once a grid value is set in any of the fields, all work from then on is
done using that value.
Figure 3-11. Editor Control GridsTab
You can define two placement grids. These allow you to easily align your through parts on a
coarse grid and make the grid for SMD parts less restrictive; however, a route grid is not
required in Expedition PCB and typically, the router works best when not restricted to a route or
via grid.

Setup Parameters
If you want to use the Gridless pad entry for all pads option on the Pad Entry tab to route traces
gridless into pads as well as around pads that are off the route grid, you must select a Route
Grid. Gridless pad entry for all pads allows better pad entry as well as being able to route
between pads when the clearances are precise.
Filter Tab
The Filter tab allows you to include or exclude nets from access by the Auto Route, Item Select,
Area Select, Select All, Net Inquire, Netline Order, Hazard Review and all interactive routing
commands. This allows you to restrict the selection of objects based on the net name and can be
very useful in dense designs where you are working on critical nets.
The Display class type pulldown option is set to Net Class and is inactive and read-only if CES
has not been used in the design. The Constraint Class option only appears if you have used CES
in the design.
Figure 3-12. Editor Control Filter Tab
The Find Net option can be used to search for the net name in the Include or Exclude list.
Selecting the Apply filter to netlines option allows Excluded netlines to become invisible.
Tuning Tab
The Tuning tab allows you to set the rules defining how the tuning algorithms work. (A tuned
net is considered to be any net whose length is constrained by any of the following Net

Setup Parameters
Properties: maximum length/delay, matched length/delay or if a delay formula has been

defined.).
For the minimum spacing distance or factor option, you can also add an entry as a factor of the
trace width by entering the number followed by an x. The default value is 0x. If you enter a
factor, the design units are ignored. For example: If you enter 2x and the trace width is 10, the
spacing would be 20.
Figure 3-13. Editor Control Tuning Tab
Less restrictive tuning rules allow the router to easily add trace length to routes in order to meet
the rules defined in Net Properties. However, if your manufacturing process requires specific
distances or clearances on tuning, these can be defined here.
Jumpers Tab
This tab allows you to set the jumper grid, determine jumper placement angle and configure the
space bar to add jumpers instead of a via (the default action in Plow). A jumper part is defined
in the Parts Database (with a part type of jumper) referencing a jumper cell. This tab is not
selectable if there are no jumper parts defined for the design.

Net Classes and Clearances
Figure 3-14. Editor Control Jumpers Tab

The Setup > Net Classes and Clearances dialog allows you to group and assign properties to
the nets used in your design. These groups are called Net Classes.
Note
If your design/ database has used CES for physical rules, the Net Classes and Clearances
dialog is unavailable.
The following attributes on the first tab within the Net Class dialog can be defined per net class:
Vias to be used by span

Allowed routing layers
Minimum, typical and expansion trace widths per layer
Width defined by impedance based on layer stackup
Differential pair spacing per layer
A net class can contain an unlimited number of nets, but the number of physical rules applied to
the net classes (width, cross-class clearances, via cells and via pad stack) is constrained to 250
design rule classes. Even if you have more than 250 net classes, you can avoid hitting this
limitation by limiting the number of classes that have cross-class clearances and using the

common clearance rules, widths and via padstacks for net classes that do not have cross-class
clearances.
In the Net Class Via drop-down, there are two special vias that can be selected, (Default Via)
and (None). (Default Via) allows you to default to the via defined in Setup Parameters for the
selected Net Class name. (None) allows you to disable a via from being used for specific via
spans for the selected Net Class name. If you change a net class via to (None) in a net class in
the Master scheme, all user-defined schemes change automatically to (None) for that netclass.
If, for example, you change the Master scheme from (None) to "VIA010", the user-defined
schemes net class via changes to "Default Via".
You can define multiple Net Class schemes that allow you to define alternate clearances for
specific areas of your design. The Net Class schemes can then be applied to user-defined areas
on the board called Rule Areas.
During Auto Route sessions, the expansion width is only enabled for finishing passes, but the
maximum width is used for all of the interactive routing methods (Plow, Route...) when
enabled. Because Expansion Width allows for the routing of many sections of differing widths
causing impedance inconsistencies, Expansion Widths are not used when tuning high-speed
nets.
If you have defined a Width/Impedance table in the Layer Stack dialog (in the Setup
Parameters), that data is used instead of calculating a new typical width. The Impedance value
is only used to determine the Typical Width. It is not used by other calculations. If a plane layer
is not defined, the following error message appears: Unable to calculate impedance with current
layer stackup. Default value used. The default value is 50 ohms.
Clearances Tab
On the Clearances tab of the Net Classes dialog, you can define clearance rule sets. These rule
sets can then be applied to define the clearances between the nets defined within two Net
Classes. General Clearance Rules are not specific to objects that have net names. General Rule
Sets are editable and allow you to define the from / to clearance for a variety of PCB elements.
Contour & Mounting Hole to Mounting Hole

The clearance between holes. Mounting hole to mounting hole clearances are used during Batch
DRC verification only as a manufacturing check. The Net Class pad to pad clearance between
mounting hole pads is used during net class verification as an electrical verification.
Contour & Mounting Hole to Non-Plane Conductor

This is used as the clearance between the contour holes/mounting holes and traces/pads/resistor
shapes.

Contour & Mounting Hole to Plane Conductor

This is used as the default clearance for contours to plane conductors. This clearance can be
changed in the Planes Processor dialog for each net and layer. Mounting holes will use the
larger of this clearance and the Other Object Minimum (on the Planes Processor dialog) when
generating plane data for mounting holes. Contours will use the larger of this clearance and the
Other Object Minimum (on the Planes Processor dialog) when generating plane data for
contours.
Placement Outline to Placement Outline

This clearance is used for clearance checking between placement outlines of one cell to
placement outlines of another.
Placement Outline to Placement Obstruct

This is used for clearance checking between placement outlines and placement obstructs.
Placement Outline to Board Edge

This is used for clearance checking between placement outlines and the board outline.
Plane to Resistor
This is used for clearance checking between resistor shapes and traces/planes.
Pad to Resistor
This is used for clearance checking between resistor shapes and all pads.
Testpoint Center to Testpoint Center

This is the minimum clearance that must be maintained between the centers of all test pads
ensuring the test probes have enough room between them.
Clearance Rule Sets are the Plane to Trace, Plane to Pad, Plane to Via, Via to Via, Via to Pad,
and Pad to Pad clearances by layer. These rule sets are independent of nets or net classes.
The Pad to Pad clearance is the one used for checking between part pads, fiducial pads, test
pads, edge connector pads, mounting hole pads and part holes. Mounting hole to mounting hole
clearances are used during Batch DRC verification only as a manufacturing check. The Net
Class pad to pad clearance between mounting hole pads is used during net class verification as
an electrical verification.

Net Properties
On negative planes, clearance distances become the sum of the clearances used by the annular
rings. For example, if a via to component clearance is set to 10th and the via to pad clearance is
set to 10th, the clearances in these instances will be maintained at 20th on negative planes.
Net Class to Net Class rules are groups of net classes which have been defined to have a specific
rule set used for specific layers. These cross-class clearances sets are used based on specific
groupings to general groups. The clearance within a specific grouping is used before the
clearance within a more general grouping.
Toggle Plane Clearance Rules

When you select the toggle plane clearance rules icon, the table adds the following
clearances; plane to trace, plane to pad, plane to via and plane to plane. If you select this icon
and change the clearances for the additional fields, those clearances are used. If you toggle this
option off, even though the values are no longer seen, they are still used.
Toggle Embedded Passives Clearance Rules

When you select the toggle passives clearance rules icon (only available if you have the
correct license), the table adds the following clearances; mask to trace, mask to pad, mask to
via, mask to resistor, resistor to trace, resistor to pad, resistor to via and resistor to resistor. If
you select this icon and change the clearances for the additional fields, those clearances are
used. If you toggle this option off, even though the values are no longer seen, they are still used.
Net Properties
The Setup - Net Properties dialog allows you to define individual net based routing rules; Net
Class assigned to nets, custom topology for specific nets, timing parameters, crosstalk
parameters, maximum number of vias, matched length groups, differential pairs and delay
formulas.
Note
If your design/ database has used CES for physical rules, the Net Properties dialog is
unavailable.
The Find Net field allows you to enter a net name, a partial net name or use an asterisk as a wild
card character to locate and select the entered net name in the Net Name column.
The Net Order tab displays all the nets in the design. Each net may be assigned to a net class,
assigned a netline order and have pin order defined. Any net not assigned to a specific net class
is included in the (Default) Net Class.

Net Properties
Figure 3-15. Net Properties Net Order Tab
The Net Order tab can be used at any time during the design process to order nets. Typically, it
would be used to order nets prior to placing components. If the nets are to be chained, a pin type
(source, driver, load, terminator, test point, connector) should be assigned to each pin to allow
proper ordering. Plane nets can only be defined as MST.
The Timing and Differential Pairs tab allows you to define nets that have a maximum length or
delay, matched net groups based on their length or delay tolerance, and define the differential
pairs in your design. The differential pair tolerance allows you to set up a matched group of
differential pairs that have to be within a matched group tolerance and at the same time maintain
a tolerance between the nets of the individual pairs. Any violations are reported in the Review
Hazards - Differential Pair - Delay or Length Tolerances sections.
Figure 3-16. Net Properties Timing and Differential Pairs
A maximum length assigned to a net can either be specified as a distance, a delay, or as a

percentage over the Manhattan length of a net. If the Maximum length or delay value is set,

Net Properties
Expedition PCB routes the net within the length. If a trace cannot be completed within the
maximum values, it appears as a Length or Delay Hazard in the Review Hazards dialog. While
interactively routing, tuning rings appear for nets that have a maximum length or delay. This
ring defines the length that is left before the maximum is exceeded. Care should be taken when
assigning these values, as it is possible to assign values that will make routing impossible.
Differential pairs are composed of two nets (carrying a signal and its inverse), generally derived
from the outputs of a single gate. These nets are active at the same time and have the same
number of inputs and terminators. Differential pairs are defined in this dialog so that the signal
and its inverse arrive at the differential inputs with identical characteristics. To achieve this,
these nets are routed with adjacent traces and paired vias.
Differential pair tolerances may also be set in this dialog. The differential pair tolerance is a
length or delay tolerance that is applied between the two nets of the differential pair. The
differential pair tolerance allows you to set up a matched group of differential pairs that have to
be within a matched group tolerance and at the same time maintain a tolerance between the nets
of the individual pairs.
For example, a group of differential pairs have to be within 250(th) of each other, but the nets
within each diff pair must match within 25(th). You would enter 25 in the Diff Pair Tol. column.
Any violations are reported in the Review Hazards - Differential Pair - Delay or Length
Tolerances sections.
The Crosstalk tab allows you to assign values for the maximum crosstalk or the maximum
parallelism allowed on individual nets. A net can have Maximum Crosstalk or Parallelism Rules
Factor rules defined, but not both. The values entered in this tab are used to determine the
existence of these hazards within your design. Crosstalk estimation is based on the layer stackup
and the timing parameters displayed in Setup Parameters.

Net Properties
Figure 3-17. Net Properties Crosstalk Tab
The Other tab settings define the maximum stub length, the maximum number of vias, and the
nets supply voltage. The Maximum Stub Length value is used during routing of chained or
custom topology nets. If the stub length has been exceeded by a net, Review Hazards displays
this as an Online Stub Length hazard. Ideally all netline connections for chained and custom
topology nets should be made with independent paths between the device pins at the end of the
netlines. This can often be difficult or impossible. In some instances, a trace must be shared by
two or more netline connections. This shared interconnect is called a stub.
Figure 3-18. Net Properties
The Delay Formulas tab allows you to enter the formulas for pin to pin delays on custom nets.
These formulas can be used to constrain pin to pin delays, match delays between a set of pins,
and define relationships between a set of pins.

Draw
Figure 3-19. Net Properties Format Variables
All custom topology nets in your design are organized into a spreadsheet format allowing you to
enter a delay defined in terms of electrical length.
Figure 3-20. Net Properties Custom Topology
Draw
For more information on the functionality of the Expedition PCB drawing module called Draw,
refer to Appendix A - Draw. The drawing module is for creating and editing lines, arcs,
polylines, polygons, rectangles, circles and text. Graphic objects such as plane shapes, reserved
areas, rule areas and route obstructs must be created and/or modified by you while in Draw
mode.

Draw
Plane Shapes
At the beginning of the design process and/or after placement, define the areas and layers on the
board that will be used for plane signals. Plane shapes can be placed with the Place Plane Shape
command. The plane shape can be defined using a Polygon, Rectangle or Circle.
Plane shapes are used by the Planes Processor command to determine the extents of
positive and negative plane data.
These areas are critical in determining if a net can simply be fanned out into a plane or if it has
to be fully routed. Plane shapes can be placed on any signal layer of the board.
Plane shapes may be placed on signal layers or the plane could encompass the entire layer.
If an entire layer consists of a single plane signal, a plane shape does not have to be defined. The
option of defining the route border to be used for a signal plane signal on a layer can be set
within Setup Parameters.
Each positive plane shape can override the Area Fill Parameters; Hatch Option Width and
Hatch Distance. These attributes are only used for positive planes. If one of these attributes is
defined for the shape, they all must be defined. Also, a route attribute allows you to define
whether traces other than the plane net are allowed to pass within the plane shape.

Draw
Place an Actual Plane Shape

You can place actual plane shape outlines in the design. You can only allow place actual plane
shape outlines on valid routing layers. You can select the layer and the traces and the
corresponding nets display. When placing actual plane shapes, you can use the options in the
Draw Properties dialog.
It is possible to scale an actual plane shape outside of the board outline. In this case, when
Planes Processor is generated, the plane data is generated outside of the route border and plane
data that outlines the shape follows the shape outside of the board outline. Either resize the
actual plane shape or use the Subtract option while in Draw mode.
Actual plane shapes outline and represent the true plane data including obstructs or holes,
islands and tie legs as they would be plotted. These shapes are always enclosed shapes and
adhere to the clearance rules and connection types defined within the parameters of each tab of
the Planes Parameters and Processor dialog.
Dynamic Area Fills

This option on the Display Control Layers Tab enables the display of area fill data inside user-
defined plane shapes placed on trace layers.
The Dynamic Area Fill command is only active when no Planes Processor generated plane data
is present on any layer of the board. You can use the Delete Plane Data command to remove all
previously generated plane data.
Dynamic area fills are only generated for positive layers which have routing enabled in Editor
Control. Dynamic area fills are not generated for negative and positive layers which do not
have routing enabled in Editor Control.
Dynamic Area Fill can be used as a tool to help visualize what positive plane data will look like
once it is generated. It is not physical data and therefore the command must be activated each
time you enter the design. When Dynamic Area Fills is enabled, a status bar appears at the
bottom of the PCB window and any positive plane net that is checked to be processed within the
Planes Processor dialog and that exists on a routing layer enabled in the Editor Control dialog is
filled.
Options for area fill hatching are defined within Draw mode using the Properties dialog.
Note
If Dynamic Area fill is turned on and you modify a plane shape in Draw mode, the
Dynamic Area Fill data will still display using the original shape and will only regenerate
when you have exited Draw mode.

Draw
In order to generate real plane data on the board before Gerber is created, you must run the
Planes Processor.
Plane Obstructs
Plane Obstructs are user-defined areas where plane data is not allowed. A Plane Obstruct may
be any of the standard closed draw objects: Polygon , Rectangle and Circle . Arcs
are allowed in the polygons. Plane Obstructs can be placed on any routing layer of the design.
As an example, planes can be generated inside plane obstructs as long as the plane shape is fully
included within the obstruct. This allows you to use the plane obstruct to isolate planes from
each other. You could have a GND net which is composed of two shapes; the inner shape is
used for GND for a power supply, the outer shape is used for GND for a digital circuit. In order
to isolate the power supply GND from the digital GND (same net), place the plane obstruct so it
totally encloses the inner shape.
Route and Via Obstructs

Trace route and via route obstructs are used to prohibit the routing commands from placing
conductive material in areas that might cause interference problems. Route obstructs are also
used as plane obstructs by the Planes Processor.
When placing a route obstruct, the shapes do not have to be orthogonal. Trace route obstructs
and via route obstructs are respected by the automatic router and interactive routing commands.
If for some reason a trace or via violates a route obstruct, it is flagged by Batch DRC as a
proximity violation.
Route trace obstructs prohibit placing routes within the area, but allow vias. Via route obstructs
prohibit vias, but traces are allowed. “Both” route/via obstructs allow neither traces nor vias
within their outlines.
Traces cannot cross over a line obstruct or be inside an area obstruct. Line obstructs are used
most often to direct the routing escape from pins.
Area obstructs keep traces or vias, or both, from a particular area. When a piece of hardware,
such as a heatsink or a bracket, is touching the surface of the design, a trace/via “Both” obstruct
should be placed on the outside layer. This prevents any traces from being routed in the area on
the outside and prohibits any vias that may be placed by internal traces.
Reserved Areas
Reserved areas are created in the Properties dialog of Draw, as closed polygons with the
Reserved Area attribute. They are used to define the reserved areas that are used to split the
design. These reserved areas will represent the split area for all layers.

Setup
Setup
This section gives you information on how to define the physical attributes of the board. If you
design a large number of boards of one or more standard sizes, it is recommended that the board
outline, mounting holes, etc., be defined in a layout template.
If you want to:

Learn about the Display Control dialog Information on page 112
Learn about placement mode Information on page 113
Learn about the Board Outline Information on page 113
Learn about the Manufacturing Outline Information on page 114
Learn about the Board Origin Information on page 114
Learn about the Mounting and Tooling Holes Information on page 114
Learn about the Route Border Information on page 114
Learn about Contour Placement Information on page 115
Learn about Part Placement Information on page 115
Learn about Placing Etch Text Information on page 118
Learn about using netline manipulation Information on page 118
Display Control
The Display Control dialog defines how design graphics are displayed. Each graphic object, or
set of objects, can be turned on/off and have their color and or graphic pattern changed. The tabs
within this dialog group graphic objects based on route layers, general graphics, part graphics,
color by net and color by hazard. In addition to controlling the display in the design, The
Display Control dialog allows you to define the colors used for each item type.
There are times when it becomes necessary to turn all items of a particular type (Trace and Pad)
either on or off. This allows you to fully inspect those items without the clutter of a fully or
partially routed design.
Options within Display Control allow you to further control the display of items within the
design. You can select to only display elements on the active layer, change the background
color of your design, turn all displayed elements to gray, and only display text which is above a
certain font size and mirror the contents of a view about the vertical axis. When changes occur
within the Display Control dialog you can select to have the graphics update only when the
Apply button is selected.

Display Control
Place Mode
Place Mode allows the selection or manipulation of parts. Package, Mechanical and Drawing
cells can be manipulated while in this mode. While in Place Mode, there are two states that can
be entered, Select and Move.
The Select state is used to select parts without moving them. These parts can be pushed or
rotated without the part entering dynamics. The Move state is used to move a part or groups of
parts. Move operates on individual parts, multiple parts, grouped parts and reusable blocks. You
can activate the Move state by double-clicking on a part or by selecting the Move command
either before or after the part is selected. While in the move state, you can move, rotate and push
parts. The parts will appear dynamically attached to the cursor.
If parts within the design have been assigned to a group, selection and movement of any
of the parts within the group cause the entire group to move together.
If a selected part is nested within a reusable block, movement of this part, or any parts,
within a reusable block cause the entire block to move.
Many commands can be active while in the Select or Move states. The Part Properties dialog
can be active while in either state and displays information about the selected part. Existing
parts can be manipulated to make room for parts that have not yet been placed.
Board Outline
The board outline defines the physical shape and size of the board and cannot be deleted. Only
one board outline can be in a design file; therefore, if a new board outline is placed in the design
file, the old board outline is removed. Use the Edit > Place > Board Outline command to define
the board area. The board outline consists of a polygon that produces a single, closed shape. The
board outline may be placed using the grid points as a reference, or the outline may be placed
using precision keyins, using the Draw properties dialog.
Manufacturing Outline
The Manufacturing Outline is only a required object within FabLink XE Pro or FabLink XE and
can be DRC'd against other designs placed within a panel. The manufacturing outline within
Expedition PCB will not be DRC'd. Use the Edit > Place > Manufacturing Outline command to
define the manufacturing area. Only one manufacturing outline can be in a design file;
therefore, if a new manufacturing outline is placed in the design file, the old manufacturing
outline is removed. The manufacturing outline consists of a polygon that produces a single,
closed shape. The outline may be placed using the grid points as a reference, or the outline may
be placed using precision keyins, using the Draw properties dialog.
Manufacturing outlines are not saved within a reusable block.

Display Control
Board Origin
The board origin defines the (0,0) point in the design file, and the location of all design elements
are referenced from it. The lower left corner of the board makes a good location for the board
origin, as it puts all parts in positive coordinate design space and provides an easy reference
point to measure from. Use the Edit > Place > Origin command to define the board origin.
Optionally a Drill Origin can be placed. This allows you to define a specific location as the 0,0
point of your NC Drill output. Board and Drill origins can be moved using the X-Y option on
the dialog.
Mounting and Tooling Holes

Mounting holes are holes drilled in the board for purposes of securing hardware to the board or
for securing the board to a fixture, and are typically non-plated holes. Mounting holes
associated with specific parts, such as connectors, are typically built into those parts. Mounting
holes placed as part of the board setup would be those used to mount the board to a fixture or to
mount hardware, such as card ejectors or stiffeners, to the board.
Figure 3-21. Place Mounting Hole
Tooling holes are holes used to register and/or secure the board during the manufacturing
process. Tooling holes are often placed outside the board outline and are cut off during the final
routing of the panel. All mounting hole padstack types found in the Local and Central Library
padstack databases are displayed. The padstack name is prefixed by Local, for padstack in the
local Padstack database, and Central, for padstacks in the Central Libraries padstack database.
Use the Edit - Place - Mounting Hole command to place any needed mounting holes and tooling
holes. Mounting holes and tooling holes may be placed using the grid points as a reference, or
they may be placed by precision keyins using the Properties dialog.
Route Border
The route border defines the area within the board that contains trace and plane data. The route
border is used by the Auto Router and Batch DRC and must lie entirely within the board outline.
The route border can be used as a plane shape by selecting this option within Setup Parameters.

Display Control
Use the Edit > Place > Route Border command to place the route border. The route border
may be placed using the grid points as a reference, or by using precision keyins on the
Properties dialog.
Contour Placement
Contours are placed on the board to define slots or cutout areas to be cut into the board. A
contour can also be placed that defines how the board is to be cut from the panel. Use the Edit >
Place > Contour command to place any contours needed in the board.
Part Placement
Placing critical parts first ensures that the location does not get congested before a critical part is
placed. Critical parts typically have mechanical constraints to their location that cannot be
changed. Connectors, card ejectors, and stiffeners fall into this category.
Figure 3-22. Place Parts and Cells

Display Control
To aid in placing parts with critical routing constraints, the parts can be sorted by Net Classes
and Clearances. This allows parts to be grouped and placed based on the nets or net classes
assigned to its pins.
The parts should be fixed or locked after placement so that they are not inadvertently moved or
shoved when other non-critical parts are placed. This ensures that interactive routines do not
move, rotate or delete the part.
Place Part respects the DRC options defined in Editor Control. These options control how a part
will be placed, if DRC is enabled, and if existing parts are allowed to be shoved out of the way
of a part being placed.
If Online DRC is set to Off or Warning while placing parts, Review Hazards lists any
Component hazards that are created.
You can push back parts during placement by pressing and holding the CTRL key while you
place the part. If this option is enabled, when a part is placed in violation, the part is
automatically placed at minimum spacing (applying the normal part to part clearance rules),
from the violated part.
If the pushback fails (not enough room to place it in an error free location), the part returns to
dynamics.
After parts are placed, the Part Properties dialog is used to change the properties. If the rotation
or location fields are changed, the cell reflects these changes based on the Absolute or Delta
selection.
Absolute data is given in absolute coordinates (that is, coordinates that are taken relative to the
0,0 point) while Delta data is based on the current cell’s location and rotation. For example, a
part is at 180 degrees and Absolute is selected. If -15 is entered into the Rotations text entry
field, the result is 345 degrees. If a part is at 180 degrees, Delta is selected and -15 is entered
into the Rotations text entry field, the result is 165 degrees.
Nested Cells
When the properties for a nested mechanical cell are displayed or reported, the height of the
mechanical cell is adjusted by the height of the package cell, (if required, this is adjusted by the
underside space of the mechanical cell).
Only the reference designator for the package cell appears in the Place Parts and Cells list;
nested cells do not appear in this list. Nesting associations can only be made within the Cell
Editor . Batch DRC and Online DRC ignore the placement and insertion outline rules
violations between package cells and their nested cells.
Within a given library (central or design), the names for mechanical and drawing cells must be
unique regardless of their partition.

Display Control
Rules within IDF Import and Export

Nested mechanical cells are exported to IDF and are merged into the package cell; however,
nested drawing cells are not exported to IDF, they are ignored. During Import IDF, any package
cells that have been moved or otherwise manipulated are relocated as before and the nested cells
maintain their original location and orientation relative to the package cell.
Rules within PCB for Nested Cells

Nested Cells "flattened" - A mechanical or drawing cell nested within a package cell behaves
just like any other mechanical or drawing cells. When in Expedition PCB, individual instances
are added.
Move - When you move the package cell, the mechanical and drawing cells move with it. You
cannot ungroup nested cells in Expedition PCB.
Rotate - When rotating a package cell with nested cells, the nested cells maintain their relative
locations and rotations with the package cell.
Push - When pushing a package cell with nested cells, the nested cells maintain their relative
locations and rotations with the package cell.
Replace Cell - When a package cell with nested cells is replaced, it is modified to match the
data in the Cell Library.
Since the package cell has references to the nested cell, it always reflects the current state of the
mechanical or drawing cells that are nested. If you replace or reset the package cell, the nested
cells are also updated in the PCB Editor.
If you modify a nested mechanical or drawing cell, it is automatically updated in the

package cell and in the PCB Editor.
You cannot replace a nested mechanical or drawing cell in the PCB Editor; you must
make the change in the package cell in the Cell Editor.
Forward Annotation - If a package cell is added or updated from the Central Library and it has
nested cells, these are also forward annotated as well as any updated mechanical and drawing
cells.
Use Place Parts to place the remaining parts

Once the critical parts are placed, the rest of your parts can be placed. There are many ways to
place parts within Expedition PCB. Parts can be sorted by reference designator, part number,
package cell, room, cluster.
Some parts such as connectors and LEDs, must be placed at precise locations. This can be
accomplished by using keyins.

Display Control
Many times the best way of interactively placing parts is using the Connected to Placed option.
This sorts the parts based on the number of connections to parts that are already placed. While
parts are being placed, Review Hazards Online DRC reports any part of the maximum net
length hazards that are created. Part hazards can be controlled using the Editor Control Parts tab
which allows you to define if Online Placement Outline hazards are Off, Warning or in
Preventative mode.
Placing Etch Text

While the part placement area is populated mainly by parts, there are various types of text that
may be etched into the board. As some companies are avoiding the use of silkscreens, many
times all board identification must be done via etch text.
Figure 3-23. Example on how to place text
On most designs, at least a board identification number and layer numbers are required to be
etched onto the board. The text can be placed using the Place Text option in the Draw
module. More complex board identification can be built into a mechanical cell. This allows you
to build the documentation once and use it for multiple boards.
Netline Manipulation
Netline manipulation enables an interactive method for manipulating the ordering of nets. With
this command you can change the topology of a net from MST to Chained or Custom ordering
and you can specify the order in which pins of Custom nets are connected by interactively
modifying, adding or deleting netlines. You can also interactively place virtual pins and guide
pins. All changes made while in this command are reflected in the Net Properties menu.
Note
If your design has used CES, you have more flexibility when defining high-speed
topologies such as T -shape, Star and H-Tree topologies.

Display Control
If a plane shape is added to an existing net that is chained or custom, the net will then change to
MST.
When you initiate the Netline Manipulation command, all net objects on the board display in
Shadow Mode - all net objects appear grey except for the selected net. When you select a net by
selecting a pin or netline, all items in the net are displayed in the select color and the view is
fitted to include all component pins and netlines associated with the selected net.
Target Pin Selected by Mouse Position

The system seeks out a new target pin for a net based on the present location of the cursor
within the display window. The following are the required steps:
Note
If an "MST" topology netline becomes selected and is dragged in the display window,
that netline will automatically become a "Custom" topology netline.
1. Pre-select a location point on the netline closer to the pin that you want to be the anchor
pin.
2. A red "+" will be placed on this pin. The entire net and objects associated with the net
will be selected.
3. Hold down the Shift key, and then select the netline you want to re-assign by selecting
and holding down the left mouse button on that netline.
4. Once the netline is selected, release the Shift key.
5. Move the cursor within a very close proximity (but not exactly over) the target pin, and
the netline is tentatively "snapped" (be redrawn) between the anchor pin and the "new"
target pin.
6. As the cursor is moved in the display window within the proximity of other pins of the
selected net, the tentative netline "snaps" from the anchor pin to these other "new" target
pins.
7. To finalize the new netline between the anchor pin and the new target pin, release the
left mouse button, and the new netline, between these pins, is created and the previous
netline between the anchor pin and the original target pin is deleted. The red "+" will
disappear after the new netline to the target pin is created.
To change the net ordering back to the original target pin select either the Edit >Undo
command or the F6 Undo action key.
Terminology
Custom - This method looks for a user-defined netline order. If netlines are not found, or if the
definition is invalid (is incomplete or has loops), the chaining algorithm is used. Only pins are

Display Control
considered as valid connection points. If a net has more than 100 pins (or a plane net) and it is
marked Custom Order, the netlines cannot be ordered, and are then generated using the
Minimum Spanning Tree (MST) algorithm.
Guide Pin - Guide Pins cannot be shoved, as they are suggestion points of where a trace should
be routed.
Anchor Pin - The pin determined as the fixed end of a change of an existing netline connection
between two pins.
Target Pin - The pin determined as the new destination end of a replacement net connection
between two pins of an existing net.
MST - The Minimum Spanning Tree (MST) algorithm is used to generate the basic connection
order. However, netlines are dynamically generated to the closest connection point during
routing. A pin may be 'starred' to more than two pins in this configuration. If a net is a plane net
(because it is on a plane layer or it has a shape on a plane shape layer) it is always MST. When
a net is MST-ordered, the net lines are purely advisory. That is, you can make a connection to
any pin, via or trace regardless of the net lines.
If you choose a netline for a MST ordered net, and if there are multiple pins of the same net, you
can use the Tab key to change the target pin of the current plow.
Chained Order
The Chain algorithm is used to generate netlines. This algorithm connects the pins in a series to
create a daisy chain. A pin can be connected to a maximum of two other pins in this
configuration. The chain's pins are ordered according to their type, as defined in the following
table. Only single pin test points defined in the schematic are included in chained and custom
ordered nets. If a net has more than 100 pins, it cannot be chained.
Only pins are considered as valid connection points.
Parts Database Attributes

This maps the part pin type definitions accordingly:
Input and Schmitt become loads.
Bi-directional, output, tristate, open collector, open drain, and open emitter become
drivers.
Test points and connectors are a direct map.
Discrete part definitions for series/parallel resistor, capacitor, RC resistor, and Thevenin
resistor become terminators.

Display Control
Cell Types
Connectors and test points are identified.
Design Capture Properties and Symbols

This is a direct map to the necessary pin types.
All remaining unrecognizable pins become loads

The pin type assigned to a pin in the part can be displayed by clicking the Pin Types
button in the Display Control dialog. Plane nets can only be defined as MST Order.
Table 3-1. Chained Order
No. of No. of No. of No. of Algorithm
Drives Loads Connectors Terminators
0 >1 0 0 Chain the loads together
>0 >=0 0 0 Chain the drives, then the loads
0 >0 1 0 Chain the connector, then the loads
>0 >=0 1 0 Chain the drives, then loads, then
connectors
>=0 >=0 2 0 Chain with the connectors on the
ends
>=0 >=0 >2 0 Chain in any order
0 >0 0 1 Chain the loads, then the terminator
>0 >=0 0 1 Chain the drives, then loads
>=0 >=0 1 1 Chain the connector, then the drives
and loads, then the terminator
>=0 >=0 >1 1 Chain in any order
>=0 >=0 >=0 2 Chain with a terminator at both ends
- unless both terminators are within
.5”. In this case, both
terminators are treated as one
terminator. See the previous
references for one terminator.
>=0 >=0 >=0 >2 Chain in any order
Virtual Pins
Virtual pins should not be placed on existing pins, vias or traces as they would violate these
existing objects. The ms and xy keyins allow virtual pins to move within Netline Manipulation.

Display Control
Note
If traces have been routed to the virtual pins, Netline Manipulation move mode will
delete the traces connected to the virtual pin.
It is recommended to use Virtual Pin dyna-move to maintain connection of the traces to the
virtual pin. This can be done anytime in the design session without Netline Manipulation being
active.
1. Locate the virtual pin in the design.

2. Using the Shift key + the left mouse button on a virtual pin, drag the virtual pin to the
desired location.
3. During the drag, the netlines to the virtual pin will adjust accordingly. If the virtual pin
is routed, the traces connected to the virtual pin adjust accordingly.
Once the virtual pins are placed, the netlines can be connected to them in the same way they are
connected to the other pins on the net.
Characteristics
The virtual pin has no padstacks and can reside on any particular layer.
The virtual pin uses trace clearances instead of pad clearances.
Vias are allowed under virtual pins.
Virtual pins have unique reference designators. These unique reference designators
make it easier to find individual virtual pins.
Virtual pin manipulation is not available in the Net Properties dialog. They are displayed
and can be moved, but new virtual pins can only be added while in Netline
Manipulation.
Virtual pins do not allow stubs. Therefore any stub rules associated with a net are
ignored with virtual pins.
Virtual pins can only be deleted from the design using the Delete key or the Delete icon
within Netline Manipulation.
Router Interaction With Virtual Pins

The automatic and autoactive router interacts with virtual pins as specified below.
Vias and T-junctions will only be placed at the exact location of the virtual pin point.
The router will not push or shove virtual pins.
Fanouts do not work with virtual pins. The router may place a via at that point during
auto route if it needs to change layers.

Display Control
If manually routing on a layer other than where the virtual pin resides, a via must be
dropped onto that layer, or the virtual pin must be moved to the active routing layer
before connecting the virtual pin.
Automatic clean-up routines for vias and virtual pins are applied upon net completions
to minimize routing challenges.
Guide Pins
Guide pins are horizontal bowties and each has its own reference designator and is numbered
sequentially in the design for the active session. Guide pins and their associated netlines may be
selected and printed, but they cannot be photoplotted.
Guide pins are placed within the route outline and cannot be DRC’d against existing pads,
planes, traces or vias. When DRC checks are run, guide pins are identified as opens on nets (if
the routing between two pins are incomplete).
Adding Guide Pins on user-defined layers

The following explains the methodology on how to change the layer associated to each guide
pin.
1. Select a netline.
2. Select the Place Guide Pin command (F4 key). All guide pins automatically default to
being placed on All Layers.
3. While adding guide pins, if you want to assign a guide pin to a single layer, PRIOR to
placing it with the left mouse button, access the popup by clicking the right mouse
button, and select the layer that the next guide pin is to be placed on. All guide pins
placed after this layer has been selected default to being placed on All Layers.
4. Add (place) as many guide pins to the net as desired between the two pins and use the
popup’s "Accept Guide Pins" command to finish.
5. If you select the Cancel Place command from the popup, the guide pins being placed
between the pins of the highlighted net are discarded. Selecting the Esc key also cancels
the placement of guide pins.
6. When creating a netline with guide pins, the Undo command removes the last placed
guide pin, subsequent selection of the Undo command removes all placed guide pins on
the active net.
To edit / delete guide pins

A single guide pin may be selected either by using the left mouse button or by using the Ctrl-left
mouse button combination to toggle selecting/unselecting a guide pin. The Ctrl-left mouse

Placement Improvement
button may be used to drag select an area with guide pins within the Netline Manipulation
mode.
1. With the Guide pin(s) selected, click the right mouse button and from the popup decide
whether to assign the guide pin(s) to a single signal layer, a single plane layer or to all
layers of the design.
2. If a guide pin's layer is set to All Layers, the guide pin changes to the layer selections
you make by using the computer keyboard up and down arrows.
3. If a guide pin is deleted within the connections between its anchor and target pins, all
remaining pins are reconnected (but not renumbered) to a serial sequence.
Using guide pins on the edge of reserved areas

Every split design could potentially route to a different layer of the guide pins on the edge of the
reserved areas as these connections to the guide pins do not connect through the layers.
Therefore, the routes in each split design meet at the guide pins on different layers. These
connections must be manually controlled to ensure they are made on the same layer. Layer
restricted guide pins will force the connection between the splits to a specific layer.
Once the design has been either fully or partially placed, there may be a need to refine the part
locations. Parts can be moved, swapped or rotated. To help reduce the connection lengths, gates
and pins may also be swapped. When all the part, gate and pin refinements have been made, all
the changes can be automatically backannotated to the schematic.
If you want to:

Learn about fixing parts Information on page 125
Learn about moving parts Information on page 125
Learn about editing cells and part numbers Information on page 125
Learn about moving circuits Information on page 127
Learn about rotating parts Information on page 128
Learn about pushing parts Information on page 128
Learn about swapping parts Information on page 130
Learn about swapping pins Information on page 131
Learn about swapping gates Information on page 130
Learn about automatically swapping by cell name Information on page 131
Learn about automatically swapping by part number Information on page 132

Fixing Parts
The Fix Part command is selected while in Place Mode and is useful for temporarily fixing
or locking cells into place. The pads of a fixed cell will appear hatched instead of solid. Some
parts, such as LEDs and connectors, have pre-defined locations in the design. Once these parts
are placed, they should be fixed into their positions to prevent their accidentally being moved.
Expedition PCB provides two methods of preventing a part from being moved or deleted. The
two commands, Fix and Lock , provide slightly different protection schemes. The most
common method is the Fix Part command. The Fix command is used to temporarily fix a part in
location but may be unfixed later in the design process. The Lock command is used to lock a
part to a location permanently throughout the design process.
Once a part has been fixed or locked, they must be unlocked using the Unfix or Unlock
commands. Mounting Holes and Fiducials may also be fixed and/or locked. These objects may
also require specific locations in which you want the objects to be permanently placed.
You must be in Route Mode to Fix/Lock mounting holes, fiducials and test points.
In Place Mode, the Fix command fixes selected cells in position. Once a cell is fixed, it cannot
be moved, pushed, deleted or rotated. Fixed cells pads are drawn as filled (hatched) outlines.
This command is useful when working with cells that must be placed in critical positions.
Editing Selected Cells and Spare Part Numbers

You can use the Cell Editor to change the selected cells local library definition wile you are in
Place mode. When you choose Edit Selected Cell, the Cell Editor opens into graphics with that
cell active. You may then edit, save and exit Cell Editor and all the parts that reference this cell
are updated within the design.
If you have the Cell Editor open and you choose Edit Selected Cell on a different cell, you are
asked to save the first one opened.
There are two modes of changing a part number for a selected cell. The first method is to assign
a new part number based on the valid part numbers which are defined for the selected cell in the
Central Library. The second method allows the assignment of a new part number based on
existing unplaced parts referenced by the schematic which are valid for the selected cell.
Move Part
Use the Move Part command when moving individual parts. This command adjusts the
locations of all package, mechanical and drawing cells. Mounting holes and fiducials must be
moved using the Edit > Properties command, while in Route Mode.
Move operates on individual parts, multiple parts, grouped parts and reusable blocks.

If parts within the design have been assigned to a group, selection and movement of any
of the parts within the group causes the entire group to move together.
If a selected part is nested within a reusable block, movement of this part, or any parts,
within a reusable block causes the entire block to move.
While a part is attached to the cursor, the following commands can be selected from the action
keys: Rotate 90, Rotate 180, Push, and Snap to Grid. Parts can also be moved using the arrow
keys or by file.
Rotate 90 Rotates the selected part counter-clockwise in 90-degree segments.
Rotate 180 Rotates the selected part counter-clockwise in 180-degree

segments.
Push Moves a selected part and its local interconnects from one side of
the board to the other.
Rip-Up Segment Un-routes the first segment on non-local traces attached to the part
or parts being moved.
Rip-Up Junction Un-routes all non-local traces back to junction.
Rip-Up All Un-routes all non-local traces back to junction and all local
interconnects (except cosmetic traces in a cell).
Snap to Grid Snaps the selected part's origin to the nearest placement grid point.
While the parts are in dynamics click the left mouse button to place the parts at the selected
location. If this location causes DRC hazards to occur, either a warning is generated, the part is
not placed, other parts are moved out of the way or the placed part is moved out of the way
based upon the following four options. These options, except Pushback, are selected within the
Editor Control > Parts tab.
Warning allows the placement outlines of the part being placed or moved to overlap the
placement outlines of existing parts. Pads are never allowed to break the defined
clearance rules.
Preventative does not allow placement outlines or pads of the part being placed or
moved to violate the placement outlines or pads of existing parts based on the Net Class
General Part to Part and Pad to Pad clearances.
Shove Part shoves any existing parts out of the way if Pad to Pad or Placement Outline
hazards will be created.
Pushback Part pushes back the part being placed or moved out of the way of existing
parts in order to prevent Pad to Pad or Placement Outline to Placement Outline hazards
from occurring. Pushback occurs when the Ctrl key is held down during placement or
movement of a cell. Pushback will place the part using the minimum defined clearances.

Your may choose to select a group of parts. If a group of parts is selected individually, using the
Shift or Ctrl key, or by fence while in this move state, you will be required to select an anchor
point for the group. The parts and any routing fully contained within the selected area, enter
dynamics, allowing these circuits to be moved.
If parts are selected, prior to the Move command being selected, parts will enter dynamics as
soon as the command is invoked and the anchor point will be the center of the selected parts.
When moving a group of parts that you consider to be a circuit, select the Move Circuit option
in order to maintain the location of existing traces and vias.
Move Circuit
Use the Move Circuit command when a group of parts is moved and you want to maintain all
routing between the parts. This command requires you to place a fence around all the parts that
are to be moved. Traces that are fully contained within the circuit are maintained and any traces
that connect outside the circuit being moved may be re-routed or adjusted as needed.
When the circuit is attached to the cursor in dynamics, choose one of the following action keys:
Rotate 90, Rotate 180, Push, or Snap to Grid.
When using Move Circuit, the following are automatically selected:
All the interconnects (traces and vias, no plane data) between the selected parts.
All plane net fanouts, (multiple vias included), within a half inch of the pin. Non-plane
nets only select out to the first via.
All the traces and vias which are locked (and connected to the traces or vias in the first
two categories) regardless of their length.
The above methodology gives you the ability to add any other traces and vias to the set of
objects moved during Move Circuit. Fixed traces are ignored if they do not fall into the first two
categories.
Any interconnect which is selected with Move Circuit is placed exactly as it was originally;
however, if it were to create a short, it is ripped up.
Snap to Grid
The selected part's origin snaps to the nearest placement grid point if that option was selected in
the Editor Control - Parts tab. If the Centroid of Pins button was selected in the Editor Control -
Parts tab, the geometric center of a part's pins is snapped to the placement grid. Multiple parts
can be snapped to grid at a time.

Rotate Part
Selected parts can be rotated, counter-clockwise, in 90- and/or 180-degree increments. The part
rotates around the grid nearest the centroid of the part. An attempt is made to preserve all
existing connections.
Multiple parts that are selected can be rotated. Each part rotates about its own centroid. To
rotate the parts as a group, you must have the parts selected in dynamics. Use the Move
command and then select rotate. This rotates the parts based on the centroid of the group.
If your Editor Control - Parts option is set to Warning you should conduct a hazard analysis,
anytime you move a part, using the Online - Component Hazard dialog. Even though no metal
to metal conflicts are allowed, it is possible to violate placement outline clearances.
Push Part
This command allows you to move a selected part and its local interconnects from one side of
the board to the other. If the selected part is currently on the top placement layer, Push moves
the part to the bottom placement layer. The part mirrors about the grid nearest the centroid of
the part and the X axis. Text within the cells will follow the Editor Control text orientation rules
when a part is pushed.
Note
RF circuits cannot be pushed.
Care should be taken when pushing parts with existing traces. If the traces connect to other pins
of the same part, they are pushed to the new side with the part. If an existing trace goes to
another part, then the trace will be rerouted. When a trace goes from the part being pushed to a
via, the trace is pushed with the part and whenever possible the via is deleted.
If the part is in dynamics and the push command is selected, the part is pushed to the opposite
side of the board. To release the part once it has been pushed, click the left mouse button on the
part. If the part cannot be released without conflict, the part remains in Click Move mode, and
you can either push the part back to its original position or press Esc to return the part to its
original board side. The active placement layer returns to the original placement layer.
If the application is set to the Editor Control - Parts tab - Warning option, anytime you move a
part, you should conduct a hazard analysis using the Component Hazard dialog. Even though no
metal to metal conflicts are allowed, it is possible to violate placement outlines.
If an SMD part is pushed from the top to the bottom layer or vice versa, the padstack attached to
the part is not pushed. Instead, one from the padstack database is used. The Padstack definition
is layer-specific. Any changes made to a part's pads using the Padstack Processor are replaced
by the Padstack Editor's default pad definition during a push between layers.

Copy Circuit
Use this command to make a copy of a group of parts with completed inter-connections.
Connecting traces with both end points inside the selected area are copied with the selected
parts. The software looks for unplaced parts and distributed parts (parts outside the board
outline) that are equivalent to the selected parts within the master circuit. Equivalency is based
on the master circuit’s part numbers and interconnections within the master circuit.
To help Copy Circuit find an equivalent circuit, order the Reference Designators between the
circuits. Therefore, your master circuit might have Reference Designators U1, R1, D1 etc. Each
circuit to be copied from the master would have Reference Designators U1X, R1X and D1X
where X is unique between the circuits. This causes the circuits to have their Reference
Designators sorted. X in the example could be A, B, C or _1, _2, _3 with each being consistent
within the circuits. After the circuit is placed, the Reference Designators can be renumbered.
Once the circuit is copied to its new location it becomes individual traces and parts. The copied
circuit is not maintained as a group and has no relationship to the master circuit from which it
was copied.
Process of designing your schematic

In order to make optimal use of the Copy Circuit command, the schematic must be defined with
each circuit as a block and the References Designators between each block packaged so they are
sorted alphabetically ascending. By designing your schematic in this way, it will aid the Copy
Circuit equivalency algorithm in finding the next equivalent circuit as fast as possible.
1. Create a new schematic for each circuit you intend to copy using Copy Circuit. Make
sure to use hierarchical connectors for any signals that enter or exit the circuit.
2. Within your main schematic, select Place->Block to place a schematic block,
referencing the schematic circuit you just created. This will be your master circuit. The
block will contain any pins for signals that enter or exit the circuit.
3. Save and Compile the iCDB.
4. Run Tools->Packager to create the packaging for your master circuit and any other
symbols placed in your project. Check the log file to verify no parts or cells were
missing.
5. Open your master circuit, this will automatically absorb the packaging that was just
done. Placed the Frozen Package property with Block as its value on all symbols in the
master circuit.
6. Open your main schematic and copy, or place, this block as many times as the circuit is
needed.
7. Run the iCDB Compiler to create iCDB instances for each block that was placed.

8. Run the Packager to package all of the circuits. The packager will base the packaging of
the copied circuits on the master circuit and by using the Frozen Package property, will
append the block number to each Reference Designator. This generates the Reference
Designators, sorted alphabetically, between each circuit.
9. Enter the Expedition PCB job and run Forward Annotation. Check the log file to verify
no parts or cells were missing.
10. Place the master circuit in Expedition PCB. This can be done easily by using Place Part
with schematic cross probe. Open the master circuit that has the original packaging on
each symbol (the Reference Designators without _XX appended). Then with Place Part
displayed and in “By schematic mode”, select each symbol and place it on the board.
The option of adding to the list can be used to group select all of the symbols within the
master circuit.
11. Once you place the master circuit, use Expedition PCB routing functionality to route the
connections that are within the circuit. Do not route any connections that exit or enter
the circuit.
12. Now that the master circuit is fully placed and routed, use the Copy Circuit command in
Expedition PCB to copy this master circuit for each instance that was defined in the
schematic.
Swap Parts
Use the Swap Parts command to swap the physical location of two parts. This command is
useful when the parts are placed in a pattern that should be maintained, but parts within the
pattern still require netline optimization. Part Swapping with grouped components is not a
supported function.
Swap parts determines the location of the parts to be swapped based on the part origin. This
allows parts of different package types to be swapped. Each part is moved to the other’s XY
origin location using each other’s rotation and side.
Swap Parts respects the Fixed and Lock settings and will not allow part swapping to occur on
fixed or locked cells.
Swap Gates
Swap Gates allows gates to be exchanged within a part and external to a part, as long as the
parts share the same part number. You can swap individual gates, gates with common pins and
symbol gate groups. The latter two are supported through the Gate Swap dialog. If you do not
choose to display the Gate Swap dialog, only individual gates may be selected and swapped. To

Automatic Placement Modification
swap gates with common pins or symbol gate groups, you must use the Gate Swap dialog. Gates
are only allowed to be swapped if a DRC violation does not get created and gate swapping is not
allowed for gate pins that have routed connections.
Swap Pins
Swap Pins allows pins within gates to be exchanged based on the swap definition defined for
the part. The purpose of pin swapping is to reduce the crossing of netlines at the package. In
many cases, just swapping two pins of a gate make the difference in successful routing.
Equivalent pins are swapped if they are within the same gate. Pins are only allowed to be
swapped if a DRC violation does not get created.
Automatic Placement Modification

In addition to the Interactive Placement Improvement process discussed in the previous section,
Expedition PCB provides automatic swapping by cell name, automatic part swapping and polar
place commands. Proper use of these commands greatly decreases the time required to take a
design from the placement phase to the routing phase.
Automatic Swap/Rotate by Cell Name

Like the semi-automatic Part swapping commands, the Automatic Swapping process provides
an automatic way to exchange parts to reduce netline length. However, unlike its interactive
counterpart, Automatic Swap/Rotate by Cell Name only swaps parts of the same package type.
This is done to prevent the introduction of placement errors in the design resulting from
swapping with a part of a larger part outline. This command swaps and/or rotates parts in an
effort to reduce the netline lengths.
If parts are placed in rows and columns and this orientation is to be maintained, only the Swap
option of the command should be used. Using the Rotate or Flip option may change a part to an
undesired rotation. Rotate and flip should be used on parts whose orientation is not critical.
The difference between Rotate and Flip is that Flip always moves in increments of 180 degrees.
The Rotate option rotates the part in 90 degree increments if the part outline is basically square,
as in quad-packs and PGAs. If the part outline is a shape other than square, the part is rotated in
180 degree increments to prevent overlap of the part with the design edge, mounting hole, or
other part. Therefore, the Flip and Rotate options are basically the same for parts with non-
square outlines.
Parts with traces cannot be moved or rotated by this command. Parts that are fixed or locked
will not be swapped. If two parts to be swapped have traces attached, the traces must be
attached to the same pin and must be of the same net, or the parts cannot be swapped. If a part is
completely routed, it will also not be considered for swapping.

Placement Verification
Automatic Swap by Part Number

Like the semi-automatic Part, Gates and Pin swapping commands, the Automatic Swapping
process provides an automatic way to exchange parts, gates and pins to reduce netline length.
Automatic Swap by Part Number swaps parts, gates and pins based on the part swap definition
for each part number in order to minimize the length of the netlines that facilitates optimum
routing. When swapping is complete, the Back Annotation process is run when the design is
saved. Back Annotation maintains consistency between the board design and its CAE input.
Automatic Swap by Part Number respects the Fix and Lock settings. Parts that are fixed or
locked are not swapped. If two parts to be swapped have traces attached, the traces must be
attached to the same pin and must be of the same net, else the parts cannot be swapped. If a part
is completely routed, it is also not considered for swapping.
Polar Placement
Parts may be moved into a defined polar (circular) array using the Polar Place command. Parts
may be rotated, placed on the top or bottom of the design, or by pin 1, part origin or part
centroid.
You cannot use polar placement on fixed parts. They must be unfixed before they can be
defined as part of the array. Parts that are already placed and are defined as being part of the
array will be moved from their current position to the array location.
Placement Verification
Before starting the routing phase of a design, verification checks should be made to validate the
placement of the design. Making checks at this point ensures that the design is error free prior to
connections being routed. Routing a design with placement errors may invalidate large
percentages of routing and may not be repairable after traces have been added to the design.
If you want to:

Learn about verifying part placement in DRC Information on page 132
Learn about mechanical verification Information on page 133
DRC - Verifying Part Placement
Batch DRC should be executed to verify that the parts in the design have been placed and/or
moved without creating spacing violations. Batch DRC is used again later in the design phase to
verify routing.
At this point in the design process, many of the Connectivity and Manufacturing checks are of
little or no use. Only the options that check for proximity violations should be selected. To

Routing
ensure consistency between which validation checks are done during Batch DRC, a DRC
scheme can be created with the options selected to verify placement, then this scheme can be
used for multiple designs. The following are suggested checks that can be run to verify
placement:
In the DRC Settings Tab:

o Area - Within the board outline
o Rules to Check - Net Class Clearances
o General Element to Element Rules
Note
If there is no check mark in the Connectivity and Special Rules and/or General Element
to Element Rules check boxes, none of the options in the Connectivity and Special Rules
or Advanced Element to Element Rules are active.
Upon completion of Batch DRC, a message displays indicating the number of DRC hazards
found in the design, dependent upon your selections. The breakdown of these hazards can be
reviewed in the created DRC.txt file through File Viewer. If errors exist, they should be
corrected and the Design Rules Checks run again. Continue this process until DRC is run with
no errors or with errors deemed to be acceptable. For example, you may want to place some
parts underneath other parts.
Caution
It is important to check the drc.txt file after each run of Batch DRC. This file can be
viewed through File Viewer. The Batch DRC hazards limit is 10,000 for proximity
checks and 10,000 for connectivity checks. If this limit is passed, Batch DRC stops
before completing verification.
Mechanical Verification
Expedition PCB provides the capability to transfer two-dimensional electronics placement data
to mechanical verification tools and back again using IDF Export and Import. This provides you
with the ability to verify that no mechanical interference exists between the parts in the design
and any related mechanical hardware. If conflicts are found, the parts can be moved in the
mechanical design software and those changes can be translated back to Expedition PCB. The
actual capabilities of the mechanical verification depend on the mechanical design package
used.
Routing
Expedition PCB provides you with both semi-automatic and automatic routing and route editing
commands.

Routing
The Automatic Routing commands provide you with access to the most powerful shape-based
automatic routing tools available. These commands allow you to work with automatic functions
on individual traces or groups of traces or to automatically route the entire design.
Prior to using either of the two sets of routing commands, there are steps that must be completed
and verified. Many of these steps can be set up and placed in your Central Libraries layout
templates. However, before starting the routing phase of a design, always make sure the items
are correct for your design configuration and rules.
You should enter Setup Parameters and verify that the correct number of layers are being used,
the plane layers have been defined, and the correct default vias have been assigned.
Enter Net Classes and Clearances and verify that the trace widths assigned to each Net
class and the clearances have been defined correctly.
Enter Net Properties and verify that each net has the correct net class defined and all
high-speed rules needed for the design have been added.
Enter Editor Control and verify that the correct layers are defined to be used for routing,
the layer pairs are defined correctly, and any other routing rule has been defined to meet
the needs of your design.
If you want to:

Learn about saving your work Information on page 134
Learn about route modes Information on page 134
Learn about route and via obstructs Information on page 111
Learn about net classes and clearances Information on page 101
Learn about net properties Information on page 104
Learn about routing costs using the Editor Control dialog Information on page 135
Route Mode
Route Mode enables all semi-automatic and automatic routing functions. Route mode is also
used for placing and manipulating traces, vias, mounting holes and fiducials. All traces and vias
are manipulated within this mode.
Saving Your Work
Use the Save command periodically and especially after performing major tasks. Saving your
data protects against data loss in the event of a system crash or power outage. You should

Routing
always save your work at the completion of major steps. The Save Copy command saves a copy
of the top level layout directory (with the option to save only the essential files) to the specified
name and location.
At various stages in the design process, for example, after completing component placement or
critical routes, we suggest saving a copy of your job. You could then return to a previous
version of the design if desired. The Editor Control AutoSave interval allows you to save your
design database at regular intervals during interactive commands and during Auto Routing.
If the Auto Router exits abnormally for any reason, and an AutoSave file exists, you are
prompted to update your design from the last AutoSave the next time the application is
initialized on that job.
Routing Costs using the Editor Control
The relative cost or expense of routing a design is defined in the Editor Control - General
dialog. These parameters define the behavior during semi-automatic routing sessions: routing
effort, enabled routing layers, directional bias settings and the layer pairings for the design.
The effort setting for semi-automatic routing defines the amount of effort a command expends
on any given connection. The more effort you specify, the more time will be spent trying to
complete a connection.
The routing and directional bias settings control whether routing layers are enabled and the
directional bias for the routing layers. All layers are candidates for routing unless overridden by
this command or are layer restricted in the Net Classes and Clearances dialog. By default, plane
layers are disabled in Editor Control.
The layer bias setting for interactive routing determines the relative difficulty of routing against
the layer bias versus placing a via. The higher the direction bias the more difficult it is to place
the trace against the bias. If you select medium or low too early in the routing process, routing
channels may quickly become blocked, making routing very difficult.
The via cost and maximum vias added settings for semi-automatic routing control the maximum
number of vias allowed during routing and tuning operations and the relative cost of adding a
via to a path. The default setting, medium, works best for most designs. These settings do not
override the maximum vias per net option under Net Properties.
Layer pairs are designed to aid the interactive routing of designs. For example, if you want to
switch to a layer, you can use the space bar to add a via and because of the layer pairings you
always know which layer you are going to. If you need to go to a different layer, you can select
that layer in the Display Control menu.
You can also define which adjacent layers of the design, differential pairs should be routed on.
If no adjacent layer pairs are defined, then differential pairs are routed on the same layer.

Routing
Placement Checking
The Editor Control - Parts dialog allows you to define how the Design Rules Checker (DRC)
handles part hazards as you move and push parts. When moving parts you can limit the display
to only those netlines directly attached to the part. DRC can be set to warn you or to prevent part
hazards. If the warning option is set, part hazards are allowed, and a warning is issued when
they occur. This option does not allow metal to metal conflicts. If the preventative option is set,
no part hazards are allowed. All hazards, including metal to metal conflicts must be resolved
before placement is allowed.
Routing Rules
The Editor Control - Routes dialog contains the general design rules governing your design as
well as the controls that override settings from the Net Classes and Clearances and Net
Properties menus. These should not be confused with design clearances. In those instances
where a design becomes impossible to finish, you can use this dialog to turn off rules and finish
routing your design. Even though you have overridden a rule on a temporary basis, Expedition
PCB always reports the override as a hazard allowing you to address it at a later date, as space
becomes available.
Note
You can control the fanout of unused single pin nets by using the "Enable fanout of single
pin nets" option on this tab. By default, this option is enabled.
Router Tuning Patterns

Any high speed net that requires modification to satisfy formula or net delay constraints can be
tuned. The settings in the Editor Control’s - Tuning dialog defines the topology requirements
for these modifications.
Tuning Meter
When dyna-moving or interactively plowing nets with high speed length or delay constraints,
you can display the tuning meter on your cursor to view length statistics. The Tuning Meter
displays the current length or delay in relation to the user-defined target length/delay
constraints.
The tuning meter displays yellow when the length or delay is less than the target tolerance. The
meter turns green when the routed trace is within tolerance and is red when the range has
exceeded the tolerance. When the Display Tuning Meter option is enabled, the tuning ellipses
will not be displayed.
When the active constraint is applied to a Net, the cursor has an "N" next to the starting line. If
the constraint is on a Pin Pair, there is no additional graphic.

Routing Interactively
Design Grid
If the via, placement, route, draw and/or jumper grids are set, all traces, vias and parts are placed
on their respective grids. If the Gridless pad entry for all pads option (on the Pad Entry tab) is
selected (only active if a Route Grid is defined), traces will route gridless into pads as well as
around pads that are off the route grid. This allows better pad entry as well as being able to
route between pads when the clearances are precise.
Even though the Auto Router is a gridless router, some designs may require grid setting. The
grid origins are defined by the Board Origin command. If you are unsure where the origin is,
position the cursor at the X, Y location 0, 0. If this is incorrect, reselect the origin using the
Place Origin command.
The route grid must be a multiple of the via grid or vice versa. If the router grid is greater than
the via grid, the via grid is ignored.
The Move and Push Part commands place the selected part onto the chosen grid, but if the part
was initially placed off-grid it remains off-grid.
If you plan on using the semi-automatic editor to route traces, you may want the same grid to
make sure that traces are on-grid. This limits the capabilities of the Auto Router. Remember, the
Auto Router is a shape-based-gridless router. It works best with no grid settings.
Net Selection Filter

The Filter allows you to work with specific groups of nets or net classes by activating specific
nets and or net classes within your design.
All nets by default are in the Included field. Nets listed here are those nets that are available for
routing by the Item Select, Area Select, Plow and Auto Route commands. This listing contains
both net classes and net names for the nets. When you select a net class, all rows in that list
having the same net class name are selected. When you select a net name, the entire row,
including net class, is selected. When you need to exclude nets, move them into the Excluded
field.
The Enable Filter allows you to turn the filter on or off without changing the contents of the list.
The semi-automatic routing tools use the same rules and clearances as the automatic router, and
they offer a wide variety of features to make interactive routing easier.
Note
Before you start routing, check the Review Hazards dialog to review and fix and
placement hazards that were created during placement manipulation.

These tools are discussed in the following sections:
If you want to:

Learn about moving traces and vias Information on page 138
Learn about Hug Trace Information on page 148
Learn about Gloss Information on page 149
Learn about curved traces Information on page 153
Learn about force plow Information on page 155
Learn about route plow Information on page 156
Learn about angle plow Information on page 156
Learn about dyna-plow Information on page 156
Learn about multi-plow Information on page 157
Learn about the route command Information on page 161
Learn about interconnect modification Information on page 164
If the Shove Trace option has been selected within Editor Control, these commands route a trace
through an area by pushing and shoving existing traces and vias out of the way. Force Plow,
Route Plow, Angle Plow, Dyna-Plow and Multi-Plow are also used for placing any pre-routes
into the design. Typically on high-speed designs, there are many signals that must be pre-routed
and tuned before routing the normal signals. Once routed these traces should be fixed to prevent
accidental modifications. If a part pin has more than one netline attached to it, these commands
always choose the shortest netline to route. They automatically change the target netline if an
anchor point is placed closer to the end of one of the other netlines.
Moving Traces and Vias in Route Mode

The Move command allows you to reposition and adjust trace segments and vias. It pushes and
shoves other traces in your path. To move an item, ensure that no other command is active,
position the cursor on the item you wish to move and drag the left-mouse button.
Selecting a horizontal or vertical trace segment moves that segment horizontally or vertically,
but selecting a trace vertex allows you to move the two line segments comprising the vertex
horizontally, vertically or diagonally. A selected via, and its connected traces, can be moved in
any direction.
Trace segments containing 45 degree angles can convert to 90 degree angles, but segments
containing 90 degree angles can only convert to 45 degree angles when the Editor Control -
Routes option allowing 45 degree corner is turned on.

Note
AutoTune attempts to retune all nets that haven't been tuned optimally when the
following functions are performed: exiting plow commands, Fit View, opening either the
Editor Control or Hazards dialogs.
If you want to work interactively with any of the above functions, minimize the dialogs
so they stay open but do not activate AutoTune, or you may stay in the Plow command.
The Plow command does not start Auto Tuning. The Fit View command, used many
times while plowing, should be also used while in the Plow command.
Multiple Via Objects

For purposes of current carrying capacity, there is a need to use multiple vias when a route path
changes layers, connecting to another trace, an area fill or plane area. In general the number of
vias to be used will be relative to the trace width and via span.
The interactive and automatic router routines respect the multiple via objects.
Multiple via objects can be manipulated like single vias in Expedition. They can be moved with
the traces and limited support of push and shove. They can push traces and default vias,
however, they cannot be shoved.
The creation of multiple via objects occur while automatic or interactive routing is taking place.
They are created from several constraints found in the Setup Parameters > Via Clearances
dialog and while routing with or selecting a multiple via object, the action keys and popup menu
allow you to change the pattern, rotation or single via count.
Single Via Object (SVO) This is a single hole via. Before the need for multiple via objects
(MVO), single via objects were known as vias.
Completely defined SVO padstacks are used to create multiple via
objects. The term via may be exchanged with the acronym SVO.
Multiple Via Object An object that represents a pattern of single via object. The
(MVO) relation is that of the master via created with a collection of two or
more single vias.
Multiple via objects use the complete padstack of a single via,
including: Pads per layer, Thermal Relief and Anti-Pads and
Holes.
A solid copper (Conductive Shape) is used on each layer to
provide interconnect between each single via object (SVO) that
make up the multiple via object (MVO).

Principles of Multiple Via Objects

1. Multiple via objects are created from multiple copies of a single via. All single via
objects within a multiple via object are identical.
2. Legal pad shapes within a single via are square, round and octagon.
3. Multiple via objects consist of two to twenty-one single vias:
Via Count Pattern (Row X Column)

2 1x2
3 1x3
4 1 x 4, 2 x 2
5 1x5
6 1 x 6, 2 x 3
8 2x4
9 3x3
10 2x5
12 2 x 6, 3 x 4
15 3x5
16 4x4
18 3x6
20 4x5
21 3x7
4. All automatically created multiple via objects patterns are symmetrical.

5. Multiple via objects are treated as a single entity by automatic and interactive routing
manipulations.
6. The connectivity point for multiple via objects is the center of the multiple via object.
7. Multiple via objects are created at 0 degree rotation.
8. The center point of the lower left single via at zero degree rotation will snap to the via
grid. This will not apply to a multiple via under pad and special multiple via objects used
for BGA fanouts.
9. Multiple via objects rotation will orbit about the connectivity origin.
10. Multiple via objects can be rotated interactively or automatically in 45 degree
increments.

11. Pad entry rules apply to multiple via objects, avoiding acute angles where possible.
12. Hazards are updated to show acute angle trace entry into multiple via objects.
13. All same net, via to via clearance options apply between multiple via objects and other
vias.
14. Same net, via to via clearances are used to create multiple via objects.
15. Before placement of a multiple via object the interactive override exists for via count,
size, pattern and rotation.
16. Multiple via objects can have their rotation, pattern or single via count changed
interactively; after they have been placed.
17. Multiple via objects offer coupling with other multiple via objects and single vias
through the Same Net, via to via clearances.
18. Via in pad options are provided for the multiple via objects in rectangular, oblong and
square pads. This requirement applies only to Automatic Routing
19. Via in pad options are provide for BGA and CSP packages using two count multiple via
objects.
20. Same net, multiple via objects to multiple via objects, multiple via objects to via and
multiple via objects to SMD pin pad fillets occur when the multiple via object's
clearance is less than the user-defined input clearance established with the option to
modify the clearance.
21. For outputs, a multiple via object is represented as the individual vias and large pad that
creates the multiple via objects.
22. Multiple via objects' hole sizes, layers and locations is available in Expedition drill
outputs.
Affected Commands
The following table represents the pulldown commands that are affected by multiple via
objects. The Remap Layers functionality automatically creates multiple via object pads on new
layers added by the command.
File > Save Any designs that are saved containing multiple via objects
cannot be opened in earlier versions of the 2005.2
software.
File > Export Treats multiple via objects as single vias and planes.

File Export > ASCII The LayoutDB.hkp file has changes reflecting multiple via
objects. Exported databases cannot be imported in earlier
versions of the 2005.2 software.
File > Split Design TeamPCB is updated to support multiple via obstructs.
File > Join Design
Edit > Undo / Redo Complete support for Undo and Redo.
Edit > Add to Select Set > Multiple via object teardrops are created only between
Teardrops multiple via objects and other object pads that are directly
connected by a trace. When a teardrop is added for a
multiple via object pad the trace attached to the multiple
via object trace is modified to ensure that the out of pad
portion of the trace is completely covered with the teardrop
shape.
Edit > Add to Select Set > Fix For Fixed and Unfixed Vias commands, multiple via
Vias / Unfix Vias objects are included with vias and these commands also
address multiple via objects.
Edit > Add to Select Set > For Locked and Unlocked Vias commands, multiple via
Lock Vias / Unlock Vias objects are included with vias and these commands also
address multiple via objects.
Edit > Find Supports the same level of select and highlight as
associated with vias.
Edit > Review > Design Status Design Status includes the single via count in the via count
section.
Edit > Review > Hazards The Multiple Via Pad Entry hazard is created for problems
with multiple via objects
Edit > Review > Minimum Multiple via objects are supported.
Distance
Edit > Review > Padstack Opens the Multiple Via Objects dialog for the selected
multiple via objects.
Edit > Place > Via Uses multiple via objects when multiple via objects are
required instead of single vias.
Edit > Modify > Padstack The Padstack Processing option is enhanced to support
Processor multiple via objects; the single via placement does not
change. The support includes the identification of multiple
via objects for padstack replacements of single vias. The
multiple via object pad is resized to accommodate the
modified single vias.
Edit > Fix and Lock Supported.
Commands

Edit > Highlight commands Supported.

Edit > Delete Commands Delete and Delete All Traces and Vias support multiple via
objects.
Edit > Properties Properties of the multiple via object display in the Padstack
Properties dialog.
Setup > Cell Editor Multiple via objects are not allowed in cells and multiple
via objects functionality is not supported in Cell Editor.
Setup > Setup Parameters Settings in Setup Parameters influence the placement of
single vias and the size of multiple via objects.
The creation of multiple via objects are dependent on the
Same Net, Via to Via clearance for their layer range. This
value is used to locate single vias in relationship to each
other within the multiple via object pattern.
For staggering multiple via objects through different layer
ranges, the Same Net values are used to stagger multiple
via objects to other multiple via objects or single vias on
different layer ranges. Via patterns supporting buildup
layers and microvias use the efficient pattern to span
several layer sets.
Setup > Editor Control The Editor Control > General tab has several influences
over the routing of multiple via objects.
Setup > Net Classes and Via and pad clearances set in Net Classes and Clearances
Clearances are applied to multiple via objects.
Setup > Net Properties The Net Properties > Other tab references Max Vias. This
value, if used, represents a multiple via object as a single
count.
Place > Move Circuit / Copy Multiple via objects are not supported for Copy Circuit or
Circuit Move Circuit with any angle rotations; only multiple via
objects with rotations at 45 and 90 degree increments are
supported.
Route> Interactive and Auto Both Interactive and Auto Route commands support
Active Routing multiple via objects.
Copy Trace - Handles multiple via objects as regular vias.
Push Trace - Allows multiple via objects insertion when
via or multiple via objects insertion is required to move a
portion of a trace to another layer.
Gloss - Multiple via objects can be rotated.

Route > Teardrops and Multiple via object teardrops are created only between
Breakout Traces > Teardrops/ multiple via objects and other object pads that are directly
Dynamic Teardrops connected by a trace. When a teardrop is added for a
multiple via object pad the trace attached to the multiple
via object trace is modified to ensure that the out of pad
portion of the trace is completely covered with the teardrop
shape.
Route > Change Width This command will not change existing multiple via
objects. However, a hazard that addresses this difference if
there should be a new or different multiple via object is
available.
Route > Remove Hanger Multiple via objects are treated as regular vias.
Route > Delete all Traces and Multiple via objects are supported.
Vias
Planes > Plane Classes Multiple via objects connect to planes by multiple via
Parameters object pads represented by conductive shapes with no tie
legs or thermal reliefs.
Internally, the multiple via object in a pad is a conductive
shape and is automatically generated on each electrical
layer where the single vias have pads. Even though it is
represented as a conductive shape it acts as a pad in terms
of pad entry rules. The multiple via object pad corners are
always chamfered (45 degrees) for round single via pads. If
a square single via is used, the multiple via object pad
displays 90 degree corners.
Analysis > DRC Window and For Design Rule Checking (DRC) of non-same net objects,
Batch DRC the following applies to multiple via objects. Interactive
DRC for multiple via objects use the Via clearances found
in Net Classes and Clearances.
A conductive shape covers all the single vias in an multiple
via object and is the metal shape used for DRC.
Individual single via pads are also used for DRC and these
use the clearances applied per netclass, which include:
Via to Via
Via to Trace
Via to Pad
Trace to Trace
Trace to Pad
Batch DRC uses the same clearance definitions as
Interactive DRC.

Analysis > Review Hazards The Multiple Via Pad Entry hazard is created for problems
with multiple via objects.
Output > Design Status Includes the single via count in the via count section of the
file.
Output > Gerber Multiple via objects Gerber out the same as vias and plane
conductive shapes.
The Padstack Processing option is enhanced to support
multiple via objects; the single via placement does not
change. The support includes the identification of multiple
via objects for padstack replacements of single vias. The
multiple via object pad is resized to accommodate the
modified single vias.
Output > NC Drill NC Drill outputs each single via. The Padstack Processing
option is enhanced to support multiple via objects; the
single via placement does not change. The support includes
the identification of multiple via objects for padstack
replacements of single vias. The multiple via object pad is
resized to accommodate the modified single vias.
Unsupported Items with Multiple Via Objects

The following are not supported in this first release.
Multiple via objects are not supported for Copy Circuit or Move Circuit with any angle
rotations; only 45 or 90 degree increments are supported.
Multiple via objects are not supported in CES. An ASCII file format is used to specify
multiple via object assignment rules.
Expedition PCB (DFL Mode) (Destination PCB) does not support multiple via objects.
MultiPlow does not support multiple via objects.
Differential Pairs does not support multiple via objects.
Multiple via objects capability is not supported in the Cell Editor.
Reusable Blocks does not support multiple via objects.
Editing multiple via objects. A multiple via object is always selected as an entire object.
There is no way to select or query an individual single via while it is part of the multiple
via object unless you use the Dissolve MVO command that converts multiple via object
into a collection of individual vias and conductive shapes.

ASCII File Format

The following is an example of the ASCII file format used to specify multiple via object
assignment rules. Once this file has been defined the rules are loaded into AutoActive upon
launch. The file is located in the job's ../xe/config directory.
MVO Rules file name: MultiViaRules.txt

MVO Rules file location: ../xe/config
MVO Rules file format: mimics the NetClassDB.hkp format
.FILETYPE MULTIVIA_RULES
.VERSION "03.02"
.CREATOR "Mentor Graphics Corporation"
.DATE <date and time file was created>
.UNITS TH
.PHYSICAL_LAYERS <n>
The value must match the physical layer count defined in the design.
.MVO_RULE_SET "(Default)"
The value can be "(Default)" or a user-defined rule set name; example "My_MVO_Rule".
..VIASPAN
Via span definition for this MVO rule set.
...LAYER_NUM_RANGE (<n>,<n>)
The value is the via-span range i.e. “(1,8)” that the MVO is based upon as defined in
Setup
Parameters>Via Definitions tab.
...PADSTACK "(Default Via)"
Via padstack for this span; “(Default Via)” means use via span defined in Job Preferences
...MVO_RULE
MVOrule defined for the via span.
....WIDTH_EQUAL_OR_GREATER <n>
The value is a trace width as per the defined units. The MVO rule applies to the trace
widths equal or greater than the defined value.
....VIA_COUNT <n>
The value is the number of vias required to build the MVO for the given trace width
range.
.NET_CLASS_SCHEME "(Master)"
The value is “(Master)”, “(Minimum)” net class scheme or user rule scheme name as
defined in CES.
..NET_CLASS "(Default)"
The value is “(Default)”, or available net class name that uses the following MVO rule set.
...USE_MVO_RULE_SET "(Default)"
The value is “(Default)” for default MVO definition or user defined MVO rule set name,
example; “My_MVO_Rule”.

Example File
.FILETYPE MULTIVIA_RULES
.VERSION "03.02"
.CREATOR "Mentor Graphics Corporation"
.DATE "Wednesday, April 27, 2005 04:33 PM"
.UNITS TH
.PHYSICAL_LAYERS 4
.MVO_RULE_SET "MyMvoRuleSet"
..VIASPAN
...LAYER_NUM_RANGE (1,2)
...MVO_RULE
....WIDTH_EQUAL_OR_GREATER 0.150
....VIA_COUNT 2
...MVO_RULE
....VIA_COUNT 3
..VIASPAN
...MVO_RULE
....VIA_COUNT 2
...MVO_RULE
....VIA_COUNT 3
...MVO_RULE
....VIA_COUNT 4
.MVO_RULE_SET "MvoRulesForPowerGroundNets"
..VIASPAN
...MVO_RULE
....VIA_COUNT 3
...MVO_RULE
....VIA_COUNT 4
...MVO_RULE
....VIA_COUNT 6

.NET_CLASS_SCHEME "(Master)"
..NET_CLASS "(Default)"
...USE_MVO_RULE_SET "MyMvoRuleSet"
.NET_CLASS_SCHEME "MyScheme"
..NET_CLASS "FREEsym402-3"
...USE_MVO_RULE_SET "MvoRulesForPowerGroundNets"
..NET_CLASS "TRUEsym1634"
Hug Traces
This command provides you with the ability to select an un-routed net and have it hug an
existing routed trace or specified draw objects in the design. The net to be hugged can be an
entire net routed between two pins or a portion of a routed net. The un-routed net will route
adjacent using the Trace to Trace clearance and typical trace widths defined in Net Classes and
Clearances to the routed net, including curves, bends, angles and other trace anomalies.
Specifying a Hug clearance

When hugging draw items you can specify a hug clearance other than is defined for the net by
using the htc keyin and specifying a clearance. All htc entries are listed in the right mouse click
pop-up menu for quick selection.
Note
The htc keyin and the hugging of draw objects are only available with a valid Flex
license.
Hug trace will only operate on continuous trace segments, which have no junctions, vias or pins
within the segments being hugged. The following criteria prevents traces from routing using the
hug trace command:
Traces which include vias in the selected span.

Traces which include T-junctions in the selected span.
Trace segments that include pins, testpoints, or any other objects making connections
within the selected span.
Hug trace will automatically push and shove vias/traces of nets which are in the way of the trace
being hugged. However hug trace will not alter the trace that is being hugged. If a segment is
selected with this criteria, an error message appears in the far right message field.

When in the command you can change the clearance by selecting them from the popup that
displays when you right-mouse click. The default clearance is named Variable. Values are only
stored for the current design session. When the design is exited the input values will be
discarded.
Hug trace portions

In the event a portion of a trace is selected to hug based on a selection of a start or end point on
the trace itself, a netline will appear from the hug trace endpoints to the un-routed pin locations.
This will only occur only if the "Netlines from Traces" checkbox is selected within the Display
Control dialog. If this option is not checked, the trace will hang in space with no netline. When
trace hangers are placed by Hug Trace, these traces will be automatically semi-fixed to ensure
that when they are connected using plow they are not glossed, causing the hugged trace to no
longer hug the target trace.
Glossing Principles
The focus of these glossing principles is to clearly define the behavior while Gloss is off and the
behavior of semi-fixed traces. The original purpose of Gloss was to automatically clean-up
traces so they were the shortest possible length and to eliminate undesirable geometries such as
acute angles, undesirable pad entries, extra segments and self-net oddities. Over time we found
that modifications were needed so designers could add and edit traces in specific user-
determined locations without Gloss (or Push & Shove) affecting them. This is especially
desirable when crafting RF circuits or adding or editing meanders to control the delay of a path.
There are multiple Gloss modes and multiple Fix states for traces. The combination of the
modes and states allow for a very flexible environment where the designer can control every
vertex or rely completely on automatic glossing.
Gloss Modes
Gloss On – A full Gloss is applied to any trace (and net) added, edited or shoved.
Gloss Partial – A mild glossing is applied to the currently added trace.
Gloss Off – The currently edited or added trace is not glossed.
Fix States (Via behavior is not mentioned here but it is the same as traces)
Unfixed – Trace may be modified by any interactive or automatic means.
Semi-Fixed – Trace may be modified interactively, but not by any automatic routines.
Fixed – Trace may not be modified by any interactive or automatic means. Fixed traces
may become unfixed by using Unfixed.
Locked – Trace may not be modified by any interactive or automatic means, not even
Unfix. Locked traces may become unfixed by using Unlock.

Note
Some routines have options to “Apply to Fixed and Locked Traces” but you must choose
that option.
Guiding Principles
1. If Gloss mode is off, nothing is glossed or shoved.
This does not count for Auto Route because it ignores Gloss modes.
2. If a trace segment is semi-fixed, automatic modifications are not applied.
Includes all Gloss modes.
Includes Auto Route.
3. If a trace is semi-fixed, any editing, in all Gloss modes, keeps the trace semi-fixed.
If while modifying the semi-fixed trace, a new segment is added, it is added as semi-
fixed in all gloss modes.
If a path has an unfixed trace segment attached to a semi-fixed trace, any modification to
the unfixed trace does not change the state of the semi-fixed trace.
4. If Gloss mode is partial, only the trace segments added from the previous click are to be
partially glossed.
There are some situations where rules 3 and 4 may not apply, but for the majority of scenarios,
the functionality works as stated.
Glossing Possibilities
This table defines what is allowed and not allowed during the different glossing modes.
Table 3-2. Glossing Possibilities

Gloss On Gloss Partial Gloss Off
Move Trace Possible?
Unfixed Segment Yes Yes Yes
Semi-Fixed Segment Yes Yes Yes
Fixed Segment No No No
Locked Segment No No No
Shove Trace Possible?
Unfixed Segment Yes Yes No
Semi-Fixed Segment No No No


Trace Added Becomes…
AutoActive Unfixed Unfixed Semi-Fixed
Interactive Unfixed Unfixed Semi-Fixed
Trace Added to Semi-Fixed Trace Becomes…
AutoActive Unfixed Unfixed Semi-Fixed
Interactive Unfixed Unfixed Semi-Fixed
Join Traces Segments Possible?
Unfixed & Unfixed Yes Yes Yes
Unfixed & Semi-Fixed No No No
Unfixed & Fixed No No No
Unfixed & Locked No No No
Delete Trace Possible?
Gloss Trace Possible?
Tune Possible?
Copy Trace Possible?

Semi-Automatic Routing

Fixed Segment Yes Yes Yes
ReRoute Possible?
Push Trace Possible?
Copy Circuit Possible?
Locked Segment Yes Yes Yes
Move Circuit Possible?
Locked Segment Yes Yes Yes
Semi-Automatic routing is made up of commands that allow you to fanout pins, route individual
traces, and multiple traces. The routing of individual traces is done using the plow command.
The plow command is broken up into Forced Plow, Route Plow and Angle Plow.
By default, the Plow commands use Gloss on all of its completed traces. Gloss changes the
entry into rectangular and round pads and gets rid of excessive bends in traces. The idea behind
this algorithm is to allow the router more room for routing. If a channel can be left open by a
slightly different exit, the push and shove routing algorithm has less work to do and the system
works faster. If you need to put a trace into the design, using a special pattern or a user-defined

trace, the Gloss mode must be toggled off. Gloss does have different settings that define how far
back on a trace gloss will operate.
If you are leaving hangers intentionally, do not use the Remove Hanger command. Use the right
mouse button to exit the Plow command and leave the hanger. The Plow command can delete
hangers on other nets. If you intend to keep the hangers, they must be fixed before re-entering
the Plow command.
You can now select anywhere on the netline in order to start plowing as opposed to only being
able to select on the pin.
You can use the Tab key to change the destination pin of the current plow if you choose a
netline for a MST ordered net and there are multiple pins of the same net.
The F8 action key (Switch End) allows you to switch to the other end of the selected netline
when plowing.
Clicking the right mouse button in graphics displays a popup menu which allows you to change
widths and via sizes.
If you are routing a trace and you want to rip up existing trace segments and try again, this can
be accomplished in the following ways:
Use the Undo command to remove the last trace segment or via.
Use the Delete command to remove the whole trace path.
Select a point on the path to remove everything between the current point and the
selected point.
These methods work for all plow modes.
Curved Traces
The ability to create concentric arc's using curved traces is only available within the route
environment while in Angle or Forced Plow. Within Multi-Plow curved traces only have
variable or flexible radius’. The F10 action key allows you to toggle the traces around a
common center point while in Plow mode.
You can set the radius of the curves in the Editor Control General Tab for Angle or Forced
Plow. Any defined radius specified in Editor Control is overridden while in Multi-Plow.
The radius of the curves can then be selected when using the command from the popup that
displays with a mouse right-click. If "Variable" is selected, the methodology reverts back to a
defined curve using the cursor. Values are only stored for the current design session. When the
design is exited the input values are discarded.

Once placed, curved traces can be modified. By selecting and holding the center of the arc, you
can dynamove the arc, which changes the radius.
As the cursor is moved, the dynamic curve exactly represents the actual trace, as if the current
cursor point location was the selected anchor point. If an anchor point is selected in a location
where clearance violations will occur, the push and shove algorithm is called to relocate the
violating elements.
You can also use the Route - Modify Corners command and convert the selected (or all) curved
traces to orthogonal corners.
Example for routing curved traces

1. Select Multi-Plow, Angle Plow or Forced Plow and start routing a trace.
2. Place an anchor point (optional, curved traces can start from a pad or via).
3. Select the F10 action key to curve the trace.
4. Stretch the trace to the desired location and select another anchor point.
Upon placing an anchor point the curved trace is placed and the route remains in curve
trace mode until you either select Toggle Curve (F10) or terminate the route.
Moving Trace Segments with Arcs

Single trace segments connected to arcs on both ends may be moved. The arcs remain the same
and the vertical traces extend to compensate for the movement of the trace segment.
Curve trace end point rules

Curve traces can end on:
Pins/pads (Avoid creating acute angles)

Trace endpoints
Via
In space (creating a hanger)
When the second point is selected (creating the arc) you can either continue placing curved
traces or toggle back to regular plow mode. Selecting cancel from the right mouse button pop-
up menu, or selecting the ESC key will cancel the curve trace command. Selecting ESC will
deselect the net being routed and return you to Plow mode.

Curve center point modification

The center of the curved trace can be selected for modification. The center modification point
works as arc modification does in Draw mode. The radius changes force the trace connection
points to adjust while the arc is being modified.
Cases and exceptions

Curve traces may be started from any trace point, pad or via, and at any angle including
existing curved traces.
Curve trace is only selectable from a trace endpoint or pad (sensitized / desensitized)
T-junctions or virtual pins are not legitimate sites for curved trace.
Curved traces stay tangent (while in dynamics) to the selected trace.
In order to maintain pad entry rules, the arc is not allowed to intersect the pad geometry.
If it is not avoidable, a corner rather than an arc is produced.
The minimum radius for a selected trace is radius > 2X the trace width. If a specified
radius is to small to allow proper placement of a curved trace an error message displays
in the Status bar.
Forced Plow
This is the default state when you select the Plow command. When in Forced Plow mode, the
prospective trace displays as a hockey stick and flows around any obstacles or pads as anchor
points are placed. As the trace flows around obstacles, Gloss will automatically cleanup any
jags that are created.
As you move the cursor over a pad or an existing trace or via, you will notice that a temporary
netline has appeared from the cursor position to the closest point on that net. There is one
exception: if you have defined the netlines as being custom or chained, you are only able to
route in the order defined by the netlines.
As you move the cursor around the screen, you will notice the hockey stick dynamically
changing shape and following the cursor. If you now click the mouse button, Expedition PCB
attempts to place a trace that corresponds to the hockey stick from the starting point to this new
location called the anchor point. An anchor point is the transitioning point between a trace
segment(s) that has been plowed and the next trace segment(s) to be plowed. This point is
typically a vertex on the trace.
This operation does not use vias to make the connection, but if the hockey stick goes over pads
or mounting holes you will notice that the trace added to the design has gone around those
items. You can now continue to the next anchor point or finishing point. If desired, the trace can
be left as a hanger.

Dyna-Plow
The Dyna-Plow command is similar to Forced-Plow except that you are continually laying
traces into your design when using Dyna-Plow. To use the Dyna-Plow command, activate the
Plow command and drag the left mouse button. You will notice that the hockey stick has now
turned from a ghost trace to a solid trace. As you move the cursor, the trace is automatically
added to the design. Once the mouse button is released, that position becomes the new anchor
point.
As you route over obstacles, the trace attempts to bend around them. If the trace cannot route
around these obstacles, the Plow command restores to the last known good position. If an
existing trace or via becomes an obstacle, Expedition PCB attempts to push that trace or via out
of the way. Remember the Plow command cannot move fixed items. As with any PCB design,
the level of pushing that can be accomplished depends on the amount of free space in the
design.
Route Plow
You can change from the default mode, Forced Plow, by activating the Toggle Plow Mode
action key. This puts you in Route Plow mode. The system tries to automatically route from the
starting point (or last anchor point) to the new anchor point (or finishing point on a pad, via or
trace). This command is governed by the settings in the Editor Control menus. This method of
routing traces is the only Plow command that automatically uses vias during the Plow
procedure.
After you have plowed the trace and are close to the target pad, or are through a difficult area,
you can finish the trace by adding the last anchor point on a part pad, trace or via. The trace
being plowed automatically attaches to that point and you are now ready to begin the next plow
trace. You can also use the Auto Finish action key. The Plow command automatically routes to
the closest point on the net being routed. This can be a trace segment, via or another part pad.
Angle Plow
You can change from the default mode, Forced Plow, by activating the Toggle Plow Mode
action key. This puts you in Angle Plow mode.
When in Angle-Plow mode, the prospective trace displays as a Route-Plow netline and is routed
from the last anchor point or start point to the target location.
If you click in the target point, the Angle-Plow command tries to route to that point (called the
plow-anchor point). If there are any violations or it is unable to reach that target point, the trace
is not displayed.
In Angle-Plow mode, a via is added to the last anchor point or near the last anchor point if it
does not match the via grid. If you accidentally added a via, use the Undo command to delete it
and change back to the old layer.

Multi-Plow
Multi-Plow is the default Plow command and allows you to select multiple interconnects and
route them simultaneously. The display in Plow is very similar to the display in Forced Plow
and Dyna-Plow. The prospective traces display as “ghost traces” in these commands, but since
the Multi-Plow command is dealing with multiple traces, a reference line accompanies the
prospective traces.
The reference line operates as a guide or baseline for the Plow command. As you route using
Plow, it changes position to that area within your group that is driving placement. Occasionally
the Plow command is unable to place the reference line, because it cannot determine the drive
position. In this situation, the prospective traces disappear and a box surrounds this area of
ambiguity.
If you have a valid Flex license, you can use the curved traces functionality within Multi-Plow.
Curved traces are variable or flexible radius only. The defined trace clearance, or selected
convergence affects the radius for each trace selected. Any defined radius specified in Editor
Control is overridden while in Plow. See Curved Traces for further information.
Plow curved traces only have variable or flexible radius’. The defined trace clearance, or
selected convergence affects the radius for each trace selected.
Any defined radius specified in Editor Control is overridden while in multi-plow

All traces start at the same bisector (start point across a horizontal line for instance) and
end at the same bisector (vertical line for instance)
Each trace has a different radius but start and stop along the same line
Traces start and stop around a common center point
Selection is the same as with single curve trace selection
Once placed, curved traces can be modified. By selecting and holding the center of the arc, you
can dynamove the arc, which changes the radius. As the cursor is moved, the dynamic curve
exactly represents the actual trace, as if the current cursor point location was the selected anchor
point. If an anchor point is selected in a location where clearance violations will occur, the push
and shove algorithm is called to relocate the violating elements.
You can also use the Route - Modify Corners command and convert the selected (or all) curved
traces to orthogonal corners.
1. Select Plow and start routing.

2. Select curved traces (F10).
3. Traces curve from the last point placed and curve around a common center point.

4. Select an end point.
Figure 3-24. Curved Trace in Multi-Plow
Upon placing an anchor point the curved trace is placed and the route remains in curve trace
mode until you either select Toggle Curve (F10) or terminate the route. The following example
shows a curved trace extending from an existing curved trace.
Figure 3-25. Curved Trace Extending from a Curved Trace
Since the Plow command works with multiple traces, via patterns are used to add vias to your
design. As with all other Plow commands vias are added at the last anchor point and the vias are
dropped through to the paired layer, but instead of a single via, multiple vias are placed in the
design in either a parallel, staggered or diagonal pattern. Click the right mouse button in
graphics to display a popup menu that allows you to change via sizes.
Via Patterns
The actual via pattern varies as you move your cursor. One dynamic pattern is illustrated in the
following sequence:
1. Display the via pattern, then drag the cursor to the right; the pattern changes.
2. Continue dragging. The resulting pattern is a flipped version of the starting pattern.

Figure 3-26. Via Patterns Examples
Press the Toggle Via function key to access other patterns that can also be dynamically
modified by cursor movement. An example of one pattern is shown below:
<Alt> Auto-Finish Preview

When you are getting close to your target pins while in Plow, you can hold down the Alt key to
get a ghosted image of what the Plow path would be if you completed the path. The following
pictures show the normal Plow graphic.
Figure 3-27. Auto Finish Examples

Leaving the cursor in the same position and pressing the Alt key results in:
Hold the Alt key down while you move your cursor. This gives you control of the pattern that
Alt Auto-Finish will create. Notice in the following picture that the pattern has changed as the
cursor has been moved to the left.
When you see the pattern you want, click the left mouse button. The connection will be made in
the pattern seen in Preview mode.
New via patterns and modification commands are available to help you quickly determine the
via placement option that best fits the design situation. The use of quick keys enables you to
quickly preview and determine what effect the different via pattern will have on the design. The
Alt - Auto Shift feature gives you greater control over the final topology of a multi-plowed
connector.

Route
Route
Route allows you to automatically route selected connection(s) using the parameters set up in
the Editor Control > General tab. The route command should not be confused with the Auto
Router. It is intended to be used for semi-automatic routing of critical nets. Typically this
command can be used to route easy, straightforward connections between pins or to create
routing, that can be adjusted manually.
If you want to:

Learn about handling planes Information on page 161
Learn about changing layers and adding vias Information on page 162
Planes Handling
Traces may be routed on layers reserved for planes. To route a net on a plane layer, disable any
net class restrictions for that layer and enable the layer, for routing, in Editor Control. Plane
shapes on a signal layer can be placed as obstruct areas and cannot be routed through. This is an
option when placing the shape.
Netlines are generated between pins and plane shapes to remind you of the connection. If there
are no plane shapes, unconnected pins in plane nets are signified by a large 'X' through the pin.
Nets with plane layers or plane shapes defined can only be designated as Free ordered.
When a plane net pin is fanned out, a via is dropped to the plane's layer using the shortest
possible via. If the layer is defined as a plane, the connection is considered complete. If the
target is a plane shape and the via does not land within the shape, the fanout via is left for a
routing pass to complete.
To perform calculations of the velocity of propagation (Vp) and characteristic impedance (Z0)
of a trace, at least one plane layer must be defined. Calculations may be performed on traces on
plane layers. Violations created by trace and via intersections with different-net planes can be
cleared upon exit.
Fanout
For SMD parts, fanouts with vias need to be created to allow connections to other layers. While
the router can place vias to complete connections, it is best to place all fanouts initially to assure
that preceding routes don't block future fanouts. Fanouts can be completed by this command, by
Auto Route, or by purely interactive routing of a trace and via.
By adjusting the via grid, you will get different fanout result. Start with the via grid
recommended by your manufacturing vendor and if this causes poor route completion, due to
blocked channels, consider the acceptability of a larger via grid or routing without a via grid.

Route
For signal nets, the fanout command uses the shortest via possible to reach the closest valid
signal layer (as defined in Net Classes and Clearances and Editor Control > Pad Entry).
For plane nets, Fanout uses the shortest via possible to reach the plane layer. Since planes do not
always cover the entire layer, a connection is complete only if a via is placed inside the plane. In
those instances where the via is left dangling, it must be connected to the plane during the
routing process. If an SMD pad is inside a plane shape of the same net, it is considered
connected.
Even when the connection is made during the fanout operation, you can later push the via and/or
trace, either manually or automatically, and maintain the connection.
Interactively, BGAs may be fanned out in a user-defined pattern, however, using the Fanout
command as well as Auto Route, BGAs are fanned out using the courtyard pattern.
Changing the Active Layers and Adding Vias

As you route using any of the Plow commands, a circle surrounds the trace at its last anchor
point if it is a valid via site. The following methods can be used to add a via and change layers
and are identical for the Forced Plow, Multi-Plow, Route Plow, Dyna-Plow and Angle Plow
commands. Exceptions regarding Multi-Plow are noted. Only those vias defined in the Setup
Parameters - Via Spans Definitions section are used. The active layer changes to its paired
(alternate) layer, and the graphics package automatically brings the new active layer to the top
of the display. (The active layer’s paired layer is defined in the Editor Control menu.)
Vias can be dropped under SMD pads based on the Editor Control via under pad settings. As
you plow out of an SMD pad, you can plow within the pad itself to a location where you want to
place the via and at this location, you can use any of the methods of changing layers to place the
via.
Adding Vias with the Add Via Action Key (Multi-Plow only)
Once you have completed a trace to an anchor point, you can add a via with the Add Via action
key, this will display the vias in a ghost image, allowing you to change the toggle via mode or
place another anchor point.
You can use the popup menu (accessed by clicking the right mouse button) to change the width
and name of the next via to be used on selected layers.
Adding Vias With the Space Bar

Once you have completed a trace to an anchor point, you can add a via by pressing the space
bar.
You can use the popup menu (accessed by clicking the right mouse button) to change the width,
layer and name of the next via.

Route
Adding Vias Using the Display Control Menu

If the Display Control menu is active, note that the active layer is always highlighted, when you
add a via it automatically changes to the active layer’s paired layer. This way you can track your
location in the design layer stack.
Activate the Display Control Layers dialog (if it is not already active), and after plowing to the
desired location in your design you can add a via by clicking on the destination layer in the
Display Control Layers dialog. You can also use the Up and Down arrow keys to select the
destination layer.
The layer highlights, and a via is added to the current anchor point. If the system can not add a
via, the active layer resorts back to the last used layer. If you are in a very complex area, it is not
always possible to add vias because of blockages by traces or other vias. Using this method
proves more successful when finishing a complex design.
Adding Vias with the arrow keys

Once you have completed a trace to an anchor point, you can add a via by pressing the up or
down arrow keys. The arrow keys scroll you through the available routing layers.
Adding Vias by Double-Clicking (All Plow commands except

Multi-Plow)
Once you have completed a trace to an anchor point, you can add a via by double-clicking.
Note
In order to add vias by double-clicking, you must have the double-click to add via option
in Editor Control's General menu turned on.
Blind and Buried Vias

If you are working with blind and buried vias, the shortest via that reaches from the current
layer to the target layer is used.
Note
To move a blind or buried via: select the via and any routing layer within the via span
except the part pad's layer and drag your cursor to activate the Move command. Once the
selected via is positioned correctly, release your mouse button.

Interconnect Modification
In all cases, the via is added at the closest via grid point to the current anchor point.
Staggered Vias (Forced Plow commands only)

Within Plow, after you have placed an anchor point, pressing the Shift key and right mouse
button, displays a popup menu listing target layers. This popup allows you to pick the layer on
which to place the staggered via. If a layer has "Restricted" next to it but is selectable, this is
because routing has been not allowed in the Net Classes and Clearances dialog for that net class.
Figure 3-28. Plow Popup
If a layer is selected as disabled for routing in Editor Control, that layer is grayed out on the
staggered via dialog and shows “Restricted”.
If a plane layer is defined on a layer and you select that layer from the popup, staggered vias are
only added to the nearest layer and you are automatically cancelled out of plow.
Expedition PCB offers a variety of editing commands to aid you in those situations where you
must complete a complex board that does not route to 100% or attempt an engineering change
order.
If you want to:

Learn about buses Information on page 165
Learn about target areas Information on page 168
Learn about copying traces Information on page 174
Learn about changing a trace width Information on page 175
Learn about the reroute command Information on page 175
Learn about removing hangers Information on page 175

Working with Buses

In the context of PCB layout, a bus is a grouping of nets (not pin pairs because they are grouped
by net name) with a bus name as defined in CES or the schematic. Typically the nets in a bus
have a common net name prefix and a sequentially numbered suffix, although you may choose
to combine a set of nets in a bus simply because they are to be routed using the bus path and bus
router methodology.
The bus path physically represents the width of the traces and their clearances and any shielding
traces and their clearances. You can change the bus packing to be different from the setting for
the overall bus per bus segment. While the bus path dialog is open, you can select the
Recalculation (F4) button to change the bus path segments widths to represent the actual
number of netlines associated to the bus path segment.
The bus path is the designated locations for a bus’ traces to be routed. Bus path supports
branching and splitting of the bus. Depending on the setting for bus packing, the path is
followed with packed or unpacked trace packing. Graphically, the line displays P for packed
bus path segments and U for unpacked path segments. Bus paths also include the identification
of a shielding net and the number of shielding traces.
As a bus is selected, the component pins and netlines (if displayed) of that bus are highlighted
for the placed components. You can then select the desired layer and draw horizontal, vertical
or 45 degree increment lines.
The bus router routes groups of nets together without layer bias with the intent of emulating
manual routing techniques.
The packing density of traces and vias in a bus path segment up to component pin convergence
points. There are two levels of packing:
Packed (1): Bus traces stay together as much as possible and the minimum trace to trace
and trace to vias clearance is used throughout the bus.
Unpacked (2): Ignore bus packing, minimum trace to trace clearances between bus
traces are not preferred, however, layer assignments (non-bias routing) are followed
along with bus path. This applies to all defined buses which do not have a defined bus
path.
These values are assigned to specific bus path segments with a default value of Packed per bus
path segment. In the bus path dialog, the value can be changed from packed to unpacked as
segments are placed or selected. Additionally, through a design setup variable, the default value
can be changed to unpacked.
Two hazards are generated if required; Review Hazards > Online > Bus Netline Span and Bus
Spacing.

Recalculation
Recalculation can be run when the Bus Path dialog is displayed by selecting the Recalculation
(F4) action key. If a bus path segment is selected, recalculation adjusts the width of all the
selected segments. If no bus paths are selected and the Bus Path dialog is displayed,
recalculation occurs on all buses.
Tip: The Recalculation button on the Review Hazards > Online Bus Hazards dialogs,
works exactly the same as the Recalculation (F4) action key.
There are other actions in the design process, beside bus path placement that may require
recalculation to run against all bus path segments in order to present accurate bus path segment
widths.
Pin/Gate Swaps
Netlist Changes
Components moved or rotated
Bus Routing and Bus Online Hazards are dependent on accurate bus path segment widths.
Therefore, as netlines are calculated, bus width recalculation will run if bus path segments are
present in the database and the Bus Path dialog is not displayed.
Bus Routing
The Auto Route Bus pass takes the bus path and turns them into flowing bus traces. Buses
without bus paths are routed with existing route passes like Route. Apart from Tune, other route
passes ignore buses with defined bus paths.
The Bus Route will follow any defined bus paths with the following capabilities:
Maintaining the notion of a bus so that interactive and automatic modification of the
nets in a bus have knowledge of the bus rules.
Routing with the defined rules for the bus, such as clearance and width rules, via rules,
layer rules, and appropriate rules related to signal integrity.
Routing without layer bias.
Intelligent fanout with or without vias which untwists netlines and fanout from
component pins in the direction of the bus in order to minimize via usage and length of
traces connecting to the bus.
Warning: Due to the complexity of PCB buses, we cannot guarantee 100% completion of bus
routing all the time: sometimes the bus path will go through areas that are too confined; there
may be conflicting bus paths or there will be insufficient room for the vias to be added.

Bus Routing Rules

1. Bus route pass only applies to nets associated to a bus through CES.
2. Bus route pass only applies to buses with defined bus paths.
3. Bus route supports partial and fragmented bus paths.
4. Buses without bus paths are routed with other Auto Route passes.
5. Bus route pass follows a defined bus path where possible.
6. Bus route pass follows the layers indicated by the bus path.
7. Bus route pass follows bus packing option specified per bus and bus path segment.
8. If specified, bus shielding traces are routed with packed bus path segments. The
shielding traces are not routed to component pins with the same net or planes.
9. Shielding traces will be positioned with markers and not removed as hangers.
10. Shielding trace widths and clearances can be different than bus trace widths and
clearances.
11. If the bus path pass cannot follow the layers indicated by the bus path, it will use layer
rules defined for the net.
12. Bus route uses the same routing algorithm for packed and unpacked bus path segments.
13. Packed bus path segments can only be Auto Routed with the Bus Route pass.
14. Unpacked bus path segments can only be Auto Routed with the pass Bus Route and
Tune.
15. Glossing for packed bus path segments is always Mild.
16. All glossing levels are available for unpacked bus path segments.
17. Bus route pass ignores layer bias.
18. Bus route supports bus via preferences input during bus path creation.
19. Bus route will NOT support routing to end points of pre-routed bus traces.
20. For Push and Shove performed from other Auto Route passes, individual bus and bus
path segment with a packed setting will treat the related traces as a unit. Nets of the bus
are moved together, this includes any associated bus shielding.
Routing Steps for Bus Route

Without dictating which order of steps to follow, the Auto Route Bus Route pass performs the
following steps:

Target Area Placement and Routing
1. Optimized fanout/pin escape is in direction of the bus to untwist netlines to the bus paths
segments. This synchronizes the order of the bus path.
2. Transform bus paths to routed traces on layers specified by the bus path and occurs for
the entire bus path. The bus packing options are used and applied per bus path segment.
At this point, nets are assigned to the traces. If bus shielding traces are specified, they
are also transformed, however, they have a net assigned to the trace.
3. Followed by the connection of component pins to the bus path traces. Shielding traces
are not routed to component pins, nor planes.
4. Next, buses are routed without layer bias and between component pin to component pin
for each identified bus.
During the route, existing, unlocked/unfixed traces may exist. The bus route respects the bus
packing per bus path segment and will apply push and shove capabilities to achieve its desired
routing.
Bus Tune
The bus tuning occurs after bus setup, bus planning (optional), and the Auto Route Bus Route
pass (optional) or interactive bus routes. The routing of buses can occur with or without defined
bus paths and if the bus was routed with Auto Route, Bus Route pass or interactively routed.

There are two ways of working with route targets; at the macro-level, with target areas or the
micro-level with individual or groups of route targets. The Display Control dialog > Layer Tab
options are used to control the display of route targets and target areas.
Four hazards are available; Review Hazards > Online > Target Area > Route Targets, Target
Areas and Straight Line Interconnects. Review Hazards > Summary > Straight Line
Interconnects Summary.
Note
Target Areas and Route Targets can only be used on regular nets defined as MST
topology. Any topology change can cause loss of target areas and route targets.
As not all signals are buses, there will be a percentage of signals known as general nets that are
routed after the bus route and must fit with the bus routes. Therefore, target area planning and
routing from component pins to route targets should be applied after bus planning is done on a
PCB design. General nets are those remaining nets when buses, critical nets and power and
ground nets are excluded.

The level of required detail varies with the designer’s experience with AutoActive and the level
of control the designer wishes to implement with the placement of route targets. While placing
or manipulating target areas, the designer can reveal the level of display and control.
The display characteristics of target areas and route targets are the same as pad layers. The
required connection from a component pin to route target is a Straight Line Interconnect (SLI)
that shares the display characteristics of its associated target area. Meanwhile the netline has the
global option of spanning from the route target.
With the Auto Route pass Straight Line Interconnects within the Items to Route option to
include Target Areas, the router connects component pins to route targets. The router considers
the route target for each individual via/route and attempts to use the minimal vias to get from
component pin to route target. If this is not possible, then it attempts to get as close as possible,
yet stay within the target area. If a via is inserted for the route target it reaches the specified
target layer. Otherwise, the endpoint of a trace is routed to the target layer for the route target.
Route targets are automatically re-located to match the route results.
Guidelines
The relationship of the following objects: component pin, SLI, route target, target areas and
netlines are as follows:
A component pin can support zero to n route targets providing it has an associated
netname.
The connectivity between a component pin and route target is shown as an SLI.
A route target is always associated to a target area.
A target area is associated to a single trace layer.
A target area can be associated with one to many route targets.
The area of the target area is where trace endpoints or vias are placed for associated
route targets.
Target Area size can be created in one of three ways:
Automatically sized to fit all route targets (default).
Input of maximum deviation distance.
Grab side and extend or contract.
Target areas can have stacked route targets (before auto routing), either
automatically optimized or interactively arranged.
The Display Control option > Netlines From Route Targets shows the netlines span
from the route targets, instead of from the component pads.

Supported Functionality
There are five sets of functionality required to support Target Areas:
Component pin(s) selection.

Specify target layer selection.
Optionally, specify maximum deviation distance for target area.
Target area/route target placement.
Auto Route pass > Straight Line Interconnects within the Items to Route includes target
areas: routing from component pins to route targets.
Unsupported Functionality for Target Areas

The following are unsupported for target areas:
Target Areas are not stored or placed with Reusable Blocks, however, they are stored in
the main PCB database.
Move Circuit does not include the Target Areas.
The Route (F2) action key in route mode.
Target Areas in the PCB Design Flow

Component placement should be complete.
Bus planning should be complete before target areas are placed for general nets.
Critical nets may be complete.
Power and ground signals may be complete.
Bus routing may be completed before route targets are placed.
Place target areas or individual route targets with Target Layer.
With Auto Route pass > Bus Route complete, run the Auto Route pass Straight Line
Interconnects within the Items to Route option to include target areas to connect
component pins to route targets.
For route targets to route targets (same net) connections, the existing Route pass is used.

Target Area Route and Auto Routing

While in Route Mode and without the Target Area dialog displayed, you can create a select set
of target areas or select an individual target area. You can also use the Edit > Select > Target
Areas, to select all target areas. The selection set is only useful for Auto Routing.
Unless the Route > Target Areas dialog is displayed, the Delete option or any other command
will not apply to target areas. In Route mode, you can select one or more target areas and click
the right mouse button to display a popup. When you select Route Targets from this popup, the
Target Areas dialog displays.
Straight Line Interconnects Auto Route Pass

The Straight Line Interconnect pass offers at least two options for the Items to Route; All Nets
option: Nets will be SLIs (default) and Selected Target Areas. The only way to Auto Route
SLIs, is by using this pass.
For the lower efforts, the priority is to insert vias into target areas, higher efforts allow trace
endpoints. In all cases, the object is to represent a via or trace endpoint at the target layer within
the constraints of the target area.
Note
Routing within the Target Area is an absolute rule.
The Straight Line Interconnect pass embraces layer specific routing by incorporate the Enable
Layer options and the Editor Control > Routes > Vias > Max length on restricted layers >
External/Internal specifics.
When SLIs are routed, they assume a non-layer bias and use few vias and minimize trace length
to route from component pins to route target. They insert a via or trace endpoint on the target
layer within the area of the associated target area. The lower efforts use vias, the higher efforts
accept trace end-points.
The first effort of the pass attempts to route from component pin, your placed route target or
optimized route target placement. Once the route target connection is located with a via or trace
endpoint, the route target is relocated to show that point.
If layer restrictions are applied and do not include the target layer, a via is dropped from the
enabled layer (with minimum via span applied) to the target area. If the netclass and via span
require a staggered via pattern from enabled layer to target layer, the Auto Route Straight Line
Interconnect pass inserts that pattern to the target area.

All other Auto Route Passes

All other Auto Route passes target the route target, if their SLI is routed. It can be routed by the
Auto Route or interactively, but it must be completed from component pin to target area before
other Auto Route passes can connect from other component pins or other Target Areas to the
route target.
Example
The SLI connection has the highest priority, if this is not connected, then the other side of the
route target should not be completed. When it is connected, any Route pass option may work on
the Netline from Route Target to other component pins or other Route Target.
Also, advance passes and effort that employ Rip-up and Retry avoid target areas. While passes
that employ Push and Shove may have access to trace and vias in target areas, providing the
route target vias are not pushed outside of the target area.
Removing Unwanted SLI Route Results

1. Display the Target Area dialog.
2. Select a Route Target (or selection set for several) and click the right mouse button. The
pop-up displays the option of Select SLI traces and vias.
3. Select the option. All associated traces and vias from component pin to Target Area
become selected.
4. Select Delete. Using this methodology it is easy to apply other functions to the selected
set; such as Lock or Fix.
Interactive Moving of Routed/Partially Routed Target

Areas
There may be cases where a fully or partially routed target area needs to be moved.
1. Display the Target Area dialog.

2. Select the Target Area.
3. Select the Move (F2) action key. Similar to moving a routed component, the SLIs that
were connected when the Move started are Re-Routed as the target area is placed in its
new location.
Unrouted Route Targets respect the setting in the Route Target Placement option of the
Target Area dialog which determines whether their placement is optimized.

Input and Formula Parameters for Automatic Calculation

of Target Areas
The following formula details are provided to calculate the size of target areas and placement of
route targets:
Most used netclass The net class associated with the majority of the route
targets of a target area.
Via2Via Clearance The Most used netclass maximum default via to via
clearance on the layer of a target area.
ViaTraceFat The maximum of the Via2Via Clearance and the space
required to place a single trace of typical width for the
Most used netclass between the two vias.
Via2xTraceFat The maximum of the Via2Via Clearance and the space
required to place two traces of typical width for the Most
used netclass between the two vias.
Via3xTraceFat The maximum of the Via2Via Clearance and the space
required to place three traces of typical width for the
Most used netclass between the two vias.
PadDiameter The Most used netclass maximum default pad diameter
on the layer of a target area .
NumOfRouteTargets The number of route targets, which equals the number of
SLIs associated with a target area.
RouteTargetGridSize The distance between the centers of two route targets.
ViaTraceFatThreshold The threshold of the number of route targets, defining if
ViaTraceFat is included in RouteTargetGridSize
calculation. The environment variable
MGC_TARGETAREA_MIN_THRESHOLD provides
such input. If it is not set, 4 is used as the default value.
Via2xTraceFatThreshold The threshold of the number of route targets, defining if
Via2xTraceFat is included in RouteTargetGridSize
calculation. The environment variable
MGC_TARGETAREA_MAX_THRESHOLD provides
such input. If it is not set, 16 is used as the default value.
Automatic Placement
The placement of route targets is determined by the number of route targets and their associated
target area. Target area is displayed as an octagon.
If NumOfRouteTargets <= ViaTraceFatThreshold,

RouteTargetGridSize =PadDiameter + Via2Via Clearance;

If NumOfRouteTargets > ViaTraceFatThreshold and NumOfRouteTargets <=
Via2xTraceFatThreshold,
RouteTargetGridSize = PadDiameter + ViaTraceFat ;
If NumOfRouteTargets > Via2xTraceFatThreshold,
RouteTargetGridSize = PadDiameter + Via2xTraceFat.
The maximum space between the octagon of target area and route targets area is Via3xTraceFat.
SLI crossovers are reduced to the minimum under a given time constraint; under which
condition each route target is placed to be close to its associated component pin.
Route targets are placed to match the via grid.
Copy Trace / Fanout
The Copy Trace command allows you to route sections of the design that contain similar
patterns. You can select a trace and copy it to complete another connection. This requires the
new trace to be placed so its endpoints are on pins of the same net. This command is useful for
routing memory nets that have the same pattern.
The copied trace can also be pushed to any layer by using the F5 action key. This command is
useful for routing memory nets which have the same pattern.
Copy Trace does not take net class rules into account. If a copied net has default, netclass rules
that are different from the destination pins, the copied net's rules are used. Vias are
added/removed where necessary.
Using Copy Trace to fanout microvias

We recommend using a combination of manual fanout and Copy Trace to accomplish any
specialized fanout patterns. The same rules are followed to determine if the traces and vias can
be added legally and the snap to center feature is applied.
1. Add the required vias and traces. They can be any valid combination of vias, traces and
layers.
2. Use Frame Select to select the traces and vias which define the fanout and choose Copy
Trace. The ghosted fanout pattern is attached to the cursor.
3. Frame select the pads where you want the fanouts applied. When you release the left
mouse button, the fanouts appear attached properly to the pins. Once in Copy Trace
mode, you can rotate the fanout patterns by typing them into the keyin field.

r90 or r180, etc.
After the rotation is applied, you can then frame select and add to pins which are at a different
orientation.
Changing a Trace Width

The Change width and “cw <width>” keyin can be used to change the width of selected traces,
either single segments or multiple segments. You can change the width of one or more trace
segments, but only if that change does not create a design-rule violation. If the new width
creates a violation for any segment, the change is not applied to that segment. However, other
segment widths can change. If selected segments cannot be changed a warning dialog is
displayed.
Any violations of the Net Classes and Clearances dialog’s default width settings are flagged.
These settings are used to automatically and interactively route your traces. Minimum /
maximum width violations are not checked.
Reroute
The Reroute command allows you to reroute selected connections when they do not meet your
standards. It can be very useful when working in tight areas and you need to reduce the number
of bends and vias.
Instead of deleting the traces and vias that define the interconnect and routing the netline a
second time, select the existing connection and reroute. The connection is routed; using the
algorithm and effort you specify in the Editor Control and glossed.
Note
Reroute removes tuned nets and differential pair routing. Once nets are tuned and or
routed differentially, they should be fixed to preserve their placement.
Remove Hanger
The Remove Hanger command allows you to remove traces and vias that do not terminate at
pins.
Fanout traces and vias, if not connected to a plane, are considered a hanger, and this command
deletes them if they are part of the selected items. A fixed hanger is not removed until it has
been unfixed. Fanouts for plane nets are also unaffected.

Using the Auto Router
Replace Cell
Replace Cell allows you to choose whether the selected parts are Replaced (default) or Reset in
the design. After planes have been generated any changes that may move pins or vias may result
in the plane data not aligning with the pins. In this case the planes must be regenerated. Changes
include: moving a part, via or mounting hole and replacing or resetting a cell.
If a reference designator was inadvertently removed, the Silkscreen Generator will not generate
data for them; therefore they will be missing in Gerber. Using this command in Reset Mode,
you can add the missing reference designator text.
Using the Auto Router

The Auto Router is a shape-based router and interconnect editor, providing both semi-automatic
and batch routing capabilities. It can push aside routed traces and vias and work in a gridded or
gridless environment. The clearances, high-speed rules and design rules that you define control
the routing process.
Even though no clearance violations are created, you can determine the relative health of your
design by tracking hazards created during manual and automatic routing. The graphical
commands allow you to zoom into and scroll through these problem areas and assess if a change
in placement is in order.
If you want to:

Learn about layer stackup Information on page 176
Learn about the technology setup Information on page 177
Layer Stackup
The properties of the materials used for a board must be defined to enable calculation of signal
integrity attributes such as characteristic impedance, trace delay and crosstalk. The stackup
consists of conductive and dielectric materials used to make up the design's layer structure. A
stackup is initially constructed using the defined signal and plane layers. A layer of dielectric is
placed above and below every conductive layer (the outer dielectrics serve as solder masks). If
there are no solder masks on the design, set the dielectric constant of the outer dielectrics to one.
The thickness and dielectric constant may be defined for dielectric layers. The thickness and
resistivity may be defined for conductive layers.
The velocity of propagation (Vp) and characteristic impedance (Z0) may be calculated for a
defined trace width on any layer of the board. Future calculations of Vp and Z0 for other signal
integrity attributes may be overridden by constructing a table of Vp and Z0 values for layer /
width combinations.

Routing Process Flow
Technology Setup
To calculate crosstalk, the rise time and voltage swing of the aggressor net's driver must be
defined. A core set of technologies is supplied with the product, giving common values for rise
time and voltage swing. A driver's technology is determined using the 'tech' field in the part.
Technologies not found in the existing list are added automatically. If a net does not have a
driver, the Default Technology values are used.
When calculating crosstalk, if there is more than one driver on a net, the smallest rise time and
largest voltage swing are used.

While the routing of a design can proceed in any order, there are common steps that are
typically followed.
If you want to:

Learn about fanout vias Information on page 177
Learn about routing critical nets Information on page 178
Learn about moving parts Information on page 182
Learn about running the Auto Router Information on page 182
Learn about dynamic teardrops and breakout traces Information on page 183
Learn about the finishing remaining opens Information on page 183
Learn about reviewing the design Information on page 183
Learn about clean-up for manufacturing Information on page 184
Learn about modifying corners Information on page 184
Fanout Vias
For SMD parts, fanouts with vias need to be created to allow connections to other layers. While
the router can place vias to complete connections, it is best to place all fanouts initially to assure
that preceding routes don't block future fanouts. Fanouts can be completed by the Auto Router,
by the Fanout command, or by purely interactive routing of a trace and via. Different fanout
results, can be achieved by adjusting the via grid. Start with the via grid recommended by your
manufacturing vendor. If this causes poor route completion due to blocked channels, consider
the acceptability of a larger via grid or routing without a via grid.
Attempts to route pin to pin connections on a single layer without additional vias being added
by planning during Effort 1, which determines how the connections can be distributed between
routing layers. The No Via/Bias pass does all of it's distribution calculations during Effort 1.

Without Effort 1 being run, the router will not plan the distribution of connections resulting in a
drop in the number of connections that are made.
Because a bias will not be used, both horizontal and vertical route channels can be easily
blocked by this pass. This pass should be used in circumstances where vias are not required for
critical nets like differential pairs which need to be routed on a specific layer and back plane
designs which have a lot of routing room and layers to route on.
The No Via/Bias pass replaces the normal Route pass in the situations described above. When
used to route critical nets, it should be limited to the layers you on which you want the bias rules
to be ignored. Any nets routed using this pass should be fully fanned out before the pass is run.
Fanout Cover Layers

By using the Editor Control dialog in conjunction with the Auto Router, you can quickly fanout
the cover layer of your design.
1. Open the Editor Control - Costs dialog and enable routing only on your design’s cover
layers.
2. Open the Auto Route dialog.
3. Turn off all routing options except Fanout.
4. Select All Nets from the Route choice box.
5. Set Fanout to start effort 1 and end effort 3 and select Route.
Routing Critical Nets

After fanout, route your critical nets. Critical nets are defined as any net whose performance
must be managed to achieve a working design. These nets should be routed first, while space is
available to achieve the optimum tuning. If you have defined rules for these nets, they can be
auto routed and the rules are adhered to. You can also manually route them using the Plow
command.
If exact vertex placement is important, you should turn glossing off to avoid unwanted topology
modifications. Net groups can be interactively tuned using Tune after the nets are completely
routed. See Auto Routing Critical Nets Example for further information.
At this stage the ordering of pins can be changed (using Netline Order) without worrying about
existing route blockages. If exact route locations are critical, the routes should be fixed to avoid
minor modifications while routing other signals. See the Auto Routing Critical Nets Example
for further information.
Prior to initializing the Auto Router, all of your parts should be placed, but if you are
experimenting with a critical or complex layout problem it is possible to place and route only

those parts. Change the route border to surround these parts to constrain stray routes (remember
to return the border to its correct position after placing the rest of the parts).
Using this procedure, a design can be partially placed and routed by sections, and after the last
part is placed the Auto Router can be used to connect the remaining connections. Traces can be
left as dangling traces and used to route sections to sections.
Auto Routing Critical Nets Example

There are two types of critical nets; those handled in the Tuning pass and those handled in the
Route pass. Tuned nets include matched net groups and nets with pin to pin delay formulas.
Critical nets handled in the routing pass include nets with maximum length / delay constraints.
To route tuned nets:
1. Display the Auto Route dialog.

2. Add three passes
3. Set the route types to Fanout, Route and Tune, and set the appropriate start and end
efforts.
4. Turn off all other options.
5. Select Route.
The Auto Router automatically fixes those nets that are routed in accordance with their delay
formula. If any segment of the net does not meet the constraints of the nets delay formula; the
Auto Router does not fix the net.
To route nets with maximum length / delay constraints, you must first use a selection method
that is recognized by the Auto Router.
To route nets with maximum length / delay constraints:
1. Use the Net Class dialog to define your nets with maximum length / delay constraints as
members of a specific net class.
2. Use the Editor Control - Filter dialog to move this net class to the Included list and all
other nets to the Excluded list.
4. Select the Filter option from the Route choice box.
5. Turn on the Route option and set the appropriate start and end efforts. Fanouts for all
nets should be completed prior to routing nets with maximum length / delay constraints
to avoid cutting off pad exits.

7. Select Route.
Auto Routing Specific Nets

If there are nets in your design that have specific routing requirements and you need to route
them separately, the following strategy allows you to define and auto route these nets.
1. Use the Net Class dialog to define these specific nets as members of a selected net class.
2. Use the Editor Control - Filter dialog to move the critical net class to the Included list
and all other nets to the Excluded list.
4. Select the Filtered Nets option from the items to Route choice box.
5. Turn on the Fanout and Route options, and set the appropriate start and end efforts.
7. Select Route.
Routing with Fences

The Auto Route Fences pass definition allows you to select the name of the defined fences (hard
or soft) to be used for each pass type. This restricts auto routing and all auto route sub-modules
that automatically route traces; Tune, Fanout, Route & Re-Route to a user-defined area (route
fence) of a board for a sub-set of the total board connectivity (Local Routing). It also provides
for the appropriate behavior of such areas with regard to Global Routing.
After creating fences ( Draw Properties > Route Fence) you can specify the fill color for hard
and soft fences on the Display Control > General Tab under Board Items. There are two types of
Route Fences:
Hard - The perimeter (edge) of a hard fence cannot be crossed when auto-routing.
Soft - The perimeter (edge) of a soft fence can be crossed but only when auto-routing to,
or from, a connection object located inside the fence area.
The Polygon, Rectangle or Circle are the only valid draw objects that can be placed as a route
fences. You can select the polygon, rectangle or circle option from the Draw toolbar which
displays automatically. The Properties dialog changes to reflect the chosen drawing option.
Hard Fences
When a Hard Fence is specified in the "Fences" option of an Auto Route pass, all routing occurs
only within the specified hard fence, subject to the selected Items to Route filter and layers. No

other routing occurs outside the active hard fence, (all other fences outside the hard fence - hard
and soft - are ignored). However, soft fences that are defined inside the active hard fence are
routed.
For the specified Hard Fence, only pins, traces, vias and thermal connections located inside
route fences are candidates for auto-route. If their nets have connections outside the fence, those
outside connection points are excluded. Traces & vias are contained within the fence area but
edges may touch the fence polygon edges. The "Items to Route" filter is applied to the
candidates as well as the allowed layers. External partial routing treats route fences as a route
obstruct if not allowed entry. Internal partial routing is allowed between two pins inside the hard
fence.
The following figures show the connection candidacy and results of routing when a hard fence
is specified. The route fence is in red, legal netline candidates for auto-routing are in green,
traces are in blue and netlines, not candidates for auto-routing, are in yellow.
Figure 3-29. Route Fence Candidates
Soft Fences
Soft fences define areas wherein routing may begin or end. Pins, traces, vias and thermal
connections located within this area are candidates for auto-route. If their nets have connections
outside the fence, those outside connection points are also candidates. For specified soft fences,
traces & vias may escape the area to complete routes to connections located outside the route
fence. The "Items to Route" filter is applied to the candidates.
Note
Spread, Via Min, and Smooth Auto Route passes do not respect soft fences. Via Min does
not treat a soft fence as a route obstruct when routed.
Routing outside a soft fence are subject to push & shove when routing inside soft fences.
Overlapping fences are treated as individual fences - they do not merge. Common connection
points are controlled by the first fence definition found for the connection, then picked up by the
next if the previous fence fails to connect. External partial routing treats encountered route
fences as a route obstruct if not allowed entry. Internal partial routing is allowed between two
pins inside the soft fence.

Auto Route Fences Pass Definition

The following figures show the connection candidacy and results of routing, when the Fences
option is selected for each soft fence defined on the board. The route fence is in red, legal
netline candidates for auto-routing are in green, traces are in blue and netlines, not candidates
for auto-routing, are in yellow.
Figure 3-30. Soft Fence Candidates
Auto Route Board Pass Definition

The following figures show the connection candidacy and results of routing, when the "Board"
option is selected for each soft fence defined on the board.
Move Parts
During the design process, it is normal to move/push parts. Once your critical nets are routed,
you may need to create additional space for your parts due to noise or heat problems. There are
numerous options available in Expedition PCB to move parts; Move Part, Push Part, Pushback
Part, move parts with the keyboard arrow keys and move parts by file.
Run the Auto Router

Once your critical nets are routed, the Auto Router should be used to route the majority of the
connections on the design.

You can graphically review the connections while they are made to determine if they are
routing as desired. For many connections, the Auto Route command is preferred over the Route
command because Auto Route can be set up for multiple effort levels and algorithms. The
Route command only routes a single algorithm and effort level.
Using the Editor Control - General tab, you can disable routing on your design’s cover layers
and enable routing on the design’s inner layers.

2. Turn on Memory, Route, Tuning (if necessary), Via Min and Finishing.
3. Set the appropriate start and end efforts.
4. Once a route is complete, the Auto Router does not continue with extraneous effort
requests. If the Auto Router is unable to complete route, and you have set the effort to
the maximum for that pass, the Auto Router spends considerable time trying to place a
route that could be better placed interactively.
5. Ensure that select All Nets is still selected in the Route choice box and select Route.
Dynamic Teardrops and Breakout Traces

Interactive teardrop placement (dynamic teardrops) allows you to place a single teardrop on a
selected pad. If you are folding no-connects, or you have a pad on which the automatic teardrop
command could not place a teardrop because it would cause violations, you can route or modify
the trace and place a teardrop on the connecting pad.
Interactive breakout traces placement (dynamic breakout traces) provides the ability to place a
single breakout trace on a selected pad. If for any reason a breakout trace could not be created
for either a pin/trace or via/trace combination, the pin/trace or via/trace combination is
highlighted once the command has finished execution. In that case, you can edit all the
highlighted pads on the board then go back into the Breakout Traces dialog and manually enter
the width and length settings for the selected pads.
Finish Remaining Opens

If the router did not finish 100% of the connections, the remaining opens have to be completed
manually. The Plow, Move and Reroute commands are primarily used in this mode. If
connections are impossible to complete, you have to modify part placement, the board outline,
or the number of layers to achieve completion.
Review Design
While the routing stages are constrained to your rules, you should always confirm that none of
the rules have been induced by temporary rule overrides. The Review Hazards command can be
used to find Online DRC errors in the design, and locate them on the display. The Hazards

Clean-Up for Manufacturing
dialog is updated dynamically, so you can instantly see the effects of efforts to fix the online
hazards. You can also cross probe the corresponding schematic to identify related symbols and
signals.
The Cross Probe Select command allows you to select any item or group of items and have the
corresponding item or group of items highlighted in the one of the design’s attached schematic
entry tools.
Clean-Up for Manufacturing

Once all connections have been made, the design should be run through a manufacturing pass to
clean up excess vias, and smooth out the routes. This can be accomplished using either the last
two passes of Auto Route, Gloss or Reroute.
The Smooth pass of the Auto Router uses the advanced glossing features that can be setup in the
Gloss Tab of Editor Control. The Breakout Traces command may be executed at this point to
reduce the number of pad/trace breaks during the hole drilling process. Teardrops also can be
generated at this point. If your board has high-speed signals that require rounded traces, Modify
Corners can be run to convert angled corners to rounded corners.
Modify Corners
If your application requires the use of rounded corners, use the Modify Corners command to
change the trace corners from angles to arcs. You should only arc your corners once your board
is routed to 100%. Arced corners are not maintained when parts and or traces are moved or
rerouted.
If you intend to modify corners that are fixed, locked, or both, you must select the Include
Fixed and Locked Corners check box
You can enter the same value for minimum radius and maximum radius to specify an exact
radius for all arcs, added to your design.
Reviewing the Design

It is wise to check the status of your design. The following utilities and commands not only
allow you to check the state of your entire design but also specific elements within the design.
If you want to:

Learn about design status Information on page 185
Learn about signal integrity attributes Information on page 185
Learn about hazards Information on page 185

Reviewing the Design
If you want to:

Learn about generating reports Information on page 185
Design Status
The Design Status command generates an ASCII file that provides information relative to your
entire design. The information gathered includes data about the board size, layers, nets, netlines
and placement information.
Signal Integrity Attributes

To calculate the velocity of propagation and the characteristic impedance of a trace on the
board, select a segment of trace. The Background Field Solver uses the trace layer, width and
the materials stackup to determine these values. If a Layer Stackup/Options table is defined for
a given layer, the Vp and Z0 values for that layer are used as the override when the trace
segment is selected.
Hazards
Whenever the status of the design changes, Review Hazards Online should be reviewed to
ensure your high-speed rules have not been violated and all of your connections have been
made.
The hazards are not affected by the status of the Optional Net Rules in Route tab of the Editor
Control. This allows you to temporarily disable a rule without losing track of any violations
caused in that mode. The graphic options (Select/Highlight/Fit) are useful for identifying
problem nets and acting on them.
Once your design is routed, Batch DRC should be run to verify the clearances within your
design, the connectivity of your design and whether your design meets your manufacturing
needs. Review Hazards Batch can be used to review and fix any hazards found by Batch DRC.
Once you have fixed any of these hazards, Batch DRC must be re-run to ensure no hazards
where created while making changes to your design.
Generating Reports
The Report Writer offers a unique, window-based interface for generating user-defined reports -
from a simple default report to a comprehensive user-defined matrix, detail or summary report.
The Report Writer gives you simple, direct ways to view and work with the information
collected.
Several report definition sample files are delivered with this product. These example files can
be edited and be used as the basis for your own reports using a third party product called Crystal

High Speed and Critical Nets
Reports. Crystal Reports is a powerful, yet easy to use program for creating custom reports, list
and form letters using data extracted from your existing databases.

The Auto Router controls all high speed/critical nets with rules defined in Net Classes and
Clearances, Net Properties and Editor Control. This way you can avoid multiple iterations of
layout and checking passes to see if the design conforms to your rules. There are times when
you want to override a rule, and that capability is provided. Because this may introduce design
inconsistencies, the hazard checker always lists the violations.
If you want to:

Review general comments on high speed nets Information on page 186
Learn about pin ordering control Information on page 186
Learn about impedance control Information on page 187
Learn about length / delay control Information on page 187
Learn about group length control Information on page 187
Learn about differential routing Information on page 190
Learn about crosstalk control Information on page 191
General Comments on High Speed Nets

When working with critical signals that need to be routed first and then fixed, you can use the
Auto Router to give you a good starting point. Because the design is empty, the Auto Router
achieves the routes with a minimum of trace length. The router also has the ability to tune the
nets during routing or when all routing is accomplished using a special tuning algorithm.
Remember to fanout all SMD pads before placing the critical signals. It is important that all
SMD pads have access to the inner layers. If there is a large number of critical nets to route,
these can easily block valuable via placement points.
If pins on a custom or chained order net are placed closer than the stub length apart, it is
possible that the router does not follow the specified connection order. This is most likely to
happen between the last load and the terminator because of their proximity.
Pin Ordering Control

You may define the order in which a net’s pins are connected by setting the net to either custom
or chained. If a net is chained, algorithms are used to order the net as efficiently as possible. If
the net is custom, a user-defined pin ordering is used. Any ordering may be manually modified
using the Netline Order command. The net’s type may also be altered in this way.

Since the advent of SMD technology, getting into and out of padstacks in a true custom
topology has become difficult. Previously, with through-hole parts, every layer was a valid I/O
point, but with SMD parts that is no longer true. With the fine pitched devices now in use, it has
become harder to fanout all the pins. If a true custom topology net were required, every pad that
was in the custom topology would require 2 fanout vias rather than just one. Because of this
limitation, the stub length net property allows you to specify the amount of “shared” trace that
can be used when attempting to route these connections.
Impedance Control
Its thickness and width, its distance to plane layer(s), and the surrounding dielectric material
(e.g. dielectric constant) determine the impedance of a trace. These properties can be defined
and evaluated in the Layer Stackup.
To control impedance along a net, you can define trace widths for each layer of the design. This
is accomplished in Net Classes and Clearances by defining the width for a layer and calculating
the impedance, or vise-versa. You can also restrict routing to specific layers. The impedance of
a selected trace segment is displayed in the command window. Plane layers must be defined
within your layer stackup in order for Expedition PCB to calculate impedances.
Length / Delay Control

In high-speed design, it is often necessary to fix the length boundaries that a signal can route
within to achieve critical timing for a signal. Because clock rates are increasing and the
propagation delays of gates are falling there is a critical time when an expected signal must
appear at a pin. To achieve this, signals are given a maximum delay, expressed in length or
time. If a signal has this restriction (set in the Net Properties dialog), these settings are respected
and routing is only allowed within that boundary. Maximum delays are applied to the net’s
electrical length (calculated as the total net length divided by the velocity of propagation (Vp)).
The interactive routing commands use a tuning ellipse to guide you to the correct length.
The Tuning Ellipse displays differently for 45 degree routing and 90 degree routing. When in 45
degree routing, the Tuning Ellipse displays as an oval or ellipse. When in 90 degree routing, the
Tuning Ellipse displays as an octagonal shape.
To constrain specific from - to’s, use delay formulas defined in the Net Properties dialog. These
formulas can be used to match delays between sets of pins, or to define relationships between a
set of pins.
Group Length Control

In high-speed design, it is often necessary to have a group of signals within a delay or length
tolerance to each other. This is to achieve critical timing for that group of signals and the ability
for the “on” state for all those signals to arrive at the same time at their destination (usually
found in data buss signals). To achieve this, the Auto Router automatically tunes these nets.

Because of the critical nature of these nets, they are usually routed first and then fixed in
position.
The automatic tuning feature is invoked as soon as the last connection of the group of signals is
made. Checks to find the longest signal of the group and then attempts to match (to within the
tolerance set up in Net Properties) the rest of the signals to that length. If a modified net is in a
matched length group and it is pushed outside the tolerance, the system automatically tries to re-
match the rest of the signals to the new length. When there is a large number of signals in a
matched length group, this procedure can take a long time.
When working with a matched length group, it is recommended that you find the signal in the
group with the longest Manhattan length and route that first using the shortest distance possible.
This helps eliminate unwanted trace length.
Note
If an unusual amount of trace length appears with matched length groups, it is normally
associated with a group of signals that have a rogue net(s). If there are 32 signals in a
matched length group and 31 of these are approximately 5 inches long and one is 12
inches long, 7 inches of trace length per signal multiplied by 31 signals are attempted to
be added. This would need 217 inches more trace length than was really needed. Be sure
to check placement and matched hazards.
The Tune command can also be used to tune matched length groups. This command only makes
nets longer to match rules. The situations in which it works are:
1. When delay formulas on a net are not within tolerance.

2. When the difference in net lengths in a matched length group exceed the defined
tolerance.
In the case of matched length nets, the selected net is not necessarily the one that is modified.
All nets are modified to match the longest net in the group. The longest net in the group is
determined once the nets have been rerouted to their shortest possible length.
The Router reroutes an item based on the rules in the Editor Control - Tuning tab. If the rules
cannot be satisfied, any improvements toward the rules are kept.
This command does not make a net shorter because there are so few ways to violate the
Manhattan Length rule. A net can be too long because:
Its Manhattan Length is greater than the Maximum Length rule.

The Maximum Delays and Lengths rule was turned off.
The design rules of a net, or group of nets were changed after routing was completed.

Pin Package Length

Creating a text file (PinPkgLengths.txt) and putting it into the ../config directory, you can define
a length value on a per-pin/per part basis that will be added to the trace length when checking
the length of the signal against the length rule. If any errors occur, a log file
"PinPkgLengthLog.txt" is created in the ../LogFiles directory that can be viewed using File
Viewer.
Whenever there is a check to determine if the trace length matches any length rule (below), the
PinPkgLength value associated with the pins on the signal is added to the length of the trace
data.
Any formula (Total Excess Length in both top and bottom lists, Numerical Formula and
Computer Formulas)
Min/max length (Excess and Routed),
Match length (Length and Delta)
Plow tuning ellipse
Hazards
The calculation of actual trace length now includes the PinPkgLengths.
If the sum of the actual trace length plus the total of the PinPkgLength is within the tolerance of
the length rule, there is no hazard.
If the sum of the actual trace length plus the total of the PinPkgLength is outside the tolerance of
the length rule, there is a hazard.
This means that can adjust the trace length until the hazard disappears. The hazard shows by
how much the sum of the trace length plus the PinPkgLength is outside of the tolerance. Since
the PinPkgLength is a constant, you can adjust the trace length by that amount.
Routines affected
Tune (interactive and automatic) whenever it is used, including AutoTune.
Hazards
Routines not affected

Everything but Tune (and routines that apply tune) and Hazards.
All trace length reports - Whenever a trace length is reported it will still be a trace length
and will not include the PinPkgLength.

Format of PinPkgLengths.txt file

UNITS <value>
PART_NUMBER <part_number>space delimiter
<pin_number> <value> Pin Number, not Pin Name. Space delimiter
UNITS must be the first line of the file or an error will be reported.
If the pin number or part number has a space in it, it is assumed that all non trivial characters
past PART_NUMBER are part of the name and that the <pin_number> is the first part of the
line up until the last numeric value.)
Notes
1. If the unit of the PinPkgLength is different from the unit of the rule in the design, the
PinPkgLength is converted.
2. The following checks are done. These errors are reported in a log file
"PinPkgLengthLog.txt", available in the ../LogFiles directory.
More than one assignment of same pin - ignore second and subsequent same pin
assignments
Unrecognized keyword - ignore line
Missing required arguments - ignore line
3. The following may occur but is ignored:
Missing part pin numbers: not all part pins require assignment.
Part Number not in design: allows use of archived file.
4. Valid values for units are Thousandths or th, Microns or um, Millimeters or mm, and
Inches or ins. These entries are case insensitive.
Differential Pair Routing

The characteristics of two signals can be matched by classifying them as a differential pair. This
is common when two nets, one carrying a signal and the other carrying its inverse, are active
simultaneously and are expected to cancel each other out. To achieve this, these nets are routed
with adjacent traces, paired vias and matching lengths.
Differential pairs are defined in the Net Properties - Timing and Differential Pairs tab, and can
be routed by any of the following Expedition PCB commands: Route, Forced Plow, Route
Plow, Multi - Plow and Auto Route.
Trace to trace clearances for differential pairs is set in the Net Class - Clearances dialog. This
value defines the distance between the two nets that comprise a differential pair. It is not a
clearance value between differential pairs and other nets.

Post Processing
If a differential pair net is to be tuned, route one of the nets using a large meander and once the
net is routed, fix it and route the unrouted portion of the differential pair using the appropriate
routing command.
Routing differential pairs with mismatched node counts

If you have differential pairs with mis-matched terminations, (one branch may have five nodes
and the other branch only has four because there may be a capacitor or other termination resistor
attached), set up the route passes as follows:
In the Auto Route dialog, run a fanout pass before the route pass, the differential pairs are
routed. Interactively, if you select the F2 action key first and then the F8 action key, the nets
will route completely.
Crosstalk Control
Coupling between two parallel signals in the form of capacitance and inductance generates
noise known as crosstalk. Unfortunately, the same techniques that reduce delays in signals, such
as increasing dielectric thickness, also increase the coupling capacitance between those signals,
thereby increasing crosstalk effects.
You may define hazard conditions for crosstalk and parallelism in Net Properties. These
guidelines do not constrain the router, but are used to check for violations shown in hazards.
Crosstalk can be reduced by: Shortening parallel segments; Increasing the clearance between
parallel segments; Separate the parallel segments with a plane; Increasing the driver rise times
and / or reducing the line impedances (i.e. increase dielectric constants, increase trace widths
and thickness, reduce trace-to-ground thickness, or increase trace clearances).
Post Processing
Once the design has been placed and routed, it should be prepared for the manufacturing and
documentation processes. The Post Processing steps prepare the design by modifying reference
designators, preparing Gerber photoplot output, CAM files and final documentation.
If you want to:

Learn about test points Information on page 192
Learn about the Padstack Editor Information on page 194
Learn about Migrating Plane Data Information on page 197
Learn about Plane Assignments Information on page 197
Learn about the Planes Processor Information on page 194
Learn about design verification Information on page 200

Post Processing
If you want to:

Learn about running Batch DRC Information on page 200
Learn about running Batch DFF Information on page 201
Learn about renumbering reference designators Information on page 203
Learn about modifying text with the Draw tool Information on page 204
Learn about generating silkscreen Information on page 204
Learn about NC Drill Information on page 205
Learn about Gerber 274X Information on page 209
Learn about Gerber 274D Information on page 210
Learn about general interfaces Information on page 211
Learn about plotting Information on page 214
Test Points
Designs that are tested using an automatic test system require that test points be added and
assigned to the nets to be tested.
The test points must be created in the Cell Editor with a cell type of Test Point.
Test Points must be placed in accordance with the test systems that the design connects to.
Some test systems only test one side of the design; others test both the top and bottom sides
together. Using a test system that requires all test points to be on one side may result in extra
vias having to be placed manually in order for all required nets to be accessible.
Test systems require that all test points be a specified distance apart and usually on a predefined
grid pattern. If your design must meet this criterion, that fact must be taken into account during
the routing phase. If vias are not routed to the grid needed for test point assignment, it may be
difficult to arrange the vias to meet the grid requirements afterward. Depending on testing
needs, varying numbers of test points may be required for each net. For example, signal nets
may only require a single test point, but power and ground nets may need to be tested at several
different points on the design.
To place all test points on a design, use the Automatic Test Point Assignment command. This
command uses the following test point definitions defined in Setup Parameters, cell name, ref.
des prefix, test side, grid, and use closed polygon assembly outlines as test point obstructs. Test
points may also be placed one at time interactively using the Place Test Point command. This
command allows the test point to be attached to connections either by designating an existing
via, through hole or trace.

Post Processing
When placing test points, use the Fix commands within the Auto Assign Test Points Menu. This
helps prevent the test points from being moved or deleted in subsequent revisions of a design,
which could result in having to create a new test fixture.
When a design is edited and traces are connected in a different configuration, there are
occasions when the assigned net for a test point may differ from the new net it is connected to.
The Assign Net Name command allows you to change the netname on floating test points.
Within the Automatic Test Point Assignment menu is the Test Point Report generator. The
reports generated apply to all test points regardless of how they were placed. The Test Summary
report (testptsum##.txt) is the data that should be used to prepare the test fixture and program
the test system. It contains information used for drilling the test fixture and programming the
test equipment.
The net name to which the test point is connected

Test point reference designator, if used
The XY location of the test point
Test point location type (part pin, via or trace)
Side of the design where the test point is located
Many companies find it useful to know the difference between the test point data from one
revision of the design to the next. The ECO Report shows that test points were added, which test
points were deleted and which test points changed from when Expedition PCB was invoked.
The ECO report (testpteco.txt) should only be executed when all test points changes have been
completed and the design is ready for archive. Once the ECO Report has been run, the old
report is removed and replaced with the new report.
Place Test Points from File

Test points can be placed using the testptlog_nn.txt files. These files reside in the
<design_dir>/pcb/ LogFiles directory. To display this option, the following environment
variable is required:
MGC_TESTPOINT_READOUT
Delete Unused Test Points

Unused test points can be deleted from the selected net using the Edit > Delete Unused Test
Points command.

Post Processing
Padstack Processor
The Padstack Processor performs operations on the padstacks in the design. Padstack
definitions are layer specific, therefore if you change a padstack on an SMD part and then push
that part from the top to the bottom layer or visa versa, the padstack used is one within the
padstack database. Thermal and clearance pads are not listed in this dialog. Changes to these
pads must be done with the Planes Generator. The operations are:
Changing Pads by layer – This allows you to increase of decrease the pad size or shape to
meet electrical or manufacturing needs.
Deleting Pads by layer – This allows you to remove pads of internal layers that are not
connected by a trace or plane data.
Changing Padstacks – This allows you to change the entire padstack shape to meet electrical
or manufacturing needs.
Resetting Padstacks – This allows you to reset padstacks back to their original library
definition.
Since these operations can invalidate the pads and holes assigned to a part, care should be given
not to make changes that effect the manufacturability of the design. Also, changes to the pads
may create clearance violations. Batch DRC should be run after the Padstack Processor has
altered the design.
Plane Classes and Parameters

The Plane Classes and Parameters is used at the point in the design process when part placement
and routing is complete and is used to generate plane data within a design. Plane data is an area
of metal that may or may not be connected to a specified net. Plane data may possibly be used to
aid heat dissipation, provide an even distribution of current, or to act as a shield for sensitive
signals. Existing plane data is deleted when new plane data is created. Plane data can also be
deleted from the design using the Delete Plane Data command. See Discard Plane Areas for
more information.
When you are ready to process planes, a dialog appears showing the elapsed time. You can
select the Cancel button on this "wait" dialog if the process is taking too long.
A plane may be a signal plane, which is one that has an associated net, or a shielding plane,
which has no associated net. For plane data to be generated for specific areas, a plane shape
must exist. The Plane Clearances and Parameters allow the option to use either user defined
plane shapes or the route border as the plane extents. Planes that use the route border as their
shape must be defined within Setup Parameters before the routing stage.

Post Processing
The clearance used between objects like pads/traces and plane metal is the larger of the Net
Class and Clearances Trace to Pad clearance and the Other Object (Minimum) defined in the
Planes Processor dialog.
When generating negative planes flashed anti-pads the Plane Clearances and Parameters will
use any round pad that has been defined in the design’s padstack database based on the
clearance pad this is required. However, if the design has been setup to generate 274-D Gerber
for manufacturing based on the Gerber Machine Format file defined for the designs attached
Gerber Plot Setup file, it will use only the route D-Code sizes that are defined within the D-
Code Mapping file assigned to each specific plane layer.
If a D-Code of the correct size can not be found, then the Plane Clearances and Parameters will
draw the clearance pad instead of flash. If the design is defined to use 274-X as the Gerber
generation mode or no mode has been defined, then the Planes Processor will use any round pad
that has been defined in the designs Padstack database based on the clearance pad this is
required.
Plane Clearances and Parameters also allows the creation of negative planes. Negative data
generation produces plane data that represents the clearances for the plane. This type of plane
data represents the places where metal does not exist. For plane artwork, the negative of the
plotted image is used to represent the plane metal.
Positive plane data may be added to an area as a solid shape, or may be generated in several
crosshatched patterns. Using the crosshatch patterns allows the plane data to be generated based
on hatch width and distance or by assigning a percentage of total plane coverage.
Both positive and negative planes allow the creation of Split Planes. To determine the plane
generation method, positive or negative, you must weigh the advantages/disadvantages of each.
The following table allows you to determine which plane method is best for you.
Table 3-3. Advantages/Disadvantages of Positive and Negative Planes

Positive Planes Negative Planes
Pro Con Pro Con
Allows hatch Large Gerber files for Smaller Gerber Files Hard to view data, is
patterns layers which are 50% or not WYSIWYG
more plane data
WYSIWYG Good for planes which Small conductive
cover 50% or more of areas create large
the layer Gerber files
Good for small Creates smaller design
conductive areas files
Allows for snapping Thermals can be
of plane elements flashed during Gerber
generation

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Split Planes
A split plane is a plane layer that has been divided into at least two different non-connected
plane areas. Each of these plane areas is used for a different signal. To create a split plane, place
plane shapes for each of the nets required. This should be done in a highlight mode to verify that
all points of the net are within the boundaries of the plane shape.
When Plane Clearances and Parameters is run, it connects only the nets of the particular plane
shape, providing clearances for all other nets. If the Split Plane shapes overlap each other, the
plane shapes priority will be used to determine how plane shapes cut into each other. Higher
priority plane shapes will cut into lower priority plane shapes when the plane metal is generated.
Discard Plane Areas

There are two options within the Plane Classes and Parameters menu that allows you to remove
pieces of plane data. These options are “All Untied Areas” and “Any Areas Less Than”.
The “All Untied Areas” option removes any plane areas that are isolated and do not connect to
the rest of the plane because of plane clearance, hatch width, and other factors. With this
parameter you can eliminate these unconnected portions. The All Untied Areas option has a
sub-option, “Areas tied to a single pad”, that allows areas tied to a single pad to be discarded.
Since these areas are not used to connect multiple pins, they can be removed automatically.
The “Any Areas Less Than” option allows you to define a minimum linear area that should be
removed from the plane net being generated. This option also removes small areas of plane
metal that could cause slivers of conductive metal.
Delete Plane Data or Actual Plane Shapes

The Delete Plane Data command allows you to delete plane data and actual plane shapes from
the board. There are two options of removing plane data from your design:
All - Removes both positive and negative plane data from all layers of your design.
Layer - Allows you to remove positive planes by net for the selected layer. If the plane
layer has negative planes, you are only allowed to remove all the plane data from the
selected layer.
Actual Plane Shapes - If Delete Plane Data by Layer is selected, this option becomes
available. When checked it allows you to select actual plane shapes on the board. Actual
plane shapes outline and represent the true plane data including obstructs or hole, islands
and tie legs as they would be plotted. These shapes are always enclosed shapes and
adhere to the clearance rules and connection types defined within the parameters of each
tab.

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Migrating Existing Plane Data

When a legacy design is opened in the new plane environment, you may want to compare the
original plane data with the results from using the new planes engine. This can be achieved by
comparing new fill data with generated Gerber files in the layout editor.
Note
A Fablink XE license is required to import Gerber files into the layout.
To simplify the verification process:
1. Open the legacy design in the new environment.

2. Generate Gerber files for all layers containing the original plane data. You can omit
everything apart from the plane data when generating the Gerber files.
3. Import Gerber files onto user draft layers. Requires a FabLink XE license.
4. Change all plane layers and plane nets in design from Static to Dynamic.
5. Display each board layout in turn, with the corresponding imported data.
Plane Assignments
Using the Plane Assignments dialog allows you to manage plane assignments for each plane
layer and plane net on the board. These display in the Layer/Net column of the table. The
default plane net state is inherited from the current plane layer state. For example, if layer 1 is
set to Dynamic, any new plane nets on this layer inherit the same plane state by default.
Individual plane nets can then be defined with a different state.
The Plane Assignments menu option is only visible in the right mouse button popup if one or
more plane shapes are selected. When opened the corresponding plane net(s) selected in the
table are displayed.
Overrides cannot be overridden by making a class assignment change in the Plane Assignments
dialog.
Signal Flooded Planes

Signal flooded plane layers allow you to route and simulate nets on designs that have no solid
power planes. When the signal layers are flooded, you can use those layers as reference layers
when determining the transmission line characteristics of nets.
When the signal layers are set as reference layers, they are used as a reference in the CES Net
Class impedance calculations and carry through in the AutoActive environment. Additionally,
when data is extracted from the AutoActive environment and pushed to ICX classic or
HyperLynx, the reference plane information is also included.

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You can select a layer to be used as a plane reference and change that reference easily during
the design process. For example, you may need to do some analysis with layer two as a
reference plane and then change the reference plane to be layer four. When the layer description
is set to Flooded Signal, then the plane type is set to Positive and it cannot be changed.
The Plane layer indicators in the General Tab of Editor Control are signified with a letter P
appended to the layer number. The Flooded Signal layers are treated the same as other signal
layers and therefore do not have a P appended.
Net Information Extraction in the AutoActive Environment

The net information that is extracted from AutoActive and sent to the various simulation tools
(including ICX Pro Verify from within AutoActive) includes the default clearances between the
area fills and the traces. This default clearance is used when determining the transmission line
characteristics of the nets that are routed beside the area fills.
The flooded signal layer type is passed to the various simulation tools in cases where the area
fills have not yet been created; the simulation treats the layer as if the fill already exists. This
feature allows you to do some what-if analysis on various net topologies before creating all of
the area fills.
Data Differences
Due to fundamental differences in the data used to estimate transmission line characteristics in
AutoActive and that used to simulate nets in the ICX, ICX Pro and HyperLynx environments,
data differences are seen.
Estimated characteristic impedances for a trace width on a specific layer can be seen by
selecting a trace segment in AutoActive or by looking at the Typical Impedance column in the
Traces and Via Properties tab of CES. Additionally, you can see the characteristic impedance of
a specified trace width in the Basic or Z0 Planning tabs of the CES Stackup Editor.
Because the CES Stackup Editor, CES and the AutoActive environment are all using the same
field solver and making the same assumptions about plane layers and flooded signal layers, the
impedance calculations in these three tools should match. On the other hand, when extracting
transmission line characteristics for simulation purposes, neighboring nets and exact location of
plane data (area fills) is used. Utilizing this extra data results in more accurate trace
characterization.

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Example Illustrating Differences

The following figure illustrates a cross section of a very simple example of a four layer design
with layer 2 and layer 3 having area fills.
Net A and Net B use the area fills as references in the real design and in a simulation
environment. The arrows in the following figure indicate the reference plane used for Net A and
Net B.
If you set layer 2 to be a Flooded Signal layer, then layer 2 is used as the reference layer for Net
A and Net B. The transmission line characteristics for Net A will not be calculated properly, as
indicated by the red trace color in the following figure.
Likewise, when layer 3 is used as a reference layer, Net B characteristics will be wrong, but Net
A will be correct.
When the flooded signal layer types are used, the transmission line characteristics are different
than those used during simulation. The AutoActive transmission line characteristics are only
estimates. Usually, these estimates are close to the actual characteristics but in cases where area
fills and partial plane shapes exist, the estimates are not as accurate.

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Design Verification
A full Design Rule Check (DRC) should always be run prior to generating manufacturing data
and/or documentation. DRC verifies that none of the design rules that were defined in Editor
Control, the Net Classes and Clearances menu or in Design Capture have been violated.
If any design rules were violated, DRC identifies and locates the errors to enable you to correct
them prior to sending the design to manufacturing. Online DRC should not be used as a
substitute for a full Batch DRC run, as it does not have all of the capabilities of Batch DRC.
If a valid license is available, you can run Batch DFF to inspect the design for potential
fabrication and assembly problems. Any problems are available for viewing using the Review
Hazards > DFF options.
Running Batch DRC

Batch DRC can verify your design for proximity, connectivity and manufacturing rules
violations. Proximity checks verify that the clearances defined in Net Classes and Clearances
are not in violation when compared to the elements placed in the design file. Connectivity
verifies that using traces or planes connects pins of the same net defined in the schematic or
netlist. Manufacturing Rules verifies that designs are not created with situation that can cause
manufacturing problems.
Caution
It is important to check the drc.txt file after each run of Batch DRC. This file can be
viewed through File Viewer. Batch DRC hazards limit is 10,000 for proximity checks and
10,000 for connectivity checks. If this limit is passed, Batch DRC stops before
completing verification.
Additional element to element rules can be defined for your manufacturing needs. By default
we load all of the clearances defined in the Net Class and Rules General Rules list. But other
clearance requirements can be added by selecting the Advanced Element to Element Rules
button. This displays a DRC element to element matrix that can be changed by adding
additional clearances to meet your manufacturing needs.
The Batch DRC command can verify proximity clearances on sections of the board defined by a
DRC window placed in the design, or on the entire board. Running DRC in windows is
especially useful on large designs. It allows you to concentrate on small sections of the design
minimizing the need to change the viewed area of the board. A run of the entire board should be
done prior to creating manufacturing data and/or documentation. See Review DRC Hazards for
further information.
If you are going to run DRC in windows, place the windows in the design using the Place DRC
Window command. Next, enter Batch DRC and select, from the menu, the options desired for
the DRC run. You can select any combination of options and make iterative DRC runs.

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When Batch DRC finishes, you should review the log files using the File Viewer. The log files
details, which checks were performed and which violations, if any, were found.
Review DRC Hazards

Review Hazards lists both Online, Batch and DFF DRC hazards. Online hazards are updated on
the fly while the design is being created. Batch Hazards are based on the last run of Batch DRC.
DFF hazards only display if a valid license is available.
After reviewing the log files, you should use the Review Hazards command to find the
violations in the design file and correct them. All of the Expedition PCB commands are
available for use while Review DRC Violations is active, which enables you to fix violations as
they are highlighted in the review session. Batch and DFF DRC should always be re-run after
fixing violations to ensure that new violations were not created during the editing process.
Running Batch DFF

If you want to run either Hole Registration analysis, and/or the Text Stroke Width analysis, the
Gerber and drill files must already be defined and attached to the job before DFF is run.
Therefore, run the Output > Gerber… and the Output > Drill… commands before starting the
DFF analysis. If you don't wish to run either/both of these analyses, this setup step may be
bypassed.

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Figure 3-31. DFF Flow
Complete Design (placement, routing, etc...)
Run Batch DRC
No
DFF Errors Found?
Yes
Creates
Analysis data Reports
Loads results into Analysis > within Design\PCB\LogFiles within Design\PCB\Work directory
Review Hazards > DFF > directory: DffSilverViolations.dat
Signal Drc.txt DrcDffViolations.dat
Plane DrcDff.txt
Drill
Soldermask
Silkscreen
Correct errors identified and save Rerun batch DRC
Create CAM Build Package
You must edit the DrcDffParameters.dat file to setup the DFF Analysis variables file. This file
is ocated within the ,,.PCB/config directory. The UNITS defined in the DrcDffParameters.dat
file do not have to be the same as in the design and if they are not the same, the data in the file is
converted to the units defined for the design. You should also make sure that the number of
layers within this file matches the number of layers within the design.
This file should be opened with a text editor (Word Pad or Notepad).
Note: All text that is shown in the sections below using the "Courier New bold font" identifies
what the user is allowed to edit. If the user modifies anything else, the DFF analysis may a) not
completely run, or b) cause the system to crash.
General notes on modifying the file:

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1. After the initial header block, the first line of every block is name of a particular DFF
analysis that will be run. If you do not want to run this test, change the word YES to
NO. If the system sees a NO, the system will go onto the next analysis block.
Do not leave the analysis as YES and just edit the values to non-realistic numbers, as the
analysis will still be done.
2. For those analyses that can be defined by layer (within Signal, Plane, and Drill
analyses), define separate values for each layer. For example, this:
.TRACE_WIDTHS YES
..LAYER1
..LAYER 2
..LAYER 3
..LAYER 4
...MINIMUM 15
...MAXIMUM 25
is NOT equivalent to:

.TRACE_WIDTHS YES
..LAYER 1
...MINIMUM 15
..MAXIMUM 25
..LAYER 2
...MINIMUM 15
...MAXIMUM 25
..LAYER 3
...MINIMUM 15
...MAXIMUM 25
3. Within each line of the DrcDffParameters.dat file, anything that follows an exclamation
point character ("!") is considered a comment for the rest of that line by the system.
4. For both Soldermask and Silkscreen analyses, different values can be set for both the top
and bottom side and of the design.
Renumbering Reference Designators

When the placement and routing phases are complete, the reference designators can be
renumbered in sequence to make parts in the final design easier to locate.
The most efficient way to accomplish reference designator re-sequencing is through the use of
the Renumber Reference Designator command. This command allows the parts to be
renumbered in one of eight numbering schemes. The Renumber Reference Designator
command renumbers the design's reference designators one side at a time, or renumbers both
sides at once.
Note
We recommend that you renumber the entire design instead of sections. This way
duplicate reference designators are not introduced into the design.

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Once the Renumber Reference Designators command completes, the reference designator
changes are back annotated into the schematic.
A file, RenumberRef.txt, is created by Back Annotation and contains the reference designators
changes created by Renumber Reference Designators. You can view this file using File Viewer.
Text Modification using Draw

When the appropriate reference designators have been placed on the parts, in the order desired,
the text may need to be moved and/or rotated to more readable locations.
Using the Text option of Draw, the reference designator text within a cell can be selected and
moved, rotated or resized. For companies whose design specifications state that all reference
designators must be readable and clear of part outlines, this command provides the quickest way
to modify reference designator locations. After entering the command, select the text and move
it to the new location. By default the Placement Outline for the selected text is highlighted.
Generating Silkscreens
Silkscreens are used to easily identify parts on a board. The silkscreen can contain a variety of
data, but usually all contain at least the silkscreen reference designators and silkscreen outlines.
The Silkscreen Generator allows silkscreen graphics to be processed for manufacturing so the
silkscreen material is broken away from Soldermask or Etch pads. This is to ensure silkscreen
does not interfere with soldering processes. Silkscreens are used to easily identify parts on a
board. The silkscreen can contain a variety of data, but usually all contain at least the silkscreen
reference designators and silkscreen outlines.
Note
In order to edit graphics generated by the Silkscreen Generator, the Edit > Modify >
Allow Cell Graphic Edits option must be enabled.
Silkscreen information can be automatically generated and placed it on the silkscreen level.
Using the options you can generate silkscreen with breaks in the lines and text to avoid pads in
the design, thus preventing manufacturing errors resulting from non-conductive ink coming in
contact with the pad area.
The Silkscreen Generator extracts component outlines for buried parts if they exist in the cell,
even if the cell is on the internal layer. It is recommend that you build buried parts using resistor
shapes and not component outlines.
The break sections of the menu allow you to specify how the items are to provide clearances for
pads and by what distance the silkscreen must clear the pads. The purpose is to prevent the

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silkscreen ink, which is non-conductive, from contacting areas where soldering may be
required.
If cells are built in such a way that all silkscreen data does not touch pads, silkscreen generation
can be skipped and Gerber can be processed using the silkscreen reference designators and
silkscreen outlines.
Drill
Drill is used to automatically generate numerical control (NC) drill output for drilling and
routing printed circuit boards (PCBs). The drill output is used to drill the proper size holes in
precise locations on a PCB. You can set an option to predrill holes larger than an entered value
that must be greater than 0.0 and less than 9999.0. Large holes (> .250") can be predrilled with a
smaller drill bit creating a pilot hole. This is helpful to insure that the larger holes location is
drilled accurately.
The drill chart and drill symbols are not associated with the board/panel instance. When
performing any operation (flip, move, delete), use the Group/Ungroup options to get the desired
behaviour. For example, before moving the board/panel instance, group it with drill symbols so
that drill symbols move with the instance.
For those drill machines that support the router option, NC Drill also generates NC profile
router output which can be used to cut slots, make cutouts within the board area and route
boards out of a panel.
If mezzanine capacitors exist in the design they are extracted to a separate drill file
(mezzanine.ncd) as they are depth dependant not layer to layer. The mezzanine.ncd file resides
in the job's ../output/NCDrill directory. The separate drill line entry is placed in the main drill
log file for the mezzanine capacitors.
NC Drill allows you to:
Extract from the design all drilled and punched holes and routed and punched slots.
Sort the holes in such a way as to minimize tool movement, tool changes, etc.
Create files to enable manufacturing to drill and route boards.
Create charts and reports that summarize the drilling operation.
Place drill symbols at correct locations in the design.
Support complex contour output of lines, polylines, polyarcs, rectangles and circles.
Change the drill manufacturing output format.
The drill executable reads design data from the Layout, Padstack and JobPreferences databases.

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The Layout database contains each instance of thru hole, via, mounting hole and slot, including
its from/to layers, X, Y location relative to the NCDrill origin or, if the NCDrill origin is not
defined, the board origin.
The hole data is sorted so that separate output files can be created for each combination of thru-
holes and via spans, plated and non-plated holes, whether the hole is drilled or punched.
Characteristics of each pin and via, such as hole diameter, plating, whether drilled, punched or
routed, shape (round, square, slot), +/- tolerances and drill symbol assignment are contained in
the Padstack database.
Via span definitions, the number of layers in the design and the design units are extracted from
the Job Preferences database.
Format File Parameters

Excellon or TruDrill data
Modal/Non-modal output
Absolute/Incremental step mode
Units for drill output files and log file (English(inches) / Metric(millimeters))
Format of output (number of decimal places before/after the decimal point)
Zero suppression
Character Set used (ASCII or EBCDIC)
Arc style to be used (Quadrant(I#J#), Radius (A#) or None
Delimiter
Comments on or off
String that determines if data is a comment (; for Excellon)
Comment String
Sequence Numbering (On or Off)
Record length
Drill Output Files

The drill output files will be formatted for Excellon drill machines and according to the
parameters specified in the Drill Format File. The files should be identical (except for date/time
info) each time they are generated, assuming no changes were made. This is to prevent the
automatic tests from failing. All files generated in previous runs will be deleted.

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Each resulting file will be optimized by hole diameter and tolerance, and by location using a
shortest-distance algorithm. A tool number will be assigned in each file for each unique
diameter/tolerance combination.
Drill File Naming Conventions

The individual created drill files will use a specific naming convention that includes the layer
range of the hole, type of hole and type of plating, in that order. All drill files will carry a .ncd
file extension, by default. These files should be sent to the board vendor for fabrication. Some
common drill file names are:
1-2Plated.ncd
ContourNonPlated.ncd
ContourPlated.ncd
ThruHoleNonPlated.ncd
ThruHolePlated.ncd
ThruHolePunchNonPlated.ncd
ThruHolePunchPlated.ncd
Drill Log File

A log file is created, detailing the total number of holes of each type and layer span, number of
holes per tool as well as a summary for the entire job. Additionally, the log file will summarize
the reading and optimization of data, as well as summarizing the creation of files and charts.
Any errors or warnings will also be output to this file. The log file will be written in the job's
../LogFiles directory and will be named NCDrill.txt. Each output file name and hole summary is
contained in the log file.
Drill Data
The NC Drill data is output in two formats; standard english (default) (drillenglish.dff)
and standard metric (drillmetric.dff). These files can be copied to a new filename
(.dff extension) that can then be modified.
Note
If the data is set to one of the standard WG2002 *.mmm files, the system will
automatically map to the equivalent new file.
A drill chart for all thru-holes and each via span will be placed in the design when the setup is
complete. The drill chart will be formatted according to the specified, selected columns and
order.

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Additionally, drill symbols will be placed in the vicinity of all holes that must be drilled,
punched or routed. For drilled holes, punched holes and punched slots, the drill symbols will be
centered over the hole or slot origin. For drilled slots, the drill symbol will be placed at the edge
of the slot where the drill bit will initially be drilled because the slot will be "routed" with the
drill bit.
In the output files created for the drill machine, the holes to be drilled are grouped smallest to
largest according to size. This grouping allows holes of the same size to be drilled before
changing the drill bit for other hole sizes. This greatly reduces the `dead' time that is required
when drill bits are changed.
The drill software removes any duplicate holes at the same X, Y coordinate, eliminating all but
the hole with the largest diameter. This ensures that the drill machines do not drill the same hole
more than once if holes are accidentally placed on top of each other in the design file.
Eliminating duplicate holes helps prevent the drill machine from breaking drill bits and
produces a more accurate printed circuit board.
Drilling time is further reduced by optimizing the movement of the drill head. Each group of
holes (each of the same size and requiring the same drill bit) are sorted according to their
location on the board. Board optimization is continuous, which causes the drill head to move
along a sweep axis within a specified bandwidth until it reaches the edge of the board. The drill
head then moves to the next axis and drills in the opposite direction.
The following figure shows an example of a drill drawing that is placed in the design.
Figure 3-32. Drill Chart
Through Holes
All Drills (unless specified) +/- 0.0000 (in)
Diameter (in) Quanity Hole Name Tolerance (in) Plated

0.0380 28 Rnd 38 +0.050 / -0.0030 Yes
0.1250 2 Rnd 125 =/-Tol 5 +/- 0.0050 Yes
0.1250 1 Rnd 125 +Tol 3 -Tol 0 +/- 0.0050 N0
0.0620 1 Rnd 62 +/- Tol 3 Non-Plated +/- 0.0030 No
The diameter column contains the hole dimensions and rotation. The rotation is indicated by a
capital "R" followed by the rotation angle. For example, 0.0300 R45.
If a hole is a square punched hole and there are many rotations in 90-degree increments, all of
those rotations will be seen as zero because the rotation of zero is equivalent to 90, 180 or 270.
However, if you have a square hole that is rotated at some other increments that are not
equivalent, then those holes will be listed separately. For example, if a 22.5 degree rotation and
a 45 degree rotation of the same hole are found, those holes will be listed separately.

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Holes that are actually slots are treated differently depending on whether the slot is specified as
"drilled" or "punched" in the padstack. If the hole is drilled, the drill diameter will be specified
and no rotation will be seen because the drill will be converted to contours, which only use the
drill diameter. However, if the slotted hole is "punched", then the height, width and rotation
angle of the punched slot will be seen in the drill chart.
The same rotation principles are used for slotted holes (punched versus drilled) in the drill
output files.
The drill chart units are in either MM (millimeter) or IN (inches) and are determined by the
Units value. It is important to note that the drill chart units can be different from the generated
output file units. This enables you to create drill output files in the formats that different vendors
prefer without having to create a new drill table. The precision of the drill chart is determined by
the Precision value in the NC Drill Generation dialog.
Gerber (274X)
When the design is complete, the next step in the design process is the creation of Gerber output
data. The Data Type can be either 274X (default) or 274D. This information is sent to a
photoplotting vendor who provides artworks. The artwork is what is used to actually create the
physical printed circuit board.
Gerber output data is created in Expedition PCB via the Gerber Output command. Gerber
requires that a valid Gerber Machine Format File has been created. This file determines the
format of the Gerber data that will be produced. D-Codes are assigned to Pads and draws on the
fly. If a flash cannot be generated for a pad, the pads will automatically be drawn during Gerber
output. To generate Gerber, select the Process Checked Output Files button.
Header and Trailer

If desired, you may also specify comment text, to appear either in the header, trailer, or both. Up
to 128 character lines may appear in each of these comment sections. This field can be used to
show the job name, company name and/or date.
Defining Screen Contents

Once you have defined each gerber filename that will be created the Contents tab allows you to
define the graphics objects that make up these files. Typically, each gerber file consists of a set
of elements that is used to manufacture your printed circuit board. You should generate one file
for each route layer within your design, and one file for each of the following: top and bottom
soldermask pads, the top and bottom solderpaste pads, the top and bottom silkscreens, the drill
drawing and the assembly drawings.

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Gerber (274D)
Follow the steps below to generate gerber in 274D.
1. Copy the delivered ..\config\VBExpPCB\sample.dmf file to your job's ..\config

directory to create your <new>.dmf file.
2. In Expedition PCB, from the Setup pulldown, select Gerber Machine Format and create
a new file with 274D as the Data Type.
3. In Expedition PCB, from the Output pulldown, select Gerber. Create or select a Gerber
Plot Setup file (.gpf). Create and define the output files to be processed.
4. In the Gerber dialog, bottom left corner, verify that the new Gerber Machine Format file
with 274D Data Type is attached. If not, browse for and attach.
5. In the Gerber dialog, in the D-Code Mapping File section browse for and attach your
<new>.dmf file to each output file to be processed.
6. In the Gerber dialog, choose either Flash or Draw Pads for each output file to be
processed.
7. Toggle ON each check box for the layers to process and then select the Process
Checked Output Files button.
An error message appears if your job specific apertures haven't been defined in your
<new>.dmf file.
8. Invoke File - File Viewer and review the log file "GerbPlot.txt" which lists all the
necessary D-Codes for each layer processed.
9. Update your <new>.dmf file with the required D-Codes and then process your gerber.
Notes
1. A D-Code Mapping File (.dmf) is required when using 274D output.
2. A .dmf file requires D-Codes for "all" the apertures in the design.
3. Use the Flash/Draw option to specify whether to flash or draw all the pads for a layer in
the output.
Custom Pads
274X
Drawn - Using the (Automatic) D-Code Mapping File option in the Gerber Output dialog the
custom pad are drawn in the output.

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Flashed - Using a D-Code Mapping File (.dmf) in the Gerber Output dialog specify the D-Code
using the .Custom option and the custom pad are flashed in the output.
.Custom ..Dcode 100 ..Name "Smiley Face 30 x 35" ..Angle 0
274D
Drawn - Using a D-Code Mapping File (.dmf) in the Gerber Output dialog exclude the D-Code
for the custom pad and it are drawn in the output.
Flashed - Using a D-Code Mapping File (.dmf) in the Gerber Output dialog specify the D-Code
using the .Custom option and the custom pad are flashed in the output.
.Custom ..Dcode 100 ..Name "Smiley Face 30 x 35" ..Angle 0
Gerber Machine Format

This command is used to define the method in which the plotter interprets and plots design
information. The data type can be in either 274X or 274D format. It is important to know your
plotter's capabilities when setting up your Gerber device. Failure to setup the device properly
can cause inaccurate results.
The Gerber Machine Format file contains the flashes and draws of your design data that is used
to generate manufacturing artwork and is referenced by Gerber Output.
Gerber Machine formats are not translated from a previous version of PCB. Any previous
Gerber formats have to be redefined.
You can select the Polygon Fill Method to be either Raster or Draw. Raster uses raster fill to
create the data with "sharp" corners. Draw uses vector fill to create the data with drawn or
"rounded" corners. Raster is only available for the 274X data type.
Caution
Although the setting in the dialog is Draw, the example file displays STROKE. If hand
editing the file, STROKE must be the entry or the format will be invalid.
General Interfaces
Expedition PCB supports the following outputs via the General Interfaces dialog. This data then
can be used by third party software to do manufacturing verification, thermal analysis and
manufacturing outputs.

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Hyperlynx Thermal
This command produces an output file that is compatible with HyperLynx. The output filename
is HyperLynxOut.txt.
Generic AIS and Generic ATE

Individual Automatic Insertion Systems and Automatic Test Equipment Systems are not
addressed by Expedition PCB. However, the system generates a generic output for both of these
type CAM systems. Once these generic ASCII files have been created, they can be edited via a
text editor to meet the specific needs of your company’s individual CAM systems. The output
files generated are vb_ate.txt for ATE and vb_ais.txt for AIS.
Mitron GenCad
This command produces an output file that is compatible with the Mitron CIMBridge
manufacturing framework system. This allows machine development via CB/Pro and test
development via CB/Test. The output filename is gencad.cad.
Fabmaster
The Fabmaster command produces output files which can be used with the Fabmaster package.
General Interfaces outputs the same log file, generalinterfaces.txt, every time one of the options
is selected. A <design_name>.fab file is also generated and can be located in the design's
../PCB/Output directory.
The supported version of Fabmaster, at board level only, is FATF Rev 1.2.
C-Link
The C-Link command produces output files which can be used with the C-Link package.
General Interfaces outputs the same log file, generalinterfaces.txt, every time one of the options
is selected. Two additional files are created in the design's ../PCB/Output directory:
<design_name>.dif and TESTFILE.PSH.
The supported version of C-Link, at board level only, is Version 4.0.
Detailed Views
Detailed views are user-defined areas of the board that can be scaled to clearly show design
detail to create customized documentation details. Detailed views have their own scale factor,
can contain specific Display Control settings and are read-only.
Note
There is a limit of 250 detailed views within any one design.

Post Processing
The only manipulation within a detailed view is the addition of text, dimension data and
graphics. Any manipulation should be created on a user-layer defined in Setup Parameters.
Caution
If a dimension is added to a detailed view, after exiting and reopening a design, the
association is lost.
The detailed view can be placed with cursor data points. When placing the detailed view, you
have the following options: polygon, rectangle or circle. You can select the drawing option
from the Draw toolbar which displays automatically. The Draw Properties dialog changes to
reflect the chosen drawing option.
Detailed views may be moved anywhere within the design plane, including the board area or
outline. The detailed view always displays on top and if placed within the board outline, the
design data may be hidden.
A copied detailed view numerically increments the last placed detail view name. This can then
be edited and the displayed layers in Display Control can be changed. The Display Control >
General Tab displays the viewable layers within the detailed view.
If the detailed view is included within the selected plot are, the information is plotted as any
other element within the design. Detailed views are WYSIWYG, therefore you should display
the elements and layers within the detail view prior to plotting.
Annotation Mode
Annotation mode is accessed by clicking the left mouse button within the scratch pad. The
scratch pad border turns red and the design displays in shadow mode. This mode allows you
access to the dimension, text and graphic placement commands. The Properties Text options are
only allowed within the annotation mode.
Dimension data within the detailed view is stored on the selected detailed view layer and is
placed within the scratch pad area. Applying dimension data is only available in annotation
mode.
To return to modification mode select the scratch pad border. To exit from annotation mode,
either select anywhere in the design or select the right mouse button and click Exit from the
popup.
Modification Mode
Modification mode allows you to change or modify the following parameters: name, scale,
mirror, rotate and font by single-clicking in the detailed view area.

Post Processing
Example
The Detailed View source rectangle is the selected user-defined area or boundary within the
design file that is displayed as a detailed view. This area can be a polygon, rectangle, or a circle
selected from the Draw commands menu, however, the source area displays as a rectangle. This
source rectangle is displayed over the layout of the design. This area is modifiable to the extent
that it can be increased/decreased in size without changing the scale and this allows it to
increase the volume without having to recreate it.
The purpose of the scratch pad is to allow an area for additional associated data such as
dimension data, text and graphics. The scratch pad area is only modifiable from within the
detailed view. Selecting the detailed view and then a handle allows you to enlarge the area.
Scratch pads may overlap.
The scratch pad can be modified or stretched only when in modification mode. When increasing
or decreasing the viewed area, the scratch pad changes; the selected area or design view does
not. The scratch pad area cannot be modified smaller then the detailed view area.
All additional data is placed on a user-specified layer. It is recommended, prior to the creation
of a detailed view, that user layers are defined and logically named.
Plotting - Archive Plots

When the design is complete and has been approved, it is time to prepare the files for archive.
For most companies, this means preparing some type of archive prints or plots. The
documentation is created and signed by the appropriate people, usually the design engineer,
CAD manager, CAD designer and the Checking department.

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Chapter 3

Expedition PCB Design Process

Expedition PCB User’s Guide, EE2007.1 75

If you want to:

General Tab in Setup Parameters

76 Expedition PCB User’s Guide, EE2007.1

To set general parameters

Expedition PCB User’s Guide, EE2007.1 77

Via Definitions Tab in Setup Parameters

78 Expedition PCB User’s Guide, EE2007.1

Figure 3-1. Allowed Via Padstacks

To create and define via definitions

Expedition PCB User’s Guide, EE2007.1 79

80 Expedition PCB User’s Guide, EE2007.1

Drag - Move Function

Trace connected on an internal range layer

Expedition PCB User’s Guide, EE2007.1 81

82 Expedition PCB User’s Guide, EE2007.1

Via Clearances Tab

Via Clearance Definitions

Figure 3-2. Net Class General Clearances

Expedition PCB User’s Guide, EE2007.1 83

Use the Same Net Via Span to Via Span Clearances

Figure 3-3. Same Net Clearances in Setup Parameters

84 Expedition PCB User’s Guide, EE2007.1

PE (Pad Edge to Pad Edge (Default)) = Pad edge to pad edge.

Multiple Via Objects

To define vias so they can be stacked

Expedition PCB User’s Guide, EE2007.1 85

86 Expedition PCB User’s Guide, EE2007.1

Buried Resistors and Rise Time

Rise time by Technology

Expedition PCB User’s Guide, EE2007.1 87

Nets with I/O's and loads

Reserved Layer Names

Cannot open Cell lib. Unable to create scratch jobprefs.

Reserved User Layer Names

88 Expedition PCB User’s Guide, EE2007.1

General Setup Rules

Expedition PCB User’s Guide, EE2007.1 89

Figure 3-4. Editor Control General Tab

90 Expedition PCB User’s Guide, EE2007.1

Expedition PCB User’s Guide, EE2007.1 91

Modification to the block's elements, move, edit, etc. is not permitted.

Gloss - All Gloss functions and entry points are disabled.

92 Expedition PCB User’s Guide, EE2007.1

Figure 3-5. Editor Control Parts Tab

Expedition PCB User’s Guide, EE2007.1 93

Figure 3-6. Editor Control Cells Tab

Clusters and Rooms Tab

94 Expedition PCB User’s Guide, EE2007.1

Figure 3-7. Editor Control Clusters and Rooms Tab

Expedition PCB User’s Guide, EE2007.1 95

Figure 3-8. Editor Control Routes Tab

96 Expedition PCB User’s Guide, EE2007.1

Figure 3-9. Editor Control Gloss Tab

Pad Entry Tab

Figure 3-10. Editor Control Pad Entry Tab

Expedition PCB User’s Guide, EE2007.1 97

Figure 3-11. Editor Control GridsTab