Anupam Sir DLD3

Bipradas Pal Chowdhury Institute of Technology
DEPARTMENT OF COMPUTER SCIENCE & TECHNOLOGY
E-CONTENTS :
Unit: 3
Name of the Topics:
Developed By:
Lecturer in Computer Science &Technology
Computer Science &Technology

Bipradas Pal Chowdhury Institute of Technology
Contents:
3.1 Simplification of Boolean expression using Boolean algebra.
3.2 Construction of logical circuits forms Boolean expressions.
3.3 Boolean expressions using Sum of products and product of sums
forms.
3.4 K-map representation of logical functions and minimization (2,3,4
variable).
3.5 Standardization of SOP & POS equations
3.6 Truth table, K-map, Simplified logical expression and logical circuit
using basic gates and universal gates of: (a) Half adder and full adder.
(b) Half subtractor and full subtractor. Binary parallel adder, adder-
subtractor, BCD adder.
3.7 Block diagram, Truth table, Logical expression and logic diagram of
Multiplexers (4:1 and 8:1), Multiplexer Cascading and use of
Multiplexer in implementation of Boolean function.
3.8 Block diagram and Truth table of Demultiplexer (1:4; 1:8; 1:16).
Block diagram and Truth table of Encoders and Decoder. Use of
Decoder in implementation of Boolean function.
3.9 Design of different code converter, BCD to 7 segment decoder,
Comparator, Parity Checker and Generator
Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 2|Page

3.1 Simplification of Boolean expression using Boolean algebra
A set of rules or Laws of Boolean Algebra expressions have
been invented to help reduce the number of logic gates needed to perform a particular
logic operation resulting in a list of functions or theorems known commonly as the Laws
of Boolean Algebra.
Boolean Algebra is the mathematics we use to analyse digital gates and circuits. We
can use these “Laws of Boolean” to both reduce and simplify a complex Boolean
expression in an attempt to reduce the number of logic gates required. Boolean
Algebra is therefore a system of mathematics based on logic that has its own set of
rules or laws which are used to define and reduce Boolean expressions.
The variables used in Boolean Algebra only have one of two possible values, a logic
“0” and a logic “1” but an expression can have an infinite number of variables all
labelled individually to represent inputs to the expression, For example, variables A, B,
C etc, giving us a logical expression of A + B = C, but each variable can ONLY be a 0
or a 1.
As well as the logic symbols “0” and “1” being used to represent a digital input or
output, we can also use them as constants for a permanently “Open” or “Closed” circuit
or contact respectively.
Description of the Laws of Boolean Algebra :
Annulment Law – A term ANDéd with a “0” equals 0 or ORéd with a “1” will equal 1
o A.0=0 A variable AND’ed with 0 is always equal to 0

o A + 1 = 1 A variable OR’ed with 1 is always equal to 1
Identity Law – A term ORéd with a “0” or ANDéd with a “1” will always equal that
term
o A + 0 = A A variable OR’ed with 0 is always equal to the variable

o A.1=A A variable AND’ed with 1 is always equal to the variable
Idempotent Law – An input that is ANDéd or ORéd with itself is equal to that input
o A+A=A A variable OR’ed with itself is always equal to the variable

o A.A=A A variable AND’ed with itself is always equal to the variable

Complement Law – A term ANDéd with its complement equals “0” and a
term ORéd with its complement equals “1”
o A .A̅= 0 A variable AND’ed with its complement is always equal to 0

o A + A̅ = 1 A variable OR’ed with its complement is always equal to 1
Commutative Law – The order of application of two separate terms is not important
o A.B=B.A The order in which two variables are AND’ed makes no

difference
o A+B=B+A The order in which two variables are OR’ed makes no
difference
Double Negation Law – A term that is inverted twice is equal to the original term
o A̿ = A A double complement of a variable is always equal to the

variable
de Morgan´s Theorem – There are two “de Morgan´s” rules or theorems,
(1) Two separate terms NORéd together is the same as the two terms inverted
(Complement) and ANDéd for example: 𝐴 ̅̅̅̅̅̅̅̅
+ 𝐵= A̅ . B̅
(2) Two separate terms NANDéd together is the same as the two terms inverted
(Complement) and ORéd for example: ̅̅̅̅̅
𝐴. 𝐵 = A̅ + B̅
Other algebraic Laws of Boolean not detailed above include:
Distributive Law – This law permits the multiplying or factoring out of an expression.
o A(B + C) = A.B + A.C (OR Distributive Law)

o A + (B.C) = (A + B).(A + C) (AND Distributive Law)
Absorptive Law – This law enables a reduction in a complicated expression to a

simpler one by absorbing like terms.
o A + (A.B) = A (OR Absorption Law)

o A(A + B) = A (AND Absorption Law)

Associative Law – This law allows the removal of brackets from an expression and
regrouping of the variables.
o A + (B + C) = (A + B) + C = A + B + C (OR Associate Law)

o A(B.C) = (A.B)C = A . B . C (AND Associate Law)
Examples:
Using the above laws, simplify the expression: (A + B)(A + C)
Q= (A + B).(A + C)
A.A + A.C + A.B + B.C – Distributive law
A + A.C + A.B + B.C – Idempotent AND law (A.A = A)
A(1 + C) + A.B + B.C – Distributive law
A.1 + A.B + B.C – Identity OR law (1 + C = 1)
A(1 + B) + B.C – Distributive law
A.1 + B.C – Identity OR law (1 + B = 1)
Q= A + (B.C) – Identity AND law (A.1 = A)
Then the expression: (A + B)(A + C) can be simplified to A + (B.C) as in the

Distributive law.

Using Boolean algebra techniques, simplify this expression:
AB + A(B + C) + B(B + C)
Q= AB + A(B + C) + B(B + C)
AB + AB + AC + BB + BC – Distributive law
AB + AB + AC + B + BC – Idempotent AND law ( BB = B )
AB + AC + B + BC – Idempotent OR law (AB + AB = AB)
AB + AC + B – Absorptive OR Law (B + B.C = B)
Q= B+AC – Absorptive OR Law (B +AB = B)
Then the expression: AB + A(B + C) + B(B + C) can be simplified to B+AC.

3.2 Construction of logical circuits forms Boolean expressions
2-input AND Gate

For a 2-input AND gate, the output Q is true if BOTH input A “AND” input B are both
true, giving the Boolean Expression of: ( Q = A and B ).
Symbol Truth Table
A B Q
0 0 0
0 1 0
1 0 0
1 1 1
Boolean Expression Q = A.B Read as A AND B gives Q
Note that the Boolean Expression for a two input AND gate can be written as: A.B or
just simply AB without the decimal point.

2-input OR (Inclusive OR) Gate
For a 2-input OR gate, the output Q is true if EITHER input A “OR” input B is true,
giving the Boolean Expression of: ( Q = A or B ).
Symbol Truth Table
A B Q
0 0 0
0 1 1
1 0 1
1 1 1
Boolean Expression Q = A+B Read as A OR B gives Q

NOT Gate (Inverter)
For a single input NOT gate, the output Q is ONLY true when the input is “NOT” true,
the output is the inverse or complement of the input giving the Boolean Expression of:
( Q = NOT A ).
Symbol Truth Table
A Q
0 1
1 0
Boolean Expression Q = NOT A or A̅ Read as inversion of A gives Q
The NAND and the NOR Gates are a combination of the AND and OR Gates
respectively with that of a NOT Gate (inverter).

2-input NAND (Not AND) Gate
For a 2-input NAND gate, the output Q is NOT true if BOTH input A and input B are
true, giving the Boolean Expression of: ( Q = not(A AND B) ).
Symbol Truth Table
A B Q
0 0 1
0 1 1
1 0 1
1 1 0
̅̅̅̅̅̅
Boolean Expression Q = 𝐴 .𝐵 Read as A AND B gives NOT-Q
Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 10 | P a g e

2-input NOR (Not OR) Gate
For a 2-input NOR gate, the output Q is true if BOTH input A and input B are NOT true,
giving the Boolean Expression of: ( Q = not(A OR B) ).
Symbol Truth Table
A B Q
0 0 1
0 1 0
1 0 0
1 1 0
Boolean Expression Q =̅̅̅̅̅̅̅̅

𝐴+𝐵 Read as A OR B gives NOT-Q
As well as the standard logic gates there are also two special types of logic gate
function called an Exclusive-OR Gate and an Exclusive-NOR Gate. The Boolean
expression to indicate an Exclusive-OR or Exclusive-NOR function is to a symbol with a
plus sign inside a circle, ( ⊕ ).
The switching actions of both of these types of gates can be created using the above
standard logic gates. However, as they are widely used functions they are now
available in standard IC form and have been included here as reference.

2-input EX-OR (Exclusive OR) Gate
For a 2-input Ex-OR gate, the output Q is true if EITHER input A or if input B is true, but
NOT both giving the Boolean Expression of: ( Q = (A and NOT B) or (NOT A and B) ).
Symbol Truth Table
A B Q
0 0 0
0 1 1
1 0 1
1 1 0
Boolean Expression Q = A ⊕ B

2-input EX-NOR (Exclusive NOR) Gate
For a 2-input Ex-NOR gate, the output Q is true if BOTH input A and input B are the
same, either true or false, giving the Boolean Expression of: ( Q = (A and B) or (NOT A
and NOT B) ).
Symbol Truth Table
A B Q
0 0 1
0 1 0
1 0 0
1 1 1
̅̅̅̅̅̅̅̅̅̅
Boolean Expression Q = 𝐴 ⊕ 𝐵

How to Write a Boolean Expression to
Simplify Circuits
For example, the outputs of the first three gates:
. . . then another sub-expression for the next gate:

Finally, the output (“Q”) is seen to be equal to the expression AB + BC(B + C):
Q. Convert the following logic gate circuit into a Boolean expression,

writing Boolean sub-expressions next to each gate output in the diagram:

Q. Convert the following logic gate circuit into a Boolean expression, writing Boolean
sub-expressions next to each gate output in the diagram:

3.3 Boolean expressions using Sum of products and product of
sums forms.
Sum of Products
So we have seen that the AND function produces the logical product of Boolean
multiplication, and that the OR function produces the logical sum of Boolean addition.
But when dealing with combinational logic circuits in which AND gates, OR gates
and NOT gates are connected together, the expressions of Sum-of-
Products and Product-of-Sums are widely used.
The Sum of Product (SOP) expression comes from the fact that two or more products
(AND) are summed (OR) together. That is the outputs from two or more AND gates are
connected to the input of an OR gate so that they are effectively OR’ed together to
create the final AND-OR logical output. For example, the following Boolean function is a
typical sum-of-product expression:
Sum of Product Expression

Q = (A.B) + (B̅.C) + (A.1)
and also
(A.B.C) + (A.C) + (B̅.C̅)
However, Boolean functions can also be expressed in nonstandard sum of products

forms like that shown below but they can be converted to a standard SOP form by
expanding the expression. So:
Q = A.B̅(C̅ + C) + ABC
Becomes in sum-of-product terms:
Q = A.B̅.C̅ + A.B̅.C + ABC
Actually this large SOP expression can be reduced further using the laws of Boolean
algebra to give a reduced SOP expression of:
Q = A.B̅ + A.C
Sum-of-Product Example
The following Boolean Algebra expression is given as:
Q = A̅(B̅C + BC + BC̅) + ABC
1. Convert this logical equation into an equivalent SOP term.
2. Use a truth table to show all the possible combinations of input conditions that will
produces an output.
3. Draw a logic gate diagram for the expression.
1. Convert to SOP term
Q = A.B.C + A̅.B̅.C + A̅.B.C + A̅.B.C̅
2. Truth Table
Sum of Product Truth Table Form
3. Logic Gate SOP Diagram
Then we have seen in this tutorial that the Sum-of-Products (SOP) expression is a
standard boolean expression that “Sums” two or more “Products” and that for a digital
logic circuit an SOP expression takes the output of two or more logic AND gates
and OR’s them together to create the final (AND-OR) output.

Product of Sum
So we have seen that the OR function produces the logical sum of Boolean addition,
and that the AND function produces the logical sum of Boolean multiplication. But when
dealing with combinational logic circuits in which AND gates, OR gates and NOT gates
are connected together, the expressions of Product-of-Sum is widely used.
The Product of Sum (POS) expression comes from the fact that two or more sums
(OR’s) are added (AND’ed) together. That is the outputs from two or more OR gates
are connected to the input of an AND gate so that they are effectively AND’ed together
to create the final (OR AND) output. For example, the following Boolean function is a
typical product-of-sum expression:
Product of Sum Expressions

Q = (A + B).(B̅ + C).(A + 1)
and also
(A + B + C).(A + C).(B̅ + C̅)
However, Boolean functions can also be expressed in nonstandard product of sum

forms like that shown below but they can be converted to a standard POS form by
using the distributive law to expand the expression with respect to the sum. Therefore:
Q = A + (B̅C)
Becomes in expanded product-of-sum terms:
Q = (A + B̅)(A + C)
Another nonstandard example is:
Q = (A + B̅) + (A.C)
Becomes as an expanded product-of-sum expession:
Q = (A + B̅ + B)(A + B̅ + C)
which can, if required be reduced using complement law and annulment law) too:
Q = (A + 1)(A + B̅ + C)
Q = A + B̅ + C
Product of Sum Example

The following Boolean Algebra expression is given as:
Q = (A + B + C)(A + B̅ + C)(A̅ + B + C̅)(A + B̅ + C̅)
1. Use a truth table to show all the possible combinations of input conditions that will
produces a “0” output.

2. Draw a logic gate diagram for the POS expression.
1. Truth Table
Product of Sum Truth Table Form
2. Logic Gate Diagram
Then we have seen in this tutorial that the Product-of-Sum (POS) expression is a
standard boolean expression that takes the “Product” of two or more “Sums”. For a
digital logic circuit the POS expression takes the output of two or more logic OR gates
and AND’s them together to create the final OR-AND logic output.
3.4 K-map representation of logical functions and
minimization (2,3,4 variable).
Karnaugh Maps (K-maps) :
• Karnaugh maps -- A tool for representing Boolean functions of up to
six variables.
• K-maps are tables of rows and columns with entries represent 1`s or
0`s of SOP and POS representations.
• An n-variable K-map has 2n cells with each cell corresponding to an n-
variable truth table value.
• K-map cells are labeled with the corresponding truth-table row.
• K-map cells are arranged such that adjacent cells correspond to truth
rows that differ in only one bit position (logical adjacency).
Minimization with Karnaugh Maps and advantages of K-map
 K-maps are used to convert the truth table of a Boolean equation into minimized
SOP form.
 Easy and simple basic rules for the simplification.
 The K-map method is faster and more efficient than other simplification techniques
of Boolean algebra.
 All rows in the K-map are represented by using a square shaped cells, in which
each square in that will represent a minterm.
 It is easy to convert a truth table to k-map and k-map to Sum of Products form
equation.
There are 2 forms in converting a Boolean equation into K-map:
1. Un-optimized form
2. Optimized form
 Un-optimized form: It involves in converting the number of 1’s into equal number of
product terms (min terms) in an SOP equation.
 Optimized form: It involves in reducing the number of min terms in the SOP
equation.

Grouping of K-map variables
 There are some rules to follow while we are grouping the variables in K-maps.
They are
 The square that contains ‘1’ should be taken in simplifying, at least once.
 The square that contains ‘1’ can be considered as many times as the grouping is
possible with it.
 Group shouldn’t include any zeros (0).
 A group should be the as large as possible.
 Groups can be horizontal or vertical. Grouping of variables in diagonal manner is
not allowed.

 If the square containing ‘1’ has no possibility to be placed in a group, then it should
be added to the final expression.
 Groups can overlap.
 The number of squares in a group must be equal to powers of 2, such as 1, 2, 4, 8
etc.
 Groups can wrap around. As the K-map is considered as spherical or folded, the
squares at the corners (which are at the end of the column or row) should be
considered as they adjacent squares.
 The grouping of K-map variables can be done in many ways, so the obtained
simplified equation need not to be unique always.
 The Boolean equation must be in must be in canonical form, in order to draw a K-
map.

Generating Gray Code
If we sketch our own Karnaugh maps, we need to generate Gray code for any size map
that we may use. This is how we generate Gray code of any size.
Note that the Gray code sequence, above right, only varies by one bit as we go down
the list, or bottom to top up the list. This property of Gray code is often useful for
digital electronics in general. In particular, it is applicable to Karnaugh maps.

Here all “ ’ ” represent “ ̅ ”
2 variable K-maps
There are 4 cells (22) in the 2-variable k-map. It will look like (see below image)
The possible min terms with 2 variables (A and B) are A.B, A.B̅, A̅.B and A̅.B̅. The
conjunctions of the variables (A, B) and (A̅, B) are represented in the cells of the top
row and (A, B̅) and (A̅, B̅) in cells of the bottom row. The following table shows the
positions of all the possible outputs of 2-variable Boolean function on a K-map.
A general representation of a 2 variable K-map plot is shown below.
When we are simplifying a Boolean equation using Karnaugh map, we represent the
each cell of K-map containing the conjunction term with 1. After that, we group the
adjacent cells with possible sizes as 2 or 4. In case of larger k-maps, we can group the
variables in larger sizes like 8 or 16.

The groups of variables should be in rectangular shape, that means the groups must be
formed by combining adjacent cells either vertically or horizontally. Diagonal shaped or
L-shaped groups are not allowed. The following example demonstrates a K-map
simplification of a 2-variable Boolean equation.
Example
1. Simplify the given 2-variable Boolean equation by using K-map.
F = A B̅ + A̅ B + A̅B̅
First, let’s construct the truth table for the given equation,
2. Simplify the logic diagram below.
Solution:

3 variable K-maps
For a 3-variable Boolean function, there is a possibility of 8 output min terms. The
general representation of all the min terms using 3-variables is shown below.
A typical plot of a 3-variable K-map is shown below. It can be observed that the
positions of columns 10 and 11 are interchanged so that there is only change in one
variable across adjacent cells. This modification will allow in minimizing the logic.
Up to 8 cells can be grouped in case of a 3-variable K-map with other possibilities being
1,2 and 4.
Example
1. Simplify the given 3-variable Boolean equation by using k-map.
F = X’ Y Z + X’ Y’ Z + X Y Z’ + X’ Y’ Z’ + X Y Z + X Y’ Z’
First, let’s construct the truth table for the given equation,

We put 1 at the output terms given in equation.
There are 8 cells (23) in the 3-variable k-map. It will look like (see below image).
The largest group size will be 8 but we can also form the groups of size 4 and size 2, by
possibility. In the 3 variable Karnaugh map, we consider the left most column of the k-
map as the adjacent column of rightmost column. So the size 4 group is formed as
shown below.
And in both the terms, we have ‘Y’ in common. So the group of size 4 is reduced as the
conjunction Y. To consume every cell which has 1 in it, we group the rest of cells to
form size 2 group, as shown below.

The 2 size group has no common variables, so they are written with their variables and
its conjugates. So the reduced equation will be X Z’ + Y’ + X’ Z. In this equation, no
further minimization is possible.
2.

3. Z= ∑A,B,C(1,3,6,7) SOP FORM
 From red group we get product term—

 A’C
 From green group we get product term—
 AB
 Summing these product terms we get- Final expression (A’C+AB)

4. F(A,B,C)=π(0,3,6,7) POS FORM
From red group we find terms

A B C’
Taking complement of these two
A’ B’ C
Now sum up them
(A’ + B’ + C)
From green group we find terms
B C
Taking complement of these two terms
B’ C’
Now sum up them
(B’+C’)
From brown group we find terms
A’ B’ C’
Taking complement of these two
ABC
Now sum up them
(A + B + C)
We will take product of these three terms :Final expression (A’ + B’ + C) (B’ + C’) (A + B + C)

4 variable K-maps
There are 16 possible min terms in case of a 4-variable Boolean function. The general
representation of minterms using 4 variables is shown below.
A typical 4-variable K-map plot is shown below. It can be observed that both the
columns and rows of 10 and 11 are interchanged.
The possible number of cells that can be grouped together are 1, 2, 4, 8 and 16.

Example :
1. Simplify the given 4-variable Boolean equation by using k-map. F (W, X, Y, Z) =
(1, 5, 12, 13)
Sol: F (W, X, Y, Z) = (1, 5, 12, 13)
By preparing k-map, we can minimize the given Boolean equation as
F = W Y’ Z + W ‘Y’ Z

2. F(P,Q,R,S)=∑(0,2,5,7,8,10,13,15) SOP FORM
From red group we get product term—

QS
From green group we get product term—
Q’S’
Summing these product terms we get- Final expression (QS+Q’S’)

3. F(A,B,C,D)=π(3,5,7,8,10,11,12,13) POS FORM
From green group we find terms

C’ D B
Taking their complement and summing them
(C+D’+B’)
From red group we find terms
C D A’
(C’+D’+A)
From blue group we find terms
A C’ D’
(A’+C+D)
From brown group we find terms
A B’ C
(A’+B+C’)
Finally we express these as product –(C+D’+B’).(C’+D’+A).(A’+C+D).(A’+B+C’)

3.5 Standardization of SOP & POS equations
Min terms
A minterm is defined as the product term of n variables, in which each of the n variables
will appear once either in its complemented or un-complemented form. The min term is
denoted as mi where i is in the range of 0 ≤ i < 2ⁿ.
A variable is in complemented form, if its value is assigned to 0, and the variable is un-
complimented form, if its value is assigned to 1.
For a 2-variable (x and y) Boolean function, the possible minterms are:
x’y’, x’y, xy’ and xy.
For a 3-variable (x, y and z) Boolean function, the possible minterms are:
x’y’z’, x’y’z, x’yz’, x’yz, xy’z’, xy’z, xyz’ and xyz.
 1 – Minterms = minterms for which the function F = 1.

 0 – Minterms = minterms for which the function F = 0.
Any Boolean function can be expressed as the sum (OR) of its 1- min terms. The
representation of the equation will be
 F(list of variables) = Σ(list of 1-min term indices)
Ex: F (x, y, z) = Σ (3, 5, 6, 7)
The inverse of the function can be expressed as a sum (OR) of its 0- min terms. The
 F(list of variables) = Σ(list of 0-min term indices)

Ex: F’ (x, y, z) = Σ (0,1, 2, 4)
Examples of canonical form of sum of products expressions (min term canonical form):
i) Z = XY + XZ′
ii) F = XYZ′ + X′YZ + X′YZ′ + XY′Z + XYZ
In standard SOP form, the maximum possible product terms for n number of variables
are given by 2ⁿ. So, for 2 variable equations, the product terms are 22 = 4. Similarly, for
3 variable equations, the product terms are 23 = 8.

Max terms
A max term is defined as the product of n variables, within the range of 0 ≤ i < 2ⁿ. The
max term is denoted as Mi. In max term, each variable is complimented, if its value is
assigned to 1, and each variable is un-complimented if its value is assigned to 0.
For a 2-variable (x and y) Boolean function, the possible max terms are:
x + y, x + y’, x’ + y and x’ + y’.
For a 3-variable (x, y and z) Boolean function, the possible maxterms are:
x + y + z, x + y + z’, x + y’ + z, x + y’ + z’, x’ + y + z, x’ + y + z’, x’ + y’ + z and x’ + y’ + z’.
 1 – Max terms = max terms for which the function F = 1.

 0 – max terms = max terms for which the function F = 0.
Any Boolean function can be expressed the product (AND) of its 0 – max terms. The
 F(list of variables) = Π (list of 0-max term indices)
Ex: F (x, y, z) = Π (0, 1, 2, 4)
The inverse of the function can be expressed as a product (AND) of its 1 – max terms.
The representation of the equation will be
 F(list of variables) = Π (list of 1-max term indices)
Ex: F’ (x, y, z) = Π (3, 5, 6, 7)
Examples of canonical form of product of sums expressions (max term canonical form):
i. Z = (X + Y) (X + Y′)
ii. F = (X′ + Y + Z′) (X′ + Y + Z) (X′ + Y′ + Z′)
In standard POS form, the maximum possible sum terms for n number of variables are
given by 2ⁿ. So, for 2 variable equations, the sum terms are 22 = 4. Similarly, for 3
variable equations, the sum terms are 23 = 8.

Truth table representing minterm and maxterm –
Conversion of SOP form to POS form

To convert the SOP form into POS form, first we should change the Σ to Π and then
write the numeric indexes of missing variables of the given Boolean function.
Example:
The SOP function
F = ∑ A, B, C (0, 2, 3, 5, 7) = A’ B’ C’ + A B’ C’ + A B’ C + ABC’ + ABC is written in

POS form by
Step 1: changing the operational sign to Π
Step 2: writing the missing indexes of the terms, 001, 100 and 110. Now write the sum
form for these noted terms.
001 = (A + B + C) 100 = (A + B’ + C’) 110 = (A + B’ + C’)
Writing down the new equation in the form of POS form,
F = Π A, B, C (1, 4, 6) = (A + B + C) * (A + B’ + C’) * (A + B’ + C’)

Conversion of POS form to SOP form
To convert the POS form into SOP form, first we should change the Π to Σ and then
write the numeric indexes of missing variables of the given Boolean function.
Example:
The POS function F = Π A, B, C (2, 3, 5) = A B’ C’ + A B’ C + ABC’ is written in SOP

form by
Step 1: changing the operational sign to Σ
Step 2: writing the missing indexes of the terms, 000, 001, 100, 110, and 111. Now
write the product form for these noted terms.
000 = A’ * B’ * C’ 001 = A’ * B’ * C 100 = A * B’ * C’
110 = A * B* C’ 111 = A * B * C
Writing down the new equation in the form of SOP form,
F = Σ A, B, C (0, 1, 4, 6, 7) = (A’ * B’ * C’) + (A’ * B’ * C) + (A * B’ * C’) + (A * B* C’) + (A

* B * C)

Truth table, K-map, Simplified logical expression and logical
3.6
circuit using basic gates and universal gates of: (a) Half adder
and full adder. (b) Half subtractor and full subtractor. Binary
parallel adder, adder-subtractor, BCD adder.
Half Adder
TRUTH TABLE:
K-Map

logical circuit using basic gates
Using NAND gate:

Using NOR gate:
Full Adder
TRUTH TABLE:

Using NAND gate:

Using NOR gate:
Half subtractor
TRUTH TABLE:

Using NAND gate:

Using NOR gate:
Full subtractor
TRUTH TABLE:

Using NAND gate:
Using NOR gate:

2 bit Binary parallel adder
4 bit Binary parallel adder

2-bit binary Adder-Subtractor
4-bit binary Adder-Subtractor

BCD Adder
BCD stand for binary coded decimal. Suppose, we have two 4-bit
numbers A and B. The value of A and B can varies from 0(0000 in binary)
to 9(1001 in binary) because we are considering decimal numbers.
The output will varies from 0 to 18, if we are not considering the carry
from the previous sum. But if we are considering the carry, then the
maximum value of output will be 19 (i.e. 9+9+1 = 19).
When we are simply adding A and B, then we get the binary sum. Here,
to get the output in BCD form, we will use BCD Adder.
Example 1:
Input :
A = 0111 B = 1000
Output :
Y = 1 0101
Explanation: We are adding A(=7) and B(=8).

The value of binary sum will be 1111(=15).
But, the BCD sum will be 1 0101,
where 1 is 0001 in binary and 5 is 0101 in binary.

Example 2:
Input :
A = 0101 B = 1001
Output :
Y = 1 0100
Explanation: We are adding A(=5) and B(=9).

The value of binary sum will be 1110(=14).
But, the BCD sum will be 1 0100,
where 1 is 0001 in binary and 4 is 0100 in binary.
Note – If the sum of two number is less than or equal to 9, then the value
of BCD sum and binary sum will be same otherwise they will differ by 6
(0110 in binary).

We are adding “0110” (=6) only to the second half of the table.
The conditions are:
1. If C’ = 1 (Satisfies 16-19)
2. If S3′.S2′ = 1 (Satisfies 12-15)
3. If S3′.S1′ = 1 (Satisfies 10 and 11)
So, our logic is

C' + S3'.S2' + S3'.S1' = 1
Implementation :

3.7 Block diagram, Truth table, Logical expression and logic diagram of
Multiplexers (4:1 and 8:1), Multiplexer Cascading and use of
Multiplexer in implementation of Boolean function.
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection lines and
single output line. One of these data inputs will be connected to the output based on the values of
selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So,
each combination will select only one data input. Multiplexer is also called as Mux.
4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y.
The block diagram of 4x1 Multiplexer is shown in the following figure.
One of these 4 inputs will be connected to the output based on the combination of inputs present
at these two selection lines. Truth table of 4x1 Multiplexer is shown below.
Selection Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3
We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit
diagram of 4x1 multiplexer is shown in the following figure.
8x1 Multiplexer
In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer. We
know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas, 8x1
Multiplexer has 8 data inputs, 3 selection lines and one output.

So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since, each 4x1
Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the
outputs of first stage as inputs and to produce the final output.
Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0 and one output
Y. The Truth table of 8x1 Multiplexer is shown below.
We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering the above
Truth table. The block diagram of 8x1 Multiplexer is shown in the following figure.
The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data inputs of upper
4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1 Multiplexer are I 3 to I0. Therefore, each
4x1 Multiplexer produces an output based on the values of selection lines, s1 & s0.

The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present
in second stage. The other selection line, s2 is applied to 2x1 Multiplexer.
 If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I 3 to I0 based on the
values of selection lines s1 & s0.
 If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I 7 to I4 based on the
values of selection lines s1 & s0.
Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs as
one 8x1 Multiplexer.

Cascading of Multiplexers
Cascading refers to a process where large Multiplexers can be designed and
implemented using smaller Multiplexers.
Example:
8:1 Mux can be designed using two 4:1 Multiplexers and similarly it can be designed
using four 2:1 Multiplexers as shown in the below figure.

Implement the following expression using 8:1
mux F(A,B,C,D)=∑m(0,1,3,5,7,10,11,13,14,15)
 Implement of 8:1 mux
 Multiplexer (8:1mux)

mux F(A,B,C,D)=∑m(0,1,2,4,6,9,12,14)

mux F(A,B,C,D)=∑m(0,2,6,10,11,12,13)+ ∑d(3,8,14)

3.8Block diagram and Truth table of Demultiplexer
(1:4; 1:8; 1:16). Block diagram and Truth table of
Encoders and Decoder. Use of Decoder in
implementation of Boolean function.
The data distributor, known more commonly as a Demultiplexer or “Demux” for short,
is the exact opposite of the Multiplexer we saw in the previous tutorial.
The demultiplexer takes one single input data line and then switches it to any one of a
number of individual output lines one at a time. The demultiplexer converts a serial
data signal at the input to a parallel data at its output lines as shown below.
1-to-4 Channel De-multiplexer
The Boolean expression for this 1-to-4 Demultiplexer above with outputs A to D and
data select lines a, b is given as:
F = ̅̅̅
𝑎𝑏A + a̅bB + ab̅C + abD

4 Channel Demultiplexer using Logic Gates
1-to-8 Demultiplexer
The below figure shows the block diagram of a 1-to-8 demultiplexer that consists of
single input D, three select inputs S2, S1 and S0 and eight outputs from Y0 to Y7.
It is also called as 3-to-8 demultiplexer due to three select input lines. It distributes one
input line to one of 8 output lines depending on the combination of select inputs.
The truth table for this type of demultiplexer is shown below. The input D is connected
with one of the eight outputs from Y0 to Y7 based on the select lines S2, S1 and S0.
For example, if S2S1S0=000, then the input D is connected to the output Y0 and so on.

From this truth table, the Boolean expressions for all the outputs can be written as
follows.
From these obtained equations, the logic diagram of this demultiplexer can be
implemented by using eight AND gates and three NOT gates as shown in below figure.
The different combinations of the select lines , select one AND gate at given time , such
that data input will appear at a particular output.

1-to-16 Demultiplexer
1-to-16 Demultiplexer Working: A demultiplexer obtains in data from one line and directs this to any of
its N outputs depending upon the status of the selected inputs. If the no. of output lines is N (16), no. of
select lines m is specified by 2m = N that is, 24 = 16. Therefore, the no. of select lines required for a 1 to
16 demultiplexer is 4. Table illustrates the Truth Table of this Demultiplexer. The input can be send to
any of the 16 outputs, D0 to D15. The input goes to D0 if DCBA = 0000. The input goes to D1 if DCBA
= 0001 and so on.
Fig.(a) demonstrates the logic diagram of a 1-to-16 demultiplexer, contains 8 NOT gates, 16 NAND
gates, one data input line(G), 4 select lines (A,B,C,D) and 16 output lines (that is D0, D1, D2 ------D16).
8 NOT gates stop excessive loading of the driving source. Individual data input line G is implemented
along with a NOR gate utilized as negative AND gate. A low level in all input G1 and G2 is needed to
make the output G high. The output G of allows is one of the inputs to whole 16 NAND gates. G should
be high for the gates to be allowed. If allow or enable gate is not activated so all 16 de-multiplexer outputs
will be high not respective of the state of the select lines A, B, C, D.
Truth Table

1-to-8 DEMUX using Two 1-to- 4 Demultiplexers
When the application requires a large demultiplexer with more number of output pins,
then we cannot implement by a single integrated circuit. In case if more than 16 output
pins are needed, then two or more demultiplexer ICs are cascaded to fulfill the
requirement.
For example, if the application needs 32 output lines from a DEMUX, then we cascade
two 1:16 demultiplexers or three 1:8 demultiplexers. Therefore, by cascading the two or
more demultiplexers, a large demultiplexer can be implemented.
Consider the case that a 1-to-8 demultiplexer can be implemented by using two 1-to-4
demultiplexers with a proper cascading.
In the above figure, the highest significant bit A of the selection inputs are connected to
the enable inputs such that it is complemented before connecting to one DEMUX and
to the other it is directly connected.
By this configuration, when A is set to zero, one of the output lines from Y0 to Y3 is
selected based on the combination of select lines B and C. Similarly, when A is set to
one, based on the select lines one of the output lines from Y4 to Y7 will be selected.

Binary code of N digits can be used to store 2N distinct elements of coded information. This is what
encoders and decoders are used for. Encoders convert 2N lines of input into a code of N bits
and Decoders decode the N bits into 2N lines.
Encoders –
An encoder is a combinational circuit that converts binary information in the form of a 2 N input lines
into N output lines, which represent N bit code for the input. For simple encoders, it is assumed
that only one input line is active at a time.
As an example, let’s consider Octal to Binary encoder. As shown in the following figure, an octal-
to-binary encoder takes 8 input lines and generates 3 output lines.
As seen from the truth table, the output is 000 when D0 is active; 001 when D1 is active; 010 when
D2 is active and so on.
Implementation –
From the truth table, the output line Z is active when the input octal digit is 1, 3, 5 or 7. Similarly, Y
is 1 when input octal digit is 2, 3, 6 or 7 and X is 1 for input octal digits 4, 5, 6 or 7. Hence, the
Boolean functions would be:
X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7

Z = D1 + D3 + D5 + D7
Hence, the encoder can be realised with OR gates as follows:
One limitation of this encoder is that only one input can be active at any given time. If more than
one inputs are active, then the output is undefined. For example, if D6 and D3 are both active,
then, our output would be 111 which is the output for D7. To overcome this, we use Priority
Encoders.
Another ambiguity arises when all inputs are 0. In this case, encoder outputs 000 which actually is
the output for D0 active. In order to avoid this, an extra bit can be added to the output, called the
valid bit which is 0 when all inputs are 0 and 1 otherwise.
Decoders –
A decoder does the opposite job of an encoder. It is a combinational circuit that converts n lines of
input into 2n lines of output.
Let’s take an example of 3-to-8 line decoder.

Implementation –
D0 is high when X = 0, Y = 0 and Z = 0. Hence,
D0 = X’ Y’ Z’
Similarly,
D1 = X’ Y’ Z
D2 = X’ Y Z’
D3 = X’ Y Z
D4 = X Y’ Z’
D5 = X Y’ Z
D6 = X Y Z’
D7 = X Y Z
Hence,

Decoder as a De-Multiplexer –
A Decoder with Enable input can function as a demultiplexer. A demultiplexer is a circuit that
receives information from a single line and directs it to one of possible output lines.
A demultiplexor receives as input, selection lines and one Input line. These selection lines
are used to select one output line out of possible lines. To implement a demultiplexor, we
use a decoder with Enable input. The selection lines of the demultiplexer are
the input lines that the decoder gets and the one input line of demulitplexer is the Enable input
of the Decoder.
Making 1:4 demultiplexer using 2:4 Decoder with Enable input. Let A, B be the selection lines and
EN be the input line for the demultiplexer.
The decoder shown below functions as a 1:4 demultiplexer when EN is taken as a data input line
and A and B are taken as the selection inputs. The single input variable E has a path to all four
outputs, but the input information is directed to only one of the output lines, as specified by the
binary combination of the two selection lines A and B. This can be verified from the truth table of
the circuit.
Truth Table-
Combinational Logic Implementation using Decoder –

A decoder takes input lines and has output lines. These output lines can provide
the minterms of input variables.
Since any boolean function can be expressed as a sum of minterms, a decoder that can generate
these minterms along with external OR gates that form their logical sums, can be used to form a
circuit of any boolean function.
For example, if we need to implement the logic of a full adder, we need a 3:8 decoder and OR
gates. The input to the full adder, first and second bits and carry bit, are used as input to the
decoder. Let x, y and z represent these three bits. Sum and Carry outputs of a full adder have the
following truth tables-

Therefore we have-
The following circuit diagram shows the implementation of Full adder using a 3:8 Decoder and OR
gates.

Design of different code converter, BCD to 7
3.9
segment decoder, Comparator, Parity Checker

and Generator
Theory
Binary Codes:
A symbolic representation of data/ information is called code. The base or radix of the
binary number is 2. Hence, it has two independent symbols. The symbols used are 0
and 1. A binary digit is called as a bit. A binary number consists of sequence of bits,
each of which is either a 0 or 1. Each bit carries a weight based on its position relative
to the binary point. The weight of each bit position is one power of 2 greater than the
weight of the position to its immediate right. e. g. of binary number is 100011 which is
equivalent to decimal number 35.
BCD Codes:
Numeric codes represent numeric information i.e. only numbers as a series of 0’s and
1’s. Numeric codes used to represent decimal digits are called Binary Coded Decimal
(BCD) codes. A BCD code is one, in which the digits of a decimal number are encoded-
one at a time into group of four binary digits. There are a large number of BCD codes
in order to represent decimal digits0, 1, 2,……9, it is necessary to use a sequence of at
least four binary digits. Such a sequence of binary digits which represents a decimal
digit is called code word.
Gray Codes:
It is a non-weighted code; therefore, it is not a suitable for arithmetic operations. It is
a cyclic code because successive code words in this code differ in one bit position only
i.e. it is a unit distance code.
Applications of Gray Code:
1. In instrumentation and data acquisition system where linear or angular
displacement is measured.
2. In shaft encoders, input-output devices, A/D converters and the other
peripheral equipment.
Excess-3 code:
It is a non-weighted code. It is also a self-complementing BCD code used in decimal
arithmetic units. . The Excess-3 code for the decimal number is performed in the same
manner as BCD except that decimal number 3 is added to the each decimal unit before
encoding it to binary.
Code Converters:
The availability of a large variety of codes for the same discrete elements of information
results in the use of different codes by different digital systems. It is some time
necessary to use the output of one system as the input to the other. The conversion
circuit must be inserted between the two systems if each uses different codes for the
same information. Thus a code converter is a circuit that makes the two systems
compatible even though each uses the different code.

Binary to gray code:
Truth Table:
No. Binary Gray

D C B A G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 1 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Table 1: Binary to Gray Converter
Equations:
Diagram:
Logic diagram for Binary to Gray Convertor is given below:

Gray to Binary:
No. Gray Binary

G3 G2 G1 G0 D C B A
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 1 0 0 1 0
3 0 0 1 0 0 0 1 1
4 0 1 1 0 0 1 0 0
5 0 1 1 1 0 1 0 1
6 0 1 0 1 0 1 1 0
7 0 1 1 0 0 1 1 1
8 1 1 0 0 1 0 0 0
9 1 1 0 1 1 0 0 1
10 1 1 1 1 1 0 1 0
11 1 1 1 0 1 0 1 1
12 1 0 1 0 1 1 0 0
13 1 0 1 1 1 1 0 1
14 1 0 0 1 1 1 1 0
15 1 0 0 0 1 1 1 1
Table 2: Gray to Binary Converter
Equations:
Diagram:

BCD to Excess-3:
To convert from binary code A to binary code B, the input lines must supply the bit combination of elements as
specified by code A and the output lines must generate the corresponding bit combination of code B. A combinational
circuit performs this transformation by means of logic gates. As we want to design 4-bit code, we must use four
input variables and four output variables. Designate the four input binary variables by the symbols A,B,C,D, and the
four output variables by w, x, y, and z. The truth table relating the input and output variables is as shown. A two-
level logic diagram may be obtained directly from the Boolean expressions derived by the maps. The expressions
obtained may be manipulated for the purpose of using common gates for two or more outputs. This manipulation
illustrates flexibility obtained with multiple-output systems when implemented with three or more levels of gates.
Decimal BCD Excess-3

Digit A B C D w x y Z
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
Table 3: BCD to Excess-3 Converter
Equations:
z=D
y = CD+C’D’=CD(C+D)’
x = B’C+B’D+BC’D’= B’(C+D) +BC’D’
x = B’(C+D) +B(C+D)’
w = A+BC+BD=A+B(C+D)
Diagram:
Logic Diagram for BCD to Excess-3 Code Converter

How to design a 3-bit Binary to Gray Code
Converter?
To convert a 3-bit binary to gray code, you need to follow a few rules/formulae.
The MSB of the binary code is always equal to the MSB of the gray code. The following
bits of the gray code can be obtained by EXORing the corresponding binary bit and the
preceding binary bit. If that’s confusing, just remember this figure below.
Hence for 3-bit code converters,

G2 = B2
G1 = B1 B2
G0 = B0 B1
Based on the above equations, we can plot the following circuit diagram for a 3-
bit binary to gray code converter using EX-OR logic gates.

Truth Table for a 3-bit binary to gray code converter
B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
Note: Notice how each subsequent gray code number differs with its predecessor by
only one bit.
How to design a 4-bit Binary to Gray Code

Converter?
The process is similar to the one we saw above. The MSBs are going to be equal. The
subsequent gray code bit will be obtained by EXORing the corresponding binary bit
with the preceding binary bit. Here’s a similar diagram to the one above to help you
visualize the formula.
Based on this
G3 = B3
G2 = B2 B3
G1 = B1 B2
G0 = B0 B1
The equations above indicate the presence of three EXOR gates. Therefore the simple
combinational circuit for 4-bit binary to gray code converters is as shown below.

Truth Table for a 4-bit binary to gray code converter
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

How to design 3-bit Gray to Binary Code
Converters?
To convert from gray to binary, a slightly different approach from the one we saw above
is used. The MSBs are always equal. The next binary bit is obtained by EXORing the
corresponding gray code bit with the preceding binary bit. Let’s take a look at a visual
representation to get a clearer picture of the formula.
Based on this
B2 = G2
B1 = G1 B2
B0 = G0 B1

Truth Table for a 3-bit gray to binary code converter
G2 G1 G0 B2 B1 B0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 1 0 0
1 1 1 1 0 1
How to design a 4-bit Gray to Binary Code

Converter?
Similar to the method above, a 4 bit gray to binary converter’s truth table can be
prepared.
B3 = G3
B2 = G2 B3
B1 = G1 B2
B0 = G0 B1
Truth Table for a 4-bit gray to binary code converter

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
The circuit obtained by olving the K-maps for the above truth table is as below.

How to design a 3-bit Binary to Excess-3 Code
Converter?
An excess 3 code, as can be predicted from its name, is an excess of three of the
binary number. Simply add three to a binary number and represent that in binary form,
that will be your excess 3/xs3 code. So 0000 in binary will be equivalent to (0+3=3)
0011 in excess 3.
Yes, the number is written in binary format, and that can be a source of confusion.
Think of it this way. You have a normal number system. However, your friend wants to
be unique and says that for him, a six will be equal to your three. The representation is
the same. However, the values differ by three.
B2 B1 B0 E2 E1 E0
0 0 0 0 1 1
0 0 1 1 0 0
0 1 0 1 0 1
0 1 1 1 1 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 x x x
Let’s obtain the equations for the code converter circuit using K-maps.
E2 = B0 + B1 + B1’B2 OR E2 = B0 + B1 + B2 (if you take cells 4,5,6,7) (both are

correct)

E1 = B2 +
E0 = B0′
Hence, from the equations above we can design the following combinational logic
circuit for 3-bit binary to excess 3 code converter circuit.

How to design a 4-bit Binary to Excess-3 Code
Converter?
Following our footsteps from the designing of 3-bit binary to excess 3 code
converters, we will first draft a truth table for the 4-bit version.
Truth Table for a 4-bit binary to excess 3 code converter

B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 1 1 0 1
1 0 1 1 1 1 1 0
1 1 0 0 1 1 1 1
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
Using Kmaps, we will solve for the output terminals. Remember that since we have
don’t care conditions, there are more than one correct options for reducing the Kmap.
You might end up with different equations than the ones in this post.
You should always try to optimize for the equation that requires you to employ the least
number of logic gates.
This is because when you etch a logic circuit into an IC chip, the real estate of the chip
is an expensive resource. And the least number of logic gates that you use, the higher
will be the judicious use of space on the IC.

E3 = B2(B0 + B1) + B3
E2 = B2′(B0 + B1) + B0’B1’B2

E1 =
From the truth table
E0 = B0′
Using the above equations. we can draw the following logic circuit diagram for 4-
bit binary to excess 3 code converters.
BCD to Seven Segment Display

Decoder Theory
In Binary Coded Decimal (BCD) encoding scheme each of the decimal numbers(0-9) is
represented by its equivalent binary pattern(which is generally of 4-bits).
Whereas, Seven segment display is an electronic device which consists of seven Light Emitting
Diodes (LEDs) arranged in a some definite pattern (common cathode or common anode type),
which is used to display Hexadecimal numerals(in this case decimal numbers,as input is BCD i.e.,
0-9).
Two types of seven segment LED display:
1. Common Cathode Type: In this type of display all cathodes of the seven LEDs are
connected together to the ground or -Vcc(hence,common cathode) and LED displays digits
when some ‘HIGH’ signal is supplied to the individual anodes.
2. Common Anode Type: In this type of display all the anodes of the seven LEDs are
connected to battery or +Vcc and LED displays digits when some ‘LOW’ signal is supplied to
the individual cathodes.
But, seven segment display does not work by directly supplying voltage to different segments of
LEDs. First, our decimal number is changed to its BCD equivalent signal then BCD to seven
segment decoder converts that signals to the form which is fed to seven segment display.
This BCD to seven segment decoder has four input lines (A, B, C and D) and 7 output lines (a, b,
c, d, e, f and g), this output is given to seven segment LED display which displays the decimal
number depending upon inputs.

The Seven segment display is most frequently used the digital display in calculators, digital
counters, digital clocks, measuring instruments, etc. Usually, the displays like LED’s as well
as LCD’s are used to display the characters as well as numerical numbers. But, a seven
segment display is used to display both the numbers and characters. These displays are
frequently driven by the output phases of digital integrated circuits like decade counters as
well as latches. However the outputs of these are in the type of 4-bit BCD (Binary Coded
Decimal), so not appropriate for directly operating the seven segment display. For that, a
display decoder can be employed for converting BCD code to seven segment code. Generally,
it has four input lines as well as seven output lines. This article discusses how to design a
BCD to seven segment display decoder circuit using logic gates.
BCD to Seven Segment Display Decoder Theory

The decoder is an essential component in BCD to seven segment decoder. A decoder is
nothing but a combinational logic circuit mainly used for converting a BCD to an equivalent
decimal number. It can be a BCD to seven segment decoder. A combinational logic circuit can
be built with logic gates which include inputs as well as outputs. The output of this circuit
mainly lies in the current condition of the inputs. The best examples of this circuit
are multiplexers, demultiplexers, adders, subtractors, encoders, decoders, etc.

BCD to Seven Segment Display
The circuit design, as well as operation, mainly depends on the concepts of Boolean
algebra as well as logic gates. A seven segment LED display circuit can be built with eight
LEDs. The common terminals are either anode otherwise cathode. A general cathode seven
segment display includes 8 pins where 7-pins are input pins that are marked with from a to
g & 8th-pin is a ground pin.
Design of BCD to 7 Segment Display Decoder Circuit
The designing of BCD to seven segment display decoder circuit mainly involves four steps
namely analysis, truth table design, K-map and designing a combinational logic circuit using
logic gates.
The first step of this circuit design is an analysis of the common cathode seven segment
display. This display can be constructed with seven LEDs in the form of H. A truth table of
this circuit can be designed by the inputs combinations for every decimal digit. For instance,
decimal number ‘1’ would control a blend of b & c.
The second step is the truth table design by listing the display input signals-7, equivalent
four-digit binary numbers as well as decimal number.
The designing of the truth table for the decoder mainly depends on the kind of display.
Already we have discussed above that is, for a common cathode display, the decoder output
must be high in order to blink the segment.
The tabular form of a BCD to 7-segment decoder with a common cathode display is shown
below. The truth table consists of seven o/p columns equivalent to each of the seven
segments. For example, the column for a-segment illustrates the various arrangements for
which it is to be light up. Thus ‘a’- segment is energetic for the digits like 0, 2, 3, 5, 6, 7, 8 &
9.
By using the above truth table, for every output function, the Boolean expression can be
written.
a = F1 (X, Y, Z, W) = ∑m (0, 2, 3, 5, 7, 8, 9)

b = F2 (X, Y, Z, W) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)
c = F3 (X, Y, Z, W) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)
d = F4 (X, Y, Z, W) = ∑m (0, 2, 3, 5, 6, 8)

e = F5 (X, Y, Z, W) = ∑m (0, 2, 6, 8)
f = F6 (X, Y, Z, W) = ∑m (0, 4, 5, 6, 8, 9)
g = F7 (X, Y, Z, W) = ∑m (2, 3, 4, 5, 6, 8, 9)

The third step in this design mainly involves designing the K-map (Karnaugh’s map) for
every output expression as well as then shortening them to get inputs logic combination for
every output.
Simplification of Karnaugh -Map

The simplification of k-map of the common cathode 7 segment decoder can be done in order
to plan the combinational circuit. From the above K-map simplification, we can get the
output equations like these
a = X+Z+YW+Y’W’
b = Y’+Z’W’+ZW
c= Y+Z’+W
d = Y’W’+ZW’+YZ’W+Y’Z+X
e= Y’W’+ZW’
f= X + Z’W’+YZ’+YW’
g = X+YZ’+Y’Z+ZW’
The final step of this is a designing of a logic circuit using the above k-map equations. A
combinational circuit can be built by using 4-inputs namely A, B, C, D and outputs on display
like a, b, c, d, e, f, g. The operation of the above logic circuit can be understood with the help
of truth table only. Once all the i/ps are connected to small logic.

BCD to Seven Segment Decoder Circuit
Then the combinational logic circuit’s output will drive each and every one of output LEDs
apart from ‘g’ to transmission. Therefore the number ‘0’ will be exhibited. Similarly, for all
another grouping of the input switches, the same process would take place.
BCD Seven Segment Display Using IC 7447

Basically, light emitting diodes are two types’ namely CC-common cathode as well as CA-
common anode. In common cathode, all the eight anode terminals use only a single cathode
terminal, which is familiar. Whereas in common anode, the familiar terminal for all the
cathode terminal is of anode type.

BCD Seven Segment Display Using IC7447
A decoder is one kind of combinational logic circuit that connects the binary data from n-
input lines toward 2n output lines. The IC7447 IC is a BCD to seven segment decoder. This
IC7447 gets the binary coded decimal like the input as well as gives the outputs like the
related seven-segment code.
What is a Digital Comparator and

Magnitude Comparator
Nowadays, electronics are completely a part of human life and the whole world observes
dramatic progress in the utilization of electronic devices. Providing many advantages,
electronics is now so prevalent that it’s almost streamlined to think of the devices that don’t
make use of it than that of devices that do. The enhanced trend in electronic technology
today allowed us to discuss the widely used devices digital comparator and magnitude
comparators. Then after the extensive performance of operational amplifiers, the most
widely accepted simple electronic devices are comparators. So, let’s dive deep into the topics
of what is a digital comparator, its operation, performance, and applications.
Digital Comparator And Magnitude Comparator
A detailed discussion of digital comparator and magnitude comparator mainly includes the
following.
What is Digital Comparator?

A digital comparator or magnitude comparator is a hardware electronic device that takes two
numbers as input in binary form and determines whether one number is greater than, less than or
equal to the other number. Comparators are used in central processing unit s (CPUs)
and microcontrollers (MCUs). Examples of digital comparator include the CMOS 4063 and 4585
and the TTL 7485 and 74682.
Note: An XNOR gate is a basic comparator, because its output is "1" only if its two input bits are
equal.
The analog equivalent of digital comparator is the voltage comparator. Many microcontrollers have
analog comparators on some of their inputs that can be read or trigger an interrupt.
As data comparison is mostly required in many digital systems at the time of logical or
arithmetic functions, digital comparators are the one best option to compare data. Digital
comparators are the most appropriate combinational logic circuits used to compare relative
magnitudes of two binary numbers.
The device accepts two binary numbers (A and B)as input and generates an output based
on the magnitude of given inputs (example: A=B or A>B or A<B). Digital Comparators are
developed through logic gates like AND, NOT or NOR gates. Digital comparators are available
as identity comparators and magnitude comparators.
What is Magnitude Comparator?
Magnitude comparators are mostly utilized in microcontrollers and CPUs to address data
comparison, register and perform all other arithmetic operations. Magnitude comparators
are implemented in many devices and every auto-turn-off device is surely designed using a
comparator.
A comparator is a decision-making tool and it holds the ability to be executed in numerous
control devices. Accepting two binary numbers as input (A and B), data comparison through
magnitude comparators produces the output to indicate equality (A=B), logic 1 in two
conditions when (A>B or A<B).
Types of Magnitude Comparators
There are different kinds of magnitude comparators which include the following.
1-bit Magnitude Comparator

A comparator that compares two binary bits and produces three outputs based on the
relative magnitudes of given binary bits is called a 1-bit magnitude comparator.
Truth Table
B AB
A A=B
0
0 0 0 1
0 0
1 1 0
0
1 0 0 1
1
1 1 0 0
The truth table derives the expressions of A<B, A>B and A=B as below
AB – AB’
A=B – A’B’+AB
With these expressions, the Circuit diagram can be as follows

A comparator that compares two binary numbers (each number having 2 bits) and produces
three outputs based on the relative magnitudes of given binary bits is called a 2-bit
magnitude comparator.
Truth Table
A0 B1 B0 AB
A1
0
0 0 0 0 1 0
0 0
0 0 1 1 0
0
0 0 1 0 1 0
0 0
0 1 1 1 0
1
0 1 0 0 0 0
0 0
1 0 1 0 1
0 0 0
1 1 0 1
0 0
1 1 1 1 0
1 0 1
0 0 0 0

1 1
0 0 1 0 0
1 0 0
1 0 0 1
1 0
0 1 1 1 0
1
1 0 0 0 0 1
1 1
1 0 1 0 0
1 1
1 1 0 0 0
0
1 1 1 1 0 1
The truth table derives the expressions of A<B, A>B, and A=B as below
AB – A1B1’ + A0B1’B0’ + A1A0B0’
A=B – (A0 Ex-Nor B0) (A1 Ex-Nor B1)
With these expressions, the Circuit diagram can be as follows
2-bit magnitude
3-bit magnitude
The equal functions are A0 = B0, A1= B1, A2 = B2

Then A=B = (A0’B0’ + A0B0)(A1’B1’ + A1B1)(A2’B2’ + A2B2)
The output is A B in the cases of
A2>B2
A2 = B2 then A1>B
A2 = B2, A1 = B1 then A0>B0
A>B = A2B2’ + + [(A2’B2’ + A2B2) * A1B1’] + + [(A2’B2’ + A2B2) * [(A1’B’ + A1B1) *
A0B0’]

3-bit-logic-diagram

The input bits can be termed as A = A3 A2 A1 A0 and B = B3 B2 B1 B0

The output is A> B in the cases of
A3 = 1 and B3 = 0
A3 = B3 and A2 = 1, B2 = 0
A3 = B3 and A2= B2 and A1 = 1 and B1 = 0
A3 = B3 and A2= B2 and A1 = B1 and A0 = 1 and B0 = 0
And A>B can be expressed as
A>B = A3B3’ + (A3 Ex-Nor B3) A2B2’ + (A3 Ex-Nor B3) (A2 Ex-Nor B2) A1B1’ + (A3 Ex-
Nor B3) (A2 Ex-Nor B2) (A1 Ex-Nor B1) A0B0’
While
A<B = A3‘B3 + (A3 Ex-Nor B3) A2’B2 + (A3 Ex-Nor B3) (A2 Ex-Nor B2) A1’B1 + (A3 Ex-
Nor B3) (A2 Ex-Nor B2) (A1 Ex-Nor B1) A0’B0
And similarly, A=B can be expressed as
A=B = (A3 Ex-Nor B3) (A2 Ex-Nor B2) (A1 Ex-Nor B1)(A0 Ex-Nor B0)
With these expressions, the Circuit diagram can be as follows.

4-bit-magnitude
Mostly, 4-bit comparators are in the form of IC’s and the IC 7485 is widely used. Data
comparison can be performed by grounding A>B, A<B and A+B inputs to the Vcc terminal.
Furthermore, this integrated circuit performs a cascading operation where it helps for
cascading multiple comparators.
Here, data comparison is possible through the cascading of two 4-bit comparators. The
circuit is connected as below

8-bit-magnitude
The outputs of the lower-order comparator are connected to the corresponding cascading
inputs of the higher-order comparator
In the lower order comparator, the cascading input (A=B) needs to be connected HIGH, and
A, B needs to be connected to LOW. The result of the 8-bit comparator is the output of the
higher-order comparator.
Applications Comparator
Digital comparator and magnitude comparator is used in different applications where data
comparison is mostly required in many of the activities, and these hold many benefits too.
 Now, look into few of the applications of comparators

 Used for authorization purposes (such as password management) and biometric applications.
 These are implemented in process controllers and also in servo motor controls.
 Implemented for the data comparison of variables like temperature, the pressure is compared
with that of reference values.
 Used to address decoding circuitry in computers.

Parity generator and checker
A parity generator is a combinational logic circuit that generates the parity bit in the
transmitter. On the other hand, a circuit that checks the parity in the receiver is called
parity checker. A combined circuit or devices of parity generators and parity checkers
are commonly used in digital systems to detect the single bit errors in the transmitted
data word.
The sum of the data bits and parity bits can be even or odd . In even parity, the added
parity bit will make the total number of 1s an even amount whereas in odd parity the
added parity bit will make the total number of 1s odd amount.
The basic principle involved in the implementation of parity circuits is that sum of odd
number of 1s is always 1 and sum of even number of 1s is always zero. Such error
detecting and correction can be implemented by using Ex-OR gates (since Ex-OR gate
produce zero output when there are even number of inputs).
To produce two bits sum, one Ex-OR gate is sufficient whereas for adding three bits
two Ex-OR gates are required as shown in below figure.
Parity Generator
It is combinational circuit that accepts an n-1 bit stream data and generates the
additional bit that is to be transmitted with the bit stream. This additional or extra bit is
termed as a parity bit.
In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the
data stream and the parity bit is ‘1’ if there are odd number of 1s in the data stream.
In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data
stream and the parity bit is ‘0’ if there are odd number of 1s in the data stream. Let us
discuss both even and odd parity generators.

Even Parity Generator
Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the
three inputs A, B and C are applied to the circuits and output bit is the parity bit P. The
total number of 1s must be even, to generate the even parity bit P.
The figure below shows the truth table of even parity generator in which 1 is placed as
parity bit in order to make all 1s as even when the number of 1s in the truth table is
odd.
The K-map simplification for 3-bit message even parity generator is

From the above truth table, the simplified expression of the parity bit can be written as
The above expression can be implemented by using two Ex-OR gates. The logic
diagram of even parity generator with two Ex – OR gates is shown below. The three bit
message along with the parity generated by this circuit which is transmitted to the
receiving end where parity checker circuit checks whether any error is present or not.
To generate the even parity bit for a 4-bit data, three Ex-OR gates are required to add
the 4-bits and their sum will be the parity bit.
Odd Parity Generator
Let us consider that the 3-bit data is to be transmitted with an odd parity bit. The three
inputs are A, B and C and P is the output parity bit. The total number of bits must be
odd in order to generate the odd parity bit.
In the given truth table below, 1 is placed in the parity bit in order to make the total
number of bits odd when the total number of 1s in the truth table is even.

The truth table of the odd parity generator can be simplified by using K-map as
The output parity bit expression for this generator circuit is obtained as
P = A ⊕ B Ex-NOR C
The above Boolean expression can be implemented by using one Ex-OR gate and one
Ex-NOR gate in order to design a 3-bit odd parity generator.
The logic circuit of this generator is shown in below figure , in which . two inputs are
applied at one Ex-OR gate, and this Ex-OR output and third input is applied to the Ex-
NOR gate , to produce the odd parity bit. It is also possible to design this circuit by
using two Ex-OR gates and one NOT gate.

Parity Check
It is a logic circuit that checks for possible errors in the transmission. This circuit can be
an even parity checker or odd parity checker depending on the type of parity generated
at the transmission end. When this circuit is used as even parity checker, the number of
input bits must always be even.
When a parity error occurs, the ‘sum even’ output goes low and ‘sum odd’ output goes
high. If this logic circuit is used as an odd parity checker, the number of input bits
should be odd, but if an error occurs the ‘sum odd’ output goes low and ‘sum even’
output goes high.
Even Parity Checker

Consider that three input message along with even parity bit is generated at the
transmitting end. These 4 bits are applied as input to the parity checker circuit which
checks the possibility of error on the data. Since the data is transmitted with even
parity, four bits received at circuit must have an even number of 1s.

If any error occurs, the received message consists of odd number of 1s. The output of
the parity checker is denoted by PEC (parity error check).
The below table shows the truth table for the even parity checker in which PEC = 1 if
the error occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no
error occurs, i.e., if the 4-bit message has even number of 1s.
The above truth table can be simplified using K-map as shown below.

The above logic expression for the even parity checker can be implemented by using
three Ex-OR gates as shown in figure. If the received message consists of five bits,
then one more Ex-OR gate is required for the even parity checking.
Odd Parity Checker

Consider that a three bit message along with odd parity bit is transmitted at the
transmitting end. Odd parity checker circuit receives these 4 bits and checks whether
any error are present in the data.
If the total number of 1s in the data is odd, then it indicates no error, whereas if the total
number of 1s is even then it indicates the error since the data is transmitted with odd
parity at transmitting end.
The below figure shows the truth table for odd parity generator where PEC =1 if the 4-
bit message received consists of even number of 1s (hence the error occurred)
and PEC= 0 if the message contains odd number of 1s (that means no error).

The expression for the PEC in the above truth table can be simplified by K-map as
shown below.
After simplification, the final expression for the PEC is obtained as
PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR D)

The expression for the odd parity checker can be designed by using three Ex-NOR
gates as shown below.
Parity Generator/Checker ICs

There are different types of parity generator /checker ICs are available with different
input configurations such as 5-bit, 4-bit, 9-bit, 12-bit, etc. A most commonly used and
standard type of parity generator/checker IC is 74180.
It is a 9-bit parity generator or checker used to detect errors in high speed data
transmission or data retrieval systems. The figure below shows the pin diagram of
74180 IC.
This IC can be used to generate a 9-bit odd or even parity code or it can be used to
check for odd or even parity in a 9-bit code (8 data bits and one parity bit).
This IC consists of eight parity inputs from A through H and two cascading inputs.
There are two outputs even sum and odd sum. In implementing generator or checker
circuits, unused parity bits must be tied to logic zero and the cascading inputs must not
be equal.

RESOURCES :
1. https://www.geeksforgeeks.org/
2. https://www.allaboutcircuits.com/
3. https://www.electronics-tutorials.ws/
4. https://www.electronicshub.org/

QUESTIONS OR ASSIGNMENTS
1. Simplify: (A + C)(AD + AD̅) + AC + C
2. Simplify: A̅(A + B) + (B + AA)(A + B̅)
3. Identify each of these logic gates by name, and complete their respective truth
tables:
4. Implement the Boolean function by using basic logic gates.

F = A B C + A B C̅+ A̅ B C̅
5. Implement the Boolean function by using basic logic gates.
F = (A + B + C) * (A̅ + B̅ +C) * (A + B̅ + C)
6. Inspect each of these Boolean expressions, and determine whether each one is
a sum of products, or a product of sums:

7. Simplify the following Boolean function using K-map
f W,X,Y,Z= WX’Y’ + WY + W’YZ’
f(X,Y,Z)=∏M(0,1,2,4)
f A,B,B,C,D = A̅.B̅.C.̅ D̅ + A̅.B.C.̅ D + A̅.B.C.̅ D̅ + A.B̅.C.̅ D̅ + A̅.B̅.C.D̅ + A.B̅.C.D̅ + A̅.B̅.C.̅ D
10. Implement the given logic function using a 4:1 multiplexer
F(A,B,C) =∑ 𝑚(1,2,6,7)
F(A,B,C) =∑ 𝑚(0,2,3,6,7)
F(A,B,C,D) =∑ 𝑚(2,4,5,7,8,12,13,15)
13. Implement the given logic function using a 1:4 demultiplexer
F(A,B,C) =∑ 𝑚(0,1,5,6,7)
F(A,B,C) =∑ 𝑚(0,2,4,5,7)
F(A,B,C,D) =∑ 𝑚(0,1,3,7,8,10,13,14)
F(A,B,C,D) =∑ 𝑚(1,2,5,7,8,10,11,13,14)
F(A,B,C,D,E) =∑ 𝑚(0,1,3,7,8,10,13,14,18,20,21,22,25,27,29,31)
F(A,B,C,D,E) =∑ 𝑚(1,2,3,5,7,9,10,12,13,14,16,18,20,21,22,24,26,28,29,31)
19. Write the truth table for common cathode type BCD to seven segment
decoder.
20. Draw a 3-bit odd parity checker and a 4-bit odd parity generator

ABOUT DEVELOPER
Developer’s name: Anupam Samanta, Lecturer in
Computer Science &Technology
About: Started teaching since 2005.

He has experience to this
subject more than 14 years.
Obtained his B.Tech degree
from Haldia Institute of
Technology and M.E. in
Computer Science and
Engineering from
Jadavpur University.

Anupam Sir DLD3

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Bipradas Pal Chowdhury Institute of Technology

DEPARTMENT OF COMPUTER SCIENCE & TECHNOLOGY

Computer Science &Technology

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 2|Page

Description of the Laws of Boolean Algebra :

o A.0=0 A variable AND’ed with 0 is always equal to 0

o A + 0 = A A variable OR’ed with 0 is always equal to the variable

o A+A=A A variable OR’ed with itself is always equal to the variable

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 3|Page

o A .A̅= 0 A variable AND’ed with its complement is always equal to 0

o A.B=B.A The order in which two variables are AND’ed makes no

o A̿ = A A double complement of a variable is always equal to the

de Morgan´s Theorem – There are two “de Morgan´s” rules or theorems,

Other algebraic Laws of Boolean not detailed above include:

o A(B + C) = A.B + A.C (OR Distributive Law)

Absorptive Law – This law enables a reduction in a complicated expression to a

o A + (A.B) = A (OR Absorption Law)

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 4|Page

o A + (B + C) = (A + B) + C = A + B + C (OR Associate Law)

Using the above laws, simplify the expression: (A + B)(A + C)

A.A + A.C + A.B + B.C – Distributive law

A + A.C + A.B + B.C – Idempotent AND law (A.A = A)

A(1 + C) + A.B + B.C – Distributive law

A.1 + A.B + B.C – Identity OR law (1 + C = 1)

A(1 + B) + B.C – Distributive law

A.1 + B.C – Identity OR law (1 + B = 1)

Q= A + (B.C) – Identity AND law (A.1 = A)

Then the expression: (A + B)(A + C) can be simplified to A + (B.C) as in the

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 5|Page

AB + AB + AC + B + BC – Idempotent AND law ( BB = B )

AB + AC + B + BC – Idempotent OR law (AB + AB = AB)

AB + AC + B – Absorptive OR Law (B + B.C = B)

Q= B+AC – Absorptive OR Law (B +AB = B)

Then the expression: AB + A(B + C) + B(B + C) can be simplified to B+AC.

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 6|Page

2-input AND Gate

Symbol Truth Table

Boolean Expression Q = A.B Read as A AND B gives Q

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 7|Page

Symbol Truth Table

Boolean Expression Q = A+B Read as A OR B gives Q

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 8|Page

Symbol Truth Table

Boolean Expression Q = NOT A or A̅ Read as inversion of A gives Q

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 9|Page

Symbol Truth Table

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 10 | P a g e

Symbol Truth Table

Boolean Expression Q =̅̅̅̅̅̅̅̅

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 11 | P a g e

Symbol Truth Table

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 12 | P a g e

Symbol Truth Table

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 13 | P a g e

For example, the outputs of the first three gates:

. . . then another sub-expression for the next gate:

Bipradas Pal Chowdhury Institute of Technology, Digital Logic Design 14 | P a g e

Q. Convert the following logic gate circuit into a Boolean expression,