The document discusses DDR3 SDRAM memory. It explains that DDR3 reads and writes data on both the rising and falling clock edges, allowing it to transfer data twice as fast as SDRAM. It provides terminology for DDR3 clock frequencies and data rates. It describes the typical components of a DDR3 memory controller subsystem and details the DDR3 architecture, prefetch, and pinout. It also covers concepts like on-die termination, command descriptions, mode registers, and read/write operations.
The document discusses DDR3 SDRAM memory. It explains that DDR3 reads and writes data on both the rising and falling clock edges, allowing it to transfer data twice as fast as SDRAM. It provides terminology for DDR3 clock frequencies and data rates. It describes the typical components of a DDR3 memory controller subsystem and details the DDR3 architecture, prefetch, and pinout. It also covers concepts like on-die termination, command descriptions, mode registers, and read/write operations.
The document discusses DDR3 SDRAM memory. It explains that DDR3 reads and writes data on both the rising and falling clock edges, allowing it to transfer data twice as fast as SDRAM. It provides terminology for DDR3 clock frequencies and data rates. It describes the typical components of a DDR3 memory controller subsystem and details the DDR3 architecture, prefetch, and pinout. It also covers concepts like on-die termination, command descriptions, mode registers, and read/write operations.
The document discusses DDR3 SDRAM memory. It explains that DDR3 reads and writes data on both the rising and falling clock edges, allowing it to transfer data twice as fast as SDRAM. It provides terminology for DDR3 clock frequencies and data rates. It describes the typical components of a DDR3 memory controller subsystem and details the DDR3 architecture, prefetch, and pinout. It also covers concepts like on-die termination, command descriptions, mode registers, and read/write operations.
DDR (Double Data Rate) memory is the next generation
SDRAM. Like SDRAM, DDR is synchronous with the system clock. The big difference between DDR and SDRAM memory is that DDR reads data on both the rising and falling edges of the clock signal. SDRAM only carries information on the rising edge of a signal.
Basically this allows the DDR module to transfer data twice as
fast as SDRAM. For example, instead of a data rate of 133MHz, DDR memory transfers data at 266MHz. DDR SDRAM also consumes less power, which makes it ideal for notebook computers.
3 Typical DDR3 Memory Controller Sub-system along with its various components
4 DDR Architecture
The DDR3 SDRAM uses a double data rate
architecture to achieve high speed operation. The double data rate architecture is essentially a 8n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM consists of : A single read or write operation for the DDR3 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins
5 6 DDR3 Prefetch DDR3 is still a DDR because with each cycle two bits are being transmitted through 2 data eyes, it behaves exactly the same as all other DDR SDRAM, except that it has a 8n prefetch DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s
7 High Speed Memory Design Considerations
The Signal integrity is an challenging issue in High
speed design. The following effects are more important in High Speed Design and can cause data corruption. Reflection Crosstalk and interference SSN (simultaneously switching noise) Following solutions are employed to improve signal integrity. On die Termination (ODT) Off chip Driver Calibration (OCD) On die Decoupling
8 ODT ( On-die termination )
On-die termination (ODT) has been added to the DDR3 data
signals to improve signal integrity in the system. The termination value of RTT is the Thevinen equivalent of the resistors that terminate the DQ inputs to VssQ and VDDQ. An ODT pin is added to the DRAM so the system can turn the termination on and off as needed.
9 Pinout Description Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers Chip Select: All commands are masked when CS# is registered HIGH. CS# provides for external Rank selection on systems with multiple Ranks. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data 10 during a Write access. Pinout Description Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write, or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle Address Inputs: Provide the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank (A0-A15) Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation Burst Chop: A12 / BC# is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be perform Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when RESET# is HIGH. RESET# must be HIGH during normal operationed 11 Pinout Description Data Input/ Output (DQ): Bi-directional data bus Data Strobe (DQS): output with read data, input with write data. Edge- aligned with read data, centered in write data ZQ : Reference Pin for ZQ calibration VDDQ : DQ Power Supply: 1.5 V +/- 0.075 V VSSQ : DQ Ground VDD : Power Supply: 1.5 V +/- 0.075 V VSS : Ground VREFDQ : Reference voltage for DQ VREFCA : Reference voltage for CA
12 Simplified State Diagram
13 Mode Registers For application flexibility, various functions, features, and modes are programmable in four Mode Registers (MR0 – MR3)
They are programmed via a Mode Register Set (MRS) command
The default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e., written, after power up and/or reset MR0 : Ref Page 38 MR1 : Ref Page 41 MR2 : Ref Page 44 MR3 : Ref Page 46
14 Mode Registers The Mode Registers (MR0 to MR3) are written by asserting low on CS#, RAS#, CAS#, WE#, and select appropriate values on BA0, BA1 and BA2,
15 Command Description Mode Register Set : MRS Refresh : REF Self Refresh Entry : SRE Self Refresh Exit : SRX Single Bank Precharge : PRE Precharge all Banks : PREA Bank Activate : ACT Write (Fixed BL8 or BC4) : WR Write with Auto Precharge (Fixed BL8 or BC4) : WRA Read (Fixed BL8 or BC4) RD Read with Auto Precharge (Fixed BL8 or BC4) RDA No Operation NOP Device Deselected DES Power Down Entry PDE Power Down Exit PDX ZQ Calibration Long ZQCL ZQ Calibration Short ZQCS 16 No OPeration (NOP) Command The No OPeration (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP
(CS# LOW and RAS#, CAS#, and WE# HIGH).
This prevents unwanted commands from being registered during idle or
wait states.
Operations already in progress are not affected.
17 Deselect Command The DESELECT function prevents new commands from being executed by the DDR3 SDRAM.
(CS# HIGH)
The DDR3 SDRAM is effectively deselected.
Operations already in progress are not affected
18 ACTIVE Command The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access
The value on the BA0-BA2 inputs selects the bank
The address provided on inputs A0-A15 selects the row address
This row remains active (or open) for accesses until a precharge command is issued to that bank
A PRECHARGE command must be issued before opening a different
row in the same bank
19 PRECHARGE Command The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks
Once a bank has been precharged, it is in the idle state
Bank must be activated prior to any READ or WRITE commands being
issued to that bank
20 READ Operation During a READ or WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE
A12 = 0, BC4 A12 = 1, BL8 A12 is used only for burst length control, not as a column address.
Read data on DQ is edge aligned to DQS
Read Latency is given by RL = AL + CL
Ref Page 70 21 READ Operation
22 WRITE Operation During a WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE A12 = 0, BC4 (BC4 = burst chop, tCCD = 4) A12 = 1, BL8 A12 is used only for burst length control, not as a column address
Write data on DQ is center aligned to DQS
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR3 SDRAMs
Refer Page 83 for Write operation waveform
23 Refresh Command Refresh is the periodic command required by DRAM to maintain the charge on memory cells in the DRAM device
DDR3 SDRAM requires Refresh cycles at an average periodic interval
of tREFI
All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before the Refresh Command can be applied
Refresh commands is limited to 9 × tREFI
At any given time, a maximum of 16 REF commands can be issued
24 within 2 x tREFI Self-Refresh Operation Self-Refresh command is used when rest of the system is powered down When in the Self-Refresh mode, the DDR3 SDRAM retains data without external clocking. Clock is internally disabled during Self-Refresh Operation to save power In self refresh mode, DDR3 memory retains data without external clocking while the rest of the system is powered down. DDR3 SDRAM device has a built-in timer to accommodate Self-Refresh operation Before issuing the Self-Refresh-Entry command, the DDR3 SDRAM must be idle with all bank precharge state When the DDR3 SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and RESET#, are “don’t care 25 Power Down Mode DDR3 memories provide power down and self refresh modes to conserve power when not in use
When the memory is not accessed for a longer duration of time, it can be put in Power down mode, by making the CKE signal LOW
Data is not retained in this mode
When the power down happens while all the memory banks are pre- charged, it is called pre-charge power down
When any of the memory banks are active during power down, then it is called active power down 26 ZQ Calibration Commands ZQ Calibration command is used to calibrate DRAM Ron & ODT values
ZQCL command is used to perform the initial calibration during power-
up initialization sequence
ZQCS command is used to perform periodic calibrations to account for
voltage and temperature variations
In order to use the ZQ Calibration function, a 240 ohm +/- 1% tolerance
external resistor must be connected between the ZQ pin and ground
