ELE 704 Analog CMOS Integrated Circuits Laboratory One - Cadence Tutorial

Professor Fei Yuan September 2009

Pre-Laboratory

Pre-Laboratory must be completed and handed in prior to the commence of the corresponding Laboratory Work

1. Derive the voltage transfer function H(s) of the circuit in Fig.1. 2. Obtain the zeros and poles of H(s). 3. Determine the transfer characteristics of the circuit (low-pass, highpass, or band-pass). Find the bandwidth of the passband. 4. Sketch the Bode plot of |H(j)| and its phase plot. 5. Obtain the resonant frequency 0 and the quality factor Q of the circuit.
Vo R1=22k R2=75 C=47n L=500m

Vin

Figure 1: Schematic of RLC circuit

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2.1

Laboratory Work
Cadence Environment

A. Start Up Cadence is a set of computer-aided design tools for design, analysis, and verication of integrated circuits. To run Cadence, you need Unix commands Cadence tools: Virtuoso Composer, Analog Artist and Virtuoso Layout CMCs cmosp18 design kit Your system has been pre-congured for that. To start Cadence from your home directory, type mkdir cadence18 (rst time only) cd cadence18 cadenceenv startCds -t cmosp18 cadenceenv: This batch command loads CMCs local environment for Cadence. This environment is used to bind the cmosp18 design kit into the Design Framework II (DFII) of Cadence. startCds -t cmosp18: starts your Cadence software and launches the Cadence Command Interpreter Window (icfb) where you can check your current version of Cadence tools and the version of the design kit being used.

B. Initialization Files The Cadence environment uses three major initialization les and one model le of cmosp18. cds.lib: sets the path to the libraries used in your design. This le is created in your current folder when you start Cadence. When you start Cadence for the rst time, cds.lib will be automatically copied to the current directory. .cdsinit: Customizes specic simulation environment, i.e. Analog Artist. To make sure Analog Artist is going to be the default simulation environment, we need to Go to the directory: /CMC/tools/cadence/IC/tools/df II/samples/artist Copy the le cdsinit to your working directory ( /cadence18) Rename it to .cdsinit .cdsenv: sets global Cadence environment. C. Where to Find Help open book : Online documentation for most Cadence tools. Access through: icfb | CMC Gateway | Start Cadence Documentation. CMOS18 technology information: design rules and model parameters. Access through: icfb | CMOSP18 | CMOSP18 documentation | launch Netscape for CMOS Docs or f ile : /CMC /tools /cadence.2008a /IC.61 /tools.sun4v/df II/ local/lib/cmosp18 cmosp18 docs.html Up to this point, you have learned how to start Cadence software and where to nd on-line help. Before jumping to Cadence tools to start your circuit design project, it is benecial to have a look at Cadence facilities that support the basic operation. 3

2.2

Cadence Facilities

A. The icfb Window

Figure 2: icfb window When Cadence starts, it brings up the icfb (Integrated Circuit front-toback) window, as shown in Fig.2. It is Cadences Command Interpreter Window that can be thought of Cadence Shell. It is through icfb window that you can do all of your Cadence tasks, including le management and program execution. B. Libraries, Cells and Views Cadence uses the hierarchy of Library | Cell | View to manage design data. Cadence stores design data into libraries that are not transparent to external le systems. How each library corresponds to a physical path in the le system is registered in the le named cds.lib, which is one of the three major initialization les mentioned earlier. This le can be modied using icfb |Tools| Library Path Manager. The rst thing you should do in Cadence is to create your own library, we will come back to this point in Cadence Walk Though shortly. A cell contains Cadences design data, or more specically, the data of the designed circuit. Each cell has at least one view that is the representation of the cell. Fig.3 shows the Library Manager window. Each time when a new library or a new cell is created, a new item will appear in the corresponding 4

Figure 3: Library Manager window column of the library manager. Three libraries that will be most frequently used in the laboratories are cmosp18 - this library contains the cells of 0.18 devices, such as transistors, capacitors, and resistors. basic - this library contains ideal components of circuits. analogLib library contains basic components for analog circuits. It also contains various types of independent and dependent sources.

2.3

Design Flow

In this section, we will go through the basic design steps of Cadence CAD tools. Step 1 - Create Schematic 5

 Instance transistors and other elements from libraries Create the schematic of the circuit by connecting elements together and modify their properties. Create the Symbol view of the schematic view. Step 2 - Simulation Use simulation and waveform viewers to modify circuit parameters until design specications are met. Step 3 - Layout and DRC Map the schematic onto silicon Layout must must follow the design rules of chosen technology and pass design rule check (DRC). Step 4 - Extraction and LVS Create post-layout schematic from layout. Both the parasitic capacitances and resistances can be extracted from the layout in this step. Perform LVS (Layout versus schematic) to verify whether the post-layout schematic matches the original schematic. Step 5 - Post-Layout Simulation Simulate extracted view (post-layout schematic) by taking into account the eect of parasitic capacitances and resistances. Using simulation results to modify the layout until design specications are met. Up to this point, you have known the overall picture of the design ow. In sections that follow, we will use a simple RLC circuit as an example to walk you through these basic steps. 6

2.4

Create Schematic

In this laboratory work, You are required to do the followings Create the schematic of the RLC circuit. Create the symbol view of the circuit. Create a test xture circuit for testing the RLC circuit. Perform transient analysis, AC analysis, and DC analysis on the circuit using Cadences Spectre analog simulator. Provide a detailed comparison between the analytical results from your Pre-Laboratory Report and those obtained from the Laboratory Work. A. Create New Libraries and Schematic Views 1. Create New Libraries

Figure 4: Create library window It is necessary to have a separate library to store your design cells and their views. To do that From the icfb menu, select File | New | Library 7

 Navigate to the cadence18 directory (if not already there) Type in mylibs as the name of your new library Select to attach to an existing techle, click OK, then select the cmosp18 library when prompted. By selecting the techle, you will be able to use the cells from cmosp18 library for your design. 2. Create new design cells

Figure 5: Create schematic view window From the icfb menu, select File | New | Cellview. You are prompted for the library to place the new cell in and what type of view you are creating. Select mylibs that was created in the previous step and ensure Composer-Schematic is selected as the tool for your new cell. Note that schematic is the default name of the view. Enter rlc as the cellname and select OK to open the new cell in composer.

The rest of this section describes the steps to create the rlc circuit shown at Fig. 1 in schematic view. B. Add Components and Wires When creating a schematic, you place instances that were created previously, edit their properties e.g. resistance, capacitance, width, etc, and wire them together. In the case of the RLC circuit, you will place two resistors, one capacitor, one inductor and ground. You wire the devices together using the wire tool, and wire snapping, and then edit the property of the devices to set R1 =75k, R2 = 75, C=47nF, and L=500mH. 1. Instantiate Components

Figure 6: Add instance window 9

Table 1: Component value of RLC circuit Component R1 R2 C L Ground Library Cell analogLib res analogLib res analogLib Cap analogLib Ind basic gnd View Spectre Spectre Spectre Spectre symbol Value 75 k 75 47 nF 500 mH N/A

To place a resistor, follow these steps from the main composer window Click on the Instance Icon. The Add Instance window will appear as shown in Fig. 6. Click on the Browse button. In the browse library window, select cmosp18 library, resistor cell, and symbol view. Move the cursor to the Composer Schematic window, the resistor symbol follows. Also, note that the Add Instance window has expanded to display other parameters. Before you click on the schematic window to place the resistor symbol, edit the form, modifying the resistance value to 75k. IMPORTANT: Do not get concerned with all of the seemingly irrelevant parameters. They are used for more detailed simulations and other applications. Click in the composer window to place the resistor. Another resistor symbol follows the cursor. Place it in the window then click on Cancel on the Add Instance window. The form disappears. In the same way in which you added the resistor, add the other instances from the library, cell, and view as indicated below. To rotate an instance in Schematic Composer window, click once on it to select (left-click with the mouse), then middle-click 10

to open the auxiliary menu. Select Rotate. 2. Add I/O pins There are three types of pins in Cadence, namely, input pins, output pins, and input/output pins. To add the input and output pins, click on the Pin icon in the lower left side of the Composer window. The Add Pin form appears as shown in Fig. 7.

Figure 7: Add pin window Under Pin Names, type Vin Vout. Note that direction in the form reads input. Click once on the schematic window. The rst pin is placed. Note the other pins symbol follows the cursor as you move across the window. The Add Pin form is still active, but with only Vout displaying in the Pin Names eld; In the Add Pin form, change direction to read Output. Place the Vout pin in the schematic window. Close the Add Pin form when all pins are added. 3. Connect Wires Move the components that you just added around so that they are positioned properly. Use the ESC key to terminate the mode that you can drag the components around on the screen. 11

 To begin connecting the wires as per the schematic of Fig. 1, click on the Wire (narrow) icon. While the Add Wire window is still displaying (but not selected), press the s key on your keyboard. This snaps the wires to connect between the little diamond-shapes displaying by the nodes. Press s Key once on the begin-node, then click on the end-node. Complete the schematic of the circuit as shown in Fig.8

Figure 8: Schematic View of RLC

C. Modify the Property of Components To modify the property of the devices of the circuit, click once to select the instance, then click on the properties icon. Or using the q bindkey. 12

 Modify the value of the inductor to 500 mH, the capacitance to 47 nF and the resistance of the second resistor to 75. Note: When you enter the value of parameters, you must enter the unit. You have to explicitly indicate the standard SI given below (case-sensitive): G = Giga M = Mega k = kilo m = milli u = micro n = nano p = pico f = femto a = atto (109 ) (106 ) (103 ) (103 ) (106 ) (109 ) (1012 ) (1015 ) (1018 )

For example, for 20 femptoFarads, you just enter 20f. No space between the number and sux. Do not include the unit as they are predened in the instance property le. D. Check and Save Click on Check and Save icon. Cadence will check your design for any electrical connection rule violation. The design will be saved if no error is found. Read the messages displayed in the icfb window carefully. Make sure that no warnings and errors. If there is a warning or an error, go back to the schematic window and look for ashing boxes where the warnings/errors were found. By clicking on the ashing box, an explanation of the error will displayed in the CIW window. Fix the errors/warnings until your design is both error-free and warning-free. 13

E. Add Borders When your design is completed and is error/warning-free. You should add a border around your design to document the design. A border is treated as a cell in Cadence. However the border library path is not available in cds.lib by default. We need add the path using Library Path Editor before we can instance a border. Open icfb | Tools | Library Path Editor and add US 10ths in library name column and /CMC/tools /cadence.2000a /IC/tools/df II /samples/cdslib /sheets/US 10ths under path column at the bottom of the list as shown in Fig. 9. Dont forget to save it before quitting the Library Path Editor.

Figure 9: Add border path window

With the border library US 10th path available, click on the Instance icon and chose US 10ths | Asize and add an A-size border around the RLC schematic. To edit the border title, click on Sheet | Edit Title and ll the form appropriately. Then type in both your name and your student ID. Click Check and Save icon to save your work.

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F. Create Symbol Cellviews Now we will create a symbol view to represent the RLC circuit that has just been created. Use schematic composer | design | from cellview| crating cellview. This sequence creates a symbol using the primary input and output pins automatically. The form appears as shown in Fig. 10. Make sure Tool/Data Type is changed to Symbol, then click OK.

Figure 10: Create symbol cellview window Click OK and a new form will appear, select the Load/Save button to expand the form. Change the cyclic eld next to load to Analog. Click the Load button, this will load the Analog Symbol Generation window. Then click on OK button It is important that you click NO if a message appears calling for Overwrite Base Cell CDF. This ensures that the parameters of the base cell are not changed. A Symbol Editing window will appear. The green box denes the dimensions of the symbol. The red box denes the selection region of 15

the symbol. The cdsTerm(Vout) represents the pin-names. The cdsParam(1,2,3) represents the parameters of each instance. The cdsName( ) represents the cell-name. You can re-shape your symbol. Click on the Label icon and name the circuit properly. Save and close the window. G. Create TestFixtures A testxture is a new schematic cell used for testing the designed circuits. In this case, it contains rlc symbol as one of its instances. You will have to go through the process of creating the schematic view again to create the testxture. Go to: icfb | File | New | Cellview.... Create a new cell called test rlc, with a schematic cellview. Click OK. In the new Composer-Schematic window. Add instances, connect your new circuit using components according to the following table, and referring to the schematic in Fig. 11. To add the wire names, click on Wire Name icon. Under Names, type in Vin and Vout. Click OK. The name Vin follows the mouse as you move over the schematic window. Click on the input wire as shown in Fig. 11 to place it. The name Vout next follows the mouse pointer. Repeat the process for Vout. Click on Check and Save icon when done.

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Table 2: Components in testxture Component RLC C Input Library Mylibs analogLib analogLib Cell rlc Capacitor vsin View Symbol Spectre Symbol Value N/A 1 pF AC Magnitude = 1 Amplitude = 50 mV Frequency = 1 M Oset Voltage=0 N/A

gnd

basic

gnd

symbol

2.5

Simulation

A. Introduction This section deals with the second step in the basic design ow. To invoke Arma Analog Circuit Design Environment: Open test rlc schematic view. You may skip this step if test rlc is already open. In the test rlc schematic window, select Tools | Analog Environment. Fig.12 shows what the window looks like when fully congured. The icons on the right provide quick access to frequent commands/menus; The Design Area on the top left lists the library, cell, and cellView of the design being simulated. The Analysis Area on the top right lists the types of analysis, any arguments (i.e. time interval), and whether it is enabled to perform the simulation in the current run. 17

Figure 11: Schematic of the TextFixture of RLC circuit The Design Variables Area on the bottom left lists component setup as variables. Select Variables | Copy from Cellview and the variable will appear in this list. The Outputs Area lists names of nets/signals/expressions/ports to be plotted on the output waveform window; B. Initialize Simulation Environment In the window of Arma Analog Circuit Design Environment, do the followings Choosing a simulation engine. Select Setup | Simulator/Directory/Host. Ensure that the Simulator is set to Spectre and Project Directory to read as /cadence18 /simulation. This creates a new directory under your cadence folder. Set Model Libraries. Select Setup | Model Libraries. Add the path /CMC/kits/cmosp18.5.2/models/spectre/rf 018.scs to the list. 18

Figure 12: Arma Analog Circuit Design Environment This le contains the detailed mathematical models of the CMOS 180nm devices. Type tt in the Section eld ( make sure the path you just added is highlighted in the list while you edit this eld) and click on the Change button. This will tell the simulator that the pMOS and nMOS devices are under typical process condition. Select Setup | Environment. In the Include le eld, give the path of /cadence/icf spectre.init. The le was copied here in Section Initialization Files. Also select spectre in the include/Stimulus File Syntax eld. When you leave the simulation window, you will be prompted to save the current state. Save it using the default name state1. This will save you from repeating the initializing process for the next time you simulate the circuit. You also can use the same state le for other 19

circuits. C. Choose Analysis To begin an analysis, click on Choose Analysis icon at right area from the Simulation Environment window. A new window will appear. Do not close this window until all three-analysis modes are set. 1. Transient Analysis Select tran in the new window. Set the stop time to 3 (Note that the start time is set to 0 by default). Turn on the Enabled Field and click Apply. Note that by setting Enable Field, you enable the transient analysis. You can disable the transient analysis by resetting this option. 2. AC Analysis Select ac. Set the Sweep Variable to Frequency. Set the Sweep Range to Start: 0.01K and Stop: 10K. Set the Sweep Type to log with 20 pts decade. Turn on the Enabled Field and click Apply. 3. DC Analysis or DC Sweep Select dc. In the Sweep Variable Section, select Component Parameter. By doing so, you will be able to choose a component by clicking on it from the schematic view.

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 Select the supply source from the schematic window. A new form will appear. Assert the dc parameter and click OK. You are back to the original window (DC Analysis). Ensure the Sweep Range to Start: 0 and Stop: 100. Turn on the Enabled Field and click Apply. D. Save and Plot Simulation Data All nodal voltages are congured to be saved by the simulation environment. But save certain voltages and currents from the circuit will require a manual selection of these voltage and currents from the schematic view. From the simulation window, select Outputs | Save All. Assert Select All Node Voltages and click OK. Select Outputs | To Be Plotted | Select on Schematic. For the simulation you are about to run, only the input and output voltages are of our interest in this laboratory. The current of a branch is selected by clicking on the nodes to which the branch is connected. You can also use the component iprobe from the library AnalogLib to measure the current of any branch. The voltage of a node is selected by clicking on the wires that are connected to the node. Select the voltage of the input and output nodes. E. Run Simulation - The Waveform Window In the schematic editing window, click on Check and Save button (the rst from the top in the left-hand toolbox). If you see any error messages, correct the design and try this again. 21

 Click on the icon Run Simulation. A Waveform window showing the results of all three analyses will appear when simulation is completed. The plots of the input and output voltages are overlapped. To view them separately, click on the analysis area (i.e. AC, DC or Transient) and select Axes | To Strip. Repeat the above steps for the other two waveform windows. To change the label of an axe, double-clicking on the axis and rename the it appropriately. For the transient response window, place Marker A at the negative peak of the output waveform and Marker B at the positive peak. Markers A and B are accessible by clicking on the Crosshair Marker A/B icon on the left of the Waveform window. In the AC Response section, delete the Vin vs. Vin plot by selecting the graph and press the delete key on the keyboard. Use a Marker to measure the resonant frequency of the RLC circuit. In the DC Response section, delete the Vin vs. Vin plot. F. Print Waveforms To print from a schematic/composer window, Select Design | Plot | Submit, and click on Plot options. Chose the appropriate printer and click on OK. To print the waveforms, select Window | Hardcopy. You can also print your schematics and waveforms to an .eps le by choosing eps from Plot options.

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G. Save and Exit Cadence From the icfb window, save your defaults and session. From the Analog Artist window, click Session | Save State, give an appropriate state name and press OK. From the Waveform window, select Window | Save... Click OK. Close all windows by choosing Close Window. Exit from Cadence Properly. You can not exit Cadence by simply clicking on the X icon at the top-right corner of each window. Cadence will block you from editing your design if you do so.

Post-Laboratory Report

Post-Laboratory Report must be completed and handed in after the scheduled Laboratory Work. The followings must be included in your PostLaboratory Report. 1. The schematic of the RLC circuit with an appropriate border. Your name and student ID must be shown in the border title section. 2. The schematic of your RLC test xture circuit. 3. The waveform of the output voltage of the RLC circuit from tran, AC, and DC analyses. 4. Measure the resonant frequency, overshoot and calculate the quality factor. 5. Comment on the resonant frequency and the quality factor of the circuit obtained from analytical analysis of your Pre-Laboratory Report and those obtained from the Laboratory Work. 23