Logic Diagram:

Block Diagram:

TIMING WAVEFORMS:

Page | 1
 EXPERIMENT-1

MULTIPLUXER AND DEMULTIPLEXER

AIM: To develop the source code for MULTIPLUXER & by using VERILOG and obtain
the simulation, synthesis.

VERILOG CODE FOR 8*1 MULTIPLUXER:

module nm81(in, sel, out);

input [7:0] in;

input [2:0] sel;

output out;

reg out;

always@(sel or in)

begin

case(sel)

3'b000: out <= in[0];

3'b001: out <= in[1];

3'b010: out <= in[2];

3'b011: out <= in[3];

3'b100: out <= in[4];

3'b101: out <= in[5];

3'b110: out <= in[6];

3'b111: out <= in[7];

endcase

end

endmodule

Page | 2
SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "cxvssdaf.v" in library work
Module <nm81> compiled
No errors in compilation
Analysis of file <"nm81.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <nm81> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <nm81>.
Module <nm81> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <nm81>.
Related source file is "cxvssdaf.v".
Found 1-bit 8-to-1 multiplexer for signal <out>.
Summary:
inferred 1 Multiplexer(s).
Unit <nm81> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# Multiplexers :1
1-bit 8-to-1 multiplexer :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
Page | 3
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# Multiplexers :1
1-bit 8-to-1 multiplexer :1
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <nm81> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block nm81, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Found no macro
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : nm81.ngr
Top Level Output File Name : nm81
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 12
Cell Usage :
Page | 4
# BELS :7
# LUT3 :4
# MUXF5 :2
# MUXF6 :1
# IO Buffers : 12
# IBUF : 11
# OBUF :1
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 2 out of 960 0%
Number of 4 input LUTs: 4 out of 1920 0%
Number of IOs: 12
Number of bonded IOBs: 12 out of 66 18%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.624ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default path analysis
Total number of paths / destination ports: 15 / 1
-------------------------------------------------------------------------
Page | 5
Delay: 6.624ns (Levels of Logic = 5)
Source: sel<0> (PAD)
Destination: out (PAD)
Data Path: sel<0> to out
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 1.106 0.651 sel_0_IBUF (sel_0_IBUF)
LUT3:I0->O 1 0.612 0.000 Mmux_out_4 (Mmux_out_4)
MUXF5:I1->O 1 0.278 0.000 Mmux_out_3_f5 (Mmux_out_3_f5)
MUXF6:I1->O 1 0.451 0.357 Mmux_out_2_f6 (out_OBUF)
OBUF:I->O 3.169 out_OBUF (out)
----------------------------------------
Total 6.624ns (5.616ns logic, 1.008ns route)
(84.8% logic, 15.2% route)
=============================================================
============
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.05 secs

-->
Total memory usage is 239988 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Page | 6
LOGIC DIAGRAM:

BLOCK DIAGRAM:

TIMING WAVEFORMS:

Page | 7
 DEMULTIPLUXER

VERILOG CODE 1*8 DEMULTIPLUXER:

module vdmux1(i, sel, y);

input i;

input [2:0] sel;

output [7:0] y;

reg [7:0] y;

always@(i,sel)

begin

y=8'd0;

case(sel)

3'd0:y[0]=i;

3'd1:y[1]=i;

3'd2:y[2]=i;

3'd3:y[3]=i;

3'd4:y[4]=i;

3'd5:y[5]=i;

3'd6:y[6]=i;

default:y[7]=i;

endcase

end

endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "cxvssdaf.v" in library work

Page | 8
Module <vdmux1> compiled
No errors in compilation
Analysis of file <"vdmux1.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vdmux1> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vdmux1>.
Module <vdmux1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vdmux1>.
Related source file is "cxvssdaf.v".
Unit <vdmux1> synthesized.
=============================================================
============
HDL Synthesis Report
Found no macro
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Found no macro
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Page | 9
Optimizing unit <vdmux1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vdmux1, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Found no macro
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vdmux1.ngr
Top Level Output File Name : vdmux1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 12
Cell Usage :
# BELS :8
# LUT4 :8
# IO Buffers : 12
# IBUF :4
# OBUF :8
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 4 out of 960 0%
Number of 4 input LUTs: 8 out of 1920 0%
Number of IOs: 12
Number of bonded IOBs: 12 out of 66 18%
---------------------------
Page | 10
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.039ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default path analysis
Total number of paths / destination ports: 32 / 8
-------------------------------------------------------------------------
Delay: 6.039ns (Levels of Logic = 3)
Source: i (PAD)
Destination: y<7> (PAD)
Data Path: i to y<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 8 1.106 0.795 i_IBUF (i_IBUF)
LUT4:I0->O 1 0.612 0.357 y_7_mux00001 (y_7_OBUF)
OBUF:I->O 3.169 y_7_OBUF (y<7>)
----------------------------------------
Total 6.039ns (4.887ns logic, 1.152ns route)
(80.9% logic, 19.1% route)
=============================================================
============
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.72 secs
Page | 11
-->
Total memory usage is 240244 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

RESULT: Simulated the VERILOG codes for MULTIPLUXER AND DEMULTIPLEXER and
obtained the timing diagrams.

Page | 12
BLOCK DIAGRAM

LOGIC DIAGRAM

TIMING WAVEFORM

EXPERIMENT-2
Page | 13
 3 T0 8 DECODER
AIM: To develop the source code for3 T0 8 DECODER & by using VERILOG and
obtain the simulation, synthesis.

VERILOG CODE 3 T0 8 DECODER:

module v3to8(a,y);

input[2:0]a;

output[7:0]y;

reg[7:0]y;

always@(a)

case(a)

3'b000:y=8'b00000001;

3'b001:y=8'b00000010;

3'b010:y=8'b00000100;

3'b011:y=8'b00001000;

3'b100:y=8'b00010000;

3'b101:y=8'b00100000;

3'b110:y=8'b01000000;

3'b111:y=8'b10000000;

endcase

endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "mbbb.v" in library work
Module <v3to8> compiled
No errors in compilation
Analysis of file <"v3to8.prj"> succeeded.

Page | 14
=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <v3to8> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <v3to8>.
Module <v3to8> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <v3to8>.
Related source file is "mbbb.v".
Found 1-of-8 decoder for signal <y>.
Summary:
inferred 1 Decoder(s).
Unit <v3to8> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# Decoders :1
1-of-8 decoder :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# Decoders :1
1-of-8 decoder :1
=============================================================
============
=============================================================
============
Page | 15
* Low Level Synthesis *
=============================================================
============
Optimizing unit <v3to8> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block v3to8, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Found no macro
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : v3to8.ngr
Top Level Output File Name : v3to8
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 11
Cell Usage :
# BELS :8
# LUT3 :8
# IO Buffers : 11
# IBUF :3
# OBUF :8
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 4 out of 960 0%
Number of 4 input LUTs: 8 out of 1920 0%
Page | 16
 Number of IOs: 11
Number of bonded IOBs: 11 out of 66 16%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.039ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default path analysis
Total number of paths / destination ports: 24 / 8
-------------------------------------------------------------------------
Delay: 6.039ns (Levels of Logic = 3)
Source: a<2> (PAD)
Destination: y<7> (PAD)
Data Path: a<2> to y<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 8 1.106 0.795 a_2_IBUF (a_2_IBUF)
LUT3:I0->O 1 0.612 0.357 Mdecod_y71 (y_7_OBUF)
OBUF:I->O 3.169 y_7_OBUF (y<7>)
----------------------------------------
Total 6.039ns (4.887ns logic, 1.152ns route)
(80.9% logic, 19.1% route)

Page | 17
=============================================================
============
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.05 secs

-->
Total memory usage is 239604 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

RESULT: Simulated the VHDL and VERILOG codes for 3 T0 8 DECODER and obtained
the timing diagrams.

Page | 18
 BCD TO EXCESS 3 CODE

Block Diagram:

LOGIC DIAGRAM

TIMING WAVEFORMS

Page | 19
 EXPERIMENT-3

CODE CONVERTERS
AIM: To develop the source code for CODE CONVERTERS & by using VERILOG and
obtain the simulation, synthesis.

VERILOG CODE FRO BCD TO EXCESS-3:

module vbx(in, out);

input [3:0] in;

output [3:0] out;

reg [3:0] out;

always @ (in)

case (in)

4'b0000: out <= 4'b0000;

4'b0001: out <= 4'b0001;

4'b0010: out <= 4'b0010;

4'b0011: out <= 4'b0011;

4'b0100: out <= 4'b0100;

4'b0101: out <= 4'b1000;

4'b0110: out <= 4'b1001;

4'b0111: out <= 4'b1010;

4'b1000: out <= 4'b1011;

4'b1001: out <= 4'b1100;

default: out <= 4'b0000;

endcase

endmodule

Page | 20
SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "cnzc.v" in library work
Module <vbx> compiled
No errors in compilation
Analysis of file <"vbx.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vbx> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vbx>.
Module <vbx> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vbx>.
Related source file is "cnzc.v".
Found 16x4-bit ROM for signal <out>.
Summary:
inferred 1 ROM(s).
Unit <vbx> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# ROMs :1
16x4-bit ROM :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
Page | 21
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# ROMs :1
16x4-bit ROM :1
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vbx> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vbx, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Found no macro
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vbx.ngr
Top Level Output File Name : vbx
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :8
Cell Usage :
Page | 22
# BELS :4
# LUT4 :4
# IO Buffers :8
# IBUF :4
# OBUF :4
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 2 out of 960 0%
Number of 4 input LUTs: 4 out of 1920 0%
Number of IOs: 8
Number of bonded IOBs: 8 out of 66 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 5.895ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default path analysis
Total number of paths / destination ports: 16 / 4
-------------------------------------------------------------------------
Delay: 5.895ns (Levels of Logic = 3)
Source: in<3> (PAD)
Page | 23
 Destination: out<3> (PAD)
Data Path: in<3> to out<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 1.106 0.651 in_3_IBUF (in_3_IBUF)
LUT4:I0->O 1 0.612 0.357 Mrom_out31 (out_3_OBUF)
OBUF:I->O 3.169 out_3_OBUF (out<3>)
----------------------------------------
Total 5.895ns (4.887ns logic, 1.008ns route)
(82.9% logic, 17.1% route)
=============================================================
============
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.02 secs

-->
Total memory usage is 239348 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Page | 24
 BINARY TO GRAY CONVERTOR

Block Diagram:

LOGIC DIAGRAM:

TIMING WAVEFORMS

Page | 25
 BINARY TO GRAY

VERILOG CODE FOR BINARY TO GRAY:

module vbgr1(in, out);

input [3:0] in;

output [3:0] out;

reg [3:0] out;

always@(in)

case(in)

4'b0000: out <= 4'b0000;

4'b0001: out <= 4'b0001;

4'b0010: out <= 4'b0011;

4'b0011: out <= 4'b0010;

4'b0100: out <= 4'b0110;

4'b0101: out <= 4'b0111;

4'b0110: out <= 4'b0101;

4'b0111: out <= 4'b0100;

4'b1000: out <= 4'b1100;

4'b1001: out <= 4'b1101;

4'b1010: out <= 4'b1111;

4'b1011: out <= 4'b1110;

4'b1100: out <= 4'b1010;

4'b1101: out <= 4'b1011;

4'b1110: out <= 4'b1001;

4'b1111: out <= 4'b1000;

default:out <= 4'b0000;

endcase

endmodule
Page | 26
SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "asdcnn.v" in library work
Module <vbgr1> compiled
No errors in compilation
Analysis of file <"vbgr1.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vbgr1> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vbgr1>.
Module <vbgr1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vbgr1>.
Related source file is "asdcnn.v".
Found 16x4-bit ROM for signal <out>.
Summary:
inferred 1 ROM(s).
Unit <vbgr1> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# ROMs :1
16x4-bit ROM :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
Page | 27
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# ROMs :1
16x4-bit ROM :1
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vbgr1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vbgr1, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Found no macro
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vbgr1.ngr
Top Level Output File Name : vbgr1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :8
Cell Usage :
Page | 28
# BELS :3
# LUT2 :3
# IO Buffers :8
# IBUF :4
# OBUF :4
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 2 out of 960 0%
Number of 4 input LUTs: 3 out of 1920 0%
Number of IOs: 8
Number of bonded IOBs: 8 out of 66 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 5.776ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default path analysis
Total number of paths / destination ports: 7 / 4
-------------------------------------------------------------------------
Delay: 5.776ns (Levels of Logic = 3)
Source: in<2> (PAD)
Page | 29
 Destination: out<2> (PAD)
Data Path: in<2> to out<2>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.532 in_2_IBUF (in_2_IBUF)
LUT2:I0->O 1 0.612 0.357 Mrom_out21 (out_2_OBUF)
OBUF:I->O 3.169 out_2_OBUF (out<2>)
----------------------------------------
Total 5.776ns (4.887ns logic, 0.889ns route)
(84.6% logic, 15.4% route)
=============================================================
============
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.40 secs

-->
Total memory usage is 240308 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Page | 30
 GRAY TO BINARY CONVERTOR

Block Diagram:

LOGIC DIAGRAM:

TIMING WAVEFORM

Page | 31
 GRAY TO BINARY

VERILOG CODE GRAY TO BINARY:

module vgbi1(in, out);

input [3:0] in;

output [3:0] out;

reg [3:0] out;

always@(in)

case(in)

4'b0000: out <= 4'b0000;

4'b0001: out <= 4'b0001;

4'b0011: out <= 4'b0010;

4'b0010: out <= 4'b0011;

4'b0110: out <= 4'b0100;

4'b0111: out <= 4'b0101;

4'b0101: out <= 4'b0110;

4'b0100: out <= 4'b0111;

4'b1100: out <= 4'b1000;

4'b1101: out <= 4'b1001;

4'b1111: out <= 4'b1010;

4'b1110: out <= 4'b1011;

4'b1110: out <= 4'b1100;

4'b1011: out <= 4'b1101;

4'b1001: out <= 4'b1110;

4'b1000: out <= 4'b1111;

default:out <= 4'b0000;

endcase

endmodule
Page | 32
SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "iiyr.v" in library work
Module <vgbi1> compiled
No errors in compilation
Analysis of file <"vgbi1.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vgbi1> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vgbi1>.
WARNING:Xst:883 - "iiyr.v" line 19: Ignored duplicate item in case statement.
Module <vgbi1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vgbi1>.
Related source file is "iiyr.v".
Found 16x4-bit ROM for signal <out>.
Summary:
inferred 1 ROM(s).
Unit <vgbi1> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# ROMs :1
16x4-bit ROM :1
=============================================================
============
=============================================================
============
Page | 33
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# ROMs :1
16x4-bit ROM :1
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vgbi1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vgbi1, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Found no macro
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vgbi1.ngr
Top Level Output File Name : vgbi1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :8
Page | 34
Cell Usage :
# BELS :4
# LUT3 :1
# LUT4 :3
# IO Buffers :8
# IBUF :4
# OBUF :4
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 2 out of 960 0%
Number of 4 input LUTs: 4 out of 1920 0%
Number of IOs: 8
Number of bonded IOBs: 8 out of 66 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 5.895ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default path analysis
Total number of paths / destination ports: 15 / 4
-------------------------------------------------------------------------
Page | 35
Delay: 5.895ns (Levels of Logic = 3)
Source: in<3> (PAD)
Destination: out<3> (PAD)
Data Path: in<3> to out<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 1.106 0.651 in_3_IBUF (in_3_IBUF)
LUT4:I0->O 1 0.612 0.357 Mrom_out31 (out_3_OBUF)
OBUF:I->O 3.169 out_3_OBUF (out<3>)
----------------------------------------
Total 5.895ns (4.887ns logic, 1.008ns route)
(82.9% logic, 17.1% route)
=============================================================
============
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.41 secs

-->
Total memory usage is 239796 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "iiyr.v" in library work
Module <vgbi1> compiled
No errors in compilation
Analysis of file <"vgbi1.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vgbi1> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vgbi1>.
=============================================================
============
* HDL Synthesis *

Page | 36
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vgbi1>.
Related source file is "iiyr.v".
Found 16x4-bit ROM for signal <out>.
Summary:
inferred 1 ROM(s).
Unit <vgbi1> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# ROMs :1
16x4-bit ROM :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# ROMs :1
16x4-bit ROM :1
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vgbi1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vgbi1, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Found no macro
=============================================================
============
=============================================================
============
* Partition Report *
Page | 37
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vgbi1.ngr
Top Level Output File Name : vgbi1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :8
Cell Usage :
# BELS :4
# LUT3 :1
# LUT4 :3
# IO Buffers :8
# IBUF :4
# OBUF :4
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 2 out of 960 0%
Number of 4 input LUTs: 4 out of 1920 0%
Number of IOs: 8
Number of bonded IOBs: 8 out of 66 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
Page | 38
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 5.895ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default path analysis
Total number of paths / destination ports: 15 / 4
-------------------------------------------------------------------------
Delay: 5.895ns (Levels of Logic = 3)
Source: in<3> (PAD)
Destination: out<3> (PAD)
Data Path: in<3> to out<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 1.106 0.651 in_3_IBUF (in_3_IBUF)
LUT4:I0->O 1 0.612 0.357 Mrom_out31 (out_3_OBUF)
OBUF:I->O 3.169 out_3_OBUF (out<3>)
----------------------------------------
Total 5.895ns (4.887ns logic, 1.008ns route)
(82.9% logic, 17.1% route)
=============================================================
============
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.41 secs

-->
Total memory usage is 239796 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Page | 39
BLOCK DIAGRAM

LOGIC DIAGRAM

TIMING WAVEFORM

Page | 40
 EXPERIMENT-4

FOUR BIT COMPARATOR

VERILOG CODE FOR 4-BIT COMPARATOR:

module vcom1(a, b, aeqb, agtb, altb);

input [3:0] a;

input [3:0] b;

output aeqb;

output agtb;

output altb;

reg aeqb,agtb,altb;

always@(a or b)

begin

aeqb=0;

agtb=0;

altb=0;

if(a==b)

aeqb=1;

else if(a>b)

agtb=1;

else

altb=1;

end

endmodule

Page | 41
SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "cvded.v" in library work
Module <vcom1> compiled
No errors in compilation
Analysis of file <"vcom1.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vcom1> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vcom1>.
Module <vcom1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vcom1>.
Related source file is "cvded.v".
Found 4-bit comparator equal for signal <aeqb$cmp_eq0000> created at line 13.
Found 4-bit comparator greater for signal <agtb$cmp_gt0000> created at line 15.
Summary:
inferred 2 Comparator(s).
Unit <vcom1> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# Comparators :2
4-bit comparator equal :1
4-bit comparator greater :1
=============================================================
============

Page | 42
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# Comparators :2
4-bit comparator equal :1
4-bit comparator greater :1
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vcom1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vcom1, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Found no macro
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vcom1.ngr
Top Level Output File Name : vcom1
Output Format : NGC
Optimization Goal : Speed
Page | 43
Keep Hierarchy : NO
Design Statistics
# IOs : 11
Cell Usage :
# BELS :7
# LUT2 :1
# LUT3 :1
# LUT4 :5
# IO Buffers : 11
# IBUF :8
# OBUF :3
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 4 out of 960 0%
Number of 4 input LUTs: 7 out of 1920 0%
Number of IOs: 11
Number of bonded IOBs: 11 out of 66 16%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 8.029ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)

Page | 44
=============================================================
============
Timing constraint: Default path analysis
Total number of paths / destination ports: 40 / 3
-------------------------------------------------------------------------
Delay: 8.029ns (Levels of Logic = 5)
Source: a<1> (PAD)
Destination: altb (PAD)
Data Path: a<1> to altb
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.532 a_1_IBUF (a_1_IBUF)
LUT4:I0->O 1 0.612 0.509 aeqb426 (aeqb426)
LUT2:I0->O 3 0.612 0.520 aeqb454 (aeqb_OBUF)
LUT4:I1->O 1 0.612 0.357 altb (altb_OBUF)
OBUF:I->O 3.169 altb_OBUF (altb)
----------------------------------------
Total 8.029ns (6.111ns logic, 1.918ns route)
(76.1% logic, 23.9% route)
=============================================================
============
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.98 secs

-->
Total memory usage is 240308 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

RESULT: Simulated the VERILOG codes for FOUR-BIT COMPARATOR and obtained
the timing diagrams.

Page | 45
Logic diagram:

Graphical symbol

Transition table

TIMING WAVEFORMS

Page | 46
 EXPERIMENT-5

FLIP-FLOPS
AIM: To develop the source code for FLIP-FLOPS & by using VHDL/VERILOG and
obtain the simulation, synthesis.

VERILOG CODE FOR D FLIP-FLOP:

module vdff1(d, clk, reset, q, qb);

input d;

input clk;

input reset;

output q;

output qb;

reg q;

always@(posedge reset or negedge clk)

if(reset)

q=1'b0;

else

q=d;

assign qb=~q;

endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "cvded.v" in library work
Module <vdff1> compiled
No errors in compilation
Analysis of file <"vdff1.prj"> succeeded.

Page | 47
=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vdff1> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vdff1>.
Module <vdff1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vdff1>.
Related source file is "cvded.v".
Found 1-bit register for signal <q>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <vdff1> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# Registers :1
1-bit register :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# Registers :1
Flip-Flops :1
=============================================================
============
=============================================================
============
Page | 48
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vdff1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vdff1, actual ratio is 0.
FlipFlop q has been replicated 1 time(s) to handle iob=true attribute.
Final Macro Processing ...
=============================================================
============
Final Register Report
Macro Statistics
# Registers :2
Flip-Flops :2
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vdff1.ngr
Top Level Output File Name : vdff1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :1
# INV :1
# FlipFlops/Latches :2
# FDC_1 :2
# Clock Buffers :1
# BUFGP :1
# IO Buffers :4
# IBUF :2
# OBUF :2
Page | 49
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 1 out of 1920 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 66 7%
IOB Flip Flops: 2
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
reset | IBUF |2 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: 1.754ns
Maximum output required time after clock: 5.009ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Page | 50
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 1.754ns (Levels of Logic = 1)
Source: d (PAD)
Destination: q (FF)
Destination Clock: clk falling
Data Path: d to q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.380 d_IBUF (d_IBUF)
FDC_1:D 0.268 q
----------------------------------------
Total 1.754ns (1.374ns logic, 0.380ns route)
(78.3% logic, 21.7% route)
=============================================================
============
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 5.009ns (Levels of Logic = 2)
Source: q (FF)
Destination: qb (PAD)
Source Clock: clk falling
Data Path: q to qb
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC_1:C->Q 1 0.514 0.357 q (q_OBUF)
INV:I->O 1 0.612 0.357 qb1_INV_0 (qb_OBUF)
OBUF:I->O 3.169 qb_OBUF (qb)
----------------------------------------
Total 5.009ns (4.295ns logic, 0.714ns route)
(85.7% logic, 14.3% route)
=============================================================
============
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.44 secs

-->
Total memory usage is 240436 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Page | 51
 RS-FLIP FLOP

Block Diagram:

Logic diagram

Truth table

TIMING WAVEFORMAS

Page | 52
 SR FLIP-FLOP

VERILOG CODE SR FLIP-FLOP:

module vsrff1(s, r, clk, q, qnot);

input s;

input r;

input clk;

output q;

output qnot;

reg q;

reg x;

assign qnot = ~q;

always @ (posedge clk)

begin

case ({s,r})

2'b00 : q = q;

2'b01: q = 1'b0;

2'b10 : q = 1'b1;

2'b11 : q = x;

endcase

end

endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "cvded.v" in library work
Module <vsrff1> compiled
No errors in compilation

Page | 53
Analysis of file <"vsrff1.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vsrff1> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vsrff1>.
Module <vsrff1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vsrff1>.
Related source file is "cvded.v".
.
Found 1-bit register for signal <q>.
Found 1-bit 4-to-1 multiplexer for signal <q$mux0000> created at line 12.
Summary:
inferred 1 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <vsrff1> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# Registers :1
1-bit register :1
# Multiplexers :1
1-bit 4-to-1 multiplexer :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Page | 54
Macro Statistics
# Registers :1
Flip-Flops :1
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vsrff1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vsrff1, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Macro Statistics
# Registers :1
Flip-Flops :1
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vsrff1.ngr
Top Level Output File Name : vsrff1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :1
# INV :1
# FlipFlops/Latches :1
Page | 55
# FDRS :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers :4
# IBUF :2
# OBUF :2
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 1 out of 960 0%
Number of Slice Flip Flops: 1 out of 1920 0%
Number of 4 input LUTs: 1 out of 1920 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 66 7%
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |1 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 1.760ns (Maximum Frequency: 568.069MHz)
Minimum input arrival time before clock: 2.258ns
Maximum output required time after clock: 5.103ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
Page | 56
=============================================================
============
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 1.760ns (frequency: 568.069MHz)
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 1.760ns (Levels of Logic = 0)
Source: q (FF)
Destination: q (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: q to q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRS:C->Q 3 0.514 0.451 q (q_OBUF)
FDRS:S 0.795 q
----------------------------------------
Total 1.760ns (1.309ns logic, 0.451ns route)
(74.4% logic, 25.6% route)
=============================================================
============
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 2.258ns (Levels of Logic = 1)
Source: r (PAD)
Destination: q (FF)
Destination Clock: clk rising
Data Path: r to q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.106 0.357 r_IBUF (r_IBUF)
FDRS:R 0.795 q
----------------------------------------
Total 2.258ns (1.901ns logic, 0.357ns route)
(84.2% logic, 15.8% route)
=============================================================
============
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 5.103ns (Levels of Logic = 2)
Source: q (FF)
Destination: qnot (PAD)
Source Clock: clk rising
Data Path: q to qnot
Gate Net
Page | 57
 Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRS:C->Q 3 0.514 0.451 q (q_OBUF)
INV:I->O 1 0.612 0.357 qnot1_INV_0 (qnot_OBUF)
OBUF:I->O 3.169 qnot_OBUF (qnot)
----------------------------------------
Total 5.103ns (4.295ns logic, 0.808ns route)
(84.2% logic, 15.8% route)
=============================================================
============
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.16 secs

Page | 58
 JK-FLIP FLOP

(a) Logic diagram

(b) Graphical symbol

TIMING WAVEFORMS

Page | 59
 JK FLIP-FLOP

VERILOG CODE FOR JK FLIP-FLOP:

module vjkff1(J, K, CLK, Q, Qnot);

input J;

input K;

input CLK;

output Q;

output Qnot;

reg Q;

assign Qnot = ~Q;

always @ (posedge CLK)

begin

case ({J,K})

2'b00 : Q = Q;

2'b01: Q = 1'b0;

2'b10 : Q = 1'b1;

2'b11 : Q = ~Q;

endcase

end

endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "cvded.v" in library work
Module <vjkff1> compiled
No errors in compilation
Analysis of file <"vjkff1.prj"> succeeded.

Page | 60
=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vjkff1> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vjkff1>.
Module <vjkff1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vjkff1>.
Related source file is "cvded.v".
Found 1-bit register for signal <Q>.
Found 1-bit 4-to-1 multiplexer for signal <Q$mux0000> created at line 11.
Summary:
inferred 1 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <vjkff1> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# Registers :1
1-bit register :1
# Multiplexers :1
1-bit 4-to-1 multiplexer :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# Registers :1
Flip-Flops :1
Page | 61
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vjkff1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vjkff1, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Macro Statistics
# Registers :1
Flip-Flops :1
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vjkff1.ngr
Top Level Output File Name : vjkff1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :2
# INV :1
# LUT3 :1
# FlipFlops/Latches :1
# FD :1
# Clock Buffers :1
Page | 62
# BUFGP :1
# IO Buffers :4
# IBUF :2
# OBUF :2
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 1 out of 960 0%
Number of Slice Flip Flops: 1 out of 1920 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 66 7%
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK | BUFGP |1 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 1.875ns (Maximum Frequency: 533.234MHz)
Minimum input arrival time before clock: 2.495ns
Maximum output required time after clock: 5.103ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Page | 63
Timing constraint: Default period analysis for Clock 'CLK'
Clock period: 1.875ns (frequency: 533.234MHz)
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 1.875ns (Levels of Logic = 1)
Source: Q (FF)
Destination: Q (FF)
Source Clock: CLK rising
Destination Clock: CLK rising
Data Path: Q to Q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 3 0.514 0.481 Q (Q_OBUF)
LUT3:I2->O 1 0.612 0.000 Mmux_Q_mux000011 (Q_mux0000)
FD:D 0.268 Q
----------------------------------------
Total 1.875ns (1.394ns logic, 0.481ns route)
(74.3% logic, 25.7% route)
=============================================================
============
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Total number of paths / destination ports: 2 / 1
-------------------------------------------------------------------------
Offset: 2.495ns (Levels of Logic = 2)
Source: K (PAD)
Destination: Q (FF)
Destination Clock: CLK rising
Data Path: K to Q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.106 0.509 K_IBUF (K_IBUF)
LUT3:I0->O 1 0.612 0.000 Mmux_Q_mux000011 (Q_mux0000)
FD:D 0.268 Q
----------------------------------------
Total 2.495ns (1.986ns logic, 0.509ns route)
(79.6% logic, 20.4% route)
=============================================================
============
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 5.103ns (Levels of Logic = 2)
Source: Q (FF)
Destination: Qnot (PAD)
Source Clock: CLK rising
Data Path: Q to Qnot
Gate Net
Page | 64
 Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 3 0.514 0.451 Q (Q_OBUF)
INV:I->O 1 0.612 0.357 Qnot1_INV_0 (Qnot_OBUF)
OBUF:I->O 3.169 Qnot_OBUF (Qnot)
----------------------------------------
Total 5.103ns (4.295ns logic, 0.808ns route)
(84.2% logic, 15.8% route)
=============================================================
============
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.80 secs

-->
Total memory usage is 240244 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Page | 65
 T-FLIP FLOP

LOGIC DIAGRAM:

Graphical symbol

Transition table

TIMING WAVEFORMS

Page | 66
 T FLIP-FLOP

VERILOG CODE T FLIP-FLOP:

module vtff1(Q, Qnot, CLK, T);

output Q;

output Qnot;

input CLK;

input T;

reg Q;

assign Qnot=~Q;

always@(posedge CLK)

begin

case({T})

2'b00:Q=0;

2'b01:Q=1;

2'b10:Q=1;

2'b11:Q=0;

endcase

end

endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "cvded.v" in library work
Module <vtff1> compiled
No errors in compilation
Analysis of file <"vtff1.prj"> succeeded.

Page | 67
=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vtff1> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vtff1>.
Module <vtff1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vtff1>.
Related source file is "cvded.v".
Found 1-bit register for signal <Q>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <vtff1> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# Registers :1
1-bit register :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# Registers :1
Flip-Flops :1
=============================================================
============
=============================================================
============
Page | 68
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vtff1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vtff1, actual ratio is 0.
FlipFlop Q has been replicated 1 time(s) to handle iob=true attribute.
Final Macro Processing ...
=============================================================
============
Final Register Report
Macro Statistics
# Registers :2
Flip-Flops :2
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vtff1.ngr
Top Level Output File Name : vtff1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :4
Cell Usage :
# BELS :1
# INV :1
# FlipFlops/Latches :2
# FD :2
# Clock Buffers :1
# BUFGP :1
# IO Buffers :3
# IBUF :1
# OBUF :2
Page | 69
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 1 out of 1920 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 66 6%
IOB Flip Flops: 2
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK | BUFGP |2 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: 1.754ns
Maximum output required time after clock: 5.009ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 1.754ns (Levels of Logic = 1)
Page | 70
 Source: T (PAD)
Destination: Q (FF)
Destination Clock: CLK rising
Data Path: T to Q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.380 T_IBUF (T_IBUF)
FD:D 0.268 Q
----------------------------------------
Total 1.754ns (1.374ns logic, 0.380ns route)
(78.3% logic, 21.7% route)
=============================================================
============
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 5.009ns (Levels of Logic = 2)
Source: Q (FF)
Destination: Qnot (PAD)
Source Clock: CLK rising
Data Path: Q to Qnot
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.514 0.357 Q (Q_OBUF)
INV:I->O 1 0.612 0.357 Qnot1_INV_0 (Qnot_OBUF)
OBUF:I->O 3.169 Qnot_OBUF (Qnot)
----------------------------------------
Total 5.009ns (4.295ns logic, 0.714ns route)
(85.7% logic, 14.3% route)
=============================================================
============
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.16 secs

-->
Total memory usage is 239732 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

RESULT: Simulated the VERILOG codes for FLIP-FLOPS and obtained the timing
diagram

Page | 71
BLOCK DIAGRAM

LOGIC DIAGRAM

TIMING WAVEFORM

Page | 72
 EXPERIMENT-6

8-BIT SHIFT REGISTER

VERILOG CODE FOR 8-BIT SHIFT REGISTER:

module SHIFT1(r, clk, reset, w, q);

input [7:0] r;

input clk;

input reset;

input w;

output [7:0] q;

integer i;

reg[7:0]q;

always @ (r or clk or w or reset)

begin

if(clk==1)

if(reset==1)

q=r;

else

if(reset==0)

begin

for(i=0;i<7;i=i+1)

begin

q[i]=q[i+1];

end

q[7]=w;

end
Page | 73
end

endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "cvded.v" in library work
Module <SHIFT1> compiled
No errors in compilation
Analysis of file <"SHIFT1.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <SHIFT1> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <SHIFT1>.
Module <SHIFT1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <i> in unit <SHIFT1> has a constant value of 111 during
circuit operation. The register is replaced by logic.
Synthesizing Unit <SHIFT1>.
Related source file is "cvded.v".
===========================================
HDL Synthesis Report
Macro Statistics
# Latches :8
1-bit latch :8
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
Page | 74
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# Latches :8
1-bit latch :8
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <SHIFT1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SHIFT1, actual ratio is 0.
Latch q_7 has been replicated 1 time(s) to handle iob=true attribute.
Final Macro Processing ...
=============================================================
============
Final Register Report
Found no macro
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : SHIFT1.ngr
Top Level Output File Name : SHIFT1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 19
Page | 75
Cell Usage :
# BELS :8
# LUT3 :8
# FlipFlops/Latches :9
# LD :9
# Clock Buffers :1
# BUFGP :1
# IO Buffers : 18
# IBUF : 10
# OBUF :8
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 4 out of 960 0%
Number of Slice Flip Flops: 8 out of 1920 0%
Number of 4 input LUTs: 8 out of 1920 0%
Number of IOs: 19
Number of bonded IOBs: 19 out of 66 28%
IOB Flip Flops: 1
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |9 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 1.878ns (Maximum Frequency: 532.496MHz)
Minimum input arrival time before clock: 2.781ns
Page | 76
 Maximum output required time after clock: 4.137ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 1.878ns (frequency: 532.496MHz)
Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Delay: 1.878ns (Levels of Logic = 1)
Source: q_1 (LATCH)
Destination: q_0 (LATCH)
Source Clock: clk falling
Destination Clock: clk falling
Data Path: q_1 to q_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 2 0.588 0.410 q_1 (q_1)
LUT3:I2->O 1 0.612 0.000 q_0_mux00001 (q_0_mux0000)
LD:D 0.268 q_0
----------------------------------------
Total 1.878ns (1.468ns logic, 0.410ns route)
(78.2% logic, 21.8% route)
=============================================================
============
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 20 / 9
-------------------------------------------------------------------------
Offset: 2.781ns (Levels of Logic = 2)
Source: reset (PAD)
Destination: q_7 (LATCH)
Destination Clock: clk falling
Data Path: reset to q_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 8 1.106 0.795 reset_IBUF (reset_IBUF)
LUT3:I0->O 2 0.612 0.000 q_7_mux00001 (q_7_mux0000)
LD:D 0.268 q_7
----------------------------------------
Total 2.781ns (1.986ns logic, 0.795ns route)
(71.4% logic, 28.6% route)
=============================================================
============
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 8 / 8
Page | 77
-------------------------------------------------------------------------
Offset: 4.137ns (Levels of Logic = 1)
Source: q_6 (LATCH)
Destination: q<6> (PAD)
Source Clock: clk falling
Data Path: q_6 to q<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 2 0.588 0.380 q_6 (q_6)
OBUF:I->O 3.169 q_6_OBUF (q<6>)
----------------------------------------
Total 4.137ns (3.757ns logic, 0.380ns route)
(90.8% logic, 9.2% route)
=============================================================
============
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.82 secs

RESULT: Simulated the VERILOG codes for SHIFT REGISTER and obtained the timing
diagrams.

Page | 78
 SYNCHRONOUS COUNTER

LOGIC DIAGRAM:

Block Diagram:

TIMING WAVEFORM

Page | 79
 EXPERIMENT-7

COUNTERS
AIM: To develop the source code for COUNTERS by using VERILOG and obtain the
simulation, synthesis.

VERILOG CODE FOR SYNCHRONOUS COUNTER:

module counter (out,clk);

output [4:1] out;

input clk;

reg [4:1] out;

initial

begin

out=1'd14;

end

always @(posedge clk)

out <= out -1;

endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "cvded.v" in library work
Module <counter> compiled
No errors in compilation
Analysis of file <"counter.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <counter> in library <work>.

Page | 80
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <counter>.
Module <counter> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <counter>.
Related source file is "cvded.v".
Found 4-bit down counter for signal <out>.
Summary:
inferred 1 Counter(s).
Unit <counter> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# Counters :1
4-bit down counter :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# Counters :1
4-bit down counter :1
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <counter> ...
Mapping all equations...
Building and optimizing final netlist ...
Page | 81
Found area constraint ratio of 100 (+ 5) on block counter, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Macro Statistics
# Registers :4
Flip-Flops :4
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : counter.ngr
Top Level Output File Name : counter
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :4
# LUT2 :1
# LUT3 :1
# LUT4 :1
# VCC :1
# FlipFlops/Latches :4
# FD :3
# FDR :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers :4
# OBUF :4
=============================================================
============
Device utilization summary:
---------------------------
Page | 82
Selected Device : 3s100evq100-5
Number of Slices: 2 out of 960 0%
Number of Slice Flip Flops: 4 out of 1920 0%
Number of 4 input LUTs: 3 out of 1920 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 66 7%
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 2.045ns (Maximum Frequency: 489.010MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 4.221ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.045ns (frequency: 489.010MHz)
Total number of paths / destination ports: 10 / 4
-------------------------------------------------------------------------
Delay: 2.045ns (Levels of Logic = 1)
Source: out_2 (FF)
Destination: out_2 (FF)
Source Clock: clk rising
Page | 83
 Destination Clock: clk rising
Data Path: out_2 to out_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 4 0.514 0.651 out_2 (out_2)
LUT2:I0->O 1 0.612 0.000 Mcount_out_xor<1>11 (Result<1>)
FD:D 0.268 out_2
----------------------------------------
Total 2.045ns (1.394ns logic, 0.651ns route)
(68.2% logic, 31.8% route)
=============================================================
============
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 4.221ns (Levels of Logic = 1)
Source: out_1 (FF)
Destination: out<1> (PAD)
Source Clock: clk rising
Data Path: out_1 to out<1>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 5 0.514 0.538 out_1 (out_1)
OBUF:I->O 3.169 out_1_OBUF (out<1>)
----------------------------------------
Total 4.221ns (3.683ns logic, 0.538ns route)
(87.3% logic, 12.7% route)
=============================================================
============
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.87 secs

RESULT: Simulated the VERILOG codes for COUNTERS and obtained the timing
diagrams.

Page | 84
 MOORE FSM

Block Diagram:

STATE DIAGRAM

TIMING WAVEFORM

Page | 85
 EXPERIMENT-8

FINITE STATE MACHINES

VERILOG CODE FOR MOORE FSM:

module vmo1(clk, x, z);

input clk;

input x;

output z;

reg [1:0] state;

parameter [1:0] zero =2'b00,

one=2'b01,

two=2'b10,

three=2'b11;

assign z=state[1] & state[0];

always@(posedge clk)

case(state)

zero:if(x==0)

state<=zero;

else

state<=one;

one:if(x==0)

state<=two;

else

state<=one;

two:if(x==0)

Page | 86
state<=zero;

else

state<=three;

three:if(x==0)

state<=two;

else

state<=one;

default:state<=zero;

endcase

endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "fnnv.v" in library work
Module <vmo1> compiled
No errors in compilation
Analysis of file <"vmo1.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vmo1> in library <work> with parameters.
one = "01"
three = "11"
two = "10"
zero = "00"
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vmo1>.
one = 2'b01
three = 2'b11
two = 2'b10
Page | 87
 zero = 2'b00
Module <vmo1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vmo1>.
Related source file is "fnnv.v".
Found 2-bit register for signal <state>.
Found 2-bit 4-to-1 multiplexer for signal <state$mux0000> created at line 12.
Summary:
inferred 2 D-type flip-flop(s).
inferred 2 Multiplexer(s).
Unit <vmo1> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# Registers :1
2-bit register :1
# Multiplexers :1
2-bit 4-to-1 multiplexer :1
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# Registers :2
Flip-Flops :2
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vmo1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vmo1, actual ratio is 0.
Page | 88
Final Macro Processing ...
=============================================================
============
Final Register Report
Macro Statistics
# Registers :2
Flip-Flops :2
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vmo1.ngr
Top Level Output File Name : vmo1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :3
Cell Usage :
# BELS :2
# LUT2 :1
# LUT3 :1
# FlipFlops/Latches :2
# FD :2
# Clock Buffers :1
# BUFGP :1
# IO Buffers :2
# IBUF :1
# OBUF :1
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 1 out of 960 0%
Number of Slice Flip Flops: 2 out of 1920 0%
Page | 89
 Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 3
Number of bonded IOBs: 3 out of 66 4%
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 1.843ns (Maximum Frequency: 542.608MHz)
Minimum input arrival time before clock: 2.518ns
Maximum output required time after clock: 5.184ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 1.843ns (frequency: 542.608MHz)
Total number of paths / destination ports: 2 / 1
-------------------------------------------------------------------------
Delay: 1.843ns (Levels of Logic = 1)
Source: state_0 (FF)
Destination: state_1 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: state_0 to state_1
Gate Net
Page | 90
 Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.514 0.449 state_0 (state_0)
LUT3:I1->O 1 0.612 0.000 Mmux_state_mux000021
(state_mux0000<0>)
FD:D 0.268 state_1
----------------------------------------
Total 1.843ns (1.394ns logic, 0.449ns route)
(75.6% logic, 24.4% route)
=============================================================
============
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 2.518ns (Levels of Logic = 2)
Source: x (PAD)
Destination: state_1 (FF)
Destination Clock: clk rising
Data Path: x to state_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.532 x_IBUF (x_IBUF)
LUT3:I0->O 1 0.612 0.000 Mmux_state_mux000021
(state_mux0000<0>)
FD:D 0.268 state_1
----------------------------------------
Total 2.518ns (1.986ns logic, 0.532ns route)
(78.9% logic, 21.1% route)
=============================================================
============
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 2 / 1
-------------------------------------------------------------------------
Offset: 5.184ns (Levels of Logic = 2)
Source: state_1 (FF)
Destination: z (PAD)
Source Clock: clk rising
Data Path: state_1 to z
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.514 0.532 state_1 (state_1)
LUT2:I0->O 1 0.612 0.357 z1 (z_OBUF)
OBUF:I->O 3.169 z_OBUF (z)
----------------------------------------
Total 5.184ns (4.295ns logic, 0.889ns route)
(82.9% logic, 17.1% route)

Page | 91
=============================================================
============
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.11 secs

-->
Total memory usage is 239348 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Page | 92
 MEALY FSM

Block Diagram:

STATE DIAGRAM

TIMING WAVEFORMS

Page | 93
 MEALY FSM
VERILOG CODE FOR MEALY FSM:

module vmealy1(clk, x, z);

input clk;

input x;

output z;

reg [1:0] state;

parameter [1:0] zero=2'b00,

one=2'b01,

two=2'b10;

assign z=x&state[1];

always@(posedge clk)

case(state)

zero:if(x==0)

state<=zero;

else

state<=one;

one:if(x==0)

state<=two;

else

state<=one;

two:if(x==0)

state<=zero;

else

state<=one;

default:state<=zero;

endcase
Page | 94
endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "fnnv.v" in library work
Module <vmealy1> compiled
No errors in compilation
Analysis of file <"vmealy1.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <vmealy1> in library <work> with parameters.
one = "01"
two = "10"
zero = "00"
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <vmealy1>.
one = 2'b01
two = 2'b10
zero = 2'b00
Module <vmealy1> is correct for synthesis.

=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <vmealy1>.
Related source file is "fnnv.v".
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States |3 |
| Transitions |3 |
| Inputs |0 |
| Outputs |1 |
| Clock | clk (rising_edge) |

Page | 95
 | Reset |x (positive) |
| Reset type | synchronous |
| Reset State | 01 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <vmealy1> synthesized.
=============================================================
============
HDL Synthesis Report
Found no macro
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <state/FSM> on signal <state[1:2]> with user encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 10
-------------------
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# FSMs :1
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <vmealy1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vmealy1, actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Page | 96
Macro Statistics
# Registers :2
Flip-Flops :2
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : vmealy1.ngr
Top Level Output File Name : vmealy1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :3
Cell Usage :
# BELS :2
# GND :1
# LUT2 :1
# FlipFlops/Latches :2
# FDR :1
# FDS :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers :2
# IBUF :1
# OBUF :1
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 1 out of 960 0%
Number of Slice Flip Flops: 2 out of 1920 0%
Number of 4 input LUTs: 1 out of 1920 0%
Number of IOs: 3
Number of bonded IOBs: 3 out of 66 4%
Page | 97
 Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 1.139ns (Maximum Frequency: 877.963MHz)
Minimum input arrival time before clock: 2.352ns
Maximum output required time after clock: 5.078ns
Maximum combinational path delay: 5.847ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 1.139ns (frequency: 877.963MHz)
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 1.139ns (Levels of Logic = 0)
Source: state_FSM_FFd2 (FF)
Destination: state_FSM_FFd1 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: state_FSM_FFd2 to state_FSM_FFd1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDS:C->Q 1 0.514 0.357 state_FSM_FFd2 (state_FSM_FFd2)
Page | 98
 FDR:D 0.268 state_FSM_FFd1
----------------------------------------
Total 1.139ns (0.782ns logic, 0.357ns route)
(68.7% logic, 31.3% route)
=============================================================
============
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 2.352ns (Levels of Logic = 1)
Source: x (PAD)
Destination: state_FSM_FFd2 (FF)
Destination Clock: clk rising
Data Path: x to state_FSM_FFd2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 3 1.106 0.451 x_IBUF (x_IBUF)
FDS:S 0.795 state_FSM_FFd2
----------------------------------------
Total 2.352ns (1.901ns logic, 0.451ns route)
(80.8% logic, 19.2% route)
=============================================================
============
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 5.078ns (Levels of Logic = 2)
Source: state_FSM_FFd1 (FF)
Destination: z (PAD)
Source Clock: clk rising
Data Path: state_FSM_FFd1 to z
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 1 0.514 0.426 state_FSM_FFd1 (state_FSM_FFd1)
LUT2:I1->O 1 0.612 0.357 z1 (z_OBUF)
OBUF:I->O 3.169 z_OBUF (z)
----------------------------------------
Total 5.078ns (4.295ns logic, 0.783ns route)
(84.6% logic, 15.4% route)
=============================================================
============
Timing constraint: Default path analysis
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 5.847ns (Levels of Logic = 3)
Source: x (PAD)
Destination: z (PAD)
Page | 99
 Data Path: x to z
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 3 1.106 0.603 x_IBUF (x_IBUF)
LUT2:I0->O 1 0.612 0.357 z1 (z_OBUF)
OBUF:I->O 3.169 z_OBUF (z)
----------------------------------------
Total 5.847ns (4.887ns logic, 0.960ns route)
(83.6% logic, 16.4% route)
=============================================================
============
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.64 secs

-->
Total memory usage is 240180 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

RESULT: Simulated the VERILOG codes for MOORE AND MEALY FSM and obtained
the timing diagrams.

Page | 100
Page | 101
 EXPERIMENT-9

FULL ADDER
AIM: To develop the source code for FSM by using VERILOG and obtain the
simulation, synthesis.

VERILOG CODE FOR FULL ADDER:

module Full_Adder_Structural_Verilog(
input X1, X2, Cin,
output S, Cout
);
wire a1, a2, a3;
xor u1(a1,X1,X2);
and u2(a2,X1,X2);
and u3(a3,a1,Cin);
or u4(Cout,a2,a3);
xor u5(S,a1,Cin);
endmodule

SYNTHESIS REPORT:

=============================================================
============
* HDL Compilation *
=============================================================
============
Compiling verilog file "fnnv.v" in library work
Module <Full_Adder_Structural_Verilog> compiled
No errors in compilation
Analysis of file <"Full_Adder_Structural_Verilog.prj"> succeeded.

=============================================================
============
* Design Hierarchy Analysis *
=============================================================
============
Analyzing hierarchy for module <Full_Adder_Structural_Verilog> in library <work>.
=============================================================
============
* HDL Analysis *
=============================================================
============
Analyzing top module <Full_Adder_Structural_Verilog>.
Module <Full_Adder_Structural_Verilog> is correct for synthesis.

Page | 102
=============================================================
============
* HDL Synthesis *
=============================================================
============
Performing bidirectional port resolution...
Synthesizing Unit <Full_Adder_Structural_Verilog>.
Related source file is "fnnv.v".
Found 1-bit xor2 for signal <S>.
Found 1-bit xor2 for signal <a1>.
Unit <Full_Adder_Structural_Verilog> synthesized.
=============================================================
============
HDL Synthesis Report
Macro Statistics
# Xors :2
1-bit xor2 :2
=============================================================
============
=============================================================
============
* Advanced HDL Synthesis *
=============================================================
============
=============================================================
============
Advanced HDL Synthesis Report
Macro Statistics
# Xors :2
1-bit xor2 :2
=============================================================
============
=============================================================
============
* Low Level Synthesis *
=============================================================
============
Optimizing unit <Full_Adder_Structural_Verilog> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Full_Adder_Structural_Verilog,
actual ratio is 0.
Final Macro Processing ...
=============================================================
============
Final Register Report
Found no macro

Page | 103
=============================================================
============
=============================================================
============
* Partition Report *
=============================================================
============
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=============================================================
============
* Final Report *
=============================================================
============
Final Results
RTL Top Level Output File Name : Full_Adder_Structural_Verilog.ngr
Top Level Output File Name : Full_Adder_Structural_Verilog
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :2
# LUT3 :2
# IO Buffers :5
# IBUF :3
# OBUF :2
=============================================================
============
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 66 7%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=============================================================
============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

Page | 104
 FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 5.776ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=============================================================
============
Timing constraint: Default path analysis
Total number of paths / destination ports: 6 / 2
-------------------------------------------------------------------------
Delay: 5.776ns (Levels of Logic = 3)
Source: X1 (PAD)
Destination: Cout (PAD)
Data Path: X1 to Cout
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.532 X1_IBUF (X1_IBUF)
LUT3:I0->O 1 0.612 0.357 Cout1 (Cout_OBUF)
OBUF:I->O 3.169 Cout_OBUF (Cout)
----------------------------------------
Total 5.776ns (4.887ns logic, 0.889ns route)
(84.6% logic, 15.4% route)
=============================================================
============
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.24 secs
-->
Total memory usage is 239348 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

RESULT: Simulated the VERILOG codes for FULL ADDER and obtained the timing
diagrams.
Page | 105
Page | 106