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EDITED BY BILL TRAVIS & ANNE WATSON SWAGER

Sof t w ar e PLL l ocks VCXO t o r ef er ence

MARTIN OSSMANN, PHILIPS RESEARCH LABS, AACHEN, GERMANY
The circuit in Figure 1 provides a precisely controlled clock signal. The method modifies the controllers quartz oscillator such that the control voltage at point P1 controls the frequency. A D/A converter using an R-2R ladder network connected to output port D generates the control voltage. A precise reference-frequency signal connects to the controllers analog-comparator input, AIN0. In this application, the reference frequency is 162 kHz (derived from a long-wave broadcast station). You can use any other 10- to 200-kHz frequency. The Atmel (www.atmel.com) AT90S1200 controller performs a PLL function to lock the clock to the reference. You can use the precise frequency available at point P2 to clock mCs or other digital circuitry. An 18-instruction program provides the PLL function (Listing 1 ). You can download Listing 1 from EDNs Web site, www.ednmag.com. At the registered-user area, go into the Software Center to download the file from DI-SIG, #2229. Figure 2 shows the operating principle. The variables dds0 to dds3 hold a 32-bit, direct-digital-synthesis (DDS)-type numerical oscillator. The routine XORs the

LISTING 1AT90S1200 CODE FOR PLL

FREQUENCY LOCK

FIGURE 1

A microcontroller can provide a PLL function to obtain a precise reference-locked frequency. www.ednmag.com EDN AUGUST 3, 1998

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most significant bit with the reference signal that enters the controller via the analog comparator. A count-and-dump function integrates the XOR output over 255 DDS cycles. Upon every 256th DDS cycle, the phase value routes to the DAC at Port D of the controller. Every loop lasts exactly 12 clock cycles. Thus, the DDS cycle frequency is one-twelfth of the controllers clock frequency. The program performs a

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phase comparison between the DDS and the reference. The DAC voltage controls the VCXO. By using other increments for the DDS, you can easily adapt the program for other clock or reference frequencies. You can also use the circuit for demodulating phase-modulated signals. (DI #2229) e To Vote For This Design, Circle No. 301

FIGURE 2

The frequency-lock circuit in Figure 1 uses DDS techniques to provide a precise submultiple of the reference frequency.

Spi ce i nt r oduces dead t i me i n si mul at i ons

CHRISTOPHE BASSO, MOTOROLA SEMICONDUCTOR, TOULOUSE, FRANCE
Bridge or half-bridge designs using MOSFETs or insulated-gate bipolar transistors need some dead time between commutations to avoid any cross-conduction current spikes. This statement is also valid for switch-mode power supplies that use synchronous rectification. In creating simulations, it is sometimes difficult to write the stimuli so as to define a dead time between commutations. Classic PULSE or PWL commands are impractical, especially when either frequency or pulse width changes during the simulation run. Figure 1 shows a approach to simulating dead time that

FIGURE 1

An inverter, a few XOR gates, and some passive components generate a deadtime interval for switch commutation. 116 b EDN AUGUST 3, 1998

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you can build around a few logic XOR gates. The principle uses the truth table of an XOR or XNOR gate: that the output is high or low only when both inputs have different logic states. The logic states come from the RC networks R1-C1 and R4-C5. The output of the IC1 and IC4 gates is thus a short pulse whose width depends on the RC time constants of the input network. This pulse blanks the signal delivered to the output and thus generates the required dead time. You can easily model the logic functions using Intusofts (www.intusoft.com) IsSpice4 Analog Behavioral Modeling features (List ing 1 ). You need to feed the subcircuit with the dead-time value as well as the output high and low levels. The input clock is TTL/CMOS-compatible. By changing the B5 line to V= V(26,20)<100MV ? {VHIGH} : {VLOW}, the generator becomes suitable for driving a synchronous rectifier (Figure 2 ). Figure 3 clearly shows the absence of overlap between commutations. You can download Listing 1 from EDNs Web site, www.ednmag.com. At the registered-user area, go into the Software Center to download the file from DISIG, #2228. (DI #2228) e To Vote For This Design, Circle No. 302

FIGURE 2

The circuit in Figure 1 generates the dead time to prevent cross-conduction in this synchronous-rectifier circuit. FIGURE 3

LISTING 1ISSPICE4 ANALOG BEHAVIORAL MODELING FEATURES

Current waveforms for the MOSFETs in Figure 2 show no simultaneous conduction. 118 b EDN AUGUST 3, 1998

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Ci r cui t t r ansl at es TTY cur r ent l oop t o RS- 232C

JERZY CHRZASZCZ, WARSAW UNIVERSITY, POLAND
The circuit in Figure 1a provides signal translation between a passive current-loop (TTY) interface and a duplex RS-232C port. The current flowing in the receiver loop causes the transistor to pull down RxD; when the transistor turns off, R1 pulls up RxD. In like manner, the current in the transmitter loop switches on for a negative TxD voltage and off for a positive voltage. The supply power comes from the interface control lines, so you must properly preset these lines. Unfortunately, terminal programs do not usually support direct control of handshake signals. In other words, you must write your own service routine for the serial port to obtain a negative supply. Worse, some RS-232C-like ports feature just one handshake line, rendering the circuit in Figure 1a unusable. In such cases, you could use the interface in Figure 1b . Because the transmitter output acts as the negative supply rail, the circuit can receive data only when TxD remains inactive. This limitation obviously precludes full-duplex transmission. Note also that transmitted data directly echoes at the RxD input. However, if half-duplex operation is satisfactory and you can tolerate local echo, this circuit may be the one of choice. In both circuits, external diodes (for example, 1N4148) protect the LEDs against reverse voltages. The values of R1 and R2 depend on the optocoupler type and loop current. You can use CNY75B optocouplers with 5.1 and 220V for R1 and R2, respectively. (DI #2230) e To Vote For This Design, Circle No. 303

FIGURE 1

An optocoupler and two resistors configure a TTY-to-RS-232C translator. Use the circuit in (a) when a negative supply is available; otherwise, use the circuit in (b).

80186 t i mer pi ns pr ovi de gener al I/ O

SK SHENOY, NPOL, KOCHI, INDIA
Intels (www.intel.com) 80186 is a highly integrated mP common in embedded applications. It combines 15 to 20 common iAPX86 system components, such as a DMA controller, an interrupt controller, timers, a clock generator, a bus interface, and chip-select logic on one chip. Unfortunately, unlike many mCs, it provides no general-purpose I/O pins. However, if you require only a couple of input or latched-output lines, you can use the built-in timer I/O pins as general-purpose input or output lines by using this programming method (Listing 1 ). The 80186 has two timers (0 and 1), each with two external pins: one for input, one for output. However, the structure of the timers allows you to use any pair of pins, either for input or output, one at a time, but not simultaneously. In other words, you cannot use Timer1_Out pin as a latched output and Timer1_In pin as an input at the same time. This limitation exists because, when you use Timer_In for input, the state of Timer_Out may change. Thus, you can simultaneously obtain two latched outputs, two input lines, or one input and one output line. Finally, a lag of a few microseconds occurs for an output to respond, because the output is the result not of a single Out instruction but of a sequence of instructions. Moreover, you can see from the code in Listing 1 that in some cases one or two timer ticks must elapse before the state changes. The same situation exists in sampling an input level.

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FIGURE 1

You can use the timer pins in an 80186 mP to obtain a gener-

TABLE 2DEFAULT 80186 TIMER REGISTER ADDRESSES

Register name Mode/control word Max count B Max count A Count register Timer0 FF56H FF54H FF52H FF50H Timer1 FF5EH FF5CH FF5AH FF58H Timer2 FF66H Not present FF62H FF60H

However, in all but the most demanding applications, this delay of a few microseconds should be unobjectionable. For such applications, this technique can save on the additional hardware you need to provide an external port. The demo program uses the setup in Figure 1 . To output a bit, the routine makes the Timer1_Out pin assume either a 1 or 0 state by activating MaxCount A or B, respectively, and stopping the timer in that state. The state of the Timer_Out pin reflects which Max register the timer uses (register 1 for Max Reg A). To read an input fed to the Timer0_In pin, the routine keeps Timer0 running. Timer0 is configured so that it counts only if the Timer0_In pin is high. Thus, if Timer0 increments during two consecutive reads separated by a small delay greater than a timer clock period, it means the input level is high. Listing 1 is a demo C program for obtaining output via the Timer1_Out pin and inputs via the Timer0_In pin. The program sends logic 1 or 0 to the Timer1_Out pin, based on the key (1 or 0) the user presses. If Timer1_Out connects to Timer0_In, as the dashed line in Figure 1 shows, the program reads and displays the inputs logic level through the Timer0_In pin. In the demo system, an RS-232C port on the 80186 hardware, connected to a terminal, serves for user keyboard input. TABLE 1TIMER CONTROL-WORD BITS The demo C program is written and compiled using an Intel IC86 compiler on an 8-MHz Bit 0 Set to 1 for continuous-mode running; 0 for one-shot mode 80186 system. However, the same technique is Bit 1 1 for time to alternate between maximum-count register A and B; 0 for A only Bit 2 1 to select external clock for the timer; 0 for internal, that is, CPU clock/4 applicable to other mPs/mCs having similar Bit 3 If 1, Timer 2 output is used as clock, else internal clock (CPU clock/4) is used timer capabilities. Table 1 gives the timer conBit 4 If 0, the input level gates the timer on or off (timer will count for a high) trol-word bits. Table 2 provides the default Bit 5 This is a read-only bit set when the timer reaches its maximum value Bit 11 This bit has to be 0 80186 timer register addresses. Bit 12 This read-only bit indicates which maximum-count register is in use (0 indicates A) You can download Listing 1 from EDNs Web Bit 13 If set, interrupts are generated on every terminal count Bit 14 If 0, Bit 15 (enable/disable) is ignored, else Bit 15 will take effect site, www.ednmag.com. At the registered-user Bit 15 If set, the timer is enabled; 0 stops the timer area, go into the Software Center to download Notes: All bits except bits 5 and 12 are read/write. the file from DI-SIG, #2231. (DI #2231) e
Bits 5 and 12 are read-only. Bits not shown don't care.

To Vote For This Design, Circle No. 304

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Li near i zi ng an RTD i s easy w i t h Spi ce

RICHARD FAEHNRICH, CONSULTANT, ARLINGTON HEIGHTS, IL
A popular way to design an accurate temperature probe using an inherently nonlinear devicea resistance temperature detector (RTD)uses positive multiplicative feedback. However, the transfer function of this method is also nonlinear, making an analytical approach difficult. A simpler method uses Spice to optimize the RTDs response by exciting the sensor with a particular waveform and performing simple signal processing on the circuits output. You can also measure the outputs nonlinearity while quickly trying a range of feedback parameters. The block diagrams of the multiplicative-feedback circuit (Figure 1a and Reference 1 ) show how the scheme multiplies the input by a fraction of the output and a fixed term. The transfer function is
y = x K G 11 ( x G) .

a straight line to the curve and measure the maximum deviation of the output curve from this line. Another way is to perform a quadratic fit and monitor the second-order coefficient as a measure of straightness. Although both of these methods work, extracting the data from Spice output files

FIGURE 2

y (V(3))

(a)

4 TIME (SEC)

10

Notice that when the feedback factor, a, is zero, the gain is simply equal to xKG. To understand the method, assume initially that x is linear. Introducing a small positive or negative a generates an output that is concave upward or downward, respectively. Now, if the input x exhibits an upward or downward curve, then the proper choice of a bends the curve in the opposite direction to improve the overall linearity. One way to measure the nonlinearity of the output is to fit

a (V(6))

(b)

4 TIME (SEC)

10

FIGURE 1
dy dt (V(8))

(c)

10

TIME (SEC)

dy dt (V(8))

(d)

4 TIME (SEC)

10

Multiplicative feedback (a) is one way to linearize an RTD. You can drive a corresponding Spice circuit (b) with a triangle waveform to measure the circuits nonlinearity and determine the value of a, for which the derivative of the output is flattest. 124 b EDN AUGUST 3, 1998

Spice makes it easy to view the output (a), the value of a (b), and the derivative of the output for two horizontal scales (c and d). The optimum value of a is the point at which the derivative is flattest, which occurs approximately 3 to 4 sec into the simulation, or when a ' 18 mV.

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and curve-fitting over a range of values for a are difficult and time-consuming. FIGURE 3 Alternatively, you can obtain some measure of nonlinearity by sweeping the temperature with a linear ramp function and then taking a derivative of the output response. A linear output should produce a constant derivative, and a concave upward or downward response produces an increasing or decreasing derivative, respectively. Therefore, the goal of this optimizing method is to find the value of a that results in the flattest derivative. However, because the input-ramp function increases without bound, this method instead uses a triangle wave to sweep the temperature. Now, by slowly sweeping a over many cycles of the triangle wave, a single simulation can measure the circuits performance with varying parameters. In the Spice circuit, VTEMP drives the A practical implementation of the RTD linearizing circuit includes linearity, gain, input temperature linearly from 0 to and offset adjustments. 4008 C with a 1-Hz triangle waveform (Figure 1b ). (You can download the corresponding Spice three adjustments until the circuit achieves the correct outnetlist from EDNs Web site, www.ednmag. com. At the reg- put voltages for the RTD resistances corresponding to the low, istered-user area, go into the Software Center to download midpoint, and high calibration temperatures (Figure 3 and the file from DI-SIG, #2224.) ERTD simulates the RTDs Reference 2 ). This circuit realizes the fixed gain and feedback response versus temperature using a second-order polynomi- terms as currents. Op amp IC1 implements the multiplier by al. To counteract the RTDs concave-downward behavior, the first summing the fixed and feedback currents and then mulcircuit introduces a positive feedback factor, a, with a con- tiplying the result by the RTDs resistance. IC2 provides addicave-upward characteristic. VALPHA sweeps a linearly for 10 tional gain, G, producing an output voltage given by sec. Therefore, the simulation determines the performance of V OUT = R RTD (i FIXED + i FB ) G , the circuit for the a range over 10 cycles of the triangle wave. The sum of the positive-feedback term, EFB, and a fixed term, VFIX, controls the gain of the multiplying block, EMULT. where G=R2/R1. The feedback-factor calculation is EGAIN provides a gain of G. Current source GDIFF and induci 1 tor LDIFF form the differentiator. = FB = . VOUT R FB The linearized output and the a parameter appear in Fig ure 2a and b, respectively. Figure 2c shows the output derivative, and Figure 2d shows only the tops of the derivatives A feedback factor of a =0.00002 (RFB=50 kV) in Figure 3 positive cycles. Note how the derivative in Figure 2d flattens, reduces the linearity error from 3.08 C to less than 0.18 C surrounded by a decreasing and increasing derivative to the over a 4008 C range. (DI #2224) e left and right of the optimal behavior, respectively. You can start with a broad range for a and then quickly narrow the References search after several simulations. Note that sweeping alpha during the triangle-wave cycles has some influence on the 1. Sheingold, D, Transducer Interfacing Handbook, Anaoutput response and, consequently, its derivative. However, log Devices, Norwood, MA, 1980, pg 99. this effect lessens as you narrow the range of a. 2. The Linear Applications Handbook, 1990, Linear You can implement the positive-feedback factor as a poten- Technology, Application Note 6, pg 2. tiometer with an adjustment range that brackets the optimum value as determined by your simulations. Note that the To Vote For This Design, Circle No. 305 overall gain and offset of the output versus temperature vary as a varies. Therefore, the final circuit should include a gain and offset adjustment in addition to the linearity adjustment. In one suggested circuit implementation, you repeat the

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To: Design Ideas Editor, EDN Magazine 275 Washington St, Newton, MA 02458 I hereby submit my Design Ideas entry. Name Title Phone E-mail Company Fax Entry blank must accompany all entries. (A separate entry blank for each author must accompany every entry.) Design entered must be submitted exclusively to EDN, must not be patented, and must have no patent pending. Design must be original with author(s), must not have been previously published (limited-distribution house organs excepted), and must have been constructed and tested. Fully annotate all circuit diagrams. Please submit software listings and all other computerreadable documentation on a IBM PC disk in plain ASCII. Exclusive publishing rights remain with Cahners Publishing Co unless entry is returned to author, or editor gives written permission for publication elsewhere. In submitting my entry, I agree to abide by the rules of the Design Ideas Program. Signed Country Design Idea Title Your vote determines this issues winner. Vote now, by circling the appropriate number on the reader inquiry card. ZIP Date

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