I.

SEQUENTIAL LOGIC CCTS:

include: flipflops (which are the basic building blocks), counters & registers.

in comb. ccts, present op depends on present ip.

IN OUT
comb
cct

example: half-adder cct, two ips (1 and 1) when summed produce SUM=0 and CARRY=1. using the same
adder, two ips (0 and 1) when summed produce SUM=1 and CARRY=0. the second (present) o/p has
nothing to do with the first (past) o/p.

in sequential ccts, the present o/p depends on present i/p as well as past o/p(s)

To convert a comb cct into a seq cct, the o/p has to be used in a memory.

IN OUT
comb
cct

MEMORY
past o/p or
feedback

example: a counter that counts from 0 to 9, adds 1 to the input. so 0+1=1; 1+1=2; and so on. it has to
recall the previous o/p to add 1 to it and so forth so the previous o/p needs to be stored in a memory.

this memory stores single bits (0 or 1). it is the flip flop.

II. MULTIVIBRATOR CIRCUITS

is a cct used to implement simple two-state devices such as flip flops.

they generate a clock or timing waveform.

There are three types:

1. Astable – the o.p is not stable in either state and continually switches from one state to the
other. it does not reqire an input such as clock pulse.
2. Monostable – one of the states is stable but the other is not. a trigger causes the circuit to enter
the unstable state and the cct will return to stable state after a set time.

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 3. Bistable – cct is stable in either state. the cct can be flipped from one state to the other by an
external event or trigger.

III. SR LATCH

is a storage element. stores ‘o’ or ‘1’ bits.

NAND SR LATCH

if S&R change, o/p can change. this is overcome using a clock signal to
control stored value.

S=set & R=reset;

if S=1; Q=1 (cct is set to ‘1’) & if R=1; Q=0 (cct is reset back to ‘0’)

TT FOR NAND
GATE:
A B Y
(S) (R) (Q)
0 0 1
0 1 1
1 0 1
1 1 0

Case 1: S=0, R=1 (if any i/p is 0, the o/p will be 1); Q=1. Q provides the i/p for Q’, so i/ps are (1,1), then
Q’=0. to store the data, the o/p must not change even if i/ps S&R change. to find this out, make S=1,
R=1. at NAND 1, i/ps are (S=1,Q’=0), thus Q=1. at NAND2, i/ps are (Q=1, R=1), thus Q’=0. when S=1,R=1,
there is memory. past o/p does not change.

Case 2: S=1, R=0 (if any i/p is 0, the o/p will be 1); Q’=1. Q’ provides the i/p for Q, so i/ps are (1,1), then
Q=0. to store the data, the o/p must not change even if i/ps S&R change. to find this out, make S=1, R=1.
at NAND 1, i/ps are (S=1,Q’=1), thus Q=0. at NAND2, i/ps are (Q=0, R=1), thus Q’=1. when S=1,R=1, there
is memory. past o/p does not change.

Case 3: S=0, R=0 (if any i/p is 0, the o/p will be 1); thus Q=1 as well as Q’=1, which is contradicting and
ultimately the outputs are changed hence these inputs are not used.

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TT FOR SR LATCH WITH
NAND GATE:
S R Q Q’
0 0 Not used
0 1 1 0
1 0 0 1
1 1 Memory

IV. LATCH VS FLIP-FLOP

the difference between a latch and a flipflop is a control input - clock pulse

a clock is a digital waveform/signal used to step a digital circuit through a sequence of states (HIGH &
LOW) so that the cct works only if the CLK is HIGH. if CLK is LOW, o/ps can be changed. it prevents the
flip-flop’s state from changing until the o/p (hence i/p) is stable so that other ccts which depend on the
o/p from the flip-flop are not affected by instability of the flip-flop’s inputs.

the clock pulse triggers the memory to change state.

two types of triggering:

1. level triggering
2. edge triggering- positive & negative edge triggering

V. TYPES OF FLIPFLOPS
1. SR FLIP-FLOP:

flip-flops are bistable. Can either be at logic level ‘0’ or level ‘1’.

TT FOR SR LATCH WITH

R*=(R.CLK)’=R’+CLK’ (by DeMorgan’s Law)

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 the triangle reps that it is edge-triggered. if it is not there, it is level triggered.

TT FOR SR FF row 1: IF CLK is LOW, S*=S’+1=1. R*=1. the values for S’ & R’ will not
CLK S R Q Q’ change the value for S* & R* thus x=don’t care.
0 x x Memory
1 0 0 Memory row 2: If CLK is HIGH, S*=S’=1& R*=R’=1
1 0 1 0 1
1 1 0 1 0 row 3: S*=1; R*=0; from tt for SR latch,
1 1 1 Not used
row 4: S*=0, R*=1. from tt for sr latch,

row 5: S*=0, R*=0, from tt for sr latch,

SMMARISED TT FOR SR FF
CLK S R Qn+1
0 x x Qn (value in
memory)
1 0 0 Qn (value in
memory)
1 0 1 0
1 1 0 1
1 1 1 Invalid
S & R are always complementing each other. to store bit ‘0’ in SR FF, set i/p should be ‘0’ and reset i/p
‘1’. to store bit ‘1’, set i/p should be ‘1’ & reset i/p ‘0’.

2. D FLIP-FLOPS (most widely used)

S & R are always complementing each other. to store bit ‘0’ in SR FF, set i/p should be ‘0’ and reset i/p
‘1’. to store bit ‘1’, set i/p should be ‘1’ & reset i/p ‘0’.

In D-FF, 1 in/p is supplied instead and complement the other with a not gate/inverter.

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TT FOR D FF:
CLK D Qn+1
0 x Qn
1 0 0
1 1 1
when clock is ‘0’, cct won’t take any i/p (x=don’t care)so o/p will be previous i/p.

when clock is HIGH and i/p =0 then S=0&R=1; thus, o/p Qn+1=0 (from SR FF TT)

when clock is HIGH and i/p =1 then S=1&R=0; thus, o/p Qn+1=1 (from SR FF TT)

condition S=1&R=1 has been eliminated in this FF.

3. JK FLIPFLOPS

creates a condition in which state S=1&R=1 can be used.

o/p Q is fed into NAND gate at R & Q’ is fed into NAND gate at S to creat i/ps K & J respectively.

if clk=0, o/p at both J & K NAND gates is 1. when the (S,R) i/p at the NAND latch is (1,1), the o/p is
stored. therefore memory state.

no change when you compare the tt for sr ff and jk ff. o/p are same. so when clk=1, j=1,k=0; Q=1, Q’=0.
when clk=1, j=0& k=1; Q=0 & Q’=1.

when clk=1, j=1 & k=1; assume Q-0 & Q’=1. at NAND K, i/p=(1,1,0). at NAND J, i/ps = (1,1,1). from NAND
gate tt, op at J=0 & K=1. ths Q=1&Q’=0. the o/p has changed so the i/p will also change and so forth so
that the o/p Q goes like 0, 1, 0, 1, 0, 1… and the opposite values for Q’ (this is called race around
condition where the value of the o/p keeps changing leading to uncertainty)

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 4. T FLIPFLOPS

J & K i/ps are same but CLK i/p is inverted.

TT FOR T FF:
CLK T Qn+1
0 x Qn
(Memory)
1 0 Qn
(Memory)
1 1 Qn’
(toggling)
when clk is ‘0’ nothing is being stored so past o/p remains same.

when clk is HIGH and i/p T=0 (both J&K are ‘0’), past o/p is used.

when cllk is HIGH and T=1 (both J&K are ‘1’), o/p toggles.

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