Key Specifications CPU z Dolby Digital/Dolby Digital Plus Decoder-Converter z Quad-core ARM Cortex A7, up to 1.5 GHz dominant z Dolby True HD decoding frequency z DTS and DTS HD core decoding z Integrated multimedia acceleration engine NEON z Dolby Digital/DTS transparent transmission z Hardware Java acceleration z AAC-LC and HE AAC V1/V2 decoding z Integrated hardware floating-point coprocessor z APE, FLAC, Ogg, AMR-NB, and AMR-WB decoding z Downmixing, resampling, highly dynamic volume control 3D GPU z High-quality Karaoke, supporting echo cancellation and z Quad-core Mali450 G.711v (u/a), AMR-NB, AMR-WB, and AAC-LC audio z OpenGL ES 2.0/1.1/1.0 OpenVG 1.1, EGL encoding Memory Interfaces Image and Display Processing (Imprex z DDR3/DDR3L interface Processing Engine) − Maximum 2 GB capacity z Hardware overlaying of multi-channel graphics and video − 32-bit memory inputs − Maximum 800 MHz frequency (DDR-1600) z Three OSD layers z NAND flash interface z Four video layers − SLC/MLC flash memory z Screen mirroring − 8-bit data width z Ultra-low-delay video processing − Maximum 64 GB capacity z Letter box and PanScan − Maximum 60-bit ECC z Full format 3D video processing and display z eMMC/tSD/fSD flash memory z Multi-tap vertical and horizontal scaling of videos and Video Decoding graphics; free scaling z H.265 Main Profile@L5.0 High-tie z Enhanced full-hardware TDE z H.264 BP/MP/HP@L5.0 z Full-hardware anti-aliasing and anti-flicker z Full-HD 3D videos (MVC), blu-ray navigation z CSC with configurable coefficients z MPEG1 z Image enhancement and denoising z MPEG2 SP@ML, MP@HL z Deinterlacing z MPEG4 SP@L0−3, ASP@L0−5, GMC z Sharpening z MPEG4 short header format (H.263 baseline) z Chrominance, luminance, contrast, and saturation z AVS baseline profile @L6.0, AVS-P16 (AVS+) adjustment z VC-1 SP@ML, MP@HL, AP@L0−3 z Video Db/Dr processing z VP6/8 Audio/Video Interfaces z 4K x 2K decoding z PAL, NTSC, and SECAM standard output, and forcible z Low delay decoding standard conversion z Simultaneous 4-channel HD decoding z Aspect ratio of 4:3 or 16:9 and forcible aspect ratio Image Decoding conversion z Full HD JPEG hardware decoding, maximum 64 z 4K x 2K/1080p50/1080p30/1080p24/1080i60/1080i50 megapixels /720p/576p/576i/480p/480i output z MJPEG decoding z One SD output and one HD output from the same source or z PNG hardware decoding, maximum 64 megapixels different sources Video and Image Encoding z Digital video interfaces z One HDMI 1.4a TX with HDCP 1.2 output z H.264 BP/MP/HP@L4.2 video encoding, 1080p@30 fps z Analog video interfaces z JPEG hardware encoding, maximum 1080p@30 fps − One CVBS interface z VBR or CBR mode for video encoding − One embedded VDAC that supports cable detection z Low delay encoding z Audio interfaces Audio Encoding and Decoding − Audio-left and audio-right channels z G.711 (u/a) audio decoding − SPDIF interface z MPEG L1/L2 − Embedded ADAC output z DRA decoding 2 − One I S/PCM digital audio input/output
Manufacture Center of Huawei Electrical, Huawei Base, Bantian, Longgang District, Shenzhen, P. R. China Postal Code: 518129 1 www.hisilicon.com Issue: 00B03 Date: 2014-08-20 Hi3798M V100 Hi3798M V100 Brief Data Sheet − HDMI audio output z Integrated POR module Peripheral Interfaces Other Specifications z One USB 3.0 host port z Embedded secure boot module, supporting z Three USB 2.0 host ports anti-ROM-flashing z Boot and debugging over the USB port z SSVP, providing end-to-end video content protection z One 4-bit SDIO 3.0 interface z 2-layer PCB design z One 10 Mbit/s or 100 Mbit/s adaptive Ethernet port with z Various boot modes the integrated FE PHY z USB bootstrap when the flash memory is empty z One IR receiver with one input interface z Integrated standby processor, supporting various z Multiple I2C interfaces low-power modes and less than 30 mW standby power z Multiple UART interfaces consumption z Multiple GPIO interfaces z Low-power design such as AVS and DVFS
Functional Block Diagram
Hi3798M V100 is a cost-effective chip solution targeted at the over-the-top (OTT) STB market. It brings the best user experience in the industry in terms of stream compatibility, smoothness and picture quality of live video playback, and STB performance. With an integrated high-performance quad-core processor and embedded NEON, Hi3798M V100 meets differentiated service requirements. Its dedicated HiFi audio processor supports high-performance Dolby 7.1 and DTS Master Audio processing. To meet the growing requirements on multimedia playback, visual communication, and multi-screen transcoding, Hi3798M V100 supports HD video decoding in various formats (including H.265, H.264, MVC, MPEG1, MPEG2, MPEG4, AVS+, VC-1, VP6, and VP8) and high-performance H.264 encoding. Hi3798M V100 provides a smooth man-machine interface and rich gaming experience with a high-performance 2D/3D acceleration engine. It also enables flexible connection schemes with one Ethernet port, three USB 2.0 ports, one USB 3.0 port, and more peripheral interfaces.
Manufacture Center of Huawei Electrical, Huawei Base, Bantian, Longgang District, Shenzhen, P. R. China Postal Code: 518129 2 www.hisilicon.com Issue: 00B03 Date: 2014-08-20 Hi3798M V100 Hi3798M V100 Brief Data Sheet
z DTS, mentioned in this document, is a registered trademark of DTS Inc. and its subsidiaries. Any parties intending to use the trademark must obtain the permission from DTS Inc. or its subsidiaries. z Dolby, mentioned in this document, is a registered trademark of Dolby Laboratories, Inc. Any parties intending to use the trademark must obtain the permission from Dolby Laboratories, Inc.
Acronyms and Abbreviations
ADAC audio digital-to-analog converter ADB Android debug bridge AVS adaptive voltage scaling BGA ball grid array CBR constant bit rate CSC color space conversion CVBS composite video broadcast signal DRA dynamic resolution adaptation DSP digital signal processor DVFS dynamic voltage frequency scaling ECC error correcting code eMMC embedded multimedia card FE fast Ethernet GMC global motion compensation GPIO general-purpose input/output GPU graphics processing unit HDMI high-definition multimedia interface HEVC high efficiency video coding I2C inter-integrated circuit IR infrared I2S inter-IC sound JPEG Joint Photographic Experts Group MJPEG Motion Joint Photographic Experts Group MLC multi-level cell MPEG Moving Picture Experts Group MVC multiview video coding NTSC National Television System Committee OTT over-the-top PCB printed circuit board PCM pulse-code modulation POR power-on reset ROI region of interest SDIO secure digital input/output SLC single-level cell SPDIF Sony/Philips digital interface SPI serial peripheral interface SSVP super secure video path STB set-top box TDE two-dimensional engine UART universal asynchronous receiver transmitter VBI vertical blanking interval VBR variable bit rate VDAC video digital-to-analog converter
Manufacture Center of Huawei Electrical, Huawei Base, Bantian, Longgang District, Shenzhen, P. R. China Postal Code: 518129 3 www.hisilicon.com Issue: 00B03 Date: 2014-08-20
