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Experiment Title. 1

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Experiment Title.

Student Name: Pranay .G UID: 22BAI71080


Branch: CSE-AI/ML Section/Group: 109-B
Semester: II Date of Performance: Feb 25, 2023
Subject Name: Digital Electronics Subject Code: 22ECH-101

1. Aim: (a.) Design a Burglar Alarm using AND Gate


(b.) Design a single doorbell ringer for both front and back doors using OR Gate
(c.) Design an Automatic Fan Controller using NOT Gate

2. Requirements :
i. Software : TinkerCad
ii. Hardware : Breadboard, Connecting Wires, IC for 7408,7432,7404, Power Supply,
Slideswitch , 220 ohm resistor, LED, piezo, DC motor.
3. Circuit Diagram:
(a) Schematic Diagram for Burglar Alarm using AND Gate :

(b) Schematic Diagram for Doorbell Ringer using OR Gate :


(c) Schematic Diagram for Automatic Fan Controller using NOT Gate :

4. Simulation Results :
(a) Burglar Alarm Using AND Gate
Concept Used : An AND gate is a fundamental logic gate in digital electronics that
take in two or more binary inputs and produces a single binary output, which is high
(1) only if all of the inputs are high (1).
The AND gate is represented by the symbol shown below, which has two inputs (A
and B) and one output (Y).

The output of AND gate is determined by the logical operation of multiplication. If


both inputs are 1, the output is 1. Otherwise, the output is 0.
The truth table for an AND gate is as follows :

Truth Table :

For example, if input A is 1 and input B is 1, the output Y is 1. However, if either


input A or input B is 0, the output Y is 0.
The AND gate is a fundamental building block of digital logic circuit and is used in
many applications, such as in design of the microphones, memory units and control
units.
(b) Single Doorbell using OR Gate

Concept Used : AN OR gate is a digital logic gate that performs a logical OR


operation on its input signals. An OR gate has two or more input terminals and one
output terminal. The output of an OR gate is “true” or 1 if at least one of its input
signals is “true” or “1”. If all of the input signals are “false” or “0”, then the output of
the OR gate is also “false” or “0”.
The OR gate is represented by the symbol shown below, which has two inputs (A and
B) and one output (Y).

The output of OR gate is the logical sum of its input signals. In other words, the
output is true if either of the input signal is true or if both are true.
The truth table for an OR gate is as follows :
Truth Table :

This makes the OR gate a useful building block in digital circuits where multiple
inputs need to be combined in a way that it is sensitive to the presence of any of one
of them. For example, OR gates are commonly used in the design of electronic circuits
that control lightning, heating, and other household appliances.

(c) Automatic Fan Controller using NOT Gate

Concept Used : A NOT gate is a digital logic gate that performs a logical NOT
operation on its input signal. A NOT gate has one input terminal and one output
terminal. The output of a NOT gate is the opposite (or inverse) of its input signal. If
the input is “true” or “one”, the output is “false” or “0”, and if the input is “false” or
“0”, the output is “true” or “1”.
The OR gate is represented by the symbol shown below, the input is usually labelled
A, and the output is labelled O.
The NOT gate is sometimes referred to as an inverter because it “inverts” the input
signal. The truth table for a NOT gate is shown below :

Truth Table :

It is a fundamental building block in digital circuits, used to compliment or invert a


signal as needed. For example, NOT gates can be used to convert a positive logic
signal (where “1” represents “true”) to a negative logic signal (where “0” represents
“true”), or vice versa. NOT gates are also used in combination with other gates to
perform more complex logic operations.

5. Observations : Validating the truth tables of logic gates involves analyzing the behavior of
different logic gates and verifying that their outputs match their expected truth values for all
possible input combinations. Here are some observations that can be made during this
process:

1. AND gate: The AND gate produces an output of 1 only when both of its inputs are 1.
When one or both inputs are 0, the output is 0. This behaviour is consistent with the AND
gate's truth table.
2. OR gate: The OR gate produces an output of 1 when one or both of its inputs are 1. It
produces an output of 0 only when both inputs are 0. This behaviour is consistent with
the OR gate's truth table.

3. NOT gate: The NOT gate produces an output that is the opposite of its input. When the
input is 1, the output is 0, and when the input is 0, the output is 1. This behaviour is
consistent with the NOT gate's truth table.

Observing and verifying the output behaviour of logic gates using their truth tables is an
important step in digital electronics, as it helps ensure that the circuits are functioning as
expected and that the logical operations are being carried out correctly.

6. Troubleshooting:

1. Messy Circuit Connection & loose connection.

2. Incorrect gate implementation: Another error that can occur is when the gate is not
implemented correctly. For example, if you are testing an AND gate and accidentally
implement an OR gate instead, you will get incorrect results. Double-check your gate
implementation to make sure it matches the logic symbol for the gate you are testing.

3. Faulty equipment: Finally, it's possible that the error is not related to the gate or the
truth table, but rather to faulty equipment. Make sure that your testing equipment is
working properly and is calibrated correctly.

7. Result: The integrated circuits and their connection on the breadboard were studied and

implemented. The practical applications of logic gates(AND,OR & NOT ) were

studied and implemented.


Learning outcomes (What I have learnt):

1. Understanding the concept of logic gates.

2. Identifying the logical function of a gate.

3. Evaluating the performance of a circuit.

4. Verifying the correctness of a gate.

Evaluation Grid:

Sr. No. Parameters Marks Obtained Maximum Marks


1. Worksheet completion including writing 12
learning objectives/Outcomes.(To be
submitted at the end of the day).
2. Viva 8
3. Student Engagement in 10
Simulation/Demonstration/Performance
and Controls/Pre-Lab Questions.
Signature of Faculty (with Date): Total Marks Obtained:

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