IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO.

3, MARCH 2018 2723

Switching Frequency Determination of DC–DC

Converters With Hysteretic Control
Chung-Chieh Fang and Richard Redl, Life Fellow, IEEE

Abstract—Hysteretic control provides unique advantages in dc– is proportional to the load current in discontinuous conduction
dc converter applications but it is less popular than other types of mode. That property is useful in applications where high effi-
control because the switching frequency depends on the operating ciency must be maintained over a wide range of load currents. A
point, the feedback ripple, and the component parasitics. Further-
more, it is difficult to predict the frequency due to the complex disadvantage of hysteretic current control is that the switching
interaction of those factors. This paper proposes harmonic balance frequency depends on the input and output voltages. It is pos-
analysis to systematically determine the switching frequency of the sible to eliminate that dependence by stabilizing the frequency
buck and boost-like converters with hysteretic current control, and or synchronizing the converter to an external clock [12]–[16],
extends the method to buck converters with hysteretic voltage con- but those measures require additional circuitry and might lead
trol. The analysis includes the most important second-order effects
(feedback ripple, component parasitics, a second output capacitor, to performance compromises.
and switching delays). For the less complex cases the switching Besides the input/output voltages the switching frequency is
frequency is expressed in closed form, and for the more complex also influenced by the ripple voltage at the output of the error
cases the paper proposes a graphical solution. The predictions are amplifier and by component parasitics. The effect of the ripple
verified by simulations and, for the buck converter with hysteretic voltage on the frequency was analyzed in [5] and [6], but the
current control, by experiments. The derived results are useful for
designing a converter with predictable switching frequency, and analysis covered only the special case of the type-II compen-
can also be employed during the design process of a converter with sator with a pole frequency well above the switching frequency
synchronized or stabilized frequency. Given an arbitrary control and a zero frequency well below the switching frequency, i.e.,
scheme or circuit variation, the switching frequency can be readily when the compensator gain could be approximated with a con-
obtained by following the proposed approach. stant at the switching frequency and at its first few harmonics.
Index Terms—Circuit parameter effect, hysteretic current The switching frequency is a critical parameter of any dc–dc
control, hysteretic voltage control, switching frequency. converter; therefore, its accurate prediction in self-oscillating
I. INTRODUCTION converters (e.g., the ones with hysteretic current-mode control)
has a great practical value. Even if the frequency of the converter
YSTERETIC control is one of the earliest self-oscillating
H control techniques for dc–dc converters. There are two
main types of hysteretic control, hysteretic current control and
is stabilized or the converter is synchronized to an external clock,
the knowledge of the self-oscillating frequency is important for
the design of the stabilizing or synchronizing circuit.
hysteretic voltage control. Hysteretic current control was in- Hysteretic voltage control is also known since the early 1960s
vented in the early 1960s [1] and a patent was issued to its in- [17]. It is often used for low-cost buck converters, either in its
ventor in 1984 [2]. It was reinvented in 1977 [3] and since then original form or combined with an error amplifier [18]. Similarly
several papers were published about its behavior and analysis to hysteretic current control, the switching frequency strongly
[4]–[11]. It has been established that hysteretic current control depends on the operating conditions, component parasitics, and,
has some very interesting and practically important properties, when an error amplifier is used, the feedback ripple.
including unconditional stability of the current loop (i.e., there This paper presents a systematic method to determine the
is no need to add a stabilizing ramp to the current signal), a switching frequency of the buck converter and various boost-
virtually constant magnitude and a negligible phase shift of the like converters (BLC, e.g., boost, buck–boost, SEPIC) with
control-to-inductor current transfer function, accurate tracking hysteretic current/voltage control and with an arbitrary com-
of the control voltage by the average inductor current in contin- pensator. The analysis includes the effects of the equivalent
uous conduction mode (CCM), and a switching frequency that series inductance (ESL) of the output capacitor, a second output
capacitor with a time constant different from the first capaci-
Manuscript received January 16, 2017; accepted April 11, 2017. Date of
publication April 18, 2017; date of current version December 1, 2017. Recom- tor, the turn-off and turn-on delays, and the internal frequency
mended for publication by Associate Editor Pradeep S. Shenoy. (Corresponding dependence of the gain of the error amplifier.
author: Chung-Chieh Fang.) Harmonic balance analysis (HBA) is a useful tool to investi-
C.-C. Fang is with Sunplus Technology, Science Park, Hsinchu 30076,
Taiwan (e-mail: fangcc3@yahoo.com). gate the steady-state operation of the converter and to determine
R. Redl is with Redl Consulting, Montevaux 14, CH-1726 Farvagny-le-Petit, its stability [19]. The methods used in [5], [6], and [20] attempt
Switzerland (e-mail: richardredl@gmail.com). predicting the switching frequency by direct inspection of the
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. signal waveforms. Such an approach cannot be easily extended
Digital Object Identifier 10.1109/TPEL.2017.2695584 to a converter with parasitics and arbitrary compensation. On

0885-8993 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

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2724 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 3, MARCH 2018

TABLE I
D-TRANSFORMS OF TYPICAL TRANSFER FUNCTIONS

Fig. 1. A hysteretic current mode buck converter with optional C 3 and R 3 .

In the s-domain, let T (s) := −va y(s)/vL (s), which has two
parts contributed by the current and voltage loops respectively,
i.e., T (s) = Ti (s) + Tv (s) = va (Gi (s) + Gc (s)Gp (s)). Then
∞

y(t) = − cn ej n ω s t T (jnωs ) (2)
n =−∞

 ∞  −j n ω s d 
e −1
y(0) = T (jnωs ) = 0 (3)
n =−∞
j2nπ

 ∞  
Fig. 2. Model of the buck converter with hysteretic current control. 1 − ej n ω s d
y(d) = T (jnωs ) = −VH (4)
n =−∞
j2nπ

the other hand, HBA can be easily adapted to any converter and with dc offsets having no effect on the switching frequency.
compensator combination. In HBA, analyzing parasitic effects Define an expression of signal difference V = y(0) − y(d) with
is straightforward. a unit of voltage, and a D-transform D as
In Section II, HBA is applied to a buck converter with hys- ∞  
cos(nωs d) − 1
teretic current control. In Section III, HBA is extended to buck V := D[T (s)] := T (jnωs ). (5)
converters with various second-order effects, to BLC, and to n =−∞
jnπ
buck converters with hysteretic voltage control. That section When V is plotted as a function of a variable, such a plot is called
also includes experimental and simulation results that verify the a V-plot. In (5), T (s) is evaluated at s = jnωs where ωs is large
predictions. Section IV presents the summary. compared with other component frequencies such as 1/RC.
For the D-transform purpose, a transfer function 1/(s + ω), for
II. BUCK CONVERTER WITH HYSTERETIC CURRENT CONTROL example, can be approximated as 1/s because D[1/(s + ω)] ≈
D[1/s] if ωs  ω. Such approximation, denoted by  in this
Consider a buck converter with hysteretic current control (see paper, greatly simplifies the derivation of D[T (s)] for a complex
Fig. 1) in CCM, which can be represented by a model [21] shown expression of T (s).
in Fig. 2, where vs is the source voltage, vd is the diode voltage, Subtracting (4) from (3) and using (5) lead to an equation to
vo is the output voltage, vr is the reference voltage, vc is the obtain fs ,
control voltage, vL is the inductor voltage with an amplitude
va , iL is the inductor current, Rs is the sensing resistance, V := D[T (s)] = y(0) − y(d) = VH (6)
y = vc − Rs iL is the feedback signal, and Gc (s) is the transfer
where the dc offsets of (3) and (4) cancel each other. Let
function of the voltage-loop compensator. Let the equivalent
V = Vi + Vv , where Vi = D[Ti (s)] and Vv = D[Tv (s)] are for
series resistance (ESR) of the output capacitor be Rc . Let ρ =
the current and voltage loops, respectively. Note that the D-
R/(R + Rc ) ≈ 1. Let the ESR zero be ωr = 1/Rc C. Let the
transform has a linear property such that D[aTi (s) + bTv (s)] =
switching period be T and the duty ratio be D. Let fs = 1/T ,
aD[Ti (s)] + bD[Tv (s)]. Table I shows the D-transforms of some
ωs = 2πfs , d = DT , and the efficiency be η. Let the hysteresis
typical transfer functions [19], and D[e−s ]=1 for  ≤ d ≤
band be VH . The control switch of the converter is turned ON
T − , which leads to D[1] = 1.
when Rs iL ≤ vc and turned OFF when Rs iL ≥ vc + VH .
Express α(D, p) in Table I as a Taylor series
Throughout the paper, all signals are assumed in steady state. ∞
α
n =0 n (D)(−p) n
and α(D, 0) = α0 (D). Based on the
As in [22], represent vL by Fourier series,
plot of α(D, p) shown in Fig. 3, α0 (D) ≥ α(D, p) ≥ 0 and
∞ α(D, ∞) = 0. For p > 3, α(D, p) ≈ 1/p. From [19], αn (D) =
 1 − e−j n ω s d
vL (t) = va cn ej n ω s t where cn = . (1) D[ωsn +1 /sn +1 ]. Using partial fraction decomposition, an arbi-
n =−∞
j2nπ trary T (s) can be generally decomposed as a summation of

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FANG AND REDL: SWITCHING FREQUENCY DETERMINATION OF DC–DC CONVERTERS WITH HYSTERETIC CONTROL 2725

Fig. 3. Plot of α(D, p), for D-transform. Fig. 5. V-plot shows fs = 352 kHz.

Then, from (6) and Table I


va Rs α0 (D) va g
V= + α1 (D)
ωs L LCωs2
  
1 1
+ − (α(D, p) − α0 (D)) = VH . (10)
p r

Fig. 4. Type-II compensator and its transfer function. Since α(D, p) ≤ α0 (D), Vv ≥ 0 and fs > f0 if p > r, but fs <
f0 if p < r. If p = r, fs = f0 . Introducing a pole generally
1/(s + ωp ) and 1/sn (for n ≥ 1), and D[T (s)] can be easily decreases fs , because decreasing p leads to decrease of V, and
obtained from Table I. If the voltage loop is open (and Vv = 0), introducing a zero increases fs .
from (5) For p > 3, α(D, p) ≈ 1/p, then (10) leads to
   
va R s
V = Vi = D[Ti (s)] = D Rs C + g 1
ωr − ω1p D(1 − D)
sL fs =  . (11)
1
∞
va Rs (cos(2πD) − 1) va Rs D(1 − D)
VH LC
va + g
ωp ωr − ω1p
= 2 π2 f L
= = VH
n =1
n s fs L
If a PI compensator is used, setting ωp → ∞ in (11) leads to
va Rs D(1 − D)
fs = := f0 (7)
LVH (Rs + gRc )(1 − D)Dva  gRc
fs = = 1+ f0 > f0 (12)
agreed with [6, Table 1]. As VH increases, fs decreases. Now LVH Rs
close the voltage loop. Since Vi + Vv = VH , fs < f0 if Vv < 0,
but fs > f0 if Vv > 0. also agreed with [6, Table 1]. Note that (10) depends on C, while
In Fig. 2, if a type-II compensator as in Fig. 4 (with ideal (7) and (12) are independent of C.
amplifier) is used
Kc (1 + s/ωz ) III. CIRCUIT VARIATIONS TO SHOW PARAMETER EFFECT
Gc (s) = . (8)
s(1 + s/ωp ) A. ESL: fs ↑
Let g = Kc /ωz . The PI compensator is a special case of the When the ESL Lc of the output capacitor is significant
type-II compensator. Setting ωp → ∞ in (8) leads to a PI com-
pensator Gc (s) = g + Kc /s. Lc Cs2 + Rc Cs + 1
Generally, ωz ωs , Gc (s)  g/(1 + s/ωp ), and Gp (s) 
LLc Cs3 /R + LCs2 /ρ + (L/R + Rc C)s
va R s va g(1 + s/ωr ) Lc Cs2 + Rc Cs + 1 Lc Cs2 + Rc Cs + 1
T (s) = Ti (s) + Tv (s)  + . (9)   .
sL LCs2 (1 + s/ωp ) LCs2 (1 + sLc /R) LCs2

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2726 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 3, MARCH 2018

TABLE II
NEW EXPRESSIONS OF α(D, p), α 0 (D) AND α 1 (D) FOR THE CONVERTER WITH SWITCHING DELAY

for D < δ for δ ≤ D ≤ 1 − δ for 1 − δ < D

−s  1 1
α  (D , p) := D[ e s + ωωp s ] −2π D 2 e −2 π p δ e 2 π p δ (α (D , p) − p )+ p −2π (1 − D ) 2 e −2 π p δ
e −s  ω s
α 0 (D ) := D[ s ] −2π D 2 α 0 (D ) − 2π δ −2π (1 − D ) 2
e −s  w s 2
α 1 (D ) := D[ s 2 ] 2 2
2π D (2δ − 1) 2 2
2π δ − 2π δ α 0 (D ) 2π (1 − D ) 2 (2δ − 1)
2

If the type-II compensator (8) is used with Gp (s) TABLE III

THE MEASURED fs AGREES WITH HBA PREDICTIONS
T (s) Ti (s) + Tv (s) Rs g(Lc Cs2 + Rc Cs + 1)
=  +
va va sL LCs2 (1 + s/ωp ) Exp. C 1 (pF) C 3 (μF) measured f s (kHz) predicted f s (kHz)


Rs g 1 Rc C − ω1p Lc C − RωcpC + ω1p2 1 0 0 40.1 39.4
= + + + . 2 10 0 34 34.2
sL LC s2 s 1 + ωsp 3 100 0 27.1 27.6
4 0 10 34.6 34
Then, from (6) and Table I 5 10 10 30.3 30.3
   6 100 10 26.4 26.8
VLC 1 α0 (D) gα1 (D)
= Rs C + g Rc C − +
va ωp ωs ωs2
 
Rc C 1 VH LC Take the buck converter with Gc (s) = g or g + Kc /s, for
+ g Lc C − + 2 pα(D, p) = . example. From (10) and Table II
ωp ωp va
(13) ((Rs + gRc )C − g)D(1 − D)
fs = . (17)
For p > 3, pα(D, p) ≈ 1, and (13) leads to LCVH /va + (Rs + gRc )C − g2 /2
 
Rs C + g Rc C − ω1p D(1 − D) C. Composite Capacitor: Adding a Pole ωr (1 + C/C3 ), fs ↓
fs =  . (14)
VH LC
− g Lc C − RωcpC + ω12 As in Fig. 1, to further reduce the ripple voltage, one may
va p add an optional second output capacitor C3 , which is usually
As Lc increases, fs increases. For ωp → ∞, similar to [20, a ceramic or film capacitor with negligible ESR R3 . Then,
eq. (4)] for the hysteretic voltage control from [23]
 
(Rs + gRc )D(1 − D) 1 + s/ωr C 1 + sR3 C3
fs = (15) Gp (s)  · (18)
LCs2 C + C3 1 + s/ωq
v a − gLc
VH L

and Lc < VH L/va g is required. where a new pole ωq = ωr (1 + C/C3 )Rc /(Rc + R3 ) ≈
ωr (1 + C/C3 ) > ωr is introduced, which causes fs to decrease.
If R3 C3 1/ωs and a PI compensator is used, (11) still applies
B. Switching Delay: fs ↓
but with g replaced by gC/(C + C3 ) and ωp replaced by ωq .
If there exist a turn-on delay  := δT and a turn-off delay 2 ,
then (6) becomes D. Non-ideal Amplifier: Adding a Pole, fs ↓
V := y(−) − y(d − 2 ) = VH (16) Let the nonideal amplifier be a(s) = A/(1 + s/ω) with a
dc gain A, a pole ω, and unity gain bandwidth Aω. Based on
where y(−) and y(d − 2 ) can be determined from (2), and fs
circuit analysis, the type-II compensator transfer function (8) is
can be determined from (16).
modified to
Example 1: Consider a buck converter with a PI compen-
sator: vs = 20 V, vr = 5 V,  = 100 ns, 2 = 0, L = 10 μH, a(s)Gc (s)
Gc (s) =
C = 100 μF, Rc = 0.02 Ω, Rs = 1 Ω, R = 1 Ω, R1 = 1 kΩ, 1 + a(s) + (1 + R1 /Rb )Gc (s)
C2 = 10 nF, R2 = 50 kΩ, and VH = 2 V. Kc (1 + s/ωz )
The simulation shows fs = 350 kHz, closely agreed with the  (19)
s(1 + s/ωp )(1 + s/(g  ωp + Aω))
V-plot [see Fig. 5, based on (16) and (2)], which gives a graphical
solution of fs = 352 kHz.  where g  = g(1 + R1 /Rb ), with two well-separated poles ωp =
For symmetrical switching delay with  = 2 and δ < 1/2, ωp /(1 + g  ωp /Aω) g  ωp + Aω. If the PI compensator is
the analysis in the previous sections still applies [19], but with used, ωp → ∞ and ωp ≈ Aω/g  and the other pole is at in-
T (s) replaced by T  (s) = e−s T (s), and α(D, p), α0 (D) and finity. The larger pole is generally much greater than ωs and has
α1 (D) replaced respectively by α (D, p), α0 (D) and α1 (D) negligible effect on the switching frequency. All the analysis
shown in Table II. above applies but with ωp replaced by ωp .

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FANG AND REDL: SWITCHING FREQUENCY DETERMINATION OF DC–DC CONVERTERS WITH HYSTERETIC CONTROL 2727

Fig. 6. The measured waveforms and fs agree with simulations and HBA; (a)–(c) for Exp.1 and (d)–(f) for Exp.6.

Fig. 7. Equivalent sensing circuit without changing fs .

Example 2: (Experimental verification) Consider a buck

converter with vs = 24 V, vr = 2.5 V,  = 2 = 250 ns, L =
200 μH, C = 75 μF, Rc = 0.185 Ω, Rs = 0.1 Ω, R = 5 Ω,
R1 = 8.2 kΩ, Rb = 2.7 kΩ, R2 = 220 kΩ, C2 = 1 nF, and
VH = 0.1 V. The error amplifier has a dc gain 100 dB and unity Fig. 8. Model of the BLC with hysteretic current control.
gain bandwidth 10 MHz. There is an extra gain 0.01426 at the
output of the error amplifier. Six experiments (Exp.1–6) are
TABLE IV
conducted and summarized in Table III . For Exp.4–6, a second v a FOR DIFFERENT CONVERTERS [22]
output capacitor C3 is added. As expected, adding C1 or C3
decreases fs . Take Exp.1 and Exp.6 for example as shown in
Buck Boost Buck–boost Flyback SEPIC
Fig. 6, the measured waveforms and fs agree with simulations
and HBA. v a (v L amplitude) vs Vo
η vs − Vo
η vs + Vo
ηN vs + Vo
η
From (7), f0 = 29.24 kHz, and fs deviates from f0 due to the
voltage loop ripple. Here, ωr = 72 rad/s. Based on the previous
discussion on (10), for C1 = 10 pF, ωr < ωp = 257 rad/s and
F. BLC: Opposite Effect
fs > f0 . For C1 = 100 pF, ωr > ωp = 46 rad/s and fs < f0 . 
For the BLC [22], the model is shown in Fig. 8 with va shown
E. Equivalent Current Sensing With Same fs in Table IV for different converters [22], and (6) and (7) still
apply. Here, Tv (s) = −Gc (s)Gp (s)Id , where Id = Vo /R(1 −
The self-inductance Ls associated with Rs causes a step in
D) is the diode current [22]. The negative sign of Tv (s) gives
the current-sense signal, which effectively reduces the hysteresis
opposite effect, compared with the buck converter.
and therefore increases the frequency. To eliminate such effect,
If the type-II compensator (8) is used
an equivalent sensing circuit [24] without changing the switch-
ing frequency is shown in Fig. 7, where v4 is sensed for current T (s) Ti (s) + Tv (s) Rs gId (1 + s/ωr )
= ≈ − . (20)
feedback. va va sL va Cs(1 + s/ωp )

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2728 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 3, MARCH 2018

Then, from (6) and Table I TABLE V

PARAMETER EFFECTS ON fs
   
Rs va α0 (D) gId p
V= − α0 (D) + − 1 α(D, p)
ωs L Cωs r Parameter Effect Buck BLC

= VH . (21) Additional C 3 ↑ Pole ω q ≈ ω r (1 + C

C3 )↓ fs ↓ fs ↑
ωp
Error amp. bandwidth A ω ↓ Pole ω p ≈ g ω p
↓ fs ↓ fs ↑
Since α0 (D) ≥ 0 and α(D, p) ≥ 0, Vv ≤ 0 and fs ≤ f0 if p ≥ 1+
Aω
1
r. This is opposite to the buck converter case (where fs ≥ f0 if ESR R c ↑ Zero ω r = RcC ↓ fs ↑ fs ↓

p ≥ r). ESL L c ↑ Magnitude |G p (s)(j ω )| ↑ fs ↑ fs

For p < 0.2, α(D, p) ≈ α0 (D) + α2 (D)p2 and from (21) Delay  ↑ Phase ∠T (j ω ) ↓ fs ↓ fs ↓

 
Rs (1 − D) Rc va D
fs ≈ − . (22) IV. SUMMARY
L RR1 C1 VH
Hysteretic control provides unique advantages in dc–dc con-
For p > 3, α(D, p) ≈ 1/p and from (21) verter applications but it is less popular than other types of
  control because the switching frequency depends on the oper-
R s va gId gva Rc D(1 − D)
fs ≈ − + . ating point, the feedback ripple and the component parasitics.
L C 2L VH + gId Rc (1 − r/p)
(23) Furthermore, it is difficult to predict the frequency due to the
As a special case, if a PI compensator is used, then set p → ∞ complex interaction of those factors.
in (23) and the result agrees with [6, Table 1]. This paper proposes HBA to systematically determine the
Example 3: Consider a boost converter with vs = 13.9 V, switching frequency of the buck and boost-like converters with
vr = 5.94 V,  = 2 = 0, L = 100 μH, C = 75 μF, Rc = hysteretic current/voltage control. The analysis includes the
0.185 Ω, Rs = 0.1 Ω, R = 28.8 Ω, R1 = 8.2 kΩ, Rb = 2.7 most important second-order effects (feedback ripple, compo-
kΩ, R2 = 100 kΩ, C2 = 1 nF, and VH = 0.1 V. There is an nent parasitics, a second output capacitor, and switching de-
extra gain 0.01426 at the output of the compensator and g = lays). For the less complex cases, the switching frequency is
0.01426Kc /ωz = 0.158. For C1 = 0.01, 10, and 100 pF, the expressed in closed form and for the more complex cases the
simulations show fs = 40.8, 40.65, and 48.9 kHz, respectively, paper proposes a graphical solution. The predictions are verified
closely agreed with (23), which show fs = 40.8, 41.9, and by simulations and, for the buck converter with hysteretic cur-
52 kHz. rent control, by experiments. The derived results are useful for
From (7), f0 = 58.43 kHz. Opposite to the buck converter designing a converter with predictable switching frequency, and
case, adding the voltage loop makes fs < f0 .  can also be employed during the design process of a converter
with synchronized or stabilized frequency.
Table V summarizes the effects of the various parameters on
G. Hysteretic Voltage Control: Special Case of Hysteretic fs . For the buck converter, adding a pole generally decreases
Current Control by Setting Rs = 0 fs , and adding a zero to the converter increases fs . For BLC,
By setting Rs = 0 to cut off the current loop, all above derived the opposite is true. For both converters, adding delay decreases
expressions can be applied to the hysteretic voltage control. fs . Given an arbitrary control scheme or circuit variation, the
Consider a hysteretic V2 controlled buck converter [18]. Let the switching frequency can be readily obtained by following the
compensator transfer function be Gc (s) + g2 , where Gc (s) is approach proposed in this paper.
the same as (8). Then
  REFERENCES
T (s) g 1 + ωsr
= (Gc (s) + g2 )Gp (s)  s + g2 . [1] T. A. Froeschle, “Two-state modulation techniques for power sys-
va 1 + ωp LCs2 tems,” Bose Corporation Semi-Annu. Rep. for US Army Electronics
(24) Command, Natick, MA, USA, Contract DA28-043-AMC-022812(E),
From (6) and Table I and for p > 3 Nov. 1968.
[2] T. A. Froeschle, “Current-controlled two-state modulation,” U.S. Patent
 4 456 872, Jun. 26, 1984.
g +g 2
ωr − g
ωp D(1 − D) [3] A. Weinberg and D. O’Sullivan, “LC3 : Application to voltage reg-
fs =  . (25) ulation,” in ESTEC Spacecraft Power Conditioning Seminar, 1977,
1 1
VH LC
va − g
ωp ωp − ωr
pp. 165–173.
[4] A. Capel, G. Ferrante, D. O’Sullivan, and A. Weinberg, “Application of
the injected current model for the dynamic analysis of switching regulators
Example 4: Consider a hysteretic V2 controlled buck con- with new concept of LC3 modulator,” in Proc. IEEE Power Electron. Spec.
Conf., 1978, pp. 300–306.
verter: vs = 5 V, vr = 1.5 V, g2 = 1, L = 2 μH, C = 50 μF, [5] R. Redl and I. Novak, “Current-mode control of switching voltage
Rc = 0.01 Ω, R = 0.5 Ω, R1 = 10 kΩ, C1 = 100 pF, C2 = 2 regulators—A new method of improving regulation parameters (in Hun-
nF, R2 = 5 kΩ, and VH = 0.02 V. garian),” Hiradastechnika, vol. 29, no. 11, pp. 321–334, 1978.
[6] R. Redl and I. Novak, “Instabilities in current-mode controlled switching
From (25), fs = 265 kHz, closely agreed with the simulation, voltage regulators,” in Proc. IEEE Power Electron. Spec. Conf., 1981,
which shows fs = 262 kHz.  pp. 17–28.

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FANG AND REDL: SWITCHING FREQUENCY DETERMINATION OF DC–DC CONVERTERS WITH HYSTERETIC CONTROL 2729

[7] R. Redl and N. Sokal, “Current-mode control, five different types, used [20] Designing Fast Response Synchronous Buck Regulators Using the
with the three basic classes of power converters: Small-signal AC and TPS5210, Texas Instruments, TX, USA, 1999. [Online]. Available:
large-signal DC characterization, stability requirements, and implemen- www.ti.com/lit/pdf/slva044
tation of practical circuits,” in Proc. IEEE Power Electron. Spec. Conf., [21] C.-C. Fang and R. Redl, “Subharmonic instability limits for the peak-
1985, pp. 771–785. current-controlled buck converter with closed voltage feedback loop,”
[8] R. Redl, “Small-signal high-frequency analysis of the free-running IEEE Trans. Power Electron., vol. 30, no. 2, pp. 1085–1092, Feb. 2015.
current-mode-controlled converter,” in Proc. IEEE Power Electron. Spec. [22] C.-C. Fang and R. Redl, “Subharmonic instability limits for the peak-
Conf., 1991, pp. 897–906. current-controlled boost, buck–boost, flyback, and sepic converters with
[9] Y.-F. Liu and P. C. Sen, “Large-signal modeling of hysteretic current- closed voltage feedback loop,” IEEE Trans. Power Electron., vol. 32, no. 5,
programmed converters,” IEEE Trans. Power Electron., vol. 11, no. 3, pp. 4048–4055, May 2017.
pp. 423–430, May 1996. [23] C.-C. Fang and R. Redl, “Subharmonic stability limits for the buck con-
[10] J. H. Park and B. H. Cho, “Small signal modeling of hysteretic current verter with ripple-based constant on-time control and feedback filter,”
mode control using the PWM switch model,” in Proc. IEEE Workshop IEEE Trans. Power Electron., vol. 29, no. 4, pp. 2135–2142, Apr. 2014.
Comput. Power Electron., Jul. 2006, pp. 225–230. [24] AN-1487 Current Mode Hysteretic Buck Regulators, Texas Instruments,
[11] C. J. Solis and G. A. Rincon-Mora, “Stability analysis & design of hys- TX, USA, 2013. [Online]. Available: www.ti.com/lit/pdf/snva170b
teretic current-mode switched-inductor buck DC-DC converters,” in Proc.
IEEE Int. Conf. Electron., Circuits, Sys., 2013, pp. 811–814.
[12] R. Redl and N. Sokal, “Frequency stabilization and synchronization of
free-running current-mode-controlled converters,” in Proc. IEEE Power
Electron. Spec. Conf., 1986, pp. 519–530.
Chung-Chieh Fang received the B.S. degree from National Taiwan University,
[13] T. Szepesi, “Stabilizing the frequency of hysteretic current-mode DC/DC
Taipei, Taiwan, and the M.S. and Ph.D. degrees from the University of Maryland,
converters,” IEEE Trans. Power Electron., vol. 2, no. 4, pp. 302–312, College Park, MD, USA, all in electrical engineering. He also received the J.D.
Oct. 1987.
degree from University of Idaho, Moscow, ID, USA.
[14] Y. Wen and O. Trescases, “Analysis and comparison of frequency stabi-
He is currently a Legal Manager at Sunplus Technology, Hsinchu, Taiwan.
lization loops in self-oscillating current mode DC-DC converters,” IEEE
Trans. Power Electron., vol. 28, no. 10, pp. 4753–4766, Oct. 2013.
[15] Z. Sun, L. Siek, R. P. Singh, and M. Je, “A fixed-frequency hysteretic
controlled buck DC-DC converter with improved load regulation,” in Proc.
IEEE Int. Symp. Circuits Sys., 2014, pp. 954–957.
[16] S. Kapat, “Parameter-insensitive mixed-signal hysteresis-band current
control for point-of-load converters with fixed frequency and robust stabil- Richard Redl (M’86–SM’86–F’08–LF’16) received
ity,” IEEE Trans. Power Electron., vol. 32, no. 7, pp. 5760–5770, Jul. 2017. the M.S. degree in telecommunications engineering
[17] B. P. Schweitzer and A. B. Rosenstein, “Free running-switching mode and the Ph.D. degree in radio transmitters from the
power regulator: Analysis and design,” IEEE Trans. Aerosp., vol. 2, no. 4, Technical University of Budapest, Hungary, in 1969
pp. 1171–1180, Oct. 1964. and 1973, respectively.
[18] D. Goder and W. R. Pelletier, “V 2 architecture provides ultra-fast transient He is currently an independent consultant in
response in switch mode power supplies,” in Proc. HFPC Power Convers., Switzerland.
Sep. 1996, pp. 19–23.
[19] C.-C. Fang, “Critical conditions for a class of switched linear systems
based on harmonic balance: applications to DC-DC converters,” Nonlinear
Dyn., vol. 70, no. 3, pp. 1767–1789, Nov. 2012.

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