The parasitic turn-on behavior of discrete CoolSiC™ MOSFETs

Parasitic turn-on caused by the Miller capacitance is often considered a weak spot of today’s silicon
carbide MOSFETs. In order to avoid that effect, gate-drive designs for hard-switching converters are
typically implemented with negative turn-off gate voltages. But is that really needed with CoolSiC™
MOSFETs?

By Klaus Sobe, Infineon Technologies Austria AG

Introduction stronger pull-up of the gate voltage, but also lower

A key element of all gate-drive designs is the the threshold level. On the hardware side, the
selection of the gate-voltage levels. With the major factors of influence are the undesirable
CoolSiC™ MOSFET technology, Infineon allows parasitic board capacitance parallel to CGD, an
designers to choose a turn-on gate voltage external capacitor parallel to CGS, the turn-off gate
between 18 V and 15 V, and thus configure the voltage as well as the turn-off gate resistor.
switch for highest current-carrying capability or
short-circuit ruggedness, respectively. The turn-off
gate voltage level, on the other hand, only needs
to ensure that the device remains safely turned off.
Infineon encourages designers to operate its
discrete MOSFETs at 0 V and benefit from a
simplification of the gate-drive circuit.
In order to underline that encouragement, this
article introduces an easily reproducible approach
to characterize the susceptibility of silicon carbide
MOSFETs, and presents tests results obtained
with discrete CoolSiC™ MOSFETs. Figure 1: Impact of the Miller capacitance CGD during
the turn-off of the body diode
Parasitic turn-on effect Characterization setup and approach
An unwanted turn-on of a semiconductor switch Designers often study the gate-charge curve of a
can be caused by inductive as well as capacitive specific semiconductor switch in order to get an
feedback to the gate. In conjunction with silicon impression of its susceptibility to parasitic turn-on.
carbide MOSFETs, however, it is typically the While this approach is rather straightforward – a
capacitive feedback via the Miller capacitance that brief look into the data sheet is sufficient – it does
is considered. A scenario explaining this effect is not really enable conclusions to be drawn for the
shown in Figure 1. The body diode of the low-side application. The main shortcoming is that the gate-
switch S2 conducts the load current IL until the charge characteristic is rather static in nature,
high-side switch S1 turns on. After the load current while the parasitic turn-on is clearly a dynamic
has commutated to S1, the drain-source voltage of effect. Hence, dedicated characterization tests are
S2 starts to increase. During this phase, the rising performed to assess the parasitic turn-on behavior
drain potential pulls up the gate voltage of S2 via of 1200 V/45 mΩ CoolSiC™ MOSFETs in TO-247
the Miller capacitance CGD. The turn-off gate 3-pin and 4-pin packages under application
resistor tries to counteract and pull the voltage conditions. All tests are conducted with a turn-off
down. If this resistor value is not low enough to gate voltage of 0 V.
pull the voltage down, the voltage might exceed
the threshold level, leading to a shoot-through and
an increase of switching losses.
Naturally, the risk and severity of shoot-through
events depend on the particular operation
conditions and the measurement hardware. The
most critical operating points are at high bus
voltages, steep voltage rises and high junction
temperatures. These conditions not only lead to a
 Figure 2: Hardware setup for the characterization: the
high-side switch S1 acts as “dv/dt generator”, the low-
side switch S2 is the device under test. The aim of the
test is to find the maximum turn-off gate resistance for Figure 3: Example waveforms obtained with a
S2 that still avoids parasitic turn-on. 1200 V/45 mΩ CoolSiC™ MOSFET operated at
100°C and with different values for RGoff. Compared
A half-bridge evaluation board is configured as to the reference waveform (black; 0 Ω), Q*rr of the
depicted in the schematic drawing of Figure 2. It is other waveforms are increased by 10% (orange;
essentially a commutation cell where the low-side 12 Ω) and 40% (red; 22 Ω). The symbol Q*rr denotes a
switch is the device under test and the high-side sum of three charges: (1) the reverse recovery
switch acts as dv/dt generator. When the high-side charge of the body diode, (2) the capacitive charge of
device turns on, the rising drain-source voltage on the semiconductors, the layout and the passives, and
the low-side device leads to a gate voltage (3) the contribution coming from parasitic turn-on.
increase that the turn-off gate resistor tries to limit.
Naturally, the lower the dvDS/dt, and the lower the
turn-off gate resistance, the lower is the chance of Characterization results
a parasitic turn-on. The goal of the experiment is Testing at zero load current means that the body
to identify the critical turn-off gate resistance diode of the device under tests is not forward
values for a given test case. This so-called critical biased prior to the switching transient. No diode
gate resistance is the value that causes a Q*rr recovery occurs; the transient is merely a charging
increase of 10% compared to the reference and discharging of capacitances. In this condition,
waveform obtained with 0 Ω. A threshold level of voltages induced in parasitic inductances do not
10% is large enough to get reliable measurement play a significant role. Consequently, also the
data, but small enough to be considered negligible performance of the TO-247 and the TO-247-4-pin
in most applications, cf. Figure 3. package is the same.
Tests are carried out at different temperatures, The measurement results obtained at 800 V and
different load currents and different voltage slopes. 0 A are summarized in Figure 4. It is clearly visible
The latter are adjusted using the RGon of the high- that in order to prevent parasitic turn-on, the RGoff
side switch S1. needs to be lower, the higher the dvDS/dt and the
higher the temperature. It is worth mentioning that
a turn-off gate voltage of 0 V is sufficient to prevent
parasitic turn-on even at 50 V/ns and 175°C. In
case the RGoff cannot be selected at a level that is
low enough, drivers with an active Miller-clamp
functionality such as the 1EDC30I12MH provide a
way out.
 differentiate. Both effects slow down or smooth the
voltage transient, and cause an increase of the
switching energies, not only on the diode but also
on the switch. In applications that require highest
switching speeds, parasitic turn-on limits the
performance similar to an improper freewheeling
diode.
Figure 5 shows the minimum achievable turn-on
switching losses of various silicon carbide
MOSFET technologies operated with 18/0 V on the
gate. While not all devices are able to maintain
their high-speed switching nature at such a driving
condition, the results confirm the high immunity of
CoolSiC™ MOSFETs against parasitic turn-on.

Figure 4: Critical gate resistor values as a function of

dvDS/dt for the 1200 V/45 mΩ CoolSiC™ MOSFET
under test. The measurement points were obtained at
800 V and 0 A using a turn-off gate voltage of 0 V. The
dashed lines indicate calculated trend lines.

At higher load current levels, a hard commutation

from the body diode of S2 to the MOS channel of
S1 occurs. Due to the presence of diode reverse Figure 5: Minimum achievable turn-on switching
recovery and induced voltages, the situation losses of various 1200 V silicon carbide MOSFET
technologies at 800 V, 15 A and 150°C. The devices
becomes slightly more complicated. Simply
under test have a nominal on-state resistance of 60-
speaking, three effects come into play:
80 mΩ and are operated with 18/0 V on the gate.
1) The body diode recovery slows down the
average dvDS/dt and relaxes the situation Summary and conclusion
with parasitic turn-on. This article describes a simple approach for
2) Oscillations between the commutation loop characterizing the susceptibility of a power
inductance and the device output semiconductor switch to parasitic turn-on via the
capacitance increase the dvDS/dt locally Miller capacitance. Test results obtained with
and make the situation more critical. discrete CoolSiC™ MOSFETs operated at a bus
3) Assuming a standard TO-247 package, the voltage of 800 V and a switching speed of 50 V/ns
negative feedback via the common source demonstrate that even in high-speed, two-level
terminal of S2 leads to a reduction of the converters, a turn-off gate voltage of 0 V is feasible.
gate voltage, and thus to an increased When looking at three-level circuits where the
ruggedness against parasitic turn-on. switched voltage is just half the bus voltage, the
Apparently, the weighting of the effects described situation eases entirely. In such cases, CoolSiC™
above depends on the actual hardware setup. With MOSFETs are virtually free of capacitive turn-on,
the evaluation board that was used for all tests regardless of the gate resistance value.
presented in this article, the most critical condition Assuming a carefully designed PCB layout with
is 175°C and 0 A. Thus, the area that is free of minimized gate-drain capacitance, Infineon
parasitic turn-on highlighted in Figure 4 holds for encourages power electronic engineers to operate
40 A measurements, too – regardless of whether discrete CoolSiC™ MOSFETs with a turn-off gate
the TO-247 or TO-247-4-pin is considered. voltage of 0 V. This leads to a simplification of the
Implications on high-speed switching gate-drive design without penalizing the
applications performance.
As indicated in Figure 3, the shoot-through current
caused by the capacitive turn-on and the reverse-
recovery current of the body diode are difficult to
References [4] S. Jahdi et al, “Investigation of parasitic turn-
[1] K. Sobe et al, “Characterization of the parasitic ON in silicon IGBT and Silicon Carbide
turn-on behavior of discrete CoolSiC™ MOSFET devices: A technology evaluation”,
MOSFETs”, PCIM Europe 2019, Nuremberg, ECCE-Europe 2015, Geneva, Switzerland,
Germany, May 2018 September 2015
[5] Infineon AN-2017-44: “1200V Highspeed3
[2] T. Basler et al, “Practical Aspects and Body IGBT in TO-247PLUS Evaluation Board”,
Diode Robustness of a 1200 V SiC Trench Application Note (rev 1), November 2017
MOSFET”, PCIM Europe 2018, Nuremberg,
Germany, June 2018
[3] Infineon AN-2006-01: “Driving IGBTs with
unipolar gate voltage”, Application Note,
December 2005