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2012 - solutions

Computer Systems (Monash University)

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Monash University
Semester One Examination Period
2012

Faculty Of Engineering

EXAM CODES: ECE3073

TITLE OF PAPER: COMPUTER SYSTEMS

EXAM DURATION: 3 hours writing time

READING TIME: 10 minutes

THIS PAPER IS FOR STUDENTS STUDYING AT:( tick where applicable)

o Berwick ü Clayton ü Malaysia o Off Campus Learning o Open Learning
o Caulfield o Gippsland o Peninsula o Enhancement Studies o Sth Africa
o Pharmacy o Other (specify)

During an exam, you must not have in your possession, a book, notes, paper, calculator,
pencil case, mobile phone or other material/item which has not been authorised for the exam
or specifically permitted as noted below. Any material or item on your desk, chair or person
will be deemed to be in your possession. You are reminded that possession of unauthorised
materials in an exam is a discipline offence under Monash Statute 4.1.
1. Attempt ALL questions. Candidates are asked to answer all questions in the
spaces provided in the examination paper. This paper consists of 4 questions.
2. Exam paper is printed on single sided paper. Therefore, use the reverse side of
any of these pages as scrap paper for any working or calculations that are
required in deriving your answers. THESE WORKINGS HOWEVER WILL
NOT CARRY ANY MARKS TOWARDS YOUR FINAL ANSWERS.

AUTHORISED MATERIALS
CALCULATORS o YES ü NO
OPEN BOOK o YES ü NO
SPECIFICALLY PERMITTED ITEMS o YES ü NO

Q1 Q2 Q3 Q4 Total Marks

Candidates must complete this section if required to write answers within this paper

STUDENT ID __ __ __ __ __ __ __ __ DESK NUMBER __ __ __ __

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Attempt all questions

(DO NOT USE RED PEN FOR ANY PART OF YOUR ANSWERS)

QUESTION 1 (25 marks)

The following program provides service for two peripheral circuits (a and b)
responding to external events.

loop:
mov r0,status_reg_a ;read contents of status_reg_a (1 T-state)
and r0,#0002h ;test bit 1 (1 T-state)
jmpa cc_NZ,service_a ;if bit set jump to service routine (2/1 T-state/s)
mov r0,status_reg_a ;read contents of status_reg_a (1 T-state)
and r0,#0002h ;test bit 1 (1 T-state)
jmpa cc_NZ,service_a ;if bit set jump to service routine (2/1 T-state/s)
mov r0,status_reg_b ;read contents of status_reg_b (1 T-state)
and r0,#0008h ;test bit 3 (1 T-state)
jmpa cc_NZ,service_b ;if bit set jump to service routine (2/1 T-state/s)
jmpa cc_UC,loop ;jump to start of polling loop (2 T-states)

Note that the T-states given for each instruction are for the purposes of this question
only. In a jump instruction the first number of T-states applies if the jump is taken,
the second if execution continues straight on.

Question 1.1 (6 marks)

For peripheral circuit 'a' determine the maximum and minimum latency of this polling
loop in T states assuming that the computer is executing the polling loop when service
is requested. Explain your reasoning behind the answers you give.

For maximum latency, the instruction is assumed to be read at the very beginning and the input port changes slightly after
the read instruction.
mov r0, status_reg_a 1T
and r0, #0002h 1T
jmpa cc_NZ,service_a 1T
mov r0, status_reg_b 1T
and r0,#0008h 1T
jmpa cc_NZ,service_b 1T
jmpa cc_UC,loop 2T
mov r0,status_reg_a 1T
and r0,#0002h 1T
jmpa cc_NZ,service_a 2T Total: 12T

For minimum latency, the instruction is assumed to be read at the very end and the input port changes slightly before the
read instruction.
and r0, #0002h 1T
jmpa cc_NZ,service_a 2T Total: 3T

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Question 1.2 (6 marks)

For peripheral circuit 'b' determine the maximum and minimum latency of this polling
program in T states assuming that the computer is executing the polling loop when
service is requested. Explain your reasoning behind the answers you give.

For maximum latency, the instruction is assumed to be read at the very beginning and the input port changes slightly
after the read instruction.
mov r0, status_reg_b 1T
and r0,#0008h 1T
jmpa cc_NZ,service_b 1T
jmpa cc_UC,loop 2T
mov r0,status_reg_a 1T
and r0,#0002h 1T
jmpa cc_NZ,service_a 1T
mov r0, status_reg_a 1T
and r0, #0002h 1T
jmpa cc_NZ,service_a 1T
mov r0,status_reg_b 1T
and r0,#0008h 1T
jmpa cc_NZ,service_b 2T Total:15T

For minimum latency, the instruction is assumed to be read at the very end and the input port changes slightly before
the read instruction.
and r0, #0008h 1T
jmpa cc_NZ,service_b 2T Total: 3T

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Question 1.3 (13 marks)

When a computer reads an external digital signal or when it outputs a digital signal
there is only a very short time period during which the read or write is performed.
Describe the operation including a simple schematic diagram of components at the
very simplest level which can be connected to the address, data and control busses
and that can be used to:
read
i) interface a switch to a microcomputer bus so that the switch state can be
interrogated by a computer program.
Microprocessor read
A tri-state buffer is used to allow an external signal onto
the data bus for the short period. When the switch is
pressed, the input bus address will be decoded on the
address line and control line will be known to read.
The value 0 or 1 from switch will be transferred to the
data line.

write
ii) interface a light emitting diode to a microcomputer bus so that it can be switched
on or off under program control.

When the control line sends a signal to write to the LED,

address bus will provide the address to the LED, making
the decode of control and address go high and the
D-flip flop will take in any value from data bus D0.

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QUESTION 2 (25 Marks)

Question 2.1 (10 marks)

i) Draw a diagram showing the major components of a dual slope analogue

to digital converter.

ii) Describe how the dual slope analogue to digital converter functions. Your
description should incorporate the equations governing its operation.

There are two phase of the operation. The switch will be connected to the unknown input voltage Vin and
it is integrated for a fixed time Ti = Ni*Tc. The resulting integrator voltage V is::

The second measurement phase involves integrating the reference voltage -Vref until the integrator output
returns to zero.

0 as Ti = Ni*Tc and Tr = Nx*Tc

Therefore

If Vin is constant then:

as Nx is proportional to Vin

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iii) Explain the advantages and disadvantages of the dual slope analogue to
digital converter.

Advantages: 1) The dual slop ADC are able to reject high frequency noise which acts like a low-pass filter.
2) Stable.
Disadvantages: 1) Accuracy depends on Vref and the short term stability of time measurement.
2) Relatively slow due to integrating converter.

Question 2.2 (9 marks)

i) Explain why the input signal to an analogue to digital converter is

sometimes passed through a sample and hold circuit.
While conversion is being processed, the unknown input voltage needs to be constant. Hence the sample
and hold circuit will hold the input voltage at a constant value so that the ADC can complete the conversion.

ii) Draw a diagram showing the major components of a practical sample and
hold circuit.

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iii) Explain the function of each of the components in your diagram of a

sample and hold circuit.

The input operational amplifier will have a high input impedance so that they do not load the signal source
and a low output impedance so that the capacitor can be charged quickly during sample mode. The output
operational amplifier will have a high input impedance so that they do not discharge the capacitor quickly
during hold mode and a low output impedance to drive an external load. The feedback ensures the whole
circuit has a unity gain. The digital control will determines whether its in sample or hold mode.

Question 2.3 (6 marks)

With regard to sample and hold devices, explain what is meant by the following
terms:

i) acquisition time,
Acquisition time is the delay where the device changes from hold to sample until the output voltage
matches the input voltage.

ii) aperture time,

Aperture time is the difference in time between the time that hold is asserted and the location in time of
the point on the input waveform that is held.

iii) pedestal error

Pedestal error is caused by a voltage superimposed on the output due to the control signal of the FET.

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QUESTION 3 (25 Marks)

Question 3.1 (10 marks)
#include <stdio.h>
#include "includes.h"

/* Definition of Task Stacks */

#define TASK_STACKSIZE 2048
OS_STK task1_stk[TASK_STACKSIZE];
OS_STK task2_stk[TASK_STACKSIZE];
OS_STK task3_stk[TASK_STACKSIZE];

/* Definition of Task Priorities */

#define TASK1_PRIORITY 1
#define TASK2_PRIORITY 2
#define TASK3_PRIORITY 3

OS_EVENT *sem;

int Out1, Out2;

void task1(void* pdata)

{
INT8U err;

while(1){
Out1 = 0;
OSTimeDly(2);
OSSemPend(sem,0,&err);
Out1 = 1;
OSTimeDly(1); /* Delay by 1 timer tick */
OSSemPost(sem);
}
}
void task2(void* pdata)
{
INT8U err;

while(1){
Out2 = 0;
OSTimeDly(1);
OSSemPend(sem,0,&err);
Out2 = 1;
OSTimeDly(1);
OSSemPost(sem);
}
}
void task3(void* pdata)
{
printf(“Ticks: Out1 Out2\n”);
while (1){
printf(“%ld: %d %d\n”, OSTimeGet(), Out1, Out2);
OSTimeDly(1);
}
}

int main(void)

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{
OSTaskCreateExt(task1,
NULL,
(void *)&task1_stk[TASK_STACKSIZE-1],
TASK1_PRIORITY,
TASK1_PRIORITY,
task1_stk,
TASK_STACKSIZE,
NULL,
0);
OSTaskCreateExt(task2,
NULL,
(void *)&task2_stk[TASK_STACKSIZE-1],
TASK2_PRIORITY,
TASK2_PRIORITY,
task2_stk,
TASK_STACKSIZE,
NULL,
0);
OSTaskCreateExt(task3,
NULL,
(void *)&task3_stk[TASK_STACKSIZE-1],
TASK3_PRIORITY,
TASK3_PRIORITY,
task3_stk,
TASK_STACKSIZE,
NULL,
0);
sem = OSSemCreate(1);
OSStart();
return 0;
}

For the above C code running under the uC/OS-II real time kernel, show what output
is produced below. Assume that OSStart() is called just after time 0 and after each
system timer interrupt, the time produced by calling OSTimeGet() increments by 1.
You may assume that the execution time of a line of code is much shorter than a timer
tick. In your answer show just 12 lines of output from the printf statements.
Ticks: Out1 Out2
0: 0 0
1: 0 1
2: 1 0
3: 0 1
4: 0 0
5: 1 0
6: 0 1
7: 0 0
8: 1 0
9: 0 1
10: 0 0

……………………………………………………………………………………..

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10

Question 3.2 (5 marks)

Repeat Question 3.1 except swap the priorities of task1 and task2 by substituting the
code after

/* Definition of Task Priorities */

With the following:

#define TASK1_PRIORITY 2
#define TASK2_PRIORITY 1

Ticks: Out1 Out2

0: 0 0
1: 0 1
2: 1 0
3: 0 1
4: 0 0
5: 0 1
6: 1 0
7: 0 1
8: 0 0
9: 0 1
10: 1 0

……………………………………………………………………………………..

Question 3.3 (5 marks)

Explain how the uC/OS-II real time kernel measures the utilisation of a CPU when
multiple tasks are running. Your answer should outline the initialisation steps that are
performed and any assumptions, as well as the steps taken when multiple tasks are
running.
The idle task increments as integer OSIdleCtr.
Assumption: The initialization OSStatInit() must be called with just the one task running that makes this call.
OSStatInit() measures the OSIdleCtr over a period of 1 second and this is called OSIdleCtrMax. It is a maximum
since no other tasks can consume CPU cycles except the idle task during that second.
While all tasks are now running, a 2nd lowest priority task called the statistics task records the OSIdleCtr after
every second and calculates the utilisation as below. The statistic task then resets OSIdleCtr to 0 and sleeps for
another second and repeats.
The % utilisation is then [1-(OSIdleCtr/OSIdleCtrMax)]*100
Which is optimized as 100-OSIdleCtr/[OSIdleCtrMax/100] for integer arithmetic.
One additional assumption is that the utilisation is low enough to allow the statistic task to run every second.

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11

……………………………………………………………………………………..

Question 3.4 (5 marks)

Explain how priority inversion can arise when using semaphores to protect a shared
resource in a real time system. Include an example in your answer that has at least
three tasks of different priorities and a semaphore to coordinate access to a shared
resource.
A semaphore is initialized to 1 and used as a mutex for a shared resource.
A low priority task runs and waits on the semaphore, taking the resource. Before this task can complete, it is
pre-empted by a medium priority task that is computationally intensive and does not block for a long time.
A high priority task becomes ready to run and pre-empts the medium priority task. It then requests the shared
resource by waiting on the mutex semaphore, but is blocked since the low priority task holds the resource (and
is not running). Ideally the low priority task should now run and release the resource a signal on the semaphore,
but the medium priority task runs (for a long time) instead due to its higher priority. Thus the high priority task is
effectively blocked due to a low priority task holding the resource and not able to complete.

……………………………………………………………………………………..

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12

How does uC/OS-II solve the problem of priority inversion with its implementation of
a mutex?
In the above scenario, when the high priority task waits on the mutex, the uC/OS-II mutex implementation raises
the priority of the low priority task temporarily to a preset high priority. This causes the low priority task to
complete quickly in preference to the medium task and thus release the resource quickly.

QUESTION 4 (25 Marks)

The following table shows a list of periodic processes with their associated execution times
and periods in a real time system.

Process Execution time (msec) Period (msec)

P1 3 16
P2 1 4
P3 1 8
P4 2 8

Question 4.1 (2 marks)

What is the CPU utilisation that would occur if all processes are scheduled and meet their
deadlines?
(3+4+2+4)/16 = 13/16
…………………………

Question 4.2 (1 mark)

What is the number of msecs that will define the minimum cycle of scheduling?

16
…………………………..

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13

Question 4.3 (2 mark)

For a Rate Monotonic Scheduling (RMS) policy, what priorities could be allocated to each of
the processes? Use 1 for highest priority in the following table.

Process Priority (1, 2, 3 or 4)

P1 4
P2 1
P3 2 or 3
P4 3 or 2
P3 and P4 must be different priorities

Question 4.4 (5 marks)

Show how the processes would be scheduled to meet their deadlines using RMS in the
following table. P3 priority 2 shown first then P4 priority 2 after 'or'

Time Running Process Deadline

(msec) (one of P1, P2, P3, (any combination of P1, P2, P3, P4 or none)
P4 or idle)
0 P2
1 P3 or P4
2 P4
3 P4 or P3 P2
4 P2
5 P1
6 P1
7 P1 P2 P3 P4
8 P2
9 P3 or P4
10 P4
11 P4 or P3 P2
12 P2
13 idle
14 idle
15 idle P1 P2 P3 P4
16

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Question 4.5 (5 marks)

Show how the processes would be scheduled to meet their deadlines using Earliest Deadline
First (EDF) scheduling policy in the following table.

Time Running Process Deadline

(msec) (one of P1, P2, P3, (any combination of P1, P2, P3, P4 or none)
P4 or idle)
0 P2
1 P3 or P4
2 P4
3 P4 or P3 P2
4 P2
5 P1
6 P1
7 P1 P2 P3 P4
8 P2
9 P3 or P4
10 P4
11 P4 or P3 P2
12 P2
13 idle
14 idle
15 idle P1 P2 P3 P4
16

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15

The following C code has been compiled into NIOS-II assembly code as shown
below:

int i, my_array[4];
i = 0;
while (i<4){
my_array[i] *= 2;
i++;
}

0x00000378 addi sp, sp, -0x18 //reserve stack space

0x0000037c stw fp, 20(sp) //preserve old fp
0x00000380 addi fp, sp, 0x14 //update fp
0x00000384 stw zero, -20(fp) //i = 0
0x00000388 ldw r2, -20(fp) //get i
0x0000038c cmpgei r2, r2, 0x4 //check for end
0x00000390 bne r2, zero,0x48 (0x000003dc)
0x00000394 ldw r2, -20(fp) //get i
0x00000398 slli r2, r2, 0x2 //i = i*4
0x0000039c addi r3, fp, -0x14 //addr before array
0x000003a0 add r2, r2, r3 //add offset
0x000003a4 addi r4, r2, 0x4 //actual element addr
0x000003a8 ldw r2, -20(fp) //get i
0x000003ac slli r2, r2, 0x2 //end of commented code
0x000003b0 addi r3, fp, -0x14
0x000003b4 add r2, r2, r3
0x000003b8 addi r2, r2, 0x4
0x000003bc ldw r3, 0(r2)
0x000003c0 add r2, r3, zero
0x000003c4 add r2, r2, r3
0x000003c8 stw r2, 0(r4)
0x000003cc ldw r2, -20(fp)
0x000003d0 addi r2, r2, 0x1
0x000003d4 stw r2, -20(fp)
0x000003d8 br -0x54 (0x00000388)
0x000003dc ldw fp, 20(sp)
0x000003e0 addi sp, sp, 0x18

Question 4.6a (1 mark)

In terms of the frame pointer what is the memory address of i ?
fp - 20
………………………………………..

Question 4.6b (1 mark)

In terms of the frame pointer what is the memory address of my_array[0] ?

fp - 16 I think it should be fp - 10
………………………………………..

Question 4.6c (1 mark)

What address range is the code for i=0 ? (address range that make i = 0)

0x00000384
………………………………………..

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Question 4.6d (1 mark)

What address range is the code that implements the loop termination?
get i, check for i, then branch

0x00000388 to 0x00000390
………………………………………..

Question 4.6e (1 mark)

What registers are used for the address of my_array[i]?

r2 and r4
………………………………………...

Question 4.6f (5 marks)

What simple optimisations can be applied to the assembly code?
Answer:
From 0x00000394 to 0x000003a4 is similar to 0x000003a8 to 0x000003b8. So optimization can be applied by
removing one of these block of instructions.

Remove code from 0x000003a8 to 0x000003b8 by changing

0x000003bc ldw r3, 0(r4)
Remove code 0x000003c0 by changing
0x000003c4 add r2, r3, r3
Remove code 0x00000388, 0x000003a8, 0x000003cc, 0x000003d4 by using register r5 for i

**** END OF QUESTION PAPER ****

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