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    14-Decoder Circuits-31-01-2023 PDF

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    A decoder is a combinational circuit that converts a binary code with n input bits to a maximum of 2n unique output lines. It decodes the input bits and asserts one of its outputs. Decoders are used for data demultiplexing, addressing memory, seven segment displays, and port mapping I/O. Higher order decoders can be implemented using multiple lower order decoders. For example, a 3 to 8 decoder can be made using two 2 to 4 decoders. Decoders can also implement Boolean functions by generating the minterms and using OR gates.

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    14-Decoder Circuits-31-01-2023 PDF

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    26 views15 pages
    A decoder is a combinational circuit that converts a binary code with n input bits to a maximum of 2n unique output lines. It decodes the input bits and asserts one of its outputs. Decoders are used for data demultiplexing, addressing memory, seven segment displays, and port mapping I/O. Higher order decoders can be implemented using multiple lower order decoders. For example, a 3 to 8 decoder can be made using two 2 to 4 decoders. Decoders can also implement Boolean functions by generating the minterms and using OR gates.

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    A decoder is a combinational circuit that converts a binary code with n input bits to a maximum of 2n unique output lines. It decodes the input bits and asserts one of its outputs. Decoders are used for data demultiplexing, addressing memory, seven segment displays, and port mapping I/O. Higher order decoders can be implemented using multiple lower order decoders. For example, a 3 to 8 decoder can be made using two 2 to 4 decoders. Decoders can also implement Boolean functions by generating the minterms and using OR gates.

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    © All Rights Reserved
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    Download as pdf or txt
    26 views15 pages

    14-Decoder Circuits-31-01-2023 PDF

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    A decoder is a combinational circuit that converts a binary code with n input bits to a maximum of 2n unique output lines. It decodes the input bits and asserts one of its outputs. Decoders are used for data demultiplexing, addressing memory, seven segment displays, and port mapping I/O. Higher order decoders can be implemented using multiple lower order decoders. For example, a 3 to 8 decoder can be made using two 2 to 4 decoders. Decoders can also implement Boolean functions by generating the minterms and using OR gates.

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    © All Rights Reserved
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    of 15

    Decoder

    • Discrete quantities of information are represented in digital systems by binary codes.

    • A binary code of n bits is capable of representing up to 2n distinct elements of coded


    information.

    • A decoder is a combinational circuit that converts binary information from n input lines
    to a maximum of 2n unique output lines.

    • The decoders are in general called as n – to – m line decoders where m ≤ 2n

    • Their purpose is to generate the 2n (or fewer) minterms of n input variables.

    • Each combination of inputs will assert a unique output.


    • One of these outputs will be active High based on the combination of inputs present,
    when the decoder is enabled.

    • The name decoder is also used in conjunction with other code converters such as BCD to
    Seven segment decoder.

    • They are used in a wide variety of applications:

    • Data multiplexing and data demultiplexing,

    • Seven segment displays

    • Address decoders for memory and

    • Port-mapped I/O.
    2 to 4 Decoder
    • Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs D3, D2, D1 & D0.
    The block diagram of 2 to 4 decoder is shown in the following figure.

    • One of these four outputs will be ‘1’ for each combination of inputs when enable,
    E is ‘1’.
    Truth table of 2 to 4 decoder :

    From Truth table, we can write the Boolean functions for each output as
    • Logic Circuit Diagram:
    3 to 8 line decoder
    • The three inputs are decoded into eight outputs, each representing one of the
    minterms of the three input variables.
    • A particular application of this decoder is binary to octal conversion.
    Implementation of Higher order Decoders using lower order decoders
    • Implementation of 3 to 8 decoder using 2 to 4 decoders:
    • We know that 2 to 4 Decoder has two inputs, A1 & A0 and four outputs, D3 to D0.
    Whereas, 3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, D7 to D0.
    • The number of lower order decoders required for implementing higher order decoder
    can be found using the following formula.

    • Where m1 is the number of outputs of lower order decoder


    • m2 is the number of outputs of higher order decoder
    • Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder. The block
    diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following figure.
    4 to 16 Decoder

    • Implementation of 4 to 16 Decoder using 3 to 8 decoders.

    • We know that 3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs,
    D7 to D0, whereas, 4 to 16 Decoder has four inputs A3, A2, A1 & A0 and sixteen
    outputs, D15 to D0.

    • Here,
    Application of Decoder
    • A decoder provides the 2n minterms of n input variables. Each asserted output of
    the decoder is associated with a unique pattern of input bits.

    • Any Boolean function can be expressed in sum of minterms form, a decoder that
    generates the minterms of the function, together with an external OR gate that
    forms their logical sum, provides a hardware implementation of the function.

    • In this way, any combinational circuit with n inputs and m outputs can be
    implemented with an n – to - 2n line decoder and m OR gates.
    Implementation of a Full adder with a Decoder

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