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COI2 Programming Model of 8051

The document discusses the programming model of the 8051 microcontroller. It describes the various addressing modes supported, including immediate, register direct, memory direct, memory indirect, and indexed addressing. It also outlines the different types of transfer, arithmetic, logical, and conditional branching instructions. Examples are provided to illustrate the syntax of each instruction type. References for further reading on 8051 programming and microcontrollers are listed at the end.

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37 views

COI2 Programming Model of 8051

The document discusses the programming model of the 8051 microcontroller. It describes the various addressing modes supported, including immediate, register direct, memory direct, memory indirect, and indexed addressing. It also outlines the different types of transfer, arithmetic, logical, and conditional branching instructions. Examples are provided to illustrate the syntax of each instruction type. References for further reading on 8051 programming and microcontrollers are listed at the end.

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Copyright
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Microprocessors and Microcontrollers – 11EC311

Programming Model of 8051


Addressing Modes
● Immediate Addressing
– Syntax: Instruction Register, # data
– Ex: ADD A,#50h
● Register Direct Addressing
– Syntax: Instruction Register1, Register 2
– Ex: ADD A,R0
● Memory Direct Addressing
– Syntax: Instruction Register, Address
– Ex: ADD A,54h
● Memory Indirect Addressing
– Syntax: Instruction Register1, @Register2
– Ex: ADD A,@R0
● Indexed Addressing
– Syntax: Instruction Acc, @offset(acc) + base(DPTR)
– Ex: MOVC A,@A+DPTR
18/08/15 8051 Programming Model - MPMC 2
TRANSFER INSTRUCTIONS
Instruction Description Syntax Example
MOV Move data from MOV MOV A,R0
source to <dest>,<source> MOV A,@R1
Destination
MOVX Transfer btw A and MOVX MOVX A,@DPTR
Ext. RAM( Indirect <dest>,<source> MOVX @R1,A
Mode only)
MOVC Read Program MOVC A,@A+PC
memory(Indexed)
PUSH INC SP and store PUSH <src> PUSH A

POP Read and DEC POP <dest> POP B


SP
XCH Exchange data XCH reg, reg XCH A,B
XCHD Exchange Lower XCHD reg,reg XCHD A,@R1
order Nibble
18/08/15 8051 Programming Model - MPMC 3
TRANSFER INSTRUCTIONS
MOV A,Rn
MOV A, Direct
MOV A,@Ri
MOV A,#Data
MOV Rn,A
MOV Rn,Direct
MOV Rn,#Data
MOV Direct,A
MOV Direct, Rn
18/08/15 8051 Programming Model - MPMC 4
TRANSFER INSTRUCTIONS

MOV Direct, Direct


MOV Direct,@Ri
MOV Direct,#Data
MOV @Ri,A
MOV @Ri,Direct
MOV @Ri,#Data
MOV DPTR,#Data16
MOVX A,@Ri
MOVX A,@DPTR
18/08/15 8051 Programming Model - MPMC 5
TRANSFER INSTRUCTIONS

PUSH Direct
POP Direct
XCH A,Rn
XCH A, Direct
XCH A,@Ri
XCHD A,@Ri
MOVX @Ri,A
MOV @DPTR,A

18/08/15 8051 Programming Model - MPMC 6


ARITHMETIC INSTRUCTIONS

Instruction Description Syntax Example


ADD Addition ADD operand,opearnd ADD A,B

ADDC ADD with carry ADDC ADDC A,B


operand,opearnd
SUBB Sub with carry SUBB operand,opearnd SUBB A,B
INC Increment 1 INC Register INC A
DEC Decrement 1 DEC Register DEC R0
MUL Multiply and store in MUL AB MUL AB
B:A
DIV A=Quo(A/B) DIV AB DIV AB
B=Rem(A/B)
DAA Decimal Adjust Acc DAA DAA
18/08/15 8051 Programming Model - MPMC 7
ARITHMETIC INSTRUCTIONS
ADD A,Rn
ADD A,Direct
ADD A,@Ri
ADD A,#Data
ADDC A,Rn
ADDC A,@Data
SUBB A,Rn
ADDC A, Direct
ADDC A,@Ri
18/08/15 8051 Programming Model - MPMC 8
ARITHMETIC INSTRUCTIONS
SUBB A, Direct
SUBB A,@Ri
SUBB A,#Data
INC A DEC Direct
INC Rn DEC @Ri
INC Direct INC DPTR
INC @Ri MUL AB
DEC A DIV AB
DEC Rn DA A
18/08/15 8051 Programming Model - MPMC 9
LOGICAL INSTRUCTIONS

Instruction Description Syntax Example

ANL AND ANL operand,operand ANL A,10h


ORL OR ORL operand,operand ORL 23h,#10h
XRL XOR XRL operand,operand XRL 23h,A
CLR Mov 00h CLR operand CLR A
CPL NOT CPL operand CPL 21h
RL Rotate left 1 RL op RL A
RLC Rotate left through RLC op RLC A
carry
RR Rotate right1 RR op RR A
RRC Rotate right RRC op RRC A
through carry

18/08/15 8051 Programming Model - MPMC 10


LOGICAL INSTRUCTIONS

ANL A,Rn
ANL A,Direct
ANL A,@Ri
ANL A,#Data
ANL Direct,A
ANL Direct,#Data
ORL A,Rn
ORL A,Direct
ORL A,@Ri
18/08/15 8051 Programming Model - MPMC 11
LOGICAL INSTRUCTIONS

ORL A,#Data
ORL Direct,A
ORL Direct,#Data CLR A
XRL A,Rn CPL A
XRL A,Direct RL A
XRL A,@Ri RLC A
XRL A,#Data RR A
XRL Direct,A RRC A
XRL Direct,#Data SWAP A
18/08/15 8051 Programming Model - MPMC 12
UNCONDITIONAL BRANCHING INSTRUCTIONS
Instruction Description Syntax Example
SJMP TO 8bit relative SJMP addr SJMP here
addr
LJMP Long jump 16bit LJMP addr LJMP here
AJMP Absolute Jump AJMP 11bit addr AJMP here
11bit
JMP Jump JMP addr JMP here
ACALL Absolute call at ACALL addr ACALL here
PC:addr
LCALL Long call LCALL addr LCALL here
RET Return from RET RET
subroutine
RETI Return from RETI RETI
Interrupt
NOP No Operation NOP NOP
18/08/15 8051 Programming Model - MPMC 13
CONDITIONAL BRANCHING INSTRUCTIONS

Instruction Description Syntax Example

CJNE Compare and jump CJNE Reg,<byte>,addr CJNE A,#10,start


if not equal
DJNZ Decrement and DJNZ Reg,addr DJNZ A,start
jump if not zero
JZ Jump if 0 JZ addr JZ there
JNZ Jump if not zero JNZ addr JNZ here
JC Jump if Carry JC addr JC here
JNC Jump is No carry JNC addr JNC here
JB Jump if bit JB P1.0,addr JB P1.0,there
JNB Jump if no bit JNB P0.3,addr JNB P0.3,start
JBC Jump if bit and JBC P2.5,addr JBC P2.5,next
clear bit
18/08/15 8051 Programming Model - MPMC 14
BIT MANIPULATION INSTRUCTIONS

Instruction Example
ANL ANL C,bit

ORL ORL C,bit


MOV MOV C,P3.2
CLR CLR C
SETB SETB P1.1
CPL CPL P.2.0

18/08/15 8051 Programming Model - MPMC 15


References

● https://www.sites.google.com/site/sripathroykoganti/my-forms

● The 8051 Microcontroller, 3rd Edition, Ayala, CENGAGE


Learning
● Microcontrollers[Theory and Applications], Ajay V
Deshmukh, Tata McGraw Hill
● The 8051 Microcontroller and Embedded Systems,
Muhammad Ali Mazidi, Pearson Education

18/08/15 8051 Programming Model - MPMC 16


Thank You

18/08/15 8051 Programming Model - MPMC 17

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