AND9093/D

Using MOSFETs in Load

Switch Applications

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APPLICATION NOTE
Introduction
In today’s market, power management is more important for the same die area. Thus, for high current applications the
than ever. Portable systems strive to extend battery life while N-channel transistor is preferred.
meeting an ever increasing demand for higher performance. When using an N-channel MOSFET in a load switch
Load switches provide a simple and inexpensive method for circuit, the drain is connected directly to the input voltage
the system to make the appropriate power management rail and the source is connected to the load. The output
decisions based on which peripherals or sub-circuits are voltage is defined as the voltage across the load, and
currently in use. Load switches are found in notebooks, cell therefore:
phones, hand held gaming systems and many other portable V S + V OUT (eq. 1)
devices.
The load switch is controlled by the system, and connects In order for the N-channel MOSFET to turn on, the
or disconnects a voltage rail to a specific load. By turning gate-to-source voltage must be greater than the threshold
unused circuitry off, the system as a whole can run more voltage of the device. This means that:
efficiently. The load switch provides a simple means to V G w V OUT ) V th (eq. 2)
power a load when it is in demand and allows the system to In order to meet Equation 2, a second voltage rail is
maximize performance. needed to control the gate. Therefore, the input voltage rail
can be considered independently of the pass transistor.
Load Switch Basics
A load switch is comprised of two main elements: the pass Because of this, the N-channel load switch can be used for
transistor and the on/off control block, as shown in Figure 1. very low input voltage rails or for higher voltage rails, as
long as the gate-to-source voltage VGS remains higher than
P-channel the threshold voltage of the device. The designer must
Load Switch
ensure that the device maximum ratings and the safe
operating area of the MOSFET are not violated.
+ When using a P-channel MOSFET in a load switch circuit
VIN Load (as in Figure 1, the source is directly connected to the input
−
On/Off voltage rail and the drain is connected to the load. In order
Control
for the P-channel load switch to turn on, the source-to-gate
voltage must be greater than the threshold voltage.
Therefore:
Figure 1. Example Load Switch Circuit
V IN w V G ) V th (eq. 3)
The pass transistor is most commonly a MOSFET (either At minimum, the input voltage rail must be greater than
N-channel or P-channel) that passes the voltage supply to the threshold voltage of the selected pass transistor
a specified load when the transistor is on. (assuming the gate voltage is 0 V when the load switch is
turned on).
N-channel and P-channel Considerations
The selection of a P-channel or N-channel load switch The P-channel MOSFET has a distinct advantage over the
depends on the specific needs of the application. The N-channel MOSFET, and that is in the simplicity of the
N-channel MOSFET has several advantages over the on/off control block. The N-channel load switch requires an
P-channel MOSFET. For example, the N-channel majority additional voltage rail for the gate; the P-channel load switch
carriers (electrons) have a higher mobility than the does not. As with the N-channel MOSFET, the designer
P-channel majority carriers (holes). Because of this, the must ensure that the device maximum ratings and the safe
N-channel transistor has lower RDS(on) and gate capacitance operating area of the P-channel MOSFET are not violated.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

February, 2014 − Rev. 1 AND9093/D
 AND9093/D

Load Switch Control Circuit Considerations source. As with the N-channel control circuit, resistor R1 is
There are multiple ways to implement the on/off control selected so that milliamps of current or less flow through R1
block in a load switch circuit. This section will cover one when Q1 is on. A standard range is 1 kW – 10 kW.
control circuit example for the N-channel and one for the For both control circuit implementations, the small-signal
P-channel load switch. NMOS transistor, Q1, can be integrated into the same
N-channel package as the pass transistor.
Load Switch VOUT
Efficiency Considerations
Efficiency is critical to the success of the overall power
+ Load
management of the system. In a load switch circuit, the load
VIN R1
− current flows directly through the pass transistor when it is
+ turned on. Therefore, the main power loss is the conduction
VGATE loss.
−

Q1 P LOSS + I LOAD 2 @ R DS(on) (eq. 4)

EN
The RDS(ON) of the pass transistor causes a voltage drop
between the input voltage and the output voltage, as shown
in Equation 5. For applications requiring high load currents
Figure 2. N-channel Example Control Circuit
or low voltage rails, this voltage drop becomes critical. The
Figure 2 shows an example load switch control circuit for voltage drop will increase as the load current increases, and
an N-channel pass transistor. A logic signal from the system the voltage drop at maximum load must be taken into
power management control circuitry turns the load switch consideration when selecting the pass transistor.
on and off via a small-signal NMOS transistor, Q1. When V OUT + V IN * I LOAD @ R DS(on) (eq. 5)
EN is LOW, Q1 is off and the pass transistor gate is pulled
As discussed in previous sections, the N-channel
up to VGATE to keep it turned on. When EN is HIGH, Q1
MOSFET has an RDS(on) advantage over the P-channel
turns on, the pass transistor gate is pulled to ground, and the
MOSFET for a given die size. The RDS(on) of an N-channel
load switch turns off. Resistor R1 is selected so that
device can be two times lower than the RDS(on) of
milliamps of current or less flow through R1 when Q1 is on.
a P-channel device of similar die area. This difference is
A standard range is 1 kW – 10 kW.
most prominent at higher currents, but the N-channel
An additional voltage source, VGATE, is needed to keep
RDS(on) advantage becomes less prominent at lower
the gate-to-source forward biased. As expressed in
currents. For applications such as cell phones and other
Equation 2, the gate voltage must be larger than the sum of
portable low power devices, higher efficiency can be
the output voltage and the threshold voltage. This may be
attained using a P-channel pass transistor, with the
undesirable for systems that do not have an extra voltage rail
advantage of a simpler control circuit.
available.
To illustrate this, let’s assume that a 30 mW N-channel
P-channel transistor and a 50 mW P-channel transistor have similar die
Load Switch VOUT size. The efficiency impact of the two devices will be
examined for a high current application and a low current
R1
+ application.
Load
VIN For the first example, consider an application that requires
−
a maximum load current of 10 A. Using Equations 4 and 5,
Q1
EN the power loss at the maximum load is calculated to be 3 W
for the N-channel transistor, and the voltage drop across the
transistor is 300 mV. The power loss at the maximum load
is 5 W for the P-channel transistor, and the voltage drop
Figure 3. P-channel Example Control Circuit
across the transistor is 500 mV.
Figure 3 shows an example load switch control circuit for Now consider an application in which the maximum
a P-channel pass transistor. As with the N-channel example, current is 2 A. The power loss at maximum load is 120 mW
a logic signal from the system power management control for the N-channel device and 200 mW for the p-channel
circuitry turns the load switch on and off via a small-signal device. The voltage drop for the N-channel transistor is
NMOS transistor, Q1. When EN is LOW, Q1 is off and the 60 mV and is 100 mV for the P-channel transistor.
gate is pulled up to VIN. When EN is HIGH, Q1 turns on, the As a final example, consider an application with an
pass transistor gate is pulled to ground, and the load switch 850 mA maximum load current. The 30 mW N-channel
turns on. As long as the input voltage rail is higher than the transistor’s power loss is 21.7 mW compared to the
threshold voltage of the PMOS transistor, it will turn on 36.1 mW power loss of the 50 mW P-channel transistor of
when EN is HIGH without the need of an additional voltage similar die size. For low current applications, the N-channel

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 AND9093/D

RDS(ON) advantage becomes negligible. P-channel pass P-channel

transistors can be designed to have RDS(on) as low as 8 mW. Load Switch VOUT
Low RDS(on) is critical for maximizing the efficiency of the VIN +
Load
R2 C1
load switch circuit and minimizing the voltage drop across
−
the pass transistor. The specific conditions of the load switch
application must be considered to make the final decision to R1 CLOAD RLOAD
use a PMOS or NMOS pass transistor.

Gate-to-Source Voltage Considerations Q1

The applied gate-to-source voltage of the pass transistor EN
directly affects the efficiency of the circuit because RDS(on)
is inversely proportional to the applied gate-to-source
Figure 5. Load Switch with Capacitive Load
voltage. Figure 4 shows an example RDS(on) curve over
a VGS range. When the load switch is first turned on, an inrush current
event occurs on the input as the CLOAD is charged. This can
be seen in Equation 6:
dV
I inrush + C LOAD @ (eq. 6)
dt
The faster the device switches on, the higher the inrush
current will be. This potentially harmful inrush current can
be reduced by controlling the load switch turn-on
characteristics.
Figure 6 shows the simplified MOSFET turn-on transfer
curves. There are four main regions for device turn-on, and
each will be briefly addressed.

Figure 4. Example RDS(on) vs. VGS Curve

The available VGS of the circuit must be considered when

selecting the pass transistor. Operating too close to the knee
of the RDS(on) curve can lead to higher conduction losses.
Any small change in the gate-to-source voltage could result
in a large change in the RDS(on).

Turn-on Considerations
Proper turn-on of the load switch pass transistor is critical
for maximizing circuit performance and maintaining safe
operation of the individual components. Optimal turn-on
speed depends on the needs of the specific application and
the device parameters of the selected load switch. If the
turn-on speed is too fast, a transient current spike occurs on
Figure 6. MOSFET Turn-on Waveforms
the input voltage supply, known as inrush current.
During Region 1, VSG increases until it reaches VTH.
Inrush Current Because the device is off, VSD remains at VDD. During
Inrush current occurs when the load switch is first turned Region 2, VSG rises above the VTH and the device begins to
on and is connected to a capacitive load, as shown in turn on. Additionally, ID increases to the final load current
Figure 5. The capacitive load could be a battery, a DC:DC and CGS charges.
circuit, or other sub-circuit. The turn-on speed of the pass In Region 3, VSG remains constant as VSD decreases to its
transistor directly influences the amount of inrush current saturation level, and CGD charges. During Region 4, both
seen on the input of the load switch. CGS and CGD are fully charged, the device is fully on, and
Inrush current causes a dip in the input supply voltage that VSG rises to its final drive voltage, VDR. The plateau
can adversely impact the functionality of the entire system. voltage, VPL,is defined as:
Likewise, inrush current spikes can potentially damage the
I LOAD
load switch circuit components or reduce the lifetime of the V PL + V th ) (eq. 7)
components. g fs

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 AND9093/D

In order to control the turn-on speed of the load switch, an For many designs, the equivalent CLOAD may be an
external resistor R1 and external capacitor C1 are added to unknown. If this is the case, CLOAD can be estimated from
the load switch circuit as shown in Figure 7. the measured inrush current waveform of the circuit without
P-channel
the addition of R1 and C1. Figure 9 shows an example inrush
Load Switch VOUT
current waveform for a load switch circuit similar to
Figure 5.
VIN +
R2 C1
−
CLOAD RLOAD
R1

Q1
EN

Figure 7. Inrush Current Limiting Circuit

The selection of R1, R2 and C1 is very important to the

performance of the load switch circuit. C1 must be much
larger than the CGD of the load switch device so this
capacitance will dominate over CGD. By placing C1
Figure 9. Example Inrush Current Without R1 or C1
between the drain and source of the pass transistor, Region 3
of the VSD curve becomes linear and the MOSFET The load capacitance, CLOAD, can be estimated using the
slew-rate, dVSD/dt, can be controlled. following equation:
R1 and R2 form a voltage divider that determines the 1
voltage seen at the gate of the pass transistor. R1 and R2 can C LOAD + @ Dt @ DI (eq. 11)
2
be calculated by using Equation 8 when the small-signal
For the example current waveform shown in Figure 9,
N-channel device is on.
CLOAD is estimated as:
R1 V SG,MAX
+1* (eq. 8) 1
C LOAD + @ 1.6 ms @ 18 A + 1.28 mF
R1 ) R2 V IN 2
In order to ensure that VSG does not exceed the maximum
rating of the device, VSG,MAX is used. VSG,MAX can be Inrush Current Example
found in the device datasheet (see Figure 8). R2 is the Consider the P-channel load switch circuit shown in
pull-up resistor described in previous sections, and is Figure 7 with the following parameters:
recommended to be between 1 kW and 10 kW. Table 1. LOAD SWITCH CIRCUIT EXAMPLE
Circuit Parameters PMOS Parameters
VIN = 10 V VSD,MAX = 20 V
ILOAD,MAX = 5 A VSG,MAX = 8 V
IIN,MAX = 8 A VTH = −0.67 V
Figure 8. Maximum VGS Spec Example from
Datasheet CLOAD = 1 mF gfs = 5.9 S

R1 and C1 determine the turn-on speed of the pass First, R1 and R2 must be selected. For this example,
transistor. C1 can be calculated by using Equation 9, where a 1 kW resistor was selected for R2. R1 was calculated by
IINRUSH is the desired maximum inrush current for the load rearranging Equation 8 and solving for R1:
switch circuit.
V IN * V SGMAX
ǒ Ǔ
R2
V IN ) VPL V PL C LOAD R1 + RR @ + + 250 W
C1 + ) @ (eq. 9) V SGMAX 4
R1 R2 I INRUSH
Next, C1 is calculated using Equation 10 and the
Plugging Equation 7 into Equation 9, C1 becomes: parameters in Table 1.

ȡV IN ) V th *
ǒ I
LOAD
g Ǔ V th * ǒ I
LOAD
g
Ǔȣ (eq. 10)
C LOAD
+ȧ ȧ@ I
fs fs
C1 )
R1 R2
Ȣ Ȥ
INRUSH

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 AND9093/D

ǒ 10 * 0.67 * ǒ5.9Ǔ −0.67 * ǒ5.9Ǔ

Ǔ
5 5 of the device, and can potentially damage other components
1 mF
C1 + ) @ within the system.
250 1000 3 The load switch must have a continuous current rating
greater than the maximum load current of the application.
C 1 + 10.8 nF Likewise, the MOSFET must not be operated outside of the
Therefore, for the example circuit, the inrush current will maximum VDS and VGS specifications. The device
be limited to 3 A by selecting a 1 kW pull-up resistor (R1), datasheet specifies the absolute maximum ratings and also
a 250ĂW resistor for R2 and a 10 nF capacitor for C1. contains a figure showing the Safe Operating Area (SOA).
The designer must evaluate whether the device will operate
Turn-on Speed within its specified SOA for the application.
Turn-on speed plays an important role in the behavior of Figure 11 shows an example MOSFET SOA for an
the load switch. As mentioned, a fast device turn-on creates N-channel device. The outer boundaries of the safe
an inrush current. A softer turn-on reduces this current spike. operating area are determined by: the RDS(on) at maximum
However, caution must be taken when slowing down the junction temperature, the maximum drain current IDM, and
MOSFET turn-on. the rated breakdown voltage VDSS of the device. IDM is
Figure 10 shows a standard load switch datasheet transfer limited by the package, source wires, gate wires and die
curve. Drain current versus gate-to-source voltage is plotted characteristics.
at three different temperatures.

Figure 11. Example MOSFET SOA

Figure 10. Example Transfer Curve for a Load Switch
The basic power and current equations used to generate
All three temperature curves will intersect at a specific the SOA curve are:
VGS. This point is known as the inflection point. For a VGS PD PD
above the inflection point, RDS(on) increases as temperature V DS + or ID + (eq. 12)
increases. Thus, as the device heats up, cells that are carrying ID V DS

Ǹ
higher current will become more resistive and current will RD
be shared with cells carrying lower current. This MOSFET ID + (eq. 13)
property creates a uniform current sharing across all the R DS(on), MAX@TJMAX
cells. Below the inflection point, the MOSFET behaves First, the outer boundaries of the SOA are drawn: the
more like a bipolar transistor. As the device heats up, a cell maximum ID and VDS lines. Next, the RDS(on) boundary is
with higher current than the surrounding cells will continue drawn by using Equations 12 and 13 to determine the end
to take more current. If the device remains within this points, and the slope of the RDS(on) boundary line is:
transition region for too long, thermal runaway can occur.
RD
The load switch should be operated with a VGS above the
inflection point to ensure proper device function. The R DS(on), MAX@TJMAX
threshold voltage for the example device shown in Figure 10 The DC line is determined by the maximum continuous
is around 0.8 V. The inflection point occurs around 1.75 V. power the device can dissipate. The continuous power
For the example device, it is recommended to operate at dissipation is specified in the device datasheet. The DC line
a VGS of 1.8 V or higher. intersects the outer SOA boundaries in two places: at the
Safe Operating Area RDS(on) limit and at the VDS limit. Additional lines are
The Safe Operating Area (SOA) defines the safe operating plotted for a single pulse of 10 ms, 1 ms, 100 ms and 10 ms
conditions of the load switch. Operation outside of this duration. The safe operation region is located within the
region can degrade the performance, reliability and lifetime

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 AND9093/D

outer IDMAX and VDSMAX limits, and underneath the calculated to be 0.03 A. The second end-point is where the
RDS(on), DC and single pulse lines. DC line intersects the RDS(on) boundary. Therefore, the
The example MOSFET device from Figure 11 has the current can be calculated using Equation 13 and then
following datasheet specifications: plugging the calculated drain current into Equation 12 to
determine the corresponding voltage. For this example
Table 2. EXAMPLE MOSFET DATASHEET SPECS MOSFET, the DC line intersects the RDS(ON) boundary at
Datasheet Parameter Datasheet Value 0.18 V and 5.5 A. The calculated VDS and ID values can be
BVDSS 30 V
verified with Figure 11.
The single-pulse lines are calculated using the same
PD,CONTINUOUS 1W
methodology and equations as for the DC line, but using the
ID,MAX 45 A power dissipation for a single pulse of: 10 ms, 1 ms, 100 ms
RDS(ON)@TJMAX 33.5 mW and 10 ms.

ON Semiconductor Load Switches

The RDS(on) line for the Figure 11 example MOSFET can
ON Semiconductor has a large portfolio of P-channel and
be drawn using equations 12, 13 and the values presented in
N-channel load switches in a wide variety of packages.
Table 2. The first end-point is located at a VDS of 0.1 V, and
ON Semiconductor load switches are offered in the
the second end point is located at the ID limit of 45 A.
following configurations: single, dual, and complementary.
Similarly, the DC line can be drawn using Equations 12
Table 3 lists just a few of the vast number of load switches
and 13 to calculate the end points. The first DC line
that are currently available from ON Semiconductor. For
end-point is at a VDS of 30 V. Using Equation 12 and the PD
a complete product list please visit www.onsemi.com.
value presented in Table 2, the current at 30 VDS is

Table 3. ON SEMICONDUCTOR LOAD SWITCHES

MAX RDS(on)
(W)

Dimension VDS VGS VGS VGS VGS VGS

Package (mm) Part Number Configuration Pol (V) (V) ID (A) 4.5 V 2.5 V 1.8 V 1.5 V

XLLGA−3 0.6 x 0.6 x 0.4 NTNS3A91PZ** Single P −20 ±8 0.214 1.6 2.4 3.3 4.5

NTNS3190NZ** Single N −20 ±8 0.229 1.4 1.9 2.7 4.3

SOT−883 1.0 x 0.6 x 0.4 NTNS3A65PZ** Single P −20 ±8 0.235 1.6 2.4 3.3 4.5

NTNS3164NZ** Single N −20 ±8 0.245 1.5 2.0 4.0 6.8

1.0 x 1.0 x 0.5 NTUD3170NZ Dual N 20 ±8 0.22 1.5 2.0 3.0 4.5

SOT−963 NTUD3169CZ Complimentary N −20 ±8 0.22 1.5 2.0 3.0 4.5

P 20 ±8 0.25 5.0 6.0 7.0 10.0

SOT−723 1.2 x 1.2 x 0.5 NTK3139P** Single P −20 ±6 0.78 0.48 0.67 0.95 2.2

NTK3134N** Single N 20 ±6 0.89 0.35 0.45 0.65 1.2

NTLUS3A18PZ** Single P −20 ±8 8.2 0.018 0.028 0.050 0.090

UDFN 2.0 x 2.0 x 0.55
NTLUS3A39PZ** Single P 20 ±8 5.2 0.039 0.050 0.081 0.147

WDFN 3.3 x 3.3 x 0.8 NTTFS3A08PZ** Single P 20 ±8 14 0.0067 0.0090 −− −−

** New Products in Development. Samples Available Upon Request.

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 AND9093/D

REFERENCES

[1] C. S. Mitter. “Active Inrush Current Limiting Using [3] Q. Deng. “A Primer on High-Side FET Load
MOSFETS.” Application Note # AN1542. Motorola. Switches. EE Times, May 2007.
[2] P. H. Wilson. “Controlling ‘Inrush’ Current for Load
Switches in Battery Power Applications.” EE Times
Asia, July 2001.

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