Bd9576muf C e

Datasheet
Power Management IC
For Automotive R-Car Series
BD9576MUF-C
General Description Key Specifications
BD9576MUF-C is a Power Management Integrated  Input Voltage Range: 3.0 V to 3.6 V
Circuit (PMIC) designed specifically for use on R-Car  VOUT1 (VD50) Output Voltage: 5 V (Typ)
series processor for In-Vehicle Infotainment (IVI) Systems,  VOUT1 (VD50) Output Current: 0.2 A (Max)
Instrument Cluster Panel and Advanced Driver  VOUT2 (VD18) Output Voltage: 1.8 V (Typ)
Assistance Systems (ADAS).  VOUT2 (VD18) Output Current: 1.0 A (Max)
 VOUT3 (DDR) Output Voltage:
Features 1.35 V (Typ, DDR3L)(Note 2)
 AEC-Q100 Qualified(Note 1) 1.50 V (Typ, DDR3)(Note 2)
 Safety mechanism is implemented to support  VOUT3 (DDR) Output Current: 2.0 A (Max)
functional safety (ASIL-B)  VOUT4 (VD10A, VD10B) Output Voltage: 1.03 V (Typ)
 Customizable Power Up / Down Sequence and State  VOUT4 (VD10A, VD10B) Output Current: 5.2 A (Max)
Control  VOUTL1 (VL25) Output Voltage: 2.5 V (Typ)
 Fewer External Components Count / Compact Size  VOUTL1 (VL25) Output Current: 0.15 A (Max)
Power Control Logic with Processor Interface and  VOUTS1 (VS33) Output Voltage: VIN7 = 3.3 V (Typ)
Event Detection  VOUTS1 (VS33) Output Current: 0.3 A (Max)
 Built-in UVLO, SCP, OVP, UVP, OCP and TSD  Operating Ambient Temperature Range:
Protection -40 °C to +125 °C
 Built-in OVD,UVD,TW (Note 2) Select Voltage by the DDR_SEL pin.
 Built-in Self Diagnosis
 Built-in Mutual Monitoring Functions of VREF Special Characteristics
 Built-in Mutual Monitoring Functions of OSC  Output Voltage:
(Note 1) Grade1 (VOUT1 (VD50), VOUT2 (VD18), VOUT3 (DDR),
VOUT4 (VD10A, VD10B), VOUTL1 (VL25),
Applications VOUTS1 (VS33))
 In-Vehicle Infotainment (IVI) Systems
 Instrument Cluster Panel Package W (Typ) x D (Typ) x H (Max)
 Advanced Driver Assistance Systems (ADAS) VQFN56FV8080 8.0 mm x 8.0 mm x 1.0 mm
(Wettable Flank)
Enlarged View
VQFN56FV8080
Wettable Flank Package
〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays
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© 2019 ROHM Co., Ltd. All rights reserved. TSZ02201-0A1A0AM00350-1-2
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BD9576MUF-C
Block Diagram
VREF OVD/UVD
L_VOUT1
VREF
Boost Converter VD50
OSC1
OSC2
L_VOUT2
TSD
Buck Converter VD18
C_VOUT2
TW
I2C
L_VOUT3
Buck Converter DDR

C_VOUT3
Control
L_VOUT4A
Buck Converter VD10A

C_VOUT4
ERROR L_VOUT4B
Buck Converter VD10B
WDT
LDO25 VL25
RESET
TEST
SW VS33
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© 2019 ROHM Co., Ltd. All rights reserved. 2/90
TSZ22111 • 15 • 001 02.Oct.2020 Rev.001
BD9576MUF-C
Pin Configuration
(TOP VIEW)
TSZ22111 • 15 • 001 02.Oct.2020 Rev.001
BD9576MUF-C
Pin Description
Pin No. Pin Name I/O Function
1 PGND2 - Power GND for VOUT2

High side MOSFET source / Low side MOSFET sink pin for
3 SW2 O VOUT2
4 SW2 O VOUT2
5 VIN2 I (POWER) Power supply for VOUT2
7 FB2 I Feedback pin for VOUT2
VOUT3 Voltage is changed by DDR_SEL.
8 DDR_SEL I DDR_SEL = H: 1.5 V, DDR_SEL = L: 1.35 V
(internal 100 kΩ pull down)
11 SW3 O VOUT3
12 SW3 O VOUT3
16 AGND - GND
17 WDO O (O.D.)(Note 1) Watchdog Timer error signal.
18 RSTB I Power On (internal 100 kΩ pull down)
19 PRESETB O (O.D.)(Note 1) Reset signal for SoC
20 SYNC I External sync for DCDC (internal 100 kΩ pull down)
21 INTB O (O.D.)(Note 1) Interrupt signal
Clock signal input as Watch Dog Timer function.
22 WDI I (internal 100 kΩ pull down)
Watch Dog Timer function setting ON/OFF.
23 WDEN I (internal 100 kΩ pull down)
24 SDA I/O (O.D.)(Note 1) I2C Data
25 SCL I/O (O.D.)(Note 1) I2C CLK
26 PGD O (O.D.)(Note 1) POWER Good Function
30 SW4 O High side MOSFET source / Low side MOSFET sink pin for
VOUT4
VOUT4
Adjust shutdown timing of VD18. Multi-threshold PIN.
34 SEQCNT[1] I (internal 2 MΩ pull down)
35 VOUT1_EN I Enable control pin for VOUT1 (internal 100 kΩ pull down)
36 TEST I Connected to AGND. TEST MODE PIN
Adjust start and OFF timing. Multi-threshold PIN.
37 SEQCNT[0] I (internal 2 MΩ pull down)
(Note 1) O.D. = Open Drain
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BD9576MUF-C
Pin Description – continued

Pin No. Pin Name I/O Function
VOUT4
41 SW5 O VOUT4
44 VOUTL1 O Output of VOUTL1
45 VIN6 I (POWER) Power supply for VOUTL1
46 VIN7 I (POWER) Power supply for VOUTS1
47 VOUTS1 O SW Output
48 GATECNT O Control Gate of External PMOS SW. When use External PMOS.
If External PMOS SW is not used, please connect to GND.
49 VFIL O Output of filtering VIN.
50 VIN I (POWER) Power supply for PMIC
53 VLSO O Output of LDSW
54 VOUT1 O Output of VOUT1
55 SW1 O VOUT1
GND
- EXP-PAD (CORNER) - (EXP-PAD (CORNER) short-circuit with EXP-PAD (CENTER)
into the Package)
- EXP-PAD (CENTER) - GND (Connect to common GND of PCB)
TSZ22111 • 15 • 001 02.Oct.2020 Rev.001
BD9576MUF-C Datasheet
Physical Dimension and Packaging Infomation

Package Name VQFN56FV8080
TSZ22111 • 15 • 001 02.Oct.2020 Rev.001
BD9576MUF-C
Footprint Dimension
Package Name VQFN56FV8080
TSZ22111 • 15 • 001 02.Oct.2020 Rev.001
BD9576MUF-C
Ordering Information
B D 9 5 7 6 M U F - CE 2
Part Number Package Product Rank

MUF: VQFN56FV8080 C: for Automotive
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
VQFN56FV8080 (TOP VIEW)
Part Number Marking

BD9576MUF
LOT Number
Pin 1 Mark
TSZ22111 • 15 • 001 02.Oct.2020 Rev.001
BD9576MUF-C
Contents
General Description ........................................................................................................................................................................ 1
Features.......................................................................................................................................................................................... 1
Applications .................................................................................................................................................................................... 1
Key Specifications .......................................................................................................................................................................... 1
Special Characteristics ................................................................................................................................................................... 1
Package .......................................................................................................................................................................................... 1
Block Diagram ................................................................................................................................................................................ 2
Pin Configuration ............................................................................................................................................................................ 3
Pin Description................................................................................................................................................................................ 4
Physical Dimension and Packaging Infomation .............................................................................................................................. 6
Footprint Dimension ........................................................................................................................................................................ 7
Ordering Information ....................................................................................................................................................................... 8
Marking Diagram ............................................................................................................................................................................ 8
Contents ......................................................................................................................................................................................... 9
1. Device Feature ................................................................................................................................................................... 13
Output Voltage Table ...................................................................................................................................................... 13
Signal Line Diagram for PMIC ........................................................................................................................................ 14
2. Application ......................................................................................................................................................................... 15
3. Electrical Characteristics .................................................................................................................................................... 17
Absolute Maximum Ratings ............................................................................................................................................ 17
Thermal Resistance........................................................................................................................................................ 18
Recommended Operating Conditions............................................................................................................................. 19
DC Characteristics.......................................................................................................................................................... 20
Protection Mode (Under Voltage Lock Out) .................................................................................................................... 25
Protection Mode (Thermal Shutdown) ............................................................................................................................ 25
Protection Mode (Thermal Warning) ............................................................................................................................... 25
Protection Mode ............................................................................................................................................................. 25
Mutual Monitor Function (VREF, OSC) ........................................................................................................................... 26
4. Function Description .......................................................................................................................................................... 27
Pin Control Function ....................................................................................................................................................... 27
4.1.1 VOUT1_EN Input .................................................................................................................................................... 27
4.1.2 RSTB Input .............................................................................................................................................................. 27
4.1.3 PIN Setting Judge Timing ........................................................................................................................................ 27
4.1.4 Output Power-ON/Power-OFF Sequence ............................................................................................................... 28
4.1.5 VOUT2 (VD18) Discharge Start Timing ................................................................................................................... 29
4.1.6 Countermeasures for Hang-Up ............................................................................................................................... 29
4.1.7 Interval Setting ........................................................................................................................................................ 30
4.1.8 Initializing Control Circuit ......................................................................................................................................... 30
4.1.9 VOUT1 Mode Setting .............................................................................................................................................. 31
4.1.10 State Machine ...................................................................................................................................................... 33
Whole Sequence Control................................................................................................................................................ 35
4.2.1 Whole Sequence (State Chart)................................................................................................................................ 35
4.2.2 General Sequence Description................................................................................................................................ 35
4.2.3 I2C Accessible State Condition ............................................................................................................................... 35
4.2.4 EEPROM Load Function and Internal OSC Stable Time ......................................................................................... 36
4.2.5 Self Diagnosis ......................................................................................................................................................... 36
4.2.6 Prevention of Repetition for Protection Error, EEPROM CRC Error, Self Diagnosis Error ...................................... 36
VOUT1/VOUTL1 Disable Setting without EEPROM ....................................................................................................... 37
VOUTS1 Disable Setting without EEPROM, Internal/External SW Mode Setting .......................................................... 38
I2C I/F............................................................................................................................................................................. 39
Interrupt Function ........................................................................................................................................................... 43
4.6.1 Interrupt Function Description ................................................................................................................................. 43
4.6.2 Interruption Factor ................................................................................................................................................... 44
Power Abnormality Monitoring Function (Protection Error Detection) ............................................................................. 47
SYNC Function ............................................................................................................................................................... 49
WDT Function................................................................................................................................................................. 50
5. Register Specification ........................................................................................................................................................ 53
Register Map .................................................................................................................................................................. 53
Register Description ....................................................................................................................................................... 54
5.2.1 Recognition Code Indicator ..................................................................................................................................... 54
5.2.2 FuSa Mode (Error Detection/Rectification Mode) .................................................................................................... 54
5.2.3 Shutdown Control .................................................................................................................................................... 55
5.2.4 Spread Spectrum Clock Generation Control for Internal OSC................................................................................. 55
5.2.5 SMRB Control using I2C Control (Software Manual Reset for PRESETB) ............................................................. 56
5.2.6 Watch Dog Timer setting ......................................................................................................................................... 56
5.2.7 Oscillator Enable in STANDBY State....................................................................................................................... 56
5.2.8 The PGD Pin Output Assert Condition Setting ........................................................................................................ 57
5.2.9 PMIC Internal Status ............................................................................................................................................... 57
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5.2.10 I2C FuSa Mode Error Bit Location ....................................................................................................................... 58

5.2.11 INTB Interruption Factor and Mask Condition ...................................................................................................... 59
5.2.12 POW Setting ........................................................................................................................................................ 64
5.2.13 VOUT Voltage Tune / OVD SET / UVD SET ........................................................................................................ 67
5.2.14 VOUTS1 OCW SET ............................................................................................................................................. 73
5.2.15 VOUTS1 OCP SET .............................................................................................................................................. 73
5.2.16 Diglitch time ......................................................................................................................................................... 74
6. Typical Performance Curves .............................................................................................................................................. 75
Line Regulation............................................................................................................................................................... 75
Load Regulation ............................................................................................................................................................. 77
Power Efficiency ............................................................................................................................................................. 79
Power ON Waveform ...................................................................................................................................................... 81
Power OFF Waveform .................................................................................................................................................... 83
Load Transient ................................................................................................................................................................ 85
7. Operational Notes .............................................................................................................................................................. 87
8. Revision History ................................................................................................................................................................. 90
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BD9576MUF-C
Table 1: Output Voltage Table of Each State ......................................................................................................................... 13

Table 2: Application circuit components list............................................................................................................................ 16
Table 3: Absolute Maximum Rating ....................................................................................................................................... 17
Table 4: Recommended Operating Conditions ...................................................................................................................... 19
Table 5: DC Characteristics (Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V) ............................................ 20
Table 6: Logic Characteristics (Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V) ......................................... 24
Table 7: Protection Mode (General) ....................................................................................................................................... 25
Table 8: Protection Mode (VD50, DDR, VD18, VD10) ........................................................................................................... 25
Table 9: Protection Mode (VL25) ........................................................................................................................................... 25
Table 10: Protection Mode (VS33) ......................................................................................................................................... 25
Table 11: SEQCNT[0] Operation Mode .................................................................................................................................. 30
Table 12: SEQCNT[1] Operation Mode.................................................................................................................................. 30
Table 13: Initializing Control Circuit ........................................................................................................................................ 30
Table 14: I2C accessible condition ........................................................................................................................................ 35
Table 15: Interruption at Primary Level .................................................................................................................................. 45
Table 16: Interruption at Secondary Level 2 .......................................................................................................................... 46
Table 17: WDT setting (NG_RATIO[1:0] = “00”) ..................................................................................................................... 51
Table 21: I2C I/F Register Map .............................................................................................................................................. 53
Table 22: PMIC Internal State ................................................................................................................................................ 57
Table 23: PON/POFF Trigger Signal ...................................................................................................................................... 65
Table 24: PON/POFF Interval ................................................................................................................................................ 66
Table 25: VOUT1 Tuning Voltage .......................................................................................................................................... 67
Table 26: VOUT1 OVD Voltage ............................................................................................................................................. 67
Table 27: VOUT1 UVD Voltage .............................................................................................................................................. 68
Table 37: VOUTL1 Tuning Voltage ........................................................................................................................................ 72
Table 38: VOUTL1 OVD Voltage ........................................................................................................................................... 72
Table 39: VOUTL1 UVD Voltage ............................................................................................................................................ 72
Table 40: VOUTS1 OCW Current(Internal) and Voltage(Exernal) ......................................................................................... 73
Table 41: VOUTS1 OCP Current(Internal) and Voltage(Exernal) .......................................................................................... 73
Figure 1. An Example of Signal Line Diagram for PMIC ........................................................................................................ 14

Figure 2. Application Circuit ................................................................................................................................................... 15
Figure 3. Application Circuit (External MOS) ......................................................................................................................... 15
Figure 4. RSTB Operation Timing Chart ................................................................................................................................ 27
Figure 5. Output Power-ON Operation Timing Chart (Default Register Setting) .................................................................... 28
Figure 6. Output Power-OFF Operation Timing Chart (Default Register Setting) .................................................................. 28
Figure 7. VOUT2 Discharge Start Timing .............................................................................................................................. 29
Figure 8. SEQCNT Circuit ..................................................................................................................................................... 30
Figure 9. Whole Sequence1 (Mode B)................................................................................................................................... 31
Figure 10. Whole Sequence2 (Mode B) ................................................................................................................................. 31
Figure 11. Error Case (Mode B) ............................................................................................................................................. 32
Figure 12. Main State Machine .............................................................................................................................................. 33
Figure 13. Sub State Machine ............................................................................................................................................... 34
Figure 14. Whole Sequence (State Chart) ............................................................................................................................. 35
Figure 15. Sequence at Protection Error Occurrence (Timing Chart) .................................................................................... 36
Figure 16. VOUT1 Disable Setting without EEPROM ............................................................................................................ 37
Figure 17. VOUTL1 Disable Setting without EEPROM .......................................................................................................... 37
Figure 18. VOUT1, VOUTL1 OFF Circuit .............................................................................................................................. 37
Figure 19. VOUTS1 Disable Setting without EEPROM ......................................................................................................... 38
Figure 20. VOUTS1 Internal/External Setting ........................................................................................................................ 38
Figure 21. VOUTS1 OFF Circuit and SW Mode Selection..................................................................................................... 38
Figure 22. I2C Basic Protocol ................................................................................................................................................ 39
Figure 23. I2C Protocol (Each Access Mode) ........................................................................................................................ 39
Figure 24. I2C Protocol (FuSa Mode) .................................................................................................................................... 40
Figure 25. I2C Data Format (FuSa Mode type2 = ECC at Calculation) ................................................................................. 42
Figure 26. Error Detection Judgement by ECC Calculation ................................................................................................... 42
Figure 27. Error Correction Calculation ................................................................................................................................. 42
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BD9576MUF-C
Figure 28. Interruption Factor/Mask/Request ........................................................................................................................ 43

Figure 29. Interrupt Function Description............................................................................................................................... 43
Figure 30. System Diagram of Interruption Function ............................................................................................................. 44
Figure 31. Power Abnormality Monitoring Circuit ................................................................................................................... 47
Figure 32. Timing Chart when Protection Error Factor Occur 1 ............................................................................................. 47
Figure 33. Timing Chart when Protection Error Factor Occur 2 ............................................................................................. 48
Figure 34. Timing Chart when Protection Detection Factor Occur ......................................................................................... 48
Figure 35. WDT Function ....................................................................................................................................................... 50
Figure 36. WDT NG RATIO ................................................................................................................................................... 50
Figure 37. WDT Detection Time when NG_RATIO[1:0] = “00” ............................................................................................... 52
Figure 38. WDT Detection Time when NG_RATIO[1:0] = “01” ............................................................................................... 52
Figure 39. Modulation Waveform of SSCG ............................................................................................................................ 55
Figure 40. VOUT1 Output Voltage vs VIN ............................................................................................................................. 75
Figure 42. VOUT3 Output Voltage vs VIN (VOUT3 = 1.35 V Setting).................................................................................... 75
Figure 43. VOUT3 Output Voltage vs VIN (VOUT3 = 1.5 V Setting)...................................................................................... 75
Figure 45. VOUTL1 Output Voltage vs VIN ........................................................................................................................... 76
Figure 46. VOUT1 Output Voltage vs IOUT ........................................................................................................................... 77
Figure 48. VOUT3 Output Voltage vs IOUT (VOUT3 = 1.35 V Setting) ................................................................................. 77
Figure 49. VOUT3 Output Voltage vs IOUT (VOUT3 = 1.5 V Setting) ................................................................................... 77
Figure 51. VOUTL1 Output Voltage vs IOUT ......................................................................................................................... 78
Figure 52. VOUT1 Power Efficiency vs IOUT ........................................................................................................................ 79
Figure 54. VOUT3 Power Efficiency vs IOUT (VOUT3 = 1.35 V Setting) .............................................................................. 79
Figure 55. VOUT3 Power Efficiency vs IOUT (VOUT3 = 1.5 V Setting) ................................................................................ 79
Figure 57. VOUT1 Power ON Waveform ............................................................................................................................... 81
Figure 59. VOUT3 Power ON Waveform (VOUT3 = 1.35 V Setting) ..................................................................................... 81
Figure 60. VOUT3 Power ON Waveform (VOUT3 = 1.5 V Setting) ....................................................................................... 81
Figure 62. VOUTL1 Power ON Waveform ............................................................................................................................. 82
Figure 63. VOUTS1 Power ON Waveform............................................................................................................................. 82
Figure 64. VOUT1 Power OFF Waveform ............................................................................................................................. 83
Figure 66. VOUT3 Power OFF Waveform (VOUT3 = 1.35 V Setting) ................................................................................... 83
Figure 67. VOUT3 Power OFF Waveform (VOUT3 = 1.5 V Setting) ..................................................................................... 83
Figure 69. VOUTL1 Power OFF Waveform ........................................................................................................................... 84
Figure 70. VOUTS1 Power OFF Waveform ........................................................................................................................... 84
Figure 71. VOUT1 Load Transient (IOUT = 0 A to 100 mA (SR = 100 mA/µs)) ..................................................................... 85
Figure 72. VOUT2 Load Transient (IOUT = 0 A to 0.5 A (SR = 1 A/µs)) ................................................................................. 85
Figure 73. VOUT3 Load Transient (VOUT3 = 1.35 V Setting, IOUT = 0 A to 1 A (SR = 1 A/µs)) ........................................... 85
Figure 74. VOUT3 Load Transient (VOUT3 = 1.5 V Setting, IOUT = 0 A to 1 A (SR = 1 A/µs)) ............................................. 85
Figure 75. VOUT4 Load Transient (IOUT = 0 A to 2.05 A (SR = 1 A/µs)) ............................................................................... 86
Figure 76. VOUTL1 Load Transient (IOUT = 0 A to 75 mA (SR = 100 mA/µs)....................................................................... 86
Figure 77. Example of Monolithic IC Structure ...................................................................................................................... 88
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BD9576MUF-C
1. Device Feature
Output Voltage Table
Table 1: Output Voltage Table of Each State

Channel Rail name Output [V] Iomax [A] STANDBY ACTIVE
VD50 VOUT1 5.0 0.2 OFF ON
VD18 VOUT2 1.8 1.0 OFF ON

1.35 (DDR3L)
DDR VOUT3 1.50 (DDR3) 2.0 OFF ON
VD10A VOUT4 1.03 5.2 OFF ON
VD10B
VL25 VOUTL1 2.5 0.15 OFF ON
VS33 VOUTS1 VIN7 0.3 OFF ON

(Analog Switch)
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BD9576MUF-C
1. Device Feature – continued
Signal Line Diagram for PMIC
Bidirectional Voltage Level

Translator
BD9576MUF-C R-car V3M
I2C_SCL
I2C_SDA
INTB (Open Drain)
PRESETB (Open Drain)
PGD (Open Drain)
DDR_SEL
VIN or GND
100 kΩ
SYNC
GND (When not in use)
WDI
100 kΩ GND (When not in use)
WDEN GND (When not in use)
100 kΩ
WDO (Open Drain)
100 kΩ
SEQCNT[1:0] GND or VMID_L
or VMID_H or VIN
2 MΩ
RSTB
System Controller
100 kΩ
VOUT1_EN
100 kΩ
Figure 1. An Example of Signal Line Diagram for PMIC
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BD9576MUF-C
2. Application
VREF OVD/UVD
L_VOUT1
LOAD
VREF
Boost Converter VD50
OSC1
OSC2
L_VOUT2
TSD LOAD
Buck Converter VD18
C_VOUT2
TW
I2C
L_VOUT3
LOAD
Buck Converter DDR
C_VOUT3
Control
L_VOUT4A
LOAD
Buck Converter VD10A C_VOUT4
ERROR L_VOUT4B
Buck Converter VD10B
WDT
LDO25 VL25 LOAD

RESET
TEST
SW VS33 LOAD
Figure 2. Application Circuit
Figure 3 shows the case of external FET for VOUTS1.

When VOUTS1 uses it in 0.3 A or more, use it with external FET.
VIN
VIN
VIN7
C_VIN R_M
F_PMOS
SW VS33
VOUTS1
C_VOUTS1
GATECNT
Figure 3. Application Circuit (External MOS)
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BD9576MUF-C
2. Application - continued
Table 2: Application Circuit Components List

Value
Parts Name Unit Vendor Parts Number Size (mm)
Min(Note 1) Typ Max
C_VINx - 10 - μF MURATA GCM21BR70J106KE22 2012

C_VFIL - 1 - μF MURATA GCM188R71C105KA64 1608
C_LSO - 10 x 2 - μF MURATA GCM21BR70J106KE22 2012
C_VOUT1 - 22 - μF MURATA GCM31CR71A226KE02 3216
C_LOAD1 22 - - μF MURATA GCM31CR71A226KE02 3216
L_VOUT1 - 2.2 - μH TDK TFM252012ALMA2R2MTAA 2520
L_VOUT2 - 0.22 - μH TDK TFM252012ALMAR22MTAA 2520
- 22 - μF MURATA GCM31CR70J226KE26 3216
C_VOUT2
- or 22 - μF TDK CGA4J1X7T0J226M 2012
22 x 2 - - μF MURATA GCM31CR70J226KE26 3216
C_LOAD2
or 22 x 2 - - μF TDK CGA4J1X7T0J226M 2012
L_VOUT3 - 0.33 - μH TDK TFM252012ALMAR33MTAA 2520
- 22 - μF MURATA GCM31CR70J226KE26 3216
C_VOUT3
- or 22 - μF TDK CGA4J1X7T0J226M 2012
22 x 3 - - μF MURATA GCM31CR70J226KE26 3216
C_LOAD3
L_VOUT4A - 0.22 - μH TDK TFM252012ALMAR22MTAA 2520
L_VOUT4B - 0.22 - μH TDK TFM252012ALMAR22MTAA 2520
- 47 x 2 - μF MURATA GCM32ER70J476KE19 3225
C_VOUT4
- or 22 x 4 - μF TDK CGA4J1X7T0J226M 2012
47 x 4 - - μF MURATA GCM32ER70J476KE19 3225
C_LOAD4
C_VOUTL1 - 10 - μF MURATA GCM21BR70J106KE22 2012
C_LOADL1 1 - 300 μF - - -
C_VOUTS1 - 10 - μF MURATA GCM21BR70J106KE22 2012
C_LOADS1 1 - 300 μF - - -
F_PMOS - - - - ROHM RQ1A070ZPHZG TSMT8
R_M - 100 - kΩ ROHM MCR01MZPF1003 1005
R_PGD - 10 - kΩ ROHM MCR01MZPF1002 1005
R_EEROR - 10 - kΩ ROHM MCR01MZPF1002 1005
R_RESET - 10 - kΩ ROHM MCR01MZPF1002 1005
R_SDA - 1 - kΩ ROHM MCR01MZPF1001 1005
R_SCL - 1 - kΩ ROHM MCR01MZPF1001 1005
R_WDO - 10 - kΩ ROHM MCR01MZPF1002 1005
(Note 1) Please set in consideration of temperature properties and DC bias properties not to become less than the minimum.
Please consider it based on enough evaluations with the actual model.
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BD9576MUF-C
3. Electrical Characteristics
Absolute Maximum Ratings
Table 3: Absolute Maximum Ratings

Parameter Symbol Rating Unit
Input Voltage 1 VIN, VIN1, VIN2, VIN3, VIN4, VIN5, VIN6, VIN7 -0.3 to +7.0 V
Input Voltage 2 FB1, FB2, FB3, FB4 -0.3 to +7.0 V
Output Voltage 1 VFIL -0.3 to VIN+0.3 V
Output Voltage 2 VLSO -0.3 to VIN1+0.3 V
Output Voltage 3 VOUT1 -0.3 to +7.0 V
Output Voltage 4 VOUTL1, VOUTS1 -0.3 to VINx+0.3 V
Output Voltage 5 GATECNT -0.3 to +7.0 V
SW to GND Voltage 1 SW2, SW3, SW4, SW5 -0.3 to VINx+0.3 V
SW to GND Voltage 2 SW1 -0.3 to +10.0 V
Logic Input Voltage 1 RSTB, SDA, SCL -0.3 to +7.0 V
Logic Input Voltage 2 SYNC, WDI, WDEN, VOUT1_EN, DDR_SEL -0.3 to VIN+0.3 V
Logic Input Voltage 3 SEQCNT[0], SEQCNT[1] -0.3 to VIN+0.3 V
Logic Output Voltage 1 INTB, PGD, WDO -0.3 to +7.0 V
Logic Output Voltage 2 PRESETB -0.3 to VIN+0.3 V
Logic Output Pin Current Low 1 PRESETB, INTB, PGD, WDO -3.0 mA
Logic Output Pin Current Low 2 SDA, SCL -20.0 mA
Storage Temperature Range Tstg -55 to +150(Note 1) °C

Maximum Junction Tjmax 150 °C
Temperature
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open
circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case
the IC is operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of
the properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration
by increasing board size and copper area so as not to exceed the maximum junction temperature rating.
(Note 1) Operation is not guaranteed.
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3. Electrical Characteristics - continued
Thermal Resistance(Note 1)
Thermal Resistance (Typ)
Parameter Symbol Unit
1s(Note 3) 2s2p(Note 4)
VQFN56FV8080
Junction to Ambient θJA 59.8 22.2 °C/W
Junction to Top Characterization Parameter(Note 2) ΨJT 4.0 2.0 °C/W
(Note 1) Based on JESD51-2A (Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Material Board Size
Measurement Board
Single FR-4 114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern Thickness
Footprints and Traces 70 μm
Layer Number of Thermal Via(Note 5)

Material Board Size
Measurement Board Pitch Diameter
4 Layers FR-4 114.3 mm x 76.2 mm x 1.6 mmt 1.20 mm Φ0.30 mm
Top 2 Internal Layers Bottom
Copper Pattern Thickness Copper Pattern Thickness Copper Pattern Thickness
Footprints and Traces 70 μm 74.2 mm x 74.2 mm 35 μm 74.2 mm x 74.2 mm 70 μm
(Note 5) This thermal via connects with the copper pattern of all layers.
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Recommended Operating Conditions
Table 4: Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit
Power Supply Voltage VIN 3.0 3.3 3.6 V
Power Supply Voltage 1 VIN1 3.0 3.3 3.6 V

RSTB, SYNC, WDI,
Logic Input Voltage Low 1 WDEN, VOUT1_EN, DDR_SEL -0.3 - +0.5 V
Logic Input Voltage High 1 RSTB, SYNC, WDI, 1.2 - VIN + 0.3 V
WDEN, VOUT1_EN, DDR_SEL
Logic Input Voltage Low 2 SCL, SDA -0.3 - +0.5 V
Logic Input Voltage High 2 SCL, SDA 1.2 - VIN + 0.3 V
Input Voltage Low 3 SEQCNT[0], SEQCNT[1] -0.3 - VIN x 0.1 V
Input Voltage Middle Low 3 SEQCNT[0], SEQCNT[1] VIN x 0.2 - VIN x 0.5 V
Input Voltage Middle High 3 SEQCNT[0], SEQCNT[1] VIN x 0.6 - VIN x 0.8 V
Input Voltage High 3 SEQCNT[0], SEQCNT[1] VIN x 0.9 - VIN + 0.3 V
SYNC Input Frequency Range SYNC 1.8 2.0 2.2 MHz
SYNC Input Pulse Duty Range SYNC 45 50 55 %

Operating Ambient
Temperature Ta -40 25 +125 °C
Operating Junction Tj -40 25 +150 °C
Temperature
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DC Characteristics
Table 5: DC Characteristics (Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V)
Standard Value
Parameter Symbol Unit Conditions
Min Typ Max
[General]
STANDBY
Bias Current 1 ICC_1 - 0.5 - mA (VIN, VIN1 to VIN7
total)
ACTIVE
Bias Current 2 ICC_2 - 6 12 mA (VIN, VIN1 to VIN7
total, Switching stop)
VFIL UVLO Threshold Voltage VFIL_UVLO 2.7 2.8 2.9 V VFIL: Sweep down
VFIL UVLO Hysteresis
dVFIL_UVLO - 0.1 - V VFIL: Sweep up
Voltage
VIN1 to VIN7 UVP VIN1 to VIN7: Sweep
VIN1-7_UVP 2.6 2.7 2.8 V
Threshold Voltage down
VIN1 to VIN7 UVP Hysteresis VIN1 to VIN7: Sweep
dVIN1-7_UVP - 0.1 - V
Voltage up
VFIL Resistance R_VFIL - 10 - Ω -
[VOUT1 (VD50)]
Output Voltage VOUT1 4.91 5.00 5.09 V Io = 0 mA
Switching Frequency Fosc_VOUT1 1.912 2.250 2.588 MHz SSCG = OFF
Synchronization Frequency Fsync_VOUT1 1.8 2.0 2.2 MHz SYNC = 2 MHz
VIN to VOUT1
Soft-Start Time Rate Tssr_VOUT1 - 4.2 - V/ms (DCDC converter
Soft-start time rate)
0 V to 5 V (Include
VOUT1 Soft Start Time Tss_VOUT1 - 1.57 - ms
LDSW on time)
Upper-Side ON Resistance Ronh_VOUT1 - 250 500 mΩ -
Lower-Side ON Resistance Rohl_VOUT1 - 200 400 mΩ -
Detect a peak current
Over Current Protection OCP_VOUT1 1.2 - - A
flowing in Low-side FET
VOUT1 VOUT1 VOUT1
SCP Detecting Voltage SCP_VOUT1 V -
x 0.7 x 0.8 x 0.9
VOUT1 VOUT1 VOUT1
OVP Detecting Voltage OVP_VOUT1 V -
x 1.13 x 1.20 x 1.27
Load Switch ON Resistance Ron_LS - 200 400 mΩ -
Load Switch
OCP_LDSW 2.2 - - A -
Over Current Protection
Compared to VOUT1
OVD Detecting Voltage OVD_VOUT1 273 342 410 mV
voltage level
Compared to VOUT1
UVD Detecting Voltage UVD_VOUT1 -410 -342 -273 mV
voltage level
Output Discharge Resistance Rdis_VOUT1 - 25 50 Ω VOUT1 Discharge
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3.4 DC Characteristics – continued

(Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V)
Standard Value
Min Typ Max
[VOUT2 (VD18)]
Soft-Start Time Rate Tss_VOUT2 - 1.0 - V/ms -
Detect a peak current
Over Current Protection OCP_VOUT2 2.5 - - A
flowing in High-side FET
VOUT2 VOUT2 VOUT2
x 0.73 x 0.80 x 0.87
VOUT2 VOUT2 VOUT2
x 1.13 x 1.20 x 1.27
Compared to VOUT2
OVD Detecting Voltage OVD_VOUT2 45.1 56.0 67.6 mV
voltage level
Compared to VOUT2
UVD Detecting Voltage UVD_VOUT2 -67.6 -56.0 -45.1 mV
voltage level
Output Discharge Resistance Rdis_VOUT2 20 55 150 Ω FB2 Discharge
[VOUT3 (DDR)]
Io = 0 mA
Output Voltage 1 VOUT3_1 1.3257 1.3500 1.3743 V
DDR_SEL = L
Io = 0 mA
Output Voltage 2 VOUT3_2 1.473 1.500 1.527 V
DDR_SEL = H
Detect a peak
Over Current Protection OCP_VOUT3 3.6 - - A current flowing in
High-side FET
VOUT3 VOUT3 VOUT3
x 0.73 x 0.80 x 0.87
VOUT3 VOUT3 VOUT3
OVP Detecting Voltage OVP1_VOUT3 V -
x 1.13 x 1.20 x 1.27
DDR_SEL = L
OVD Detecting Voltage 1 OVD1_VOUT3 50.5 63.0 75.7 mV Compared to VOUT3
voltage level
DDR_SEL = H
OVD Detecting Voltage 2 OVD2_VOUT3 32 40 48 mV Compared to VOUT3
voltage level
DDR_SEL = L
UVD Detecting Voltage 1 UVD1_VOUT3 -42.7 -36.0 -28.5 mV Compared to VOUT3
voltage level
DDR_SEL = H
UVD Detecting Voltage 2 UVD2_VOUT3 -48 -40 -32 mV Compared to VOUT3
voltage level
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Standard Value
Min Typ Max
[VOUT4 (VD10A, VD10B)]
Ronh_VOUT4A
Upper-Side ON Resistance - 100 200 mΩ -
Ronh_VOUT4B
Rohl_VOUT4A
Lower-Side ON Resistance - 70 140 mΩ -
Rohl_VOUT4B
OCP_VOUT4A Detect a peak current
Over Current Protection 3.6 - - A
OCP_VOUT4B flowing in High-side FET
VOUT4 VOUT4 VOUT4
x 0.73 x 0.80 x 0.87
VOUT4 VOUT4 VOUT4
x 1.07 x 1.14 x 1.21
Compared to VOUT4
OVD Detecting Voltage OVD_VOUT4 21.0 26.0 31.5 mV
voltage level
Compared to VOUT4
UVD Detecting Voltage UVD_VOUT4 -31.5 -26.0 -21.0 mV
voltage level
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Standard Value
Min Typ Max
[VOUTL1 (VL25)]
Output Voltage VOUTL1 2.455 2.500 2.545 V Io = 0 mA
Soft-Start Time Rate Tss_VOUTL1 - 1.0 - V/ms -
ON Resistance Ron_VOUTL1 - - 2 Ω Ids = 50 mA
Over Current Protection OCP_VOUTL1 350 - - mA -
VOUTL1 VOUTL1 VOUTL1
SCP Detecting Voltage SCP_VOUTL1 V -
x 0.73 x 0.80 x 0.87
VOUTL1 VOUTL1 VOUTL1
OVP Detecting Voltage OVP_VOUTL1 V -
x 1.13 x 1.20 x 1.27
Compared to
OVD Detecting Voltage OVD_VOUTL1 103 129 155 mV VOUTL1 voltage
level
Compared to
UVD Detecting Voltage UVD_VOUTL1 -155 -129 -103 mV VOUTL1 voltage
level
Output Discharge Resistance Rdis_VOUTL1 75 150 300 Ω VOUTL1 Discharge
[VOUTS1 (VS33)]
Soft-Start Time Rate Tss_VOUTS1 - 1 - V/ms -
SW OCW Detecting Current
OCW_VOUTS1_IN 390 - - mA -
(Internal)
SW OCP-OCW difference ΔV =
ΔOCW_
Detecting Voltage 1 20 50 mV OCP_VOUTS1_EX -
VOUTS1_EX
(External) OCW_VOUTS1_EX
Output Discharge Resistance Rdis_VOUTS1 15 30 50 Ω VOUTS1 Discharge
SW ON Resistance Ron_VOUTS1 100 250 450 mΩ -
GATECNT ON Resistance Ron_GATECNT 10 25 50 Ω GATECNT = 0.5 V
GATECNT
Rup_GATECNT - 2 - MΩ -
Pull Up Resistance
SW OCP Detecting Current
OCP_VOUTS1_IN 510 - - mA -
(Internal)
SW OCP Detecting Voltage ΔV =
OCP_VOUTS1_EX 60 90 120 mV
(External) VIN7 - VOUTS1
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Table 6: Logic Characteristics (Unless otherwise specified, Tj = -40 °C to +150 °C, VIN = 3.3 V)
Standard Value
Min Typ Max
[Logic Block]
[Logic Input 1] (RSTB, SYNC, WDI, WDEN, VOUT1_EN, DDR_SEL)
Input Voltage Low 1 VIL1 -0.3 - +0.5 V -
Input Voltage High 1 VIH1 1.2 - VIN + 0.3 V -
Pull Down Resistance 1 RIN1 - 100 - kΩ -
[Logic Input 2] (SDA, SCL)

Input Voltage Low 2 VIL2 -0.3 - +0.5 V -
Input Voltage High 2 VIH2 1.2 - VIN + 0.3 V -
Input Current 2 IIN2 -1 0 +1 µA -
Acknowledge ON Voltage VACK -0.3 - +0.4 V Iload = -20 mA
[Logic Input 3] (SEQCNT[0], SEQCNT[1])

Input Voltage Low 3 VIL3 -0.3 - VIN x 0.1 V -
Input Voltage Middle Low 3 VIML3 VIN x 0.2 - VIN x 0.5 V -
Input Voltage Middle High 3 VIMH3 VIN x 0.6 - VIN x 0.8 V -
Input Voltage High 3 VIH3 VIN x 0.9 - VIN + 0.3 V -
Pull Down Resistance 3 RIN3 - 2 - MΩ -
[Logic Output Voltage Low 1] (Open Drain Output)

INTB, PGD, WDO Logic_out_low1 -0.3 - +0.7 V Iload = -3 mA
[Logic Output Voltage Low 2] (Open Drain Output)

PRESETB Logic_out_low2 -0.3 - +0.5 V Iload = -3 mA
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Protection Mode (Under Voltage Lock Out)
All power supply shuts down at the same time when the VFIL UVLO signal is detected. There is no sequence in this
shutdown mode and the BD9576MUF-C cannot receive any external signals during this time.
Protection Mode (Thermal Shutdown)
Built-in internal Thermal Shutdown (TSD) circuit is provided to protect IC from heat destruction. Operation usage should stay
within the allowable loss range. Continuous use beyond this range can cause chip temperature Tj to increase and
consequently activate the TSD circuit. Threshold is 175 °C (Typ). TSD over 10 µs shuts down all power supplies at the
same time. Please consider the set design not to exceed TSD for safety use.
Protection Mode (Thermal Warning)
Built-in internal Thermal Warning (TW) circuit is provided to protect the IC from heat destruction. Thermal Warning (TW) is
detected 30 °C lower than Thermal Shutdown (TSD). Thermal Warning (TW) is notified by the INTB pin negation.
Protection Mode
Table 7: Protection Mode (General)

Protection Mode SW Output Function
PMIC is shut down immediately.
UVLO Protection (VFIL) Hi-Z Low (Discharge)
All registers are reset.
Thermal Shutdown Hi-Z Low (Discharge)
Some registers (SEQ reset Register) are reset.
Table 8: Protection Mode (VD50, DDR, VD18, VD10)

Protection Mode SW Output Function
Under Voltage Protection[UVP] PMIC is shut down immediately.
Hi-Z Low (Discharge)
(VIN1 to VIN5)(Note 1) Some registers (SEQ reset Register) are reset.
Timer latch (1 ms).
Short Circuit Protection Hi-Z Low (Discharge) PMIC is shut down.
Over Voltage Protection Hi-Z Low (Discharge)
Duty is restricted.
Timer latch (1 ms).
Over Current Protection Hi-Z Low (Discharge)
PMIC is shut down.
(Note 1) VOUT1 or VOUTL1 output can be set to disable by connecting the VIN1 pin or the VIN6 pin to GND.
Please refer to section 4.3 VOUT1/VOUTL1 Disable Setting without EEPROM.
Table 9: Protection Mode (VL25)

Protection Mode Output Function
Low (Discharge)
(VIN6)(Note 1) Some registers (SEQ reset Register) are reset.
Timer latch (1 ms).
Short Circuit Protection Low (Discharge) PMIC is shut down.
Over Voltage Protection Low (Discharge)
(Note 1) VOUT1 or VOUTL1 output can be set to disable by connecting the VIN1 pin or the VIN6 pin to GND.
Please refer to section 4.3 VOUT1/VOUTL1 Disable Setting without EEPROM.
Table 10: Protection Mode (VS33)

Protection Mode Output Function
Low (Discharge)
(VIN7) Some registers (SEQ reset Register) are reset.
Timer latch (1 ms).
Over Current Protection Low (Discharge) PMIC is shut down.
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Mutual Monitor Function (VREF, OSC)
There are 2 blocks of OSC and VREF respectively, and those are being monitored mutually. When Mutual Monitor Function
error occurs, shuts down all power supplies at the same time.
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4. Function Description
Pin Control Function
4.1.1 VOUT1_EN Input
VOUT1 Mode is selected by VOUT1_EN (pin) condition at UVLO release timing.

At the judgement timing, VOUT1 output voltage is
Mode A: controlled sequentially by the register setting. (VOUT1_EN (pin) = H at UVLO release timing).
Mode B: controlled by VOUT1_EN (pin) individually, and register setting is ignored.
(VOUT1_EN (pin) = L at UVLO release timing).
(Note) Most of timing charts in this data sheet are based on Mode A. Regarding Mode B, please refer to section 4.1.9 VOUT1 Mode Setting.
4.1.2 RSTB Input
The RSTB pin input is control signal to start Output Power-ON / Output Power-OFF.
Output Power-ON starts by inputting RSTB = H level and Output Power-OFF starts by inputting RSTB = L level.
Between the completion of Output Power-OFF and beginning of Output Power-ON (STANDBY state),
internal functions (except particular functions) are initialized and stops the circuit oscillator for low power
consumption with OSC_EN register = “0” setting.
Even though in STANDBY state, circuit oscillation starts with OSC_EN register = “1” setting.
(Note) In case RSTB = L level is detected during Power-ON Sequence, Power-OFF sequence starts immediately.
Figure 4. RSTB Operation Timing Chart
4.1.3 PIN Setting Judge Timing
The SEQCNT[1:0] pin (Select Power-ON / Power-OFF interval) and the DDR_SEL pin (select DDR output voltage)
settings are judged just before EEPROM Load.
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4.1 Pin Control Function – continued
4.1.4 Output Power-ON / Output Power-OFF Sequence
Output Power-ON starts by input of RSTB = H level.

In Output Power-ON operation,
(1) Internal Oscillation Operation (OSC Stable), (2) EEPROM Load, (3) Self Diagnosis and (4) Power-ON sequence
are consecutively activated as shown in the following figure.
Regarding the interval T1 and T4, please refer to 4.1.7 Interval Setting.
(1) Internal Oscillation Operation: BD9576MUF-C waits 110 µs (Max) for stable oscillation internally.
(2) EEPROM Load: Some of the functions can be selected by EEPROM setting value (Max 2 ms).
(3) Self Diagnosis: BD9576MUF-C execute Self Diagnosis (Max 2 ms) before Power-ON.
(4) Power-ON sequence: Activates Output Power-ON and PRESETB = H negate in order and with interval as in
following figure. PGD is asserted when all output voltage levels are over 75 % (Typ) x VOUT.
Figure 5. Output Power-ON Operation Timing Chart (Default Register Setting)
Output Power-OFF starts by input of RSTB = L level.

For Output Power-OFF operation, Power-OFF sequence activates as in following figure.
Regarding the interval T2 and T3, please refer to 4.1.7 Interval Setting.
PGD is negated when one of the output power starts discharging.
Power-OFF operation is completed when all SHDN (= output voltage levels are under 200 mV (Typ)) is asserted.
Figure 6. Output Power-OFF Operation Timing Chart (Default Register Setting)
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4.1 Pin Control Function - continued
4.1.5 VOUT2 (VD18) Discharge Start Timing
In case all previous output’s SHDN is not asserted after the interval T3, VOUT2 output does not start discharging
until all previous output’s SHDN assertion.
4.1.6 Countermeasures for Hang-Up
In case any SHDN signal keeps low (Shutdown is not detected) during Power-Off sequence, the sequence is never
completed and sequence cannot shift to next. As countermeasure for this Hang-Up situation, Hang-Up Timer is
implemented.
Hang-Up Timer counts the time of Power-OFF Sequence, and if it continues over 400 ms, internal state transitions
to STANDBY automatically. In Mode B, VOUT1 also has Hang-Up Timer individually. If VOUT1 Power-OFF
Sequence continues over 100 ms, internal state transitions to STANDBY automatically.
Figure 7. VOUT2 Discharge Start Timing
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4.1.7 Interval Setting
Regarding the interval T1, T2, T3 and T4, they are set by the voltage setting of the SEQCNT[0] pin and the
SEQCNT[1] pin. The SEQCNT[1:0] pin input value is judged just before EEPROM Load. If EEPROM connection is
detected in the state of EEPROM Load, interval setting by the SEQCNT[1:0] pin is discarded and the setting by
EEPROM is used.
If I2C write command to POW Trigger VOUTx (VOUTx = VOUT1 to VOUT4, VOUTL1, VOUTS1) or POW Wait
VOUTx registers is detected, interval setting by the SEQCNT[1:0] pin is discarded and the setting by I2C write
command is used. Also in this case, by EEPROM connection interval setting by the SEQCNT[1:0] pin or I2C write
command are discarded and the setting by EEPROM is used.
Table 11: SEQCNT[0] Operation Mode

SEQCNT[0] SEQCNT[0]_DATA[2:0] T1 T2 T4
VIN “111” 10 ms 10 ms 25 ms
VMD_H(Note 1) “011” 8 ms 8 ms 15 ms
VMD_L(Note 2) “001” 4 ms 4 ms 10 ms
GND “000” 2 ms 2 ms 8 ms
(Note 1) VMD_H: VIN x 0.55 < Input Voltage < VIN x 0.85
(Note 2) VMD_L: VIN x 0.15 < Input Voltage < VIN x 0.55
Table 12: SEQCNT[1] Operation Mode

SEQCNT[1] SEQCNT[1]_DATA[2:0] T3
VIN “111” 50 ms
VMD_H(Note 1) “011” 40 ms
VMD_L(Note 2) “001” 30 ms
GND “000” 20 ms
(Note 1) VMD_H: VIN x 0.55 < Input Voltage < VIN x 0.85
(Note 2) VMD_L: VIN x 0.15 < Input Voltage < VIN x 0.55
VIN
VIN x 0.85
3
VIN x 0.55
SEQCNT[0]_DATA[2:0] =
“111”, “011”, “001”, “000”
VIN x 0.15
VIN
VIN or VMID_H or R1
VMID_L or GND
SEQCNT[0]
R2 2 MΩ (Typ)
(SEQCNT[1])
Ex)
VMID_H (SEQCNT_DATA[2:0] = “011”) ： R1 = 24 kΩ, R2 = 52 kΩ → VIN x 0.68　
VMID_L (SEQCNT_DATA[2:0] = “001”) ： R1 = 45 kΩ, R2 = 24 kΩ → VIN x 0.35
Please connect resistors of the total less than 200 kΩ.
Figure 8. SEQCNT Circuit
4.1.8 Initializing Control Circuit
There are 2 initialize conditions. Details of the initializing conditions are shown in following table.
Table 13: Initializing Control Circuit

Reset Name Initializing Condition Initializing Target Circuit
VDD reset UVLO of VFIL Every Control Circuit
Every Control Circuit except some I2C registers.
SEQ reset state transition to STANDBY state
In more detail, please refer Table 21 I2C I/F Register Map.
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4.1.9 VOUT1 Mode Setting
In Mode B, VOUT1 is managed in Sub State. Regarding Main State and Sub State, please refer State Machine.
VOUT1 Sub State is activated only in limited Main State. Regarding the “limited Main State”, and Sub State,
please refer Figure 12 Main State Machine and Figure 13 Sub State Machine.
Figure 9. Whole Sequence1 (Mode B)
Figure 10. Whole Sequence2 (Mode B)
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4.1.9 VOUT1 Mode Setting - continued
When protection error or Hang Up Timer Overflow occurs, all outputs start to Power-OFF at the same time
regardless the error is due to VOUT1 or other channels. In this case, VOUT1_EN (pin) = L and RSTB (pin) = L is
needed to Re Power-ON.
Figure 11. Error Case (Mode B)
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4.1 Pin Control Function – continued
4.1.10 State Machine
BD9576MUF-C has two State Machine, Main and Sub. Sub State Machine is for VOUT1 individual control in
Mode B.
Figure 12. Main State Machine
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4.1.10 State Machine - continued
Figure 13. Sub State Machine
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4. Function Description - continued
Whole Sequence Control
4.2.1 Whole Sequence (State Chart)
Figure 14. Whole Sequence (State Chart)
4.2.2 General Sequence Description
(SHUTDOWN to STANDBY)
BD9576MUF-C is in SHUTDOWN state during VIN Power off.
After the input of VIN power, internal state starts transition from SHUTDOWN to STANDBY.
In STANDBY state,
Case1: OSC disable (OSC_EN register = “0” setting)
Case2: OSC enable (OSC_EN register = “1” setting)
In Case2, I2C write in STANDBY state is possible since OSC clock is supplied.
[Output Power-ON] (STANDBY to ACTIVE)

By the input of RSTB (pin) = H level, internal state starts transition from STANDBY to ACTIVE, and it initiate Output
Power-ON. PGD (pin) output is asserted when all output voltage levels are over 75 % (Typ) x VOUT. PRESETB
(pin) is asserted with the interval setting. Then, the transition to ACTIVE state is completed.
[Output Power-OFF] (ACTIVE to STANDBY)

By the input of RSTB (pin) = L level, internal state starts transition from ACTIVE to STANDBY and it initiate Output
Power-OFF.
After Power-OFF sequence is completed, BD9576MUF-C is initialized and stops OSC, then completes transition
to STANDBY state.
(STANDBY to SHUTDOWN)
UVLO of VFIL becomes effective during VIN power OFF.
4.2.3 I2C Accessible State Condition
I2C accessibility is restricted to only in STANDBY state and ACTIVE state.
Table 14: I2C Accessible Condition

Internal State I2C read I2C write
Disable (with OSC_EN register = “0”) /
STANDBY Enable
Enable (with OSC_EN register = “1”)
EEPROM Load Disable Disable
Power-ON STANDBY, ACTIVE,
Enable Enable
Power-OFF STANDBY
Other Enable Disable
(Note) Only OSC_EN register can be written without OSC_EN register = “1” setting in STANDBY State.
Some register I2C read value in STANDBY State are 0x00 (initial value), and they may differ from the value after Power-ON.
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4.2 Whole Sequence Control – continued
4.2.4 EEPROM Load Function and Internal OSC Stable Time
By connecting external EEPROM to I2C I/F pin (I2C_SCL, I2C_SDA), functions can be customized by the
parameters written in EEPROM.
EEPROM load operates before Power-ON sequence started by RSTB = H level.
If EEPROM is connected, 2 ms (Max) EEPROM load time is needed.
Case1: with EEPROM and correct response from EEPROM, EEPROM parameters are loaded.
Case2: with EEPROM and no response (not Acknowledgement) from EEPROM, initial value is used.
Case3: with EEPROM and can not read check code (CON_CHK_CODE is not 0x8E), initial value is used.
Case4: with EEPROM and CRC error has occurred, internal state returns to STANDBY.
In Case2 and Case3, NO_EEP register is set to “1”.
In Case4, EEP_CRC_ERR register is set to “1”.
Regarding “CON_CHK_CODE” and detailed EEPROM setting, please refer to BD9576MUF-C EEPROM setting
sheet.
4.2.5 Self Diagnosis
When RSTB = H is asserted, Self Diagnosis test is started for UVD, OVD, OCW, SHDN and TW detection circuits.
Case1: If any unexpected behavior is not detected, Power-ON sequence is started.
Case2: If some unexpected behavior is detected, internal state returns to STANDBY.
4.2.6 Prevention of Repetition for Protection Error, EEPROM CRC Error, Self Diagnosis Error
When Protection Error is activated by VR (Voltage Regulator)’s malfunction, every output power is turned off at once
and transitions to STANDBY state. In this case, there is a possibility that RSTB = H level is maintained and internal
state starts transition from STANDBY to ACTIVE. At that time, every output power is turned off at once again and it
may be repeated if the factor of malfunction is not removed.
This kind of repetition is also concerned for EEPROM CRC Error or Self Diagnosis Error case.
To prevent this repetition, state transition from STANDBY does not start until the input of RSTB = L level.
Figure 15. Sequence at Protection Error Occurrence (Timing Chart)
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VOUT1/VOUTL1 Disable Setting without EEPROM
Without EEPROM setting, VOUT1 output can be set to disable by connecting VIN1 to GND.
Same with VOUTL1 output when VIN6 connecting to GND.
In this case, disable setting outputs are excluded from the Power-ON / Power-OFF sequence automatically.
VOUT1 and VOUTL1 disable setting is judged just before EEPROM Load.
Figure 16. VOUT1 Disable Setting without EEPROM
Figure 17. VOUTL1 Disable Setting without EEPROM
Boost Converter LDO25
Figure 18. VOUT1, VOUTL1 OFF Circuit
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VOUTS1 Disable Setting without EEPROM, Internal/External SW Mode Setting
VOUTS1 output mode is selected by GATECNT (pin).

Mode1: Using VOUTS1 internally (GATECNT = L)
Mode2: Using VOUTS1 externally (GATECNT = H)
Without EEPROM setting, VOUTS1 output can be set to disable by connecting VIN7 and GATECNT to GND.
In this case, disable setting outputs are excluded from the Power-ON / Power-OFF sequence automatically.
Internal/External setting is judged at the end of Self Diagnosis, and Disable setting is judged just before EEPROM Load.
When Power-On, VOUTS1 is used as internal SW for 4.1 ms (±15 %). VOUTS1 changes to external SW after POWER-
ON completion. Therefore, voltage drop may occur in VOUTS1 when big current is loaded from VOUTS1 before POWER-
ON completion.
Figure 19. VOUTS1 Disable Setting without EEPROM
Figure 20. VOUTS1 Internal/External Setting
VS33 (SW) VS33 (SW) VS33 (SW)
OFF INTERNAL SW ON (GATECNT = L) EXTERNAL SW ON (GATECNT = H)
Figure 21. VOUTS1 OFF Circuit and SW Mode Selection
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I2C I/F
I2C Slave Interface of 1ch is installed in BD9576MUF-C.
I2C Protocol
1 to 7
Figure 22. I2C Basic Protocol

Single Mode
<Single I2C Register Write Protocol>

S 0 1 1 0 0 0 0 0 A A D7 D6 D5 D4 D3 D2 D1 D0 A P
W
Slave Address Register Address Write Data
<Single I2C Register Read Protocol>

S 0 1 1 0 0 0 0 0 A A S 0 1 1 0 0 0 0 1 A D7 D6 D5 D4 D3 D2 D1 D0 NA P
W R
Slave Address Register Address Slave Address Read Data
Mutiple Mode
<Multiple I2C Register Write Protocol>

S 0 1 1 0 0 0 0 0 A A D7 D6 D5 D4 D3 D2 D1 D0 A From Master to Slave
W From Slave to Master
Slave Address Register Address ( = N) Write Data (Addr: N) S START condition
P STOP condition
D7 D6 D5 D4 D3 D2 D1 D0 A A D7 D6 D5 D4 D3 D2 D1 D0 A P A Acknow ledge
NA Not Acknow ledge
Write Data (Addr: N+1) Write Data
<Multiple I2C Register Read Protocol>

S 0 1 1 0 0 0 0 0 A A S 0 1 1 0 0 0 0 1 A D7 D6 D5 D4 D3 D2 D1 D0 A
W R
Slave Address Register Address ( = N) Slave Address Read Data (Addr: N)
D7 D6 D5 D4 D3 D2 D1 D0 A A D7 D6 D5 D4 D3 D2 D1 D0 NA P
Read Data (Addr: N+1) Read Data
Figure 23. I2C Protocol (Each Access Mode)
Slave Address
Support 7 bit Address mode
Slave Address: 0x30 (When 8 bit description, it is 0x60 in Write mode and 0x61 in Read mode)
Speed Mode
(1) Fast mode
(2) Fast mode plus
Frequency
(1) Fast mode: 400 kHz (Max)
(2) Fast mode plus: 1 MHz (Max)
I2C accessible State condition

(1) I2C read condition: except EEPROM Load state
(2) I2C write condition: In STANDBY state (with OSC_EN register = “1” setting) or ACTIVE state
(Note) For I2C write condition in STANDBY state, 110 µs (Max) wait time after OSC_EN register = “1” is needed.
ACK/NACK Criterion
NACK is output when the Slave Address is not set to 0x30.
NACK is output without the I2C accessible State condition.
ACK is output even with read/write access to register address that is not being used.
ACK is output even with write access to RO attribute register.
Bus Clear
If the data line (SDA) is stuck LOW, please send 18 clock pulses. By this procedure, SDA bus is released.
If not, then use the Hardware reset or cycle power to clear the bus.
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4.5 I2C I/F – continued
FuSa Mode (Error Detection / Rectification Mode)

FuSa (Functional Safety) mode is a function to detect/rectify transfer error. The 2nd byte of writing data at I2C transfer
is given as a FuSa byte to confirm.
Normal I2C mode or FuSa mode (type1, type2) is selectable by I2C FuSa mode register.
The transfer protocol for this uses the same conventional I2C protocol.
Continuous data write with register address increment is supported.
(Odd-bytes of writing data are the actual data and even-bytes are FuSa byte for confirmation. Address increments
every 2 bytes.)
(If FuSa byte returns with error, then the corresponding byte is not written. If the FuSa byte returns without error, then
the corresponding byte is written).
FuSa Mode is applied not only write data but also read data by I2C FuSa mode register setting.
Mode switching is valid from the next transferred byte after settings are changed.
Single Mode
<Single I2C Register Write Protocol> From Master to Slave

S 0 1 1 0 0 0 0 0 A A D7 D6 D5 D4 D3 D2 D1 D0 A A P From Slave to Master
W S START condition
Slave Address Register Address Write Data FuSa Byte P STOP condition
A Acknow ledge
NA Not Acknow ledge
<Single I2C Register Read Protocol>
S 0 1 1 0 0 0 0 0 A A S 0 1 1 0 0 0 0 1 A D7 D6 D5 D4 D3 D2 D1 D0 A NA P
W R
Slave Address Register Address Slave Address Read Data FuSa Byte
Multiple Mode
<Multiple I2C Register Write Protocol>

S 0 1 1 0 0 0 0 0 A A D7 D6 D5 D4 D3 D2 D1 D0 A A
W
Slave Address Register Address ( = N) Write Data (Addr: N) FuSa Byte (Addr: N)
D7 D6 D5 D4 D3 D2 D1 D0 A A A P
Write Data (Addr: N+1) FuSa Byte (Addr: N+1)
<Multiple I2C Register Read Protocol>

S 0 1 1 0 0 0 0 0 A A S 0 1 1 0 0 0 0 1 A D7 D6 D5 D4 D3 D2 D1 D0 A A
W R
Slave Address Register Address ( = N) Slave Address Read Data (Addr: N) FuSa Byte (Addr: N)
A A A NA P
Read Data (Addr: N+1) FuSa Byte (Addr: N+1) FuSa Byte
Figure 24. I2C Protocol (FuSa Mode)
[FuSa Mode Type1: Compare Write Data and FuSa Byte]
Write Data 8 bit == FuSa Byte 8 bit Writes properly to register.

(1) Does not write in register.
Write Data 8 bit == FuSa Byte 8 bit (2) Asserts interrupt while changing bit of I2C / Thermal
= Error Status register. (MD1 interrupt)
I2C_IMASK = “1” (Mask setting)
=> Do not assert
I2C_IMASK = “0” (Mask released)
=> Assert the INTB pin output
MD1 bit is cleared by writing in “1”.
[FuSa Mode Type2: Error Correction by FuSa Byte (Error 1 bit)]
Write Data 8 bit FuSa Byte 8 bit Writes properly to register.
(1) Rectify with FuSa Byte and writes to register.

Write Data 8 bit FuSa Byte 8 bit
(2) Asserts interrupt while changing bit of I2C / Thermal
Error Status register. (MD2_E1 interrupt)
ECC Calculation (1 bit error) => Do not assert the INTB pin output
MD2_E1 bit is cleared by writing in “1”.
(3) The cause of error is indicated in the I2C MD2_E1 Bit1
register by asserting the corresponding bit.
If P[4:0] has an error, this is indicated in the I2C
MD2_E1 Bit2 register. (Error rectification is
unnecessary.)
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[FuSa Mode Type2: Error Correction by FuSa Byte (Error more than 2 bit)]
ECC Calculation (No error)
Write Data 8 bit FuSa Byte 8 bit Writes properly to register.
Write Data 8 bit FuSa Byte 8 bit (1) Does not write in register.
(2) Asserts interrupt while changing bit of I2C / Thermal
Error Status register. (MD2_E2 interrupt)
ECC Calculation (2 bit error) => Do not assert the INTB pin output
MD2_E2 bit is cleared by writing in “1”.
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ECC Calculation Specification
Arrange and add P[4:0] on LSB as FuSa byte[7:0] for FuSa mode type2.
I2C Data Stream

D7 D6 D5 D4 D3 D2 D1 D0 A 0 0 0 P4 P3 P2 P1 P0
Write Data (Addr: N) FuSa byte (Addr: N)
Figure 25. I2C Data Format (FuSa Mode type2 = ECC at Calculation)
Transmitter [Encode]
Calculation method of P[4:0] added to DI[7:0] data (“^” means XOR calculation)
^
Receiver [Decode]
Error detecting and rectifying method by ECC Factor, receiving DI[7:0] and P[4:0].
ECC Factor Calculation Method

=> Error Detection Judgment/Error
(1) Error Detection Judgment

Error Detection Judgment based on ECC Factor
Figure 26. Error Detection Judgement by ECC Calculation
(2) Error Rectification

Error Correction is operated by following calculation for Single bit Error.
Figure 27. Error Correction Calculation
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Interrupt Function
4.6.1 Interrupt Function Description
Interruptions are notified from the INTB pin when interruption requests are enabled by any interruption factors.
The meaning of the words relevant to interruption are defined as followed.
“Interruption Factor”: Factor of any condition where an interruption is made.
“Interruption Mask”: Controls which interruption factors cause an interruption to occur.
(Masked: No interruption / No Mask: interruption occurs).
“Interruption Request”: Interruption request only becomes active when the interruption factor is active and the
interruption is not masked.
Interruption Factor
(1: With Factor / 0: Without Factor) Interruption Request
Interruption Mask (1: With request / 0: Without request)
(1: Mask / 0: Mask released)
Figure 28. Interruption Factor/Mask/Request
Each factor can be masked, read or cleared by I2C. Also, INTB utilizes active-low pin operation.
Figure 29. Interrupt Function Description
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4.6 Interrupt Function – continued
4.6.2 Interruption Factor
Interruption request notice function is implemented in 2 levels for the factor.

(1) Primary level interruption register of final stage
(2) Interruption register in secondary level of each function block stage
Following figure shows the logical flowchart of Interruption Factor/Mask/Request implemented in BD9576MUF-C.
Figure 30. System Diagram of Interruption Function
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4.6.2 Interruption Factor - continued
Following Shows All Interruption Factors.
(A) Interruption in Primary level

Interruption Factor register: INT IntReq register
Interruption Mask register: INT IntMask register
Table 15: Interruption at Primary Level

Interruption Factor Interruption Mask Detail of Interruption Active Condition of
(INT IntReq Register) (INT IntMask Register) Factor Interruption Factor
I2C Transfer Error, Error judged at writing register,
I2CTHM_INT I2CTHM_IMASK
Thermal Error (TSD, TW) Thermal Error detection
OVP_INT OVP_IMASK OVP Error Status OVP detection
SCP_INT SCP_IMASK SCP Error Status SCP detection
OCP_INT OCP_IMASK OCP Error Status OCP detection
OVD_INT OVD_IMASK OVD Error Status OVD detection
UVD_INT UVD_IMASK UVD Error Status UVD detection
UVP_INT UVP_IMASK UVP Error Status UVP detection
SYS_INT SYS_IMASK System Error Status System Error detection
(B) Interruption in Secondary Level

Regarding factors in Secondary Level, please refer the next page.
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4.6.2 Interruption Factor - continued
Table 16: Interruption at Secondary Level 2

Interruption Request Interruption Mask Detail of Interruption Factor
MD1 FuSa Mode Type1 error
MD2_E1 I2C_IMASK FuSa Mode Type2 error 1 bit
MD2_E2 FuSa Mode Type2 error more than 2 bit
TSD - Thermal Shutdown
TW TW_IMASK Thermal Warning
VOUT1_OVP VD50 power Output over voltage protection
VOUT3_OVP - DDR power Output over voltage protection
VOUTL1_OVP VL25 power Output over voltage protection
VOUT1_OCP VD50 power Output over current protection
VOUT2_OCP VD18 power Output over current protection
VOUT3_OCP DDR power Output over current protection
VOUT4A_OCP - VD10A power Output over current protection
VOUT4B_OCP VD10B power Output over current protection
VOUTS1_OCP VS33 power Output over current protection
LDSW_OCP LDSW power Output over current protection
VOUT1_SCP VD50 power Output short circuit protection
VOUT3_SCP - DDR power Output short circuit protection
VOUTL1_SCP VL25 power Output short circuit protection
VOUT1_OVD VD50 power Output over voltage detection
VOUT3_OVD - DDR power Output over voltage detection
VOUTL1_OVD VL25 power Output over voltage detection
VOUT1_UVD VD50 power Output under voltage detection
VOUT3_UVD DDR power Output under voltage detection
-
VOUTL1_UVD VL25 power Output under voltage detection
VOUTS1_OCW VS33 power Output over current warning
VIN1_UVP VD50 power Input under voltage protection
VIN2_UVP VD18 power Input under voltage protection
VIN3_UVP DDR power Input under voltage protection
VIN4_UVP - VD10A power Input under voltage protection
VIN5_UVP VD10B power Input under voltage protection
VIN6_UVP VL25 power Input under voltage protection
VIN7_UVP VS33 power Input under voltage protection
SD_ERR SD_E_IMASK Error Detection during Self Diagnosis
WDT_ERR WDT_E_IMASK WDI Input Clock Frequency Error
VREF_ERR VREF_E_IMASK Reference Voltage Mutual Monitor Error
OSC_ERR OSC_E_IMASK Oscillator Frequency Mutual Monitor Error
EEP_CRC_ERR EEPCRC_E_IMASK CRC Error during EEPROM Load
EEP_END EEP_END_IMASK EEPROM Load End
POFF_HUT_ERR POFFHUT_E_IMASK Hang-Up Timer counts over 400 ms
Hang-Up Timer for VOUT1 (only for Mode B),
V1_HUT_ERR V1_HUT_E_IMASK
100 ms
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Power Abnormality Monitoring Function (Protection Error Detection)
L_VOUT
DCDC Converter
C_VOUT
Logic
Figure 31. Power Abnormality Monitoring Circuit
Power Abnormality Monitoring Function for SCP and OCP work as follows:
LDSW_OCP function is excluded.
Figure 32. Timing Chart when Protection Error Factor Occur 1
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4.7 Power Abnormality Monitoring Function (Protection Error Detection) – continued
Power Abnormality Monitoring Function for OVP and TSD work as follows:
Figure 33. Timing Chart when Protection Error Factor Occur 2
Power Abnormality Monitoring Function for OVD and UVD work as follows:
Figure 34. Timing Chart when Protection Detection Factor Occur
OVD and UVD monitors whether the output voltage is proper or not.
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SYNC Function
The SYNC pin is used to synchronize the DC/DC switching frequency with external pulse clock signal.
SYNC input frequency range is from 1.8 MHz to 2.2 MHz, and SYNC input pulse duty range is from 45 % to 55 %.
Entering abnormal clock through the SYNC pin (e.g. out of range signal) may cause malfunction.
The external pulse clock signal is reflected in ACTIVE mode. This pin can be remained open if synchronization is not
needed. The SYNC pin needs 10 kΩ external pull down resistor when synchronization signal is supplied from R-car
SoC.
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WDT Function
Watch Dog Timer (WDT) monitors the WDI pin input by detecting the rising edge of WDI input pulse.
This function is enabled by WDEN (pin) = H in ACTIVE state. If WDT Error is detected, the WDO pin output is negated.
WDT starts from rising edge of WDIN

The detection guaranteed The detection guaranteed
WDT
WDIN WDT Fast N.G. WDT Slow N.G.
Trigger Open Window
tWF (Min)
t (ms)
tWF (Max)
tOK (Typ)
tWS (Min)
tWS (Max)
Figure 35. WDT Function
WDT FAST N.G. Detection

1. WDI input signal is ignored when WDEN = L or internal state is not ACTIVE. WDT is activated when WDEN = H.
2. For the initial duration just after WDEN goes to high, only SLOW N.G. time detection works and FAST N.G.
does not work. If rise edge of WDI comes within SLOW N.G. time, then
(1) both FAST N.G. and SLOW N.G. time detections start to work. (TYPE register (0x16[5]) = H)
(2) only SLOW N.G. time detection starts to work. (TYPE register (0x16[5]) = L)
3. These time detection monitors the time until next rising edge and when it detects WDI edge within FAST N.G.
time (tWF), WDO becomes LOW. WDO goes back to High after 100 ms (Typ) delay.
4. When WDO becomes High, WDT is activated again and operation resumes.
Only SLOW N.G. time detection works until the next first rising edge, and both SLOW and FAST N.G. starts at
the first rising edge like state 1.
When WDEN is Low, WDO becomes H and WDT is disabled. During this period, WDI input signal is ignored and WDO
output is not affected.
Regarding WDI input signal, over 200 µs H level is required to be detected as “H” level.
FAST/SLOW N.G. Detection Area is determined by FAST_NG[2:0] and NG_RATIO[1:0] register setting.
WDIN input clock duration is set by FAST_NG[2:0] register value.
rise edge of WDI

OK Area
Fast NG : OK Area = 1 : 1 Slow NG
Fast NG
NG_RATIO[1:0] = "00"

Fast NG OK Area
NG_RATIO[1:0] = "01"

Fast NG OK Area
NG_RATIO[1:0] = "10"
Fast NG : OK Area = 1 : 15
Fast NG OK Area Slow NG
NG_RATIO[1:0] = "11"
Figure 36. WDT NG RATIO
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4.9 WDT Function – continued
Table 17: WDT setting (NG_RATIO[1:0] = “00”)

Fast NG Detection (ms) tOK (ms) Slow NG Detection (ms)
FAST_NG[2:0]
tWF (Min) tWF (Max) (Typ) tWS (Min) tWS (Max)
“000” 1.7 2.3 3.0 3.6 4.6
“001” 3.4 4.6 6.0 7.4 9.2
“010” 6.8 9.2 12.0 14.5 18.5
“011” 13.5 18.5 24.0 29.5 36.5
“100” 27.5 36.5 48.0 59.5 73.0
“101” 55.0 73.0 96.0 119.0 146.0
“110” 110.0 146.0 192.0 238.0 292.0
“111” 220.0 292.0 384.0 476.0 583.0

FAST_NG[2:0]
“000” 1.7 2.3 4.8 7.2 9.2
“001” 3.4 4.6 9.7 14.8 18.4
“010” 6.8 9.2 19.0 29.0 37.0
“011” 13.5 18.5 39.0 59.0 73.0
“100” 27.5 36.5 78.0 119.0 146.0
“101” 55.0 73.0 156.0 238.0 292.0
“110” 110.0 146.0 311.0 476.0 584.0
“111” 220.0 292.0 622.0 952.0 1166.0

FAST_NG[2:0]
“000” 1.7 2.3 8.4 14.4 18.4
“001” 3.4 4.6 17.0 29.6 36.8
“010” 6.8 9.2 33.5 58.0 74.0
“011” 13.5 18.5 68.0 118.0 146.0
“100” 27.5 36.5 137.0 238.0 292.0
“101” 55.0 73.0 275.0 476.0 584.0
“110” 110.0 146.0 550.0 952.0 1168.0
“111” 220.0 292.0 1100.0 1904.0 2332.0

FAST_NG[2:0]
“000” 1.7 2.3 15.5 28.8 36.8
“001” 3.4 4.6 32.0 59.2 73.6
“010” 6.8 9.2 63.0 116.0 148.0
“011” 13.5 18.5 127.0 236.0 292.0
“100” 27.5 36.5 256.0 476.0 584.0
“101” 55.0 73.0 512.0 952.0 1168.0
“110” 110.0 146.0 1025.0 1904.0 2336.0
“111” 220.0 292.0 2050.0 3808.0 4664.0
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4.9 WDT Function – continued
Figure 37. WDT Detection Time when NG_RATIO[1:0] = “00”
Figure 38. WDT Detection Time when NG_RATIO[1:0] = “01”
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5. Register Specification
…Initializes at either VIN reset (VFIL UVLO) …Initializes only at VIN reset (VFIL UVLO)
Register Map or SEQ reset (STANDBY transition)
Table 21: I2C I/F Register Map

Address Register Name Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] R/W Default
0x00 Vendor Code 1 1 0 1 1 0 1 1 RO 0xDB
0x01 Product Code 0 1 1 1 0 1 1 0 RO 0x76
0x02 Product Revision 0 0 0 0 0 0 1 0 RO 0x02
- - - - - - - - - - - -
0x10 I2C FuSa Mode - - - SMOD_read - - I2C_SMOD[1:0] R/W 0x00
0x11 SHDN WriteProtect SHDN_WP[7:0] R/W 0x00
0x12 SHDN Cnt - - - - - - VREF_SHDN OSC_SHDN R/W 0x03
0x13 SSCG Cnt - SSCG_PERI SSCG_FORM[1:0] - - - SSCG_EN R/W 0x00
0x14 SMRB Write Protect SMRB_WP[7:0] R/W 0x00
0x15 SMRB Cnt - - - SMRB_hist - - - SMRB_asrt R/W 0x01
0x16 Watch Dog Timer setting - - TYPE NG_RATIO[1:0] FAST_NG[2:0] R/W 0x20
0x17 OSC Enable - - - - - - - OSC_EN R/W 0x00
0x18 PGD Setting - - PGD_SETTING[5:0] R/W 0x3F
- - - - - - - - - - - -
0x20 PMIC Internal Status - - - NO_EEP PMIC_STATE[3:0] RO 0x00
0x21 I2C MD2_E1 Bit 1 I2C_MD2_E1_BIT[7:0] RO 0x00
0x22 I2C MD2_E1 Bit 2 - - - I2C_MD2_E1_BIT_P[4:0] RO 0x00
0x23 I2C / Thermal Error Status - - TW TSD - MD2_E2 MD2_E1 MD1 R/W 0x00
0x24 I2C / Thermal Error Mask - - TW_IMASK - - - - I2C_IMASK R/W 0x00
0x25 OVP Error Status - - VOUTL1_OVP - VOUT4_OVP VOUT3_OVP VOUT2_OVP VOUT1_OVP R/W 0x00
0x26 SCP Error Status - - VOUTL1_SCP - VOUT4_SCP VOUT3_SCP VOUT2_SCP VOUT1_SCP R/W 0x00
0x27 OCP Error Status LDSW_OCP VOUTS1_OCP - VOUT4B_OCP VOUT4A_OCP VOUT3_OCP VOUT2_OCP VOUT1_OCP R/W 0x00
0x28 OVD Error Status - - VOUTL1_OVD - VOUT4_OVD VOUT3_OVD VOUT2_OVD VOUT1_OVD R/W 0x00
0x29 UVD / OCW Error Status - VOUTS1_OCW VOUTL1_UVD - VOUT4_UVD VOUT3_UVD VOUT2_UVD VOUT1_UVD R/W 0x00
0x2A UVP Error Status - VIN7_UVP VIN6_UVP VIN5_UVP VIN4_UVP VIN3_UVP VIN2_UVP VIN1_UVP R/W 0x00
0x2B System Status V1_HUT_ERR HUT_ERR EEP_END EEP_CRC_ERR OSC_ERR VREF_ERR WDT_ERR SD_ERR R/W 0x00
0x2C System Status Mask V1_HUT_E_IMASK HUT_E_IMASK EEP_END_IMASK EEPCRC_E_IMASK OSC_E_IMASK VREF_E_IMASK WDT_E_IMASK SD_E_IMASK R/W 0x20
- - - - - - - - - - - -
- - - - - - - - - - - -
0x30 INT IntReq SYS_INT UVP_INT UVD_INT OVD_INT OCP_INT SCP_INT OVP_INT I2CTHM_INT R/W 0x00
0x31 INT IntMask SYS_IMASK UVP_IMASK UVD_IMASK OVD_IMASK OCP_IMASK SCP_IMASK OVP_IMASK I2CTHM_IMASK R/W 0x00
- - - - - - - - - - - -
0x40 POW Write Protect POW_WP[7:0] R/W 0x00
0x41 POW Trigger VOUT1 POFF_TRG_VOUT1[3:0] PON_TRG_VOUT1[3:0] R/W 0x20
0x45 POW Trigger VOUTL1 POFF_TRG_VOUTL1[3:0] PON_TRG_VOUTL1[3:0] R/W 0x36
0x46 POW Trigger VOUTS1 POFF_TRG_VOUTS1[3:0] PON_TRG_VOUTS1[3:0] R/W 0x52
0x47 POW Trigger PRESETB POFF_TRG_PRESETB[3:0] PON_TRG_PRESETB[3:0] R/W 0x04
0x48 POW Wait VOUT1 POFF_WAIT_VOUT1[3:0] PON_WAIT_VOUT1[3:0] R/W 0x00
0x49 POW Wait VOUT2 POFF_WAIT_VOUT2[3:0] PON_WAIT_VOUT2[3:0] R/W 0x00
0x4A POW Wait VOUT3 POFF_WAIT_VOUT3[3:0] PON_WAIT_VOUT3[3:0] R/W 0x00
0x4B POW Wait VOUT4 POFF_WAIT_VOUT4[3:0] PON_WAIT_VOUT4[3:0] R/W 0x00
0x4C POW Wait VOUTL1 POFF_WAIT_VOUTL1[3:0] PON_WAIT_VOUTL1[3:0] R/W 0x00
0x4D POW Wait VOUTS1 POFF_WAIT_VOUTS1[3:0] PON_WAIT_VOUTS1[3:0] R/W 0x00
0x4E POW Wait PRESETB POFF_WAIT_PRESETB[3:0] PON_WAIT_PRESETB[3:0] R/W 0x00
- - - - - - - - - - - -
0x50 VOUT1 TUNE V1_SIGN - - - - VOUT1_TUNE[2:0] RO 0x00
0x51 VOUT1 OVD SET - VOUT1_OVD_SET[6:0] R/W 0x43
0x52 VOUT1 UVD SET - VOUT1_UVD_SET[6:0] R/W 0x43
0x53 VOUT2 TUNE V2_SIGN - - - - VOUT2_TUNE[2:0] RO 0x00
0x54 VOUT2 OVD SET - VOUT2_OVD_SET[6:0] R/W 0x37
0x55 VOUT2 UVD SET - VOUT2_UVD_SET[6:0] R/W 0x37
0x56 VOUT3 TUNE V3_SIGN - - VOUT3_TUNE[4:0] RO 0x00
0x57 VOUT3 OVD SET - VOUT3_OVD_SET[6:0] R/W 0x3E/0x27 (Note 1)
0x58 VOUT3 UVD SET - VOUT3_UVD_SET[6:0] R/W 0x23/0x27 (Note 2)
0x59 VOUT4 TUNE V4_SIGN - - VOUT4_TUNE[4:0] RO 0x00

0x5A VOUT4 OVD SET - VOUT4_OVD_SET[6:0] R/W 0x19
0x5B VOUT4 UVD SET - VOUT4_UVD_SET[6:0] R/W 0x19
0x5C VOUTL1 TUNE VL1_SIGN - - - - VOUTL1_TUNE[2:0] RO 0x00
0x5D VOUTL1　OVD SET - VOUTL1_OVD_SET[6:0] R/W 0x40
0x5E VOUTL1 UVD SET - VOUTL1_UVD_SET[6:0] R/W 0x40
0x5F VOUTS1 OCW SET - - VOUTS1_OCW_SET[5:0] R/W 0x10/0x06 (Note 3)
0x60 VOUTS1 OCP SET - - VOUTS1_OCP_SET[5:0] R/W 0x16/0x08 (Note 4)
0x61 Deglitch Time - UVD_OCW_DEG_TIM[2:0] - OVD_DEG_TIM[2:0] R/W 0x33

(Note) Please do not access to the address except above.
(Note 1) DDR_SEL (pin) = L: Default value is 0x3E.
DDR_SEL (pin) = H: Default value is 0x27.
(Note 2) DDR_SEL (pin) = L: Default value is 0x23.
DDR_SEL (pin) = H: Default value is 0x27.
(Note 3) GATECNT (pin) = L: Default value is 0x10.
GATECNT (pin) = H: Default value is 0x06.
(Note 4) GATECNT (pin) = L: Default value is 0x16.
GATECNT (pin) = H: Default value is 0x08.
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5. Register Specification – continued
Register Description
5.2.1 Recognition Code Indicator
Register Name Address D7 D6 D5 D4 D3 D2 D1 D0 R/W Default

Vendor Code 0x00 1 1 0 1 1 0 1 1 RO 0xDB
Vendor Recognition Code

0xDB: Rohm

Product Code 0x01 0 1 1 1 0 1 1 0 RO 0x76
Product Recognition Code

0x76: BD9576MUF-C

Product Revision 0x02 0 0 0 0 0 0 1 0 RO 0x02
Product Revision Recognition Code

0x02: Rev.2 Sample
5.2.2 FuSa Mode (Error Detection / Rectification Mode)

I2C FuSa Mode 0x10 - - - SMOD_read - - I2C_SMOD[1:0] R/W 0x00
I2C_SMOD[1:0] FuSa Mode Setting
“00”: General mode (NO FuSa mode) => Normal I2C format without FuSa byte.
“01”: FuSa mode type1

FuSa byte = Write data. (No error if 2 transferring data bytes are the same value.)
When error is detected
=> Do not execute writing and assert MD1 Interruption Factor bit of I2C / Thermal Error Status
register.
(Assert the INTB pin output if I2C_IMASK mask is released by I2C / Thermal Error Mask
register.)
“10”: FuSa mode type2

FuSa byte = ECC data. (Refer to section 4.5 I2C I/F for details regarding ECC mathematical operation
specification)
As a result of ECC mathematical operation,
At 1 bit Error (Rectify error of relevant bit)
=> Execute rectification writing and assert MD2_E1 Interruption Factor bit of I2C / Thermal Error
Status register.
register, and also indicate location of relevant bit on I2C MD2_E1 Bit1 register and I2C
MD2_E1 Bit2 register (for P[4:0])).
At 2 bit Error (Error Detection)
=> Do not execute writing and assert MD2_E2 Interruption Factor bit of I2C / Thermal Error Status
register.
register.)
“11”: Reserved
SMOD_read FuSa Mode Read Setting
0: FuSa Mode is applied only for I2C write data.

1: FuSa Mode is applied not only I2C write data, but also I2C read data.
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5.2 Register Description - continued
5.2.3 Shutdown Control

SHDN WriteProtect 0x11 SHDN_WP[7:0] R/W 0x00
SHDN_WP[7:0] Protection register for VREF_SHDN and OSC_SHDN

0x59: Access for SHDN Cnt is enabled.
Others: Access for SHDN Cnt is disabled.

SHDN Cnt 0x12 - - - - - - VREF_SHDN OSC_SHDN R/W 0x03
OSC_SHDN Shutdown selection when OSC Mutual Monitor Error occur
0: When OSC Mutual Monitor Error occur, OSC_ERR System Error Status Register is written “1”.
1: When OSC Mutual Monitor Error occur, OSC_ERR System Error Status Register is written “1”,
and every output power is turned off at once. Internal state transitions to STANDBY.
VREF_SHDN Shutdown selection when VREF Mutual Monitor Error occur
0: When VREF Mutual Monitor Error occur, VREF_ERR System Error Status Register is written “1”.
1: When VREF Mutual Monitor Error occur, VREF_ERR System Error Status Register is written “1”,
and every output power is turned off at once. Internal state transitions to STANDBY.
5.2.4 Spread Spectrum Clock Generation Control for Internal OSC
BD9576MUF-C has built-in SSCG (Spread Spectrum Clock Generator) with center spread.

SSCG_ SSCG_
SSCG Cnt 0x13 - SSCG_FORM[1:0] - - - R/W 0x00
PERI EN
SSCG_EN Enable signal of SSCG

0: SSCG Disable
1: SSCG Enable
SSCG_FORM[1:0] Selection of SSCG modulation waveform

“00”: Normal Triangle
“01”: Original waveform1 (A:B:C = 4:1:4)
f
+2.5 %
A B C
0% t
Modulation period
-2.5 % (1/SSCG_PERI)
Figure 39. Modulation Waveform of SSCG
SSCG_PERI
0: 122 Hz
1: 7.813 kHz
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5.2.5 SMRB Control Using I2C Control (Software Manual Reset for PRESETB)
The PRESETB pin output can be controlled by these registers.

SMRB Write Protect 0x14 SMRB_WP[7:0] R/W 0x00
SMRB_WP[7:0] Protection register for SMRB_asrt (Software Manual Reset for PRESETB)
0x9D: SMRB assert is enabled.
Others: SMRB assert is disabled.

SMRB SMRB
SMRB Cnt 0x15 - - - - - - R/W 0x01
_hist _asrt
SMRB_asrt SMRB assert register

When this register is set to “0”, PRESETB is asserted to L. After 5 ms, this register value is reset to “1” and
PRESETB is negated to H automatically.
SMRB_hist SMRB status register

If SMRB assert is occurred, this register is set to “1”. Register value does not be initialized during STANDBY
state transition. Clear condition is I2C writing “1” or UVLO.
5.2.6 Watch Dog Timer setting

Watch Dog Timer
0x16 - - TYPE NG_RATIO[1:0] FAST_NG[2:0] R/W 0x20
setting
FAST_NG[2:0], NG_RATIO[1:0] WDT N.G. detection area setting

Regarding these registers’ function, please refer to section 4.9 WDT Function.
TYPE WDT detecting type setting

0: timeout detection (SLOW N.G.)
1: window detection (FAST/SLOW N.G.)
(Note) I2C write to Watch Dog Timer setting register when the WDEN pin H level is prohibited.
5.2.7 Oscillator Enable in STANDBY State

OSC Enable 0x17 - - - - - - - OSC_EN R/W 0x00
OSC_EN Oscillator Enable/Disable Selection in STANDBY state

0: Oscillator Disable in STANDBY state
1: Oscillator Enable in STANDBY state
(Note) For I2C write condition in STANDBY state, 110 µs (Max) wait time after OSC_EN register = “1” is needed.
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5.2.8 The PGD Pin Output Assert Condition Setting

PGD Setting 0x18 - - PGD_SETTING[5:0] R/W 0x3F
PGD_SETTING[5:0] The PGD pin output assert condition

PGD_SETTING[0] = 0: VOUT1 PGD is not the factor of the PGD pin output,
1: VOUT1 PGD is the factor of the PGD pin output.
PGD_SETTING[4] = 0: VOUTL1 PGD is not the factor of the PGD pin output,
1: VOUTL1 PGD is the factor of the PGD pin output.
PGD_SETTING[5] = 0: VOUTS1 PGD is not the factor of the PGD pin output,
1: VOUTS1 PGD is the factor of the PGD pin output.
For example, the PGD pin output is asserted by VOUT1, VOUT2, VOUT3 and VOUT4 PGD when
PGD_SETTING[5:0] = 0x0F.
In this case, the PGD pin output is negated at any one of VOUT1, VOUT2, VOUT3 or VOUT4 discharge start
timing.
5.2.9 PMIC Internal Status

PMIC Internal Status 0x20 - - - NO_EEP PMIC_STATE[3:0] RO 0x00
PMIC_STATE[3:0] PMIC Internal State

PMIC Internal State is shown in the following table.
Table 22: PMIC Internal State

PMIC_STATE[3:0] Setting Value PMIC Internal State
0x0 SHUTDOWN
0x1 STANDBY
0x2 OSC Stable
0x3 Self Diagnosis
0x4 Power-ON STANDBY
0x5 Power-ON
0x6 ACTIVE
0x7 Power-OFF
0x8 Power-OFF STANDBY
0x9 to 0xF State transition
NO_EEP Judgement for EEPROM installation

0: With ACK from EEPROM (EEPROM is installed)
1: Without ACK from EEPROM (EEPROM is not installed)
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5.2.10 I2C FuSa Mode Error Bit Location

I2C MD2_E1 Bit 1 0x21 I2C_MD2_E1_BIT[7:0] RO 0x00
I2C_MD2_E1_BIT[7:0] Error bit location at FuSa mode type2

Set “1” to the bit location where error is detected and rectified in FuSa mode type2.

I2C MD2_E1 Bit 2 0x22 - - - I2C_MD2_E1_BIT_P[4:0] RO 0x00
I2C_MD2_E1_BIT_P[4:0] Error bit location (P code) at FuSa mode type2

Set “1” to the bit (P code value) location where error is detected and rectified in FuSa mode type2.
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5.2 Register Description – continued
5.2.11 INTB Interruption Factor and Mask Condition

(Note) Clear condition of Status registers is I2C writing “1” or UVLO.

I2C / Thermal Error Status 0x23 - - TW TSD - MD2_E2 MD2_E1 MD1 R/W 0x00
MD1 I2C Write Error Status in FuSa Mode Type1

0: No Interruption Factor
1: with Interruption Factor
MD2_E1 I2C Write Error Status in FuSa Mode Type2 with 1 bit error
MD2_E2 I2C Write Error Status in FuSa Mode Type2 with more than 2 bit error
TSD Thermal Shutdown Detection

TW Thermal Warning Detection


I2C / Thermal Error Mask 0x24 - - TW_IMASK - - - - I2C_IMASK R/W 0x00
I2C_IMASK FuSa Mode Error (MD1, MD2_E1, MD2_E2) Interruption Factor Mask
0: Mask Disable
1: Mask Enable
TW_IMASK Thermal Warning Interruption Factor Mask

0: Mask Disable
1: Mask Enable

VOUTL1 VOUT4 VOUT3 VOUT2 VOUT1
OVP Error Status 0x25 - - - R/W 0x00
_OVP _OVP _OVP _OVP _OVP
VOUTx_OVP (x = 1 to 4 and L1) Over Voltage Protection Detection


SCP Error Status 0x26 - - - R/W 0x00
_SCP _SCP _SCP _SCP _SCP
VOUTx_SCP (x = 1 to 4 and L1) Short Circuit Protection Detection


LDSW VOUTS1 VOUT4B VOUT4A VOUT3 VOUT2 VOUT1
OCP Error Status 0x27 - R/W 0x00
_OCP _OCP _OCP _OCP _OCP _OCP _OCP
VOUTx_OCP (x = 1 to 3, 4A, 4B and S1), LDSW_OCP Over Current Protection Detection

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5.2.11 INTB Interruption Factor and Mask Condition – continued

OVD Error Status 0x28 - - - R/W 0x00
_OVD _OVD _OVD _OVD _OVD
VOUTx_OVD (x = 1 to 4 and L1) Over Voltage Detection


UVD / OCW VOUTS1 VOUTL1 VOUT4 VOUT3 VOUT2 VOUT1
0x29 - - R/W 0x00
Error Status _OCW _UVD _UVD _UVD _UVD _UVD
VOUTx_UVD (x = 1 to 4 and L1) Under Voltage Detection

VOUTS1_OCW Over Current Warning


UVP Error Status 0x2A - VIN7_UVP VIN6_UVP VIN5_UVP VIN4_UVP VIN3_UVP VIN2_UVP VIN1_UVP R/W 0x00
VINx_UVP (x = 1 to 7) Under Voltage Protection


V1_HUT EEP_CRC
System Status 0x2B HUT_ERR EEP_END OSC_ERR VREF_ERR WDT_ERR SD_ERR R/W 0x00
_ERR _ERR
SD_ERR Self Diagnosis Error

WDT_ERR Watch Dog Timer Error

VREF_ERR Reference Voltage Mutual Monitor Error

OSC_ERR Oscillator Mutual Monitor Error

EEP_CRC_ERR CRC Error during EEPROM Load

EEP_END Notification of EEPROM Load Internal State completion

0: Before EEPROM Load Completion
1: EEPROM Load is completed
HUT_ERR Power-OFF Sequence Hang-Up Timer counts over 400 ms

V1_HUT_ERR V1 Power-OFF Hang-Up Timer counts over 100 ms

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5.2.11 INTB Interruption Factor and Mask Condition - continued

V1_HUT_ HUT_E_ EEP_END_ EEPCRC OSC_E_ VREF_E_ WDT_E_ SD_E_
System Status Mask 0x2C R/W 0x20
E_IMASK IMASK IMASK _E_IMASK IMASK IMASK IMASK IMASK
SD_E_IMASK Self Diagnosis Error Interruption Factor Mask

0: Mask Disable
1: Mask Enable
WDT_E_IMASK Watch Dog Timer Error Interruption Factor Mask

0: Mask Disable
1: Mask Enable
VREF_E_IMASK Reference Voltage Mutual Monitor Error Interruption Factor Mask

0: Mask Disable
1: Mask Enable
OSC_E_IMASK Oscillator Mutual Monitor Error Interruption Factor Mask

0: Mask Disable
1: Mask Enable
EEPCRC_E_IMASK CRC Error during EEPROM Load Interruption Factor Mask

0: Mask Disable
1: Mask Enable
EEP_END_IMASK Notification of EEPROM Load Internal State completion Interruption Factor Mask
0: Mask Disable
1: Mask Enable
HUT_E_IMASK Hang-Up Timer Interruption Factor Mask

0: Mask Disable
1: Mask Enable
V1_HUT_E_IMASK V1 Hang-Up Timer Interruption Factor Mask

0: Mask Disable
1: Mask Enable
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I2CTHM
INT IntReq 0x30 SYS_INT UVP_INT UVD_INT OVD_INT OCP_INT SCP_INT OVP_INT R/W 0x00
_INT
I2CTHM_INT Primary Level Interruption Factor of I2C / Thermal Error Status Register
OVP_INT Primary Level Interruption Factor of OVP Error Status Register

SCP_INT Primary Level Interruption Factor of SCP Error Status Register

OCP_INT Primary Level Interruption Factor of OCP Error Status Register

OVD_INT Primary Level Interruption Factor of OVD Error Status Register

UVD_INT Primary Level Interruption Factor of UVD Error Status Register

UVP_INT Primary Level Interruption Factor of UVP Error Status Register

SYS_INT Primary Level Interruption Factor of System Status Register

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SYS_ UVP_ UVD_ OVD_ OCP_ SCP_ OVP_ I2CTHM
INT IntMask 0x31 R/W 0x00
IMASK IMASK IMASK IMASK IMASK IMASK IMASK _IMASK
I2CTHM_IMASK Primary Level Interruption Factor of I2C / Thermal Error Status Register Mask
0: Mask Disable
1: Mask Enable
OVP_IMASK Primary Level Interruption Factor of OVP Error Status Register Mask
0: Mask Disable
1: Mask Enable
SCP_IMASK Primary Level Interruption Factor of SCP Error Status Register Mask
0: Mask Disable
1: Mask Enable
OCP_IMASK Primary Level Interruption Factor of OCP Error Status Register Mask
0: Mask Disable
1: Mask Enable
OVD_IMASK Primary Level Interruption Factor of OVD Error Status Register Mask
0: Mask Disable
1: Mask Enable
UVD_IMASK Primary Level Interruption Factor of UVD Error Status Register Mask
0: Mask Disable
1: Mask Enable
UVP_IMASK Primary Level Interruption Factor of UVP Error Status Register Mask
0: Mask Disable
1: Mask Enable
SYS_IMASK Primary Level Interruption Factor of System Status Register Mask

0: Mask Disable
1: Mask Enable
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5.2.12 POW Setting

POW WriteProtect 0x40 POW_WP[7:0] R/W 0x00
POW_WP[7:0] Protection register for POW Trigger and POW Wait

0xAB: Access for POW registers is enabled.
Others: Access for POW registers is disabled.

POW Trigger VOUT1 0x41 POFF_TRG_VOUT1 PON_TRG_VOUT1 R/W 0x20




POW Trigger VOUTL1 0x45 POFF_TRG_VOUTL1 PON_TRG_VOUTL1 R/W 0x36

POW Trigger VOUTS1 0x46 POFF_TRG_VOUTS1 PON_TRG_VOUTS1 R/W 0x52

POW Trigger
0x47 POFF_TRG_PRESETB PON_TRG_PRESETB R/W 0x04
PRESETB
PON_TRG_VOUTx(Note 1) Trigger Signal Setting in Power-ON Sequence
POFF_TRG_VOUTx(Note 1) Trigger Signal Setting in Power-OFF Sequence
The Order of Power-ON Sequence and Power-OFF Sequence is selected by POW Trigger VOUTx(Note 1) registers.
POW Trigger VOUTx(Note 1) registers’ value can be changed by EEPROM. Regarding default value of each
registers, please refer register map.
(e.g.)
By setting PON_TRG_VOUT2 = 0x1 (VOUT1 Enable Signal), VOUT2 starts Power-ON after VOUT1.
By setting POFF_TRG_VOUTL1 = 0x03 (VOUT3 Enable Signal), VOUTL1 starts Power-OFF after VOUT3.
By setting PON_TRG_VOUTL1 = 0xFF (Always OFF Setting), VOUTL1 never Power-ON. In this case, VOUTL1 is
excluded from the Power-ON / Power-OFF sequence automatically.
Setting over 2 signals triggering one Enable Signal is prohibited.
(Note 1) VOUTx = VOUT1 to VOUT4, VOUTL1 and VOUTS1
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5.2.12 POW Setting – continued
Table 23: PON/POFF Trigger Signal

PON_TRG_VOUTx(Note 1)
/ POFF_TRG_VOUTx(Note 1)
Trigger Signal
PON_TRG_PRESETB
/ POFF_TRG_PRESETB
0x0 RSTB (pin) = H level (Power-ON) / L level (Power-OFF)
0x1 VOUT1 Enable Signal
0x5 VOUTL1 Enable Signal
0x6 VOUTS1 Enable Signal
0x7 PRESETB (pin)
0x8 to 0xF Always OFF Setting

POW Wait VOUT1 0x48 POFF_WAIT_VOUT1 PON_WAIT_VOUT1 R/W 0x00

POW Wait VOUT2 0x49 POFF_WAIT_VOUT2 PON_WAIT_VOUT2 R/W 0x00

POW Wait VOUT3 0x4A POFF_WAIT_VOUT3 PON_WAIT_VOUT3 R/W 0x00

POW Wait VOUT4 0x4B POFF_WAIT_VOUT4 PON_WAIT_VOUT4 R/W 0x00

POW Wait VOUTL1 0x4C POFF_WAIT_VOUTL1 PON_WAIT_VOUTL1 R/W 0x00

POW Wait VOUTS1 0x4D POFF_WAIT_VOUTS1 PON_WAIT_VOUTS1 R/W 0x00

POW Wait
0x4E POFF_WAIT_PRESETB PON_WAIT_PRESETB R/W 0x00
PRESETB
PON_WAIT_VOUTx(Note 1) Interval Setting in Power-ON Sequence
POFF_WAIT_VOUTx(Note 1) Interval Setting in Power-OFF Sequence
The Interval of Power-ON Sequence and Power-OFF Sequence is selected by POW Wait VOUTx(Note 1) registers.
POW Wait VOUTx(Note 1) registers’ value can be changed by EEPROM. Regarding default value of each registers,
please refer register map.
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5.2.12 POW Setting – continued
Table 24: PON/POFF Interval

PON_WAIT_VOUTx(Note 1)
/ POFF_WAIT_VOUTx(Note 1)
Interval
PON_WAIT_PRESETB
/ POFF_WAIT_PRESETB
0x0 2 µs
0x1 500 µs
0x2 1 ms
0x3 2 ms
0x4 4 ms
0x5 5 ms
0x6 8 ms
0x7 10 ms
0x8 15 ms
0x9 20 ms
0xA 25 ms
0xB 30 ms
0xC 40 ms
0xD 45 ms
0xE 50 ms
0xF 60 ms
Please set Power-OFF interval not to exceed totally 400 ms (Power-OFF Sequence Hang Up Timer).
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5.2.13 VOUT Voltage Tune / OVD SET / UVD SET
These VOUT voltage tuning registers are set via external EEPROM.

V1_
VOUT1 TUNE 0x50 - - - - VOUT1_TUNE[2:0] RO 0x00
SIGN
V1_SIGN VOUT1 Sign Bit

0: Plus
1: Minus
VOUT1_TUNE[2:0] VOUT1 Tuning Bit

VOUT1 output voltage is tuned from default value (5.0 V) by these registers. Step: 100 mV.
Table 25: VOUT1 Tuning Voltage

VOUT1_TUNE[2:0] Tuning Voltage (mV)
0x0 0
0x1 100
0x2 200
0x3 300
0x4 400
0x5 500
0x6 Clipped to 500
0x7 Clipped to 500

VOUT1 OVD SET 0x51 - VOUT1_OVD_SET[6:0] R/W 0x43
VOUT1_OVD_SET[6:0] VOUT1 OVD setting. Step: 5 mV default 0x43: 340 mV

By setting this register as 0x00, VOUT1 OVD function is disabled.
Table 26: VOUT1 OVD Voltage

VOUT1_OVD_SET[6:0] OVD Voltage (mV)
0x00 Function Disable

0x01 to 0x2B Clipped to 225
0x2C 225
0x2D 230
…… ……
…… ……
0x54 425
0x55 to 0x7F Clipped to 425
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5.2.13 VOUT Voltage Tune / OVD SET / UVD SET - continued

VOUT1 UVD SET 0x52 - VOUT1_UVD_SET[6:0] R/W 0x43
VOUT1_UVD_SET[6:0] VOUT1 UVD setting. Step: 5 mV default 0x43: 340 mV

By setting this register as 0x00, VOUT1 UVD function is disabled.
Table 27: VOUT1 UVD Voltage

VOUT1_UVD_SET[6:0] UVD Voltage (mV)

0x01 to 0x2B Clipped to 225
0x2C 225
0x2D 230
…… ……
…… ……
0x54 425

V2_
VOUT2 TUNE 0x53 - - - - VOUT2_TUNE[2:0] RO 0x00
SIGN

0: Plus
1: Minus


0x0 0
0x1 20
0x2 40
0x3 60
0x4 80
0x5 100
0x6 120
0x7 140

VOUT2 OVD SET 0x54 - VOUT2_OVD_SET[6:0] R/W 0x37



0x10 17
0x11 18
…… ……
…… ……
0x6D 110
0x6E to 0x7F Clipped to 110
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VOUT2 UVD SET 0x55 - VOUT2_UVD_SET[6:0] R/W 0x37
VOUT2_UVD_SET[6:0] VOUT2 UVD setting. Step: 1 mV default 0x37: 56 mV



0x10 17
0x11 18
…… ……
…… ……
0x6D 110

V3_
VOUT3 TUNE 0x56 - - VOUT3_TUNE[4:0] RO 0x00
SIGN

0: Plus
1: Minus

VOUT3 output voltage is tuned from default value (1.35 V, 1.5 V) by these registers. Step: 10 mV.

0x0 0
0x1 10
0x2 20
…… ……
…… ……
0x1D 290
0x1E 300
0x1F 310
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VOUT3 OVD SET 0x57 - VOUT3_OVD_SET[6:0] R/W 0x3E/0x27
VOUT3_OVD_SET[6:0] VOUT3 OVD setting. Step: 1mV

Default value is determined by DDR_SEL (pin) condition.
DDR_SEL (pin) = L: Default value is 0x3E (63 mV).
DDR_SEL (pin) = H: Default value is 0x27 (40 mV).


0x10 17
0x11 18
…… ……
…… ……
0x6D 110

VOUT3 UVD SET 0x58 - VOUT3_UVD_SET[6:0] R/W 0x23/0x27
VOUT3_UVD_SET[6:0] VOUT3 UVD setting. Step: 1mV

Default value is determined by DDR_SEL (pin) condition.
DDR_SEL (pin) = L: Default value is 0x23 (36 mV).
DDR_SEL (pin) = H: Default value is 0x27 (40 mV).


0x10 17
0x11 18
…… ……
…… ……
0x6D 110
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V4_
VOUT4 TUNE 0x59 - - VOUT4_TUNE[4:0] RO 0x00
SIGN

0: Plus
1: Minus


0x0 0
0x1 10
0x2 20
…… ……
…… ……
0x1D 290
0x1E 300
0x1F 310

VOUT4 OVD SET 0x5A - VOUT4_OVD_SET[6:0] R/W 0x19



0x10 17
0x11 18
…… ……
…… ……
0x6D 110

VOUT4 UVD SET 0x5B - VOUT4_UVD_SET[6:0] R/W 0x19
VOUT4_UVD_SET[6:0] VOUT4 UVD setting. Step: 1mV default 0x19: 26 mV



0x10 17
0x11 18
…… ……
…… ……
0x6D 110
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VL1_
VOUTL1 TUNE 0x5C - - - - VOUTL1_TUNE[2:0] RO 0x00
SIGN
VL1_SIGN VOUTL1 Sign Bit

0: Plus
1: Minus
VOUTL1_TUNE[2:0] VOUTL1 Tuning Bit

VOUTL1 output voltage is tuned from default value (2.5 V) by these registers. Step: 40 mV.
Table 37: VOUTL1 Tuning Voltage

VOUTL1_TUNE[2:0] Tuning Voltage (mV)
0x0 0
0x1 40
0x2 80
0x3 120
0x4 160
0x5 200
0x6 240
0x7 280

VOUTL1 OVD SET 0x5D - VOUTL1_OVD_SET[6:0] R/W 0x40
VOUTL1_OVD_SET[6:0] VOUTL1 OVD setting. Step: 2 mV default 0x40: 130 mV

By setting this register as 0x00, VOUTL1 OVD function is disabled.
Table 38: VOUTL1 OVD Voltage

VOUTL1_OVD_SET[6:0] OVD Voltage (mV)

0x10 34
0x11 36
…… ……
…… ……
0x6D 220

VOUTL1 UVD SET 0x5E - VOUTL1_UVD_SET[6:0] R/W 0x40
VOUTL1_UVD_SET[6:0] VOUTL1 UVD setting. Step: 2 mV default 0x40: 130 mV

By setting this register as 0x00, VOUTL1 UVD function is disabled.
Table 39: VOUTL1 UVD Voltage

VOUTL1_UVD_SET[6:0] UVD Voltage (mV)

0x10 34
0x11 36
…… ……
…… ……
0x6D 220
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5.2.14 VOUTS1 OCW SET

0x10/
VOUTS1 OCW SET 0x5F - - VOUTS1_OCW_SET[5:0] R/W
0x06
VOUTS1_OCW_SET[5:0] VOUTS1 OCW setting. Step: 50 mA (Internal Mode), 10 mV (External Mode)

By setting this register as 0x00, VOUTS1 OCW function is disabled.
Default value is determined by GATECNT (pin) condition.
GATECNT (pin) = L: Default value is 0x10 (Internal: 800 mA).
GATECNT (pin) = H: Default value is 0x06 (External: 70 mV).
Table 40: VOUTS1 OCW Current (Internal) and Voltage (External)

VOUTS1_OCW_SET[5:0] Internal OCW Current (mA) External OCW Voltage (mV)
0x00 Function Disable Function Disable

0x01 to 0x03 Clipped to 200 Clipped to 50
0x04 200 50
0x05 250 60
0x06 300 70
…… …… ……
0x10 800 170
…… …… ……
0x18 1,200 250
0x19 to 0x3F Clipped to 1,200 Clipped to 250
Internal OCW Current has ±50 % of deviation.

This is because it depends on Ron of internal SW.
5.2.15 VOUTS1 OCP SET

0x16/
VOUTS1 OCP SET 0x60 - - VOUTS1_OCP_SET[5:0] R/W
0x08
VOUTS1_OCP_SET[5:0] VOUTS1 OCP setting. Step: 50 mA (Internal Mode), 10 mV (External Mode)

By setting this register as 0x00, VOUTS1 OCP function is disabled.
Default value is determined by GATECNT (pin) condition.
GATECNT (pin) = L: Default value is 0x16 (Internal: 1,100 mA).
GATECNT (pin) = H: Default value is 0x08 (External: 90 mV).
Table 41: VOUTS1 OCP Current (Internal) and Voltage (External)

VOUTS1_OCP_SET[5:0] Internal OCP Current (mA) External OCP Voltage (mV)
0x00 Function Disable Function Disable

0x00 to 0x05 Clipped to 300 Clipped to 70
0x06 300 70
0x07 350 80
0x08 400 90
…… …… ……
0x16 1,100 230
…… …… ……
0x1B 1,350 280
0x1C to 0x3F Clipped 1,350 Clipped to 280
Internal OCP Current has ±50 % of deviation.

This is because it depends on Ron of internal SW.
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5.2.16 Diglitch Time

Deglitch Time 0x61 - UVD_OCW_DEG_TIM[2:0] - OVD_DEG_TIM[2:0] R/W 0x33
OVD_DEG_TIM[2:0] Select OVD Deglitch Time
UVD_OCW_DEG_TIM[2:0] Select UVD and OCW Deglitch Time
0x0 : 0.5 µs Deglitch Time

0x1 : 25 µs Deglitch Time
0x4 to 0x7: 100 µs Deglitch Time
(Note) Deglitch time is only time constructed in Logic. It is added 3 µs (typ) the delay of the analog circuit part.
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6. Typical Performance Curves
Unless otherwise specified: VIN = 3.3 V, Ta = 25 °C, IOUT = 0 A
Line Regulation
5.20 1.86
5.15
1.84
5.10
1.82
5.05
VOUT2 [V]
VOUT1 [V]
5.00 1.80
4.95
1.78
4.90
1.76
4.85
4.80 1.74
3.00 3.30 3.60 3.00 3.30 3.60
VIN [V] VIN [V]
Figure 40. VOUT1 Output Voltage vs VIN Figure 41. VOUT2 Output Voltage vs VIN
1.40 1.55
1.39 1.54
1.38 1.53
1.37 1.52
VOUT3 [V]
1.36 1.51
VOUT3 [V]
1.35 1.50
1.34 1.49
1.33 1.48
1.32 1.47
1.31 1.46
1.30 1.45
3.00 3.30 3.60 3.00 3.30 3.60
VIN [V] VIN [V]
Figure 42. VOUT3 Output Voltage vs VIN Figure 43. VOUT3 Output Voltage vs VIN
(VOUT3 = 1.35 V Setting) (VOUT3 = 1.5 V Setting)
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6.1 Line Regulation - continued
1.07 2.60
1.06
1.05 2.55
VOUTL1 [V]
1.04
VOUT4 [V]
1.03 2.50
1.02
1.01 2.45
1.00
0.99 2.40
3.00 3.30 3.60 3.00 3.30 3.60
VIN [V] VIN [V]
Figure 44. VOUT4 Output Voltage vs VIN Figure 45. VOUTL1 Output Voltage vs VIN
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6. Typical Performance Curves – continued
Load Regulation
5.20 1.86
5.15
1.84
5.10
1.82
5.05
VOUT1 [V]
VOUT2 [V]
5.00 1.80
4.95
1.78
4.90
1.76
4.85
4.80 1.74
0 100 200 0.00 0.50 1.00
IOUT [mA] IOUT [A]
Figure 46. VOUT1 Output Voltage vs IOUT Figure 47. VOUT2 Output Voltage vs IOUT
1.40 1.55
1.39 1.54
1.38 1.53
1.37 1.52
VOUT3 [V]
VOUT3 [V]
1.36 1.51
1.35 1.50
1.34 1.49
1.33 1.48
1.32 1.47
1.31 1.46
1.30 1.45
0.00 1.00 2.00 0.00 1.00 2.00
IOUT [A] IOUT [A]
Figure 48. VOUT3 Output Voltage vs IOUT Figure 49. VOUT3 Output Voltage vs IOUT
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6.2 Load Regulation - continued
1.07 2.60
1.06
1.05 2.55
1.04
VOUTL1 [V]
VOUT4 [V]
1.03 2.50
1.02
1.01 2.45
1.00
0.99 2.40
0.00 1.00 2.00 3.00 4.00 5.00 0 50 100 150
IOUT [A] IOUT [mA]
Figure 50. VOUT4 Output Voltage vs IOUT Figure 51. VOUTL1 Output Voltage vs IOUT
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Power Efficiency
100 100
90 90
80 80
Power Efficiency [%]

70 70
60
VOUT2
60
VOUT1
50 50
40 40
30 30
20 20
10 10
0 0
0 50 100 150 200 0 0.25 0.5 0.75 1
IOUT [mA] IOUT [A]
Figure 52. VOUT1 Power Efficiency vs IOUT Figure 53. VOUT2 Power Efficiency vs IOUT
100
100
90 90
80 80
70
70
VOUT3 (1.5 V)
VOUT3 (1.35 V)
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0
IOUT [A] IOUT [A]
Figure 54. VOUT3 Power Efficiency vs IOUT Figure 55. VOUT3 Power Efficiency vs IOUT
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6.3 Power Efficiency - continued
100
90
80
70
60
VOUT4
50
40
30
20
10
0
0.0 1.0 2.0 3.0 4.0 5.0
IOUT [A]
Figure 56. VOUT4 Power Efficiency vs IOUT
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Power ON Waveform
VOUT1 (1 V/div)
VOUT2 (500 mV/div)
SW1 (2 V/div)
SW2 (2 V/div)
500 µs/div 500 µs/div
Figure 57. VOUT1 Power ON Waveform Figure 58. VOUT2 Power ON Waveform
VOUT3 (500 mV/div) VOUT3 (500 mV/diV)
SW3 (2 V/div) SW3 (2 V/div)
Figure 59. VOUT3 Power ON Waveform Figure 60. VOUT3 Power ON Waveform
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6.4 Power ON Waveform - continued
VOUTL1 (500 mV/div)

VOUT4 (500 mV/div)
SW4 (2 V/div)
SW5 (2 V/div)
Figure 61. VOUT4 Power ON Waveform Figure 62. VOUTL1 Power ON Waveform
VOUTS1 (500 mV/div)
500 µs/div
Figure 63. VOUTS1 Power ON Waveform
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Power OFF Waveform
VOUT1 (1 V/div)
VOUT2 (500 mV/div)
2 ms/div 5 ms/div
Figure 64. VOUT1 Power OFF Waveform Figure 65. VOUT2 Power OFF Waveform
VOUT3 (500 mV/div)

VOUT3 (500 mV/div)
5 ms/div 5 ms/div
Figure 66. VOUT3 Power OFF Waveform Figure 67. VOUT3 Power OFF Waveform
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6.5 Power OFF Waveform - continued
VOUT4 (500 mV/div)
VOUTL1 (500 mV/div)

SW4 (2 V/div)
SW5 (2 V/div)
5 ms/div 2 ms/div
Figure 68. VOUT4 Power OFF Waveform Figure 69. VOUTL1 Power OFF Waveform
VOUTS1 (500 mV/div)
500 µs/div
Figure 70. VOUTS1 Power OFF Waveform
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Load Transient
IOUT (50 mA/div) IOUT (200 mA/div)
VOUT (20 mV/div) VOUT (10 mV/div)
Figure 71. VOUT1 Load Transient Figure 72. VOUT2 Load Transient
(IOUT = 0 A to 100 mA (SR = 100 mA/µs)) (IOUT = 0 A to 0.5 A (SR = 1 A/µs))
IOUT (500 mA/div) IOUT (500 mA/div)
Figure 73. VOUT3 Load Transient Figure 74. VOUT3 Load Transient
(VOUT3 = 1.35 V Setting, IOUT = 0 A to 1 A (SR = 1 A/µs)) (VOUT3 = 1.5 V Setting, IOUT = 0 A to 1 A (SR = 1 A/µs))
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6.6 Load Transient- continued
IOUT (1 A/div) IOUT (30 mA/div)
Figure 75. VOUT4 Load Transient Figure 76. VOUTL1 Load Transient
(IOUT = 0 A to 2.05 A (SR = 1 A/µs)) (IOUT = 0 A to 75 mA (SR = 100 mA/µs)
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7. Operational Notes
1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
pins.
2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the digital
and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block.
Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the
capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However,
pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground due
to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below ground will
not cause the IC and the system to malfunction by examining carefully all relevant factors and conditions such as motor
characteristics, supply voltage, operating frequency and PCB wiring to name a few.
4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground
caused by large currents. Also ensure that the ground traces of external components do not cause variations on the
ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating conditions.
The characteristic values are guaranteed only under the conditions of each item specified by the electrical characteristics.
6. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of
connections.
7. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always
be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent
damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage.
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7. Operational Notes – continued
8. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-
pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor Transistor (NPN)
Pin A Pin B B Pin B
C
Pin A E
P B C
P+ P+ P+ N P P+
N N N N Parasitic N N N
E
Elements
Parasitic
P Substrate P Substrate
Elements
GND GND GND GND
Parasitic Parasitic N Region
Elements Elements close-by
Figure 77. Example of Monolithic IC Structure
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7. Operational Notes – continued
11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with temperature
and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Circuit (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be
within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. The IC should be powered
down and turned ON again to resume normal operation because the TSD circuit keeps the outputs at the OFF state even
if the Tj falls below the TSD threshold.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat
damage.
13. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This protection
circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should not be used
in applications characterized by continuous operation or transitioning of the protection circuit.
14. Functional Safety

“ISO 26262 process compliant to support ASIL-*”
A product that has been developed based on an ISO 26262 design process compliant to the ASIL level described in the
datasheet.
“Safety mechanism is implemented to support functional safety (ASIL-*)”
A product that has implemented safety mechanism to meet ASIL level requirements described in the datasheet.
“Functional safety supportive automotive products”
A product that has been developed for automotive use and is capable of supporting safety analysis with regard to the
functional safety.
(Note) “ASIL-*” stands for the ratings of “ASIL-A”, “-B”, “-C” or “-D” specified by each product's datasheet.
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8. Revision History
Date Revision Changes

02.Oct.2020 001 New Release
TSZ22111 • 15 • 001 02.Oct.2020 Rev.001
Notice
Precaution on using ROHM Products
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN USA EU CHINA
CLASSⅢ CLASSⅡb
CLASSⅢ CLASSⅢ
CLASSⅣ CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
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a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
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H2S, NH3, SO2, and NO2
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[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.
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Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
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Datasheet
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Datasheet

Buck Converter DDR

Buck Converter VD10A

Buck Converter VD10B

1 PGND2 - Power GND for VOUT2

Pin Description – continued

Physical Dimension and Packaging Infomation

Part Number Package Product Rank

VQFN56FV8080 (TOP VIEW)

Part Number Marking

5.2.10 I2C FuSa Mode Error Bit Location ....................................................................................................................... 58

Table 1: Output Voltage Table of Each State ......................................................................................................................... 13

Figure 1. An Example of Signal Line Diagram for PMIC ........................................................................................................ 14

Figure 28. Interruption Factor/Mask/Request ........................................................................................................................ 43

Output Voltage Table

Table 1: Output Voltage Table of Each State

VD50 VOUT1 5.0 0.2 OFF ON

VD18 VOUT2 1.8 1.0 OFF ON

VS33 VOUTS1 VIN7 0.3 OFF ON

1. Device Feature – continued

Signal Line Diagram for PMIC

Bidirectional Voltage Level

INTB (Open Drain)

PRESETB (Open Drain)

PGD (Open Drain)

Figure 1. An Example of Signal Line Diagram for PMIC

Buck Converter VD10B

LDO25 VL25 LOAD

Figure 2. Application Circuit

Figure 3 shows the case of external FET for VOUTS1.

Figure 3. Application Circuit (External MOS)

Table 2: Application Circuit Components List

C_VINx - 10 - μF MURATA GCM21BR70J106KE22 2012

Absolute Maximum Ratings

Table 3: Absolute Maximum Ratings

Input Voltage 2 FB1, FB2, FB3, FB4 -0.3 to +7.0 V

Output Voltage 1 VFIL -0.3 to VIN+0.3 V

Output Voltage 2 VLSO -0.3 to VIN1+0.3 V

Output Voltage 3 VOUT1 -0.3 to +7.0 V

Output Voltage 4 VOUTL1, VOUTS1 -0.3 to VINx+0.3 V

Output Voltage 5 GATECNT -0.3 to +7.0 V

SW to GND Voltage 1 SW2, SW3, SW4, SW5 -0.3 to VINx+0.3 V

SW to GND Voltage 2 SW1 -0.3 to +10.0 V

Logic Input Voltage 1 RSTB, SDA, SCL -0.3 to +7.0 V

Logic Input Voltage 3 SEQCNT[0], SEQCNT[1] -0.3 to VIN+0.3 V

Logic Output Voltage 1 INTB, PGD, WDO -0.3 to +7.0 V

Logic Output Voltage 2 PRESETB -0.3 to VIN+0.3 V

Logic Output Pin Current Low 2 SDA, SCL -20.0 mA

Storage Temperature Range Tstg -55 to +150(Note 1) °C

3. Electrical Characteristics - continued

Layer Number of Thermal Via(Note 5)

3. Electrical Characteristics - continued

Recommended Operating Conditions

Table 4: Recommended Operating Conditions

Power Supply Voltage VIN 3.0 3.3 3.6 V

Power Supply Voltage 1 VIN1 3.0 3.3 3.6 V

Power Supply Voltage 2 VIN2 3.0 3.3 3.6 V

Power Supply Voltage 3 VIN3 3.0 3.3 3.6 V