IRFR9310, IRFU9310, SiHFR9310, SiHFU9310

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Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
• P-Channel
VDS (V) - 400
• Surface Mount (IRFR9310, SiHFR9310)
RDS(on) () VGS = - 10 V 7.0
• Straight Lead (IRFU9310, SiHFU9310)
Qg (Max.) (nC) 13
• Advanced Process Technology
Qgs (nC) 3.2
• Fast Switching
Qgd (nC) 5.0
• Fully Avalanche Rated
Configuration Single
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
S
DESCRIPTION
DPAK IPAK Third generation power MOSFETs from Vishay utilize
(TO-252) (TO-251) advanced processing techniques to achieve low
D G on-resistance per silicon area. This benefit, combined with
D
the fast switching speed and ruggedized device design that
power MOSFETs are well known for, provides the designer
S with an extremely efficient and reliable device for use in a
G D S wide variety of applications.
G
D The DPAK is designed for surface mounting using vapor
P-Channel MOSFET
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU/SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.

ORDERING INFORMATION
Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251)
Lead (Pb)-free and
SiHFR9310-GE3 SiHFR9310TRL-GE3 SiHFR9310TR-GE3 SiHFR9310TRR-GE3 SiHFU9310-GE3
Halogen-free
IRFR9310PbF IRFR9310TRLPbFa IRFR9310TRPbFa IRFR9310TRRPbFa IRFU9310PbF
Lead (Pb)-free
SiHFR9310-E3 SiHFR9310TL-E3a SiHFR9310T-E3a SiHFR9310TR-E3a SiHFU9310-E3
Note
a. See device orientation.

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS - 400
V
Gate-Source Voltage VGS ± 20
TC = 25 °C - 1.8
Continuous Drain Current VGS at - 10 V ID
TC = 100 °C - 1.1 A
Pulsed Drain Currenta IDM - 7.2
Linear Derating Factor 0.40 W/°C
Single Pulse Avalanche Energyb EAS 92 mJ
Repetitive Avalanche Currenta IAR - 1.8 A
Repetitive Avalanche Energya EAR 5.0 mJ
Maximum Power Dissipation TC = 25 °C PD 50 W
Peak Diode Recovery dV/dtc dV/dt - 24 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150
°C
Soldering Recommendations (Peak Temperature)d for 10 s 300
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 57 mH, Rg = 25 , IAS = - 1.8 A (see fig. 12).
c. ISD  - 1.1 A, dI/dt  450 A/μs, VDD  VDS, TJ  150 °C.
d. 1.6 mm from case.

S13-0166-Rev. D, 04-Feb-13 1 Document Number: 91284

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - - 110
Maximum Junction-to-Ambient
RthJA - - 50 °C/W
(PCB Mount)a
Maximum Junction-to-Case (Drain) RthJC - - 2.5
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 μA - 400 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.41 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 μA - 2.0 - - 4.0 V
Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA
VDS = - 400 V, VGS = 0 V - - - 100
Zero Gate Voltage Drain Current IDSS μA
VDS = - 320 V, VGS = 0 V, TJ = 125 °C - - - 500
Drain-Source On-State Resistance RDS(on) VGS = - 10 V ID = - 1.1 Ab - - 7.0 
Forward Transconductance gfs VDS = - 50 V, ID = - 1.1 A 0.91 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V, - 270 -
Output Capacitance Coss VDS = - 25 V, - 50 - pF
Reverse Transfer Capacitance Crss f = 1.0 MHz, see fig. 5 - 8.0 -
Total Gate Charge Qg - - 13
ID = - 1.1 A, VDS = - 320 V,
Gate-Source Charge Qgs VGS = - 10 V - - 3.2 nC
see fig. 6 and 13b
Gate-Drain Charge Qgd - - 5.0
Turn-On Delay Time td(on) - 11 -
Rise Time tr VDD = - 200 V, ID = - 1.1 A, - 10 -
ns
Turn-Off Delay Time td(off) Rg = 21 , RD = 180 , see fig. 10b - 25 -
Fall Time tf - 24 -

Internal Drain Inductance LD Between lead, D

- 4.5 -
6 mm (0.25") from
package and center of G
nH
Internal Source Inductance LS die contactc - 7.5 -
S

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current IS MOSFET symbol D

- - - 1.9
showing the
A
integral reverse G

Pulsed Diode Forward Currenta ISM p - n junction diode S - - - 7.6

Body Diode Voltage VSD TJ = 25 °C, IS = - 1.1 A, VGS = 0 Vb - - - 4.0 V

Body Diode Reverse Recovery Time trr - 170 260 ns
TJ = 25 °C, IF = -1.1 A, dI/dt = 100 A/μsb
Body Diode Reverse Recovery Charge Qrr - 640 960 nC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. This is applied for IPAK, LS of DPAK is measured between lead and center of die contact.

S13-0166-Rev. D, 04-Feb-13 2 Document Number: 91284

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

10 10
VGS
TOP -15V
-10V

-I D , Drain-to-Source Current (A)

-I D , Drain-to-Source Current (A)

-8.0V
-7.0V
-6.0V
-5.5V TJ = 25 ° C
-5.0V
BOTTOM -4.5V
TJ = 150 ° C

1 1

-4.5V

20μs PULSE WIDTH V DS = -50V

TJ = 25 °C 20μs PULSE WIDTH
0.1 0.1
1 10 100 4 5 6 7 8 9 10
-VDS , Drain-to-Source Voltage (V) -VGS, Gate-to-Source Voltage (V)

Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics

10 2.5
VGS ID = -1.8A
RDS(on) , Drain-to-Source On Resistance

TOP -15V
-10V
-I D , Drain-to-Source Current (A)

-8.0V
-7.0V
-6.0V 2.0
-5.5V
-5.0V
BOTTOM -4.5V
(Normalized)

1.5

-4.5V 1.0

0.5

20μs PULSE WIDTH

TJ = 150 °C VGS = -10V
0.1 0.0
1 10 100 -60 -40 -20 0 20 40 60 80 100 120 140 160
-VDS , Drain-to-Source Voltage (V) TJ , Junction Temperature ( °C)

Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature

S13-0166-Rev. D, 04-Feb-13 3 Document Number: 91284

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Vishay Siliconix

500 10
VGS = 0V, f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd

-ISD , Reverse Drain Current (A)

400 Coss = Cds + Cgd
C, Capacitance (pF)

Ciss
300 TJ = 150 ° C
1

200
TJ = 25 ° C
Coss

100
Crss
V GS = 0 V
0 0.1
1 10 100 1.0 2.0 3.0 4.0 5.0
-VDS , Drain-to-Source Voltage (V) -VSD ,Source-to-Drain Voltage (V)

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage

20 100
ID = -1.1A
OPERATION IN THIS AREA LIMITED
VDS =-320V BY RDS(on)
-VGS , Gate-to-Source Voltage (V)

VDS =-200V
16 VDS =-80V
-IID , Drain Current (A)

10 10us
12

100us
8
1
1ms
4
TC = 25 °C
10ms
FOR TEST CIRCUIT TJ = 150 °C
SEE FIGURE 13 Single Pulse
0 0.1
0 4 8 12 16 10 100 1000
QG , Total Gate Charge (nC) -VDS , Drain-to-Source Voltage (V)

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area

S13-0166-Rev. D, 04-Feb-13 4 Document Number: 91284

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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Vishay Siliconix

RD
2.0 VDS

VGS
D.U.T.
Rg -
1.6 +VDD
-ID , Drain Current (A)

- 10 V
1.2 Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

0.8 Fig. 10a - Switching Time Test Circuit

0.4 td(on) tr td(off) tf

VGS
10 %
0.0
25 50 75 100 125 150
TC , Case Temperature ( °C)
90 %
VDS
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms

10
Thermal Response (Z thJC )

D = 0.50
1
0.20

0.10
0.05
PDM
0.02 SINGLE PULSE
0.1 0.01 (THERMAL RESPONSE) t1
t2

Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

S13-0166-Rev. D, 04-Feb-13 5 Document Number: 91284

For technical questions, contact: hvm@vishay.com
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Vishay Siliconix

VDS L

IAS
Rg D.U.T. -
+ VDD
A
IAS
- 20 V Driver
tp 0.01 Ω

tp

15 V
VDS

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

300
ID
EAS , Single Pulse Avalanche Energy (mJ)

TOP -0.49A
250 -0.7A
BOTTOM -1.1A

200

150

100

50

0
25 50 75 100 125 150
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Current regulator
Same type as D.U.T.

QG 50 kΩ
- 10 V 12 V 0.2 µF
0.3 µF

QGS QGD -

D.U.T. + VDS

VG
VGS

- 3 mA

Charge
IG ID
Current sampling resistors

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

S13-0166-Rev. D, 04-Feb-13 6 Document Number: 91284

For technical questions, contact: hvm@vishay.com
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Peak Diode Recovery dV/dt Test Circuit

D.U.T. +
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- - +

Rg • dV/dt controlled by Rg +
• ISD controlled by duty factor “D” VDD
• D.U.T. - device under test -

Note
• Compliment N-Channel of D.U.T. for driver

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = - 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current

ISD
Ripple ≤ 5 %

Note
a. VGS = - 5 V for logic level and - 3 V drive devices

Fig. 14 - For P-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91284.

S13-0166-Rev. D, 04-Feb-13 7 Document Number: 91284

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
www.vishay.com
Vishay Siliconix
TO-252AA Case Outline
E A MILLIMETERS INCHES
C2
b3
DIM. MIN. MAX. MIN. MAX.
A 2.18 2.38 0.086 0.094

L3
A1 - 0.127 - 0.005
b 0.64 0.88 0.025 0.035
b2 0.76 1.14 0.030 0.045
D

b3 4.95 5.46 0.195 0.215

H
C 0.46 0.61 0.018 0.024
C2 0.46 0.89 0.018 0.035
L4

D 5.97 6.22 0.235 0.245

L5

L
gage plane height (0.5 mm)

D1 4.10 - 0.161 -
E 6.35 6.73 0.250 0.265
E1 4.32 - 0.170 -
b b2 C
e H 9.40 10.41 0.370 0.410
A1
e1 e 2.28 BSC 0.090 BSC
e1 4.56 BSC 0.180 BSC
L 1.40 1.78 0.055 0.070
L3 0.89 1.27 0.035 0.050
D1

L4 - 1.02 - 0.040
L5 1.01 1.52 0.040 0.060
ECN: T13-0359-Rev. O, 03-Jun-13
DWG: 5347
E1
Notes
• Dimension L3 is for reference only.
• Xi’an, Mingxin, and GEM SH actual photo.

Revision: 03-Jun-13 1 Document Number: 71197

For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
Vishay Siliconix

TO-251AA (HIGH VOLTAGE)

4 3 A
E1 Thermal PAD E A
4
b4 0.010 0.25 M C A B c2
L2 4 A
θ2 θ1
D1 4
B
C

D
3 Seating
5 plane

L1 L3 C C
(Datum A)

L
B B

A
3 x b2 A1
c
3xb
View A - A 0.010 0.25 M C A B
2xe

Base
5 metal
Plating
b1, b3
Lead tip
(c) c1 5

(b, b2)
Section B - B and C - C

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 -
A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265
b 0.64 0.89 0.025 0.035 E1 4.32 - 0.170 -
b1 0.65 0.79 0.026 0.031 e 2.29 BSC 2.29 BSC
b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380
b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090
b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050
c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060
c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15'
c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35'
D 5.97 6.22 0.235 0.245
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.

Document Number: 91362 www.vishay.com

Revision: 15-Sep-08 1
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)

0.224
(5.690)

(6.180)
0.243
(10.668)
0.420

(2.202)
0.087
(2.286)
0.090

0.180 0.055
(4.572) (1.397)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index Return to Index

APPLICATION NOTE

Document Number: 72594 www.vishay.com

Revision: 21-Jan-08 3
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Material Category Policy

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12 1 Document Number: 91000