[Date] Project Report

[Document subtitle]

Alok Singh

PROJECT REPORT | [Document subtitle]

 Summer Training Report
On
Field Programmable Gate Arrays (FPGAs)
At

Submitted To: -
Defence Electronics Research Laboratory
Defense Research and Development Organization
Chandrayangutta Lines, Hyderabad- 500005, Telangana
Submitted by: -
Alok Singh
Under the Supervision of: -
Shri K. Bhaskar Kumar
&
Shri Radhakrishann
Scientist ‘E’
DLRL, DRDO, Hyderabad - 05
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 CERTIFICATE

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 ACKNOWLEDGMENT

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 ABSTRACT

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 CONTENT
Certificate……………………………………………………………………………………………………………ii
Acknowledgment………………………………………………………………………………………………. iii
Abstract……………………………………………………………………………………………………………… iv

Topic Page no.

Field Programmable Gate Arrays (FPGA)
1. Introduction
1.1 Historical Overview
1.2 Design
1.2.1 Logic blocks
1.2.2 Hard blocks
1.2.3 Integration
1.2.4 Clocking
1.2.5 3D architecture
2. Virtex -4
2.1 Description
2.2 System Blocks
2.3 Virtex-4 Family
2.3.1 System Blocks Specific to the Virtex-4 FX.
2.4 Virtex-4 FPGA Features
2.5 Virtex-4 FPGA ordering information.
2.6 Nallatech virtex-4 based board.
3. Virtex-5
3.1 Description
3.2 virtex-5 FPGA Logic
3.3 Virtex-5 Family
3.3.1 System blocks specific to the LXT, SXT, TXT and FXT
3.4 Virtex-5 Boards ML50x
4. Virtex-7
4.1 Description
4.2 Specifications
4.3 Virtex-7 Series
4.3.1 Spartan-7
4.3.2 Artix-7
4.3.3 Kintex-7
4.4 VC707 Evaluation Board
5. Zynq
5.1 Zynq 7000s
5.2 Zynq 7000
5.3 Zynq Ultra Scale + RFSoC ZCU216
5.3.1 Overview
5.3.2 Features

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 INTRODUCTION
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured
after manufacturing. The FPGA configuration is generally specified using a hardware description
language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit
diagrams were previously used to specify the configuration, but this is increasingly rare due to
the advent of electronic design automation tools.
FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable
interconnects allowing blocks to be wired together. Logic blocks can be configured to perform
complex combinational functions or act as simple logic gates like AND and XOR. In most
FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more
complete blocks of memory. Many FPGAs can be reprogrammed to implement different logic
functions, allowing flexible reconfigurable computing as performed in computer software.
FPGAs have a remarkable role in embedded system development because they can start
system software development simultaneously with hardware, enable system performance
simulations at a very early phase of the development, and allow various system trials and
design iterations before finalizing the system architecture.

History
In the late 1980s, the concept of FPGA was created through an experiment suggested by Steve
Casselman with funding from the Naval Surface Warfare Center. He proposed to create a
computing device with over 600,000 reprogrammable gates. His work was successful, and he
patented the creation in 1992.
The FPGA industry sprouted from programmable read-only memory (PROM)
and programmable logic devices (PLDs). PROMs and PLDs could be programmed in batches in
a factory or the field (field-programmable).
Altera was founded in 1983 and delivered the industry's first reprogrammable logic device in
1984 – the EP300 – which featured a quartz window in the package that allowed users to shine
an ultra-violet lamp on the die to erase the EPROM cells that held the device configuration.
Xilinx produced the first commercially viable field-programmable gate array in 1985 – the
XC2064. The XC2064 had programmable gates and programmable interconnects between
gates, the beginnings of modern technology and the market. The XC2064 had 64 configurable
logic blocks (CLBs), with two three-input lookup tables (LUTs).
The 1990s were a period of rapid growth for FPGAs, both in circuit sophistication and volume of
production. In the early 1990s, FPGAs were primarily used
in telecommunications and networking. By the end of the decade, FPGAs found their way into
consumer, automotive, and industrial applications.
By 2013, Altera (31 percent), Actel (10 percent), and Xilinx (36 percent) together represented
approximately 77 percent of the FPGA market.
Companies like Microsoft have started to use FPGAs to accelerate high-performance,
computationally intensive systems (like the data centers that operate their Bing search engine),
due to the performance per watt advantage FPGAs deliver. Microsoft began using FPGAs
to accelerate Bing in 2014, and in 2018 began deploying FPGAs across other data center
workloads for their Azure cloud computing platform.

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DESIGN
FPGAs can be used to implement any logical function that an ASIC can perform. As FPGA
designs employ very fast I/O rates and bidirectional data buses, it becomes a challenge to verify
the correct timing of valid data within setup time and hold time. Floor planning helps resource
allocation within FPGAs to meet these timing constraints.
Some FPGAs have analog features in addition to digital functions. The most common analog
feature is a programmable slew rate on each output pin, allowing the engineer to set low rates
on lightly loaded pins that would otherwise ring or couple unacceptably, and to set higher rates
on heavily loaded high-speed channels that would otherwise run too slowly. Also common are
quartz-crystal oscillator driver circuitry, on-chip resistance-capacitance oscillators, and phase-
locked loops with embedded voltage-controlled oscillators used for clock generation and
management as well as for high-speed serializer-deserializer (SERDES) transmit clocks and
receiver clock recovery.
Logic blocks; - The most common FPGA architecture consists of an array of logic
blocks called configurable logic blocks (CLBs), or logic array blocks (LABs), depending on the
vendor, I/O pads, and routing channels. Generally, all the routing channels have the same width
(number of signals). Multiple I/O pads may fit into the height of one row or the width of one
column in the array.
Hard blocks: - Modern FPGA families expand upon the above capabilities to include higher-
level functionality fixed in silicon. Having these common functions embedded in the circuit
reduces the area required and gives those functions increased performance compared to
building them from logical primitives. Examples of these include multipliers, generic DSP
blocks, embedded processors, high-speed I/O logic, and embedded memories.
Integration: - In 2012 the coarse-grained architectural approach was taken a step further by
combining the logic blocks and interconnects of traditional FPGAs with
embedded microprocessors and related peripherals to form a complete "system on a
programmable chip". This work mirrors the architecture created by Ron Perloff and Hanan
Potash of Burroughs Advanced Systems Group in 1982 which combined a reconfigurable CPU
architecture on a single chip called the SB24.
Clocking:- Most of the circuitry built inside of an FPGA is synchronous circuitry that requires
a clock signal. FPGAs contain dedicated global and regional routing networks for clock and
reset, typically as an incarnation of an H tree, so they can be delivered with minimal skew. Also,
FPGAs generally contain analog phase-locked loop and/or delay-locked loop components to
synthesize new clock frequencies as well as attenuate jitter. Complex designs can use multiple
clocks with different frequency and phase relationships, each forming separate clock domains.
3D architecture:- To shrink the size and power consumption of FPGAs, vendors such
as Tabula and Xilinx have introduced 3D or stacked architectures. Xilinx's approach stacks
several (three or four) active FPGA dies side by side on a silicon interposer – a single piece of
silicon that carries passive interconnect. The multi-die construction also allows different parts of
the FPGA to be created with different process technologies, as the process requirements are
different between the FPGA fabric itself and the very high-speed 28 Gbit/s serial transceivers.
An FPGA built in this way is called a heterogeneous FPGA.
Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting
other die/technologies to the FPGA using Intel's embedded multi_die interconnect bridge
(EMIB) technology.

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 Xilinx Virtex FPGA

Virtex CLB
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 VIRTEX – 4
Description: -
Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible
features, the Virtex®-4 family from Xilinx greatly enhances programmable logic design capabilities,
making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise three platform families—
LX, FX, and SX—offering multiple feature choices and combinations to address all complex applications.
The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC® processors (with a new APU
interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high-
speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4 FPGA
building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro,
and Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4
devices are produced on a state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer
technology.
System Blocks: -
• Xesium Clock Technology
o Up to twenty Digital Clock Manager (DCM) modules
o Companion Phase-Matched Clock Divider (PMCD) blocks
o Differential clocking structure for optimized low-jitter clocking and precise duty cycle
o 32 Global Clock networks
• Flexible Logic Resources
o Up to 40% speed improvement over previous generation devices.
o Cascadable variable shift registers or distributed memory capability.
o Up to 200,000 logic cells including:
- Up to 178,176 internal registers with clock enable (XC4VLX200)
- Up to 178,176 look-up tables (LUTs)
- Logic expanding multiplexers and I/O registers.
• 500 MHz XtremeDSP Slices
o Dedicated 18-bit x 18-bit multiplier, multiply-accumulator, or multiply-adder blocks.
o Optional 48-bit accumulator for multiply accumulate (MACC) operation.
o Up to 100% speed improvement over previous generation devices.
• 500 MHz Integrated Block Memory
o Up to 10 Mb of integrated block memory
o 18 Kbit blocks (memory and parity/sideband memory support).
o Configurations from 16K x 1 to 512 x 36 (4K x 4 to 512 x 36 for FIFO operation).
o Byte-write capability (connection to PPC405, etc.).
o Dedicated cascade routing to form 32K x 1 memory without using FPGA routing.
o Multi-rate FIFO support logic
- Full and Empty Flag support
- Fully programmable AF and AE Flags
- Synchronous/ Asynchronous Operation.
• Select I/O Technology
o Up to 960 user I/Os.
o Wide selections of I/O standards from 1.5V to 3.3V.
o Memory interface support for DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.
o Extremely high-performance
- 600 Mb/s HSTL & SSTL (on all single-ended I/O)
- 1 Gb/s LVDS (on all differential I/O pairs).

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 o Selected low-capacitance I/Os for improved signal integrity.
• Chip Sync Technology
o Integrated with SelectIO technology to simplify source-synchronous interfaces.
o Per-bit deskew capability built in all I/O blocks (variable input delay line).
o Dedicated I/O and regional clocking resources (pin and trees).
o Memory/Networking/Telecommunication interfaces up to 1 Gb/s+ DDR.
• Configuration
o 256-bit AES bitstream decryption provides intellectual property (IP) security.
o Improved bitstream error detection/correction capability.
o Fast Select MAP configuration.
o JTAG support.
• 90 nm Copper CMOS Process.
• 1.2V Core Voltage
• Flip-Chip Packaging including Pb-Free Package Choices.

Board Clocks
Family -
1. Virtex 4 LX: High-performance logic applications solution.
2. Virtex 4 SX: High-performance solution for digital signal processing (DSP) applications.
3. Virtex 4 FX: High-performance, full-featured solution for embedded platform applications.
System Blocks Specific to the Virtex-4 FX:
• RocketIO Multi-Gigabit Transceiver (MGT)
o Full-duplex serial transceiver (MGT) capable of 622 Mb/s to 6.5 Gb/s baud rates.
o 8B/10B, 64B/66B, user-defined FPGA logic, or no data encoding/decoding.
o Channel bonding support & CRC generation and checking.
o Programmable TX pre-emphasis or pre-equalization
o Programmable RX continuous time equalization
o Programmable RX decision feedback equalization
o User dynamic reconfiguration using secondary configuration bus

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 • PowerPC 405 Processor RISC Core
o Embedded PowerPC 405 processor (PPC405) core
- Up to 450 MHz operation
- Five-stage data path pipeline
- 16 KB instruction cache
- 16 KB data cache
- Enhanced instruction and data on-chip memory (OCM) controllers
- Additional frequency ratio options between PPC405 and Processor Local Bus.
o Auxiliary Processor Unit (APU) Interface for direct connection from PPC405 to
coprocessors in fabric
- APU can run at different clock rates
- Supports autonomous instructions: no pipeline stalls
- 32-bit instruction and 64-bit data
- 4-cycle cache line transfer
• Tri-Mode Ethernet Media Access Controller
o IEEE 802.3 compliant
o Operates at 10, 100, and 1,000 Mb/s.
o Supports tri-mode auto-detect.
o Fully monolithic 1000Base-X solution with RocketIO MGT.
o Implements SGMII through RocketIO MGT to external PHY device.
o Supports multiple PHY (MII, GMII, etc.) interfaces through an I/O resource.
o Receive and transmit statistics available through separate interfaces.
o Separate host and client interfaces.
o Support for jumbo frames & Flexible, user-configurable host interface
Vertex-4 FPGA Features:
• Input/Output (SelectIO) Blocks
IOBs are programmable and can be categorized as follows:
o Programmable single-ended or differential (LVDS) operation.
o Input block with an optional single data rate (SDR) or double data rate (DDR) register
o Output block with an optional SDR or DDR register • Bidirectional block.
o Per-bit deskew circuitry.
o Dedicated I/O and regional clocking resources.
o Built in data serializer/deserializer
The IOB registers are either edge-triggered D-type flip-flops or level-sensitive latches.
IOBs support the following single-ended standards: • LVTTL • LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) • PCI
(33 and 66 MHz) • PCI-X • GTL and GTLP • HSTL 1.5V and 1.8V (Class I, II, III, and IV) • SSTL 1.8V and 2.5V
(Class I and II).
• Configurable Logic Blocks (CLBs)
o A CLB resource is made up of four slices. Each slice is equivalent and contains:
• Two function generators (F & G)
• Two storage elements
• Arithmetic logic gates
• Large multiplexers
• Fast carry look-ahead chain
The function generators F & G are configurable as 4-input look-up tables (LUTs). Two slices in a CLB can
have their LUTs configured as 16-bit shift registers, or as 16-bit distributed RAM. In addition, the two
storage elements are either edge-triggered D-type flip-flops or level sensitive latches. Each CLB has
internal fast interconnect and connects to a switch matrix to access general routing resources.
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 • Block RAM
The block RAM resources are 18 Kb true dual-port RAM blocks, programmable from 16K x 1 to
512 x 36, in various depth and width configurations. Each port is totally synchronous and
independent, offering three “read-during-write” modes. Block RAM is cascadable to implement
large, embedded storage blocks.
• XtremeDSP Slices
The XtremeDSP slices contain a dedicated 18 x 18-bit 2’s complement signed multiplier, adder
logic, and a 48-bit accumulator. Each multiplier or accumulator can be used independently.
These blocks are designed to implement extremely efficient and high-speed DSP applications.
• Configuration
Virtex-4 devices are configured by loading the bitstream into internal configuration memory
using one of the following modes:
• Slave-serial mode
• Master-serial mode
• Slave SelectMAP mode
• Master SelectMAP mode
• Boundary-Scan mode (IEEE-1532)
Optional 256-bit AES decryption is supported on-chip (with software bitstream encryption)
providing Intellectual Property security.
Vertex-4 FPGA Ordering Information:

Nallatech (Virtex-4 based boards):

Nallatech has added four products to its COTS FPGA computing range, combining the processing and I/O
performance of Xilinx Virtex-4 FPGAs with enhancements to Nallatech’s DIME-II architecture including
host interface improvements and enhanced clocking.
The modules provide the option of Virtex-4 LX FPGAs with high performance logic capability, or the
Virtex-4 SX family optimised for DSP performance.
Nallatech’s (Cumnerauld, Scotland) roadmap for its Virtex-4 products includes support for industry
standard form factors, including cPCI, VME, PCI and PCI-104, – delivering up to 8 Virtex-4 FPGAs on a
single COTS FPGA computing platform.
The modules provide the option of Virtex-4 LX FPGAs with high performance logic capability, or the
Virtex-4 SX family optimised for DSP performance.

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Nallatech’s (Cumnerauld, Scotland) roadmap for its Virtex-4 products includes support for industry
standard form factors, including cPCI, VME, PCI and PCI-104, – delivering up to 8 Virtex-4 FPGAs on a
single COTS FPGA computing platform.
Nallatech has also released details of DIMEtalk 3, an application development environment for single-
and multiple-device FPGA computing systems that is easier to use than traditional design flows, shortens
development time, and reduces risk.
DIMEtalk 3 is the third generation of Nallatech’s DIMEtalk environment, and delivers rapid, easy to use
application development capabilities through automated configuration of system level communications,
expanded libraries of pre-tested components, support for industry leading third-party tools including
FPGA compilers, and integral DIME-C entry-level C-to-VHDL function generator.
DIME-C is available as part of an early access program and provides a convenient method for engineers
to implement complex hardware functions using high-level design entry.
DIMEtalk 3 builds on the FPGA networking capabilities of DIMEtalk 2 and offers seamless integration to
Nallatech FPGA computing hardware platforms. System-level communications between algorithm
blocks, memory and I/O interfaces are implemented quickly and easily in DIMEtalk 3 by simple drag and
drop actions via an enhanced GUI.
components, such as bridges to Xilinx Rocket I/O blocks, allow designers to make full use of embedded
FPGA architectural features.The open interfaces of DIMEtalk 3 allow engineers to augment the
development environment by using third-party compiler tools, including C to FPGA flows and graphical
development environments. Further third-party tools and techniques, such as algorithm-based design
flows and common hardware description languages such as VHDL, are also used in conjunction with
DIMEtalk 3.

Nallatech Board

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 Virtex-5
Description
Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the
Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA
family. Each platform contains a different ratio of features to address the needs of a wide variety of
advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs
contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second
generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance,
ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock
management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock
generators, and advanced configuration options. Additional platform dependant features include
power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express®
compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-
performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic
designers to build the highest levels of performance and functionality into their FPGA-based systems.
Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable
alternative to custom ASIC technology. Most advanced system designs require the programmable
strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance
logic designers, high-performance DSP designers, and high-performance embedded systems designers
with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5
LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction
layer capability.
Virtex-5 FPGA Logic:
• On average, one to two speed grade improvement over Virtex-4 devices.
• Cascadable 32-bit variable shift registers or 64-bit distributed memory capability
• Superior routing architecture with enhanced diagonal routing supports block-to-block
connectivity with minimal hops
• Up to 330,000 logic cells including:
− Up to 207,360 internal fabric flip-flops with clock enable (XC5VLX330)
− Up to 207,360 real 6-input look-up tables (LUTs) with greater than 13 million total LUT bits
− Two outputs for dual 5-LUT mode gives enhanced utilization
− Logic expanding multiplexers and I/O registers
• 550 MHz Clock Technology
Up to six Clock Management Tiles (CMTs)
− Each CMT contains two DCMs and one PLL—up to eighteen total clock generators
− Flexible DCM-to-PLL or PLL-to-DCM cascade
− Precision clock deskew and phase shift
− Flexible frequency synthesis
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 − Multiple operating modes to ease performance trade-off decisions
− Improved maximum input/output frequency
− Fine-grained phase shifting resolution
− Input jitter filtering
− Low-power operation
− Wide phase shift range
• Differential clock tree structure for optimized low-jitter clocking and precise duty cycle • 32
global clock networks & Regional, I/O, and local clocks in addition to global clocks.
• SelectIO Technology
o Up to 1,200 user I/Os
o Wide selection of I/O standards from 1.2V to 3.3V
o Extremely high-performance
− Up to 800 Mb/s HSTL and SSTL (on all single-ended I/Os)
− Up to 1.25 Gb/s LVDS (on all differential I/O pairs)
o True differential termination on-chip
o Same edge capture at input and output I/Os
o Extensive memory interface support
• 550 MHz Integrated Block Memory
o Up to 16.4 Mbits of integrated block memory
o 36-Kbit blocks with optional dual 18-Kbit mode
o True dual-port RAM cells • Independent port width selection (x1 to x72) − Up to
x36 total per port for true dual port operation − Up to x72 total per port for simple
dual port operation (one Read port and one Write port) − Memory bits plus
parity/sideband memory support for x9, x18, x36, and x72 widths −
Configurations from 32K x 1 to 512 x 72 (8K x 4 to 512 x 72 for FIFO operation)
o Multirate FIFO support logic − Full and Empty flag with fully programmable
Almost Full and Almost Empty flags.
o Synchronous FIFO support without Flag uncertainty • Optional pipeline stages for
higher performance
o Byte-write capability.
o Dedicated cascade routing to form 64K x 1 memory without using FPGA routing.
o Integrated optional ECC for high-reliability memory requirements.
o Special reduced-power design for 18 Kbit (and below) operation

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 • 550 MHz DSP48E Slices
o 25 x 18 two’s complement multiplication.
o Optional pipeline stages for enhanced performance
o Optional 48-bit accumulator for multiply accumulate (MACC) operation with
optional accumulator cascade to 96-bits.
o Integrated adder for complex-multiply or multiply-add operation.
o Optional bitwise logical operation modes.
o Independent C registers per slice.
o Fully cascadable in a DSP column without external routing resources.
• ChipSync Source-Synchronous Interfacing Logic
o Works in conjunction with SelectIO technology to simplify source-synchronous
interfaces.
o Per-bit deskew capability built into all I/O blocks (variable delay line on all inputs and
outputs).
o Dedicated I/O and regional clocking resources (pins and trees).
o Built-in data serializer/deserializer logic with corresponding clock divider support in all
I/O.
o Networking/telecommunication interfaces up to 1.25 Gb/s per I/O
• Digitally Controlled Impedance (DCI) Active I/O Termination
o Optional series or parallel termination.
o Temperature and voltage compensation.
o Makes board layout much easier − Reduces resistors − Places termination in the ideal
location, at the signal source or destination.
• Configuration
o Support for platform Flash, standard SPI Flash, or standard parallel NOR Flash
configuration
o Bitstream support with dedicated fallback reconfiguration logic
o 256-bit AES bitstream decryption provides intellectual property security and prevents
design copying
o Improved bitstream error detection/correction capability
o Auto bus width detection capability
o Partial Reconfiguration via ICAP port
• System Monitor

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 o On-Chip temperature measurement (±4°C)
o On-Chip power supply measurement (±1%)
o Easy to use, self-contained − No design required for basic operation − Autonomous
monitoring of all on-chip sensors − User programmable alarm thresholds for on-chip
sensors.
o User accessible 10-bit 200kSPS ADC − Automatic calibration of offset and gain error −
DNL = ±0.9 LSBs maximum
o Up to 17 external analog input channels supported − 0V to 1V input range − Monitor
external sensors e.g., voltage, temperature − General purpose analog inputs.
o Full access from fabric or JTAG TAP to System Monitor
o Fully operational prior to FPGA configuration and during device power down (access via
JTAG TAP only)
• 65-nm Copper CMOS Process
o 1.0V Core Voltage.
o 12-layer metal provides maximum routing capability and accommodates hard-IP
immersion.
o Triple-oxide technology for proven reduced static power consumption.
Family –
1. Virtex 5 LX: High-performance general logic applications.
2. Virtex 5 LXT: High-performance logic with advanced serial connectivity.
3. Virtex 5 SXT: High-performance signal processing applications with advanced serial
connectivity.
4. Virtex 5 TXT: High-performance systems with double density advanced serial connectivity.
5. Virtex 5 FXT: High-performance embedded systems with advanced serial connectivity.

System Blocks Specific to the LXT, SXT, TXT, and FXT Devices.
• Integrated Endpoint Block for PCI Express Compliance
o Works in conjunction with RocketIO GTP transceivers (LXT and SXT) and GTX
transceivers (TXT and FXT) to deliver full PCI Express Endpoint functionality with minimal
FPGA logic utilization.
o Compliant with the PCI Express Base Specification 1.1.
o PCI Express Endpoint block or Legacy PCI Express Endpoint block.
o x8, x4, or x1 lane width.
o Power management support.

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 o Block RAMs used for buffering.
o Fully buffered transmit and receive.
o Management interface to access PCI Express configuration space and internal
configuration.
o Supports the full range of maximum payload sizes.
o Up to 6 x 32 bit or 3 x 64-bit BARs (or a combination of 32 bit and 64 bit).
• Tri-Mode Ethernet Media Access Controller
o Designed to the IEEE 802.3-2002 specification. Operates at 10, 100, and 1,000 Mb/s.&
Supports tri-mode auto-negotiation.
o Receive address filter (5 address entries).
o Fully monolithic 1000Base-X solution with RocketIO GTP transceivers.
o Supports multiple external PHY connections (RGMII, GMII, etc.) interfaces through soft
logic and SelectIO resources.
o Supports connection to external PHY device through SGMII using soft logic and RocketIO
GTP transceivers.
o Receive and transmit statistics available through separate interface.
o Supports IEEE 802.3ah-2004 unidirectional mode & jumbo frames.
RocketIO GTP Transceivers (LXT/SXT only)
o Full-duplex serial transceiver capable of 100 Mb/s to 3.75 Gb/s baud rates.
o 8B/10B, user-defined FPGA logic, or no encoding options.
o Channel bonding support.
o CRC generation and checking.
o Programmable pre-emphasis or pre-equalization for the transmitter.
o Programmable termination and voltage swing.
o Programmable equalization for the receiver.
o Receiver signals detect and loss of signal indicator.
o User dynamic reconfiguration using secondary configuration bus.
o Out of Band (OOB) support for Serial ATA (SATA).
o Electrical idle, beaconing, receiver detection, and PCI Express and SATA spread-spectrum
clocking support.
o Less than 100 mW typical power consumption.
o Built-in PRBS Generators and Checkers.
RocketIO GTX Transceivers (TXT/FXT only)

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 o Full-duplex serial transceiver capable of 150 Mb/s to 6.5 Gb/s baud rates.
o 8B/10B encoding and programmable gearbox to support 64B/66B and 64B/67B
encoding, user-defined FPGA logic, or no encoding options.
o Electrical idle, beaconing, receiver detection, and PCI Express spread-spectrum clocking
support.
o Low-power operation at all line rates.
PowerPC 440 RISC Cores (FXT only)
o Embedded PowerPC 440 (PPC440) cores − Up to 550 MHz operation − Greater than
1000 DMIPS per core − Seven-stage pipeline − Multiple instructions per cycle − Out-of-
order execution − 32 Kbyte, 64-way set associative level 1 instruction cache − 32 Kbyte,
64-way set associative level 1 data cache − Book E compliant.
o Integrated crossbar for enhanced system performance − 128-bit Processor Local Buses
(PLBs) − Integrated scatter/gather DMA controllers − Dedicated interface for connection
to DDR2 memory controller − Auto-synchronization for non-integer PLB-to-CPU clock
ratios.
o Auxiliary Processor Unit (APU) Interface and Controller − Direct connection from PPC440
embedded block to FPGA fabric-based coprocessors − 128-bit wide pipelined APU
Load/Store − Support of autonomous instructions: no pipeline stalls − Programmable
decode for custom instructions.

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 Xilinx Virtex-5 FPGA
Virtex-5 Boards ML50x(ML505/ML506/ML507)
Features:
Xilinx Virtex-5 FPGA

♦ XC5VLX50T-1FFG1136 (ML505)

♦ XC5VSX50T-1FFG1136 (ML506)

♦ XC5VFX70T-1FFG1136 (ML507)
• Two Xilinx XCF32P Platform Flash PROMs (32 Mb each) for storing large device configurations.
• Xilinx System ACE™ CompactFlash configuration controller with Type I CompactFlash connector
• Xilinx XC95144XL CPLD for glue logic.
• 64-bit wide, 256-MB DDR2 small outline DIMM (SODIMM), compatible with EDK supported IP
and software drivers.
• Clocking

♦ Programmable system clock generator chip

♦ One open 3.3V clock oscillator socket

♦ External clocking via SMAs (two differential pairs)

• General purpose DIP switches (8), LEDs (8), pushbuttons, and rotary encoder.
• Expansion header with 32 single-ended I/O, 16 LVDS-capable differential pairs, 14 spare I/Os
shared with buttons and LEDs, power, JTAG chain expansion capability, and IIC bus expansion.

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 Virtex-7
Xilinx Virtex-7 FPGA:
Xilinx Virtex®-7 Field Programmable Gate Arrays are devices enabled by stacked silicon interconnect
(SSI) technology to address system requirements for applications. FPGAs are semiconductor devices that
are based around a matrix of configurable logic blocks (CLBs) connected via programmable
interconnects. Virtex-7 is used in applications such as 10G to 100G networking, portable radar, and ASIC
Prototyping. Virtex-7 is among four FPGA families (Spartan-7, Artix-7, and Kintex-7 are the others).
Virtex-7 devices also address system requirements ranging from small form factor, cost-sensitive, high-
volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing
capability. Virtex-7 FPGAs are optimized for system performance and integration at 28nm with up to 96
advanced serial transceivers.
Specifications

• Built on low-power (HPL), 28nm, high-k metal gate (HKMG) process technology.
• Up to 2M logic cells, VCXO component, AXI IP, and AMS integration
• Up to 2.8TB/s total serial bandwidth with up to 96 x 13.1G GTs, up to 16 x 28.05G GTs, 5,335
GMACs, 68Mb BRAM, DDR3-1866
• Up to 70% lower power than multi-chip solution
• Scalable optimized architecture, comprehensive tools, IP and TDPs.
• Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology
configurable as distributed memory.
• 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.
• High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.
• High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to max.
rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-
chip interfaces.
• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital
converters with on-chip thermal and supply sensors.
• DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance
filtering, including optimized symmetric coefficient filtering.
• Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode
clock manager (MMCM) blocks for high precision and low jitter.
• Quickly deploy embedded processing with MicroBlaze™ processor.
• Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.
• Wide variety of configuration options, including support for commodity memories, 256-bit AES
encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.
• Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flipchip packaging offering easy
migration between family members in the same package. All packages available in Pb-free and
selected packages in Pb option.
• Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core
voltage process technology and 0.9V core voltage option for even lower power.

Virtex -7 Series:

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Spartan-7 FPGA

Notes:

1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their
LUTs as distributed RAM or SRLs.
2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
3. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18
Kb blocks.
4. Each CMT contains one MMCM and one PLL.
5. Does not include configuration Bank 0.

Artix-7 FPGA

Notes:

1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their
LUTs as distributed RAM or SRLs.
2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
3. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18
Kb blocks.
4. Each CMT contains one MMCM and one PLL.
5. Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.
6. Does not include configuration Bank 0.
7. This number does not include GTP transceivers.

Kintex-7 FPGA

Notes:

1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their
LUTs as distributed RAM or SRLs.
2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
3. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18
Kb blocks.
4. Each CMT contains one MMCM and one PLL.
5. Kintex-7 FPGA Interface Blocks for PCI Express support up to x8 Gen 2.
6. Does not include configuration Bank 0.
7. This number does not include GTX transceivers.

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 Vco707 Evaluation board (Virtex 7 XC7VX485T-2FFG1761C)

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Zynq 7000s: Zynq 7000S devices feature a single-core ARM Cortex®-A9 processor mated
with 28nm Artix™ 7 based programmable logic, representing a low-cost entry point to the
scalable Zynq 7000 platform. Available with 6.25Gb/s transceivers and outfitted with commonly
used hardened peripherals, the Zynq 7000S delivers cost-optimized system integration ideal for
industrial IoT applications such as motor control and embedded vision.

Zynq 7000: Zynq 7000 devices are equipped with dual-core ARM Cortex-A9
processors integrated with 28nm Artix 7 or Kintex™ 7 based programmable logic for
excellent performance-per-watt and maximum design flexibility. With up to 6.6M logic
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cells and offered with transceivers ranging from 6.25Gb/s to 12.5Gb/s, Zynq 7000
devices enable highly differentiated designs for a wide range of embedded applications
including multi-camera drivers’ assistance systems and 4K2K Ultra-HDTV.

Zynq UltraScale+RFSoC ZCU216:

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Overview
Equipped with the industry’s only single-chip adaptable radio device, the Zynq® UltraScale+™ RFSoC
ZCU216 evaluation kit is the ideal platform for both rapid prototyping and high-performance RF
application development. Reference add-on cards and connectivity options make the ZCU216 kit
suitable for developing, testing, and debug of next-gen products while reducing development
complexity and improving time to market. Co-optimized with Xilinx’s comprehensive Vivado® Design
Suite, the ZCU216 kit comes with design files, development tools, and IPs.

the Zynq UltraScale+ RFSoC Gen 3 ZU49DR, the ZCU216 evaluation kit supports direct RF sampling of
sub-6GHz bands utilizing 16T16R high speed RF-DACs and RF-ADCs.

In addition to the excellent RF converter technology in the ZCU49DR device, the ZCU216 kit provides
add-on cards, a wide range of connectivity options, and comprehensive development tools and IPs to
help users to develop cutting-edge RF designs such as:

• 5G sub-6GHz massive-MIMO radio

• 5G mmWave intermediate frequency (IF) transceiver

• Fixed wireless access.

• Digital phased array radar

• Terrestrial satellite communications

• Spectrum analyzers

• High-speed RF testers.

Features:

• Featuring Industry’s Only Adaptable Single-Chip Radio Platform

o Zynq UltraScale+ RFSoC Gen 3 ZU49DR on the ZCU216 board
o Full sub-6GHz direct RF sampling with extended mmWave and multi-band support
o 16 14-bit resolution 2.5GSPS RF-ADCs.
o 16 14-bit resolution 10GSPS RF-DACs.
• Add-on Cards for Fast Evaluation and Rapid Prototyping
o XM650 16T16R N79 band loopback add-on card for quick loopback test
o XM655 16T16R breakout add-on card for in-depth performance measurements

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 o CLK104 RF clock add-on card for internal reference and external sampling clocking.
• Flexible I/O Options for Broad Application Development.
o FMC+ interface for I/O expansion including 12 33Gb/s transceivers and 34 user defined
differential I/O signals.
o 2 400pin RFMC 2.0 18GB/s interfaces.
o 2x2 SFP28 interfaces for 4 SFP/SFP+/zSFP+/SFP28 modules.

Board Features

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