Risc V

KU LEUVEN
FACULTY OF ENGINEERING TECHNOLOGY
CAMPUS GEEL
RISC-V
Khoruzhenko Olha
RADMEP
09.05.2023
RISC-V
First things first, RISC-V stands for the fifth generation of Reduced Instruction Set
Computer, which executes few instructions, it is an open-source hardware ISA –
Instruction Set Architecture. RISC has been created in opposition to CISC (Complex
Instruction Set Computer), because CISC has rather dense instruction sets for a very
wide variety of operations, a large part of which is left unused. So the idea was to improve
efficiency by keeping low-key simplicity [1]. So the main difference between CISC and
RISC is that the former’s CPU has few registers and a lot of instructions, while the latter’s
has a lot of registers, but few instructions, whereas memory access is limited to load and
store instructions [2]. Let’s compare the complex and simple instructions on an example
of a counter written for CISC and RISC CPUs (Fig.1).
Fig. 1 Comparison between CISC and RISC codes [2]
So let’s focus on RISC-V itself. It has modular design, which consists of alternative
base parts and additional optional extensions. A simplified general-purpose computer can
be implemented, using a base, which is responsible for instructions and their encoding,
registers, memory and addressing, control flow, logic manipulatoin and adjuncts. Base
instructions include addition, subtraction, bitwise operations, load and store, jumps and
branches. All the extensions are built to work with one another and all the bases without
conflicts. Base integer Instruction Sets come in either 32 or 64-bit address space
configuration (128-bit is halted because such large memory systems have limited
practical experience yet). There are various extensions, such as the extension for
compressed instructions, for bit manipulation, for vector operations, single- and double-
precision floating-point and so on [3].
RISC-V in the base variant has 32 integer registers (16 for the embedded version),
32 separate floating-point registers in the case of the eponymous extension used. The
first integer register is a zero register, a read of which gives 0 and storing there data is
not possible, it’s used as a placeholder for a simpler instruction set. All the other registers
are general-purpose.
As mentioned, RISC-V is a load-and-store architecture, so instructions address
only registers, with data being transferred to and from memory with load and store
instructions, the majority of which include a 12-bit offset and 2 register identifiers: one is
the base register and the second one is either a source (for a store) or destination (for a
load). The address is formed as an offset added to a base register, what allows single
instructions access data structures, e.g., in the case of the base register pointing to the
top of the stack, the local variables of a subroutine can be accessed by single instructions.
Similarly, record-type structures or memory-mapped IO devices can be accessef by load
and store instructions. Memory systems in RISC-V are shared between CPUs or threads,
so that memory operations are seen in the tread of execution in the programmed order,
but at the same time, RISC-V is simplified between threads and IO devices, so that can’t
be guaranteed here, except in cases of usage of specific instructions.
The execution pipeline of RISC-V includes six stages (Fig. 2) [4]:

 Instruction Fetch goes as follows: first, a single instruction is read from the
program counter and then instruction memory is updated to the next one.
 Instruction Pre-Decode: a 16-bit compressed instruction will be decoded
into an initial 32-bit.
 Instruction Decode: the register file is being allowed and bypass controls
are being decided at this stage.
 Execute: calculates the result for an ALU, DIV, MUL instruction; allows the
memory for a store or load; measures branches and jumps over their
expected outcomes.
Fig. 2 RISC-V architecture [4]
 Memory: accesses memory through the pipeline, adding this phase secures
high performance of the pipeline.
 Write Back: the result of the Execution stage is written into the Register File.
To boost the efficiency of the processor, a branch predictor unit (BPU) is included
in RISC-V to store past data and help the processor to decide, if a certain branch is to be
taken or not. Once the branch is executed, the predictor data gets updated [3].
There are two types of cache [4]:

 Data cache, which is used to speed up the access of data memory by buffering
recently accessed locations (can handle half-word, byte and word accesses for 32-
bit and all that plus double-word for 64-bit). It can be disabled, allowing memory
locations to be accessed directly via the Data Interface.
 Instruction Cache, which is used to speed up the instruction fetch by buffering
recently fetched instructions (fetches one parcel for every cycle on any 16-bit
boundary, but only within one block), it is configurable and also can be disabled.
RISC-V found various applications, such as use in high-performance-based

embedded systems, AI and ML. Also, it can be of great use in quite specific fields such
as edge computing, cloud servers and virtual reality, to say nothing of general-purpose
processors, computer devices and controllers, the Internet of things and so on [5].
To conclude this little overview, let’s sum up the advantages of RISC-V, the main
ones of which are simplicity, openness, configurability, which can definitely ease
things up for a developer. It allows certain flexibility in the choice of language compiler:
GCC, Linux OS and free-software compilers [1]. Since it’s an open source, it can be
used without royalties or fees, what is extremely important for studying purposes,
researchers and developers. It follows the tradition of RISC and doesn’t involve brand-
new technology. Since it’s an ISA, it describes the way in which software talks to an
underlying processor, the processor so the specification defines different instruction
set levels. There are 32-bit and 64-bit variants with additional extensions, which are
also free, modular and quite straightforward. All this allows various applications to be
built on the basis of RISC-V.
But Mr. Hyde to this Dr. Jekyll is that compilers and programmers frequently use
complex instructions, also a large number of instructions has to be saved quickly,
that’s why for keeping up a big cache memory is needed, the output can change in
the case when successive instructions within a loop depend on the earlier instruction
for execution [4]. The final features and abilities are highly dependent on the
architecture.
REFERENCES
1. “The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version
20191213”, Editors Andrew Waterman and Krste Asanovi´c, RISC-V Foundation,
December 2019
2. Corpeño, E. (2022, June 12). An Introduction to RISC-V—Understanding RISC’s
Open ISA. All About Circuits. Retrieved May 8, 2023, from
https://www.allaboutcircuits.com/technical-articles/introductions-to-risc-v-
instruction-set-understanding-this-open-instruction-set-architecture/
3. RISC-V. (2023, May 3). In Wikipedia. https://en.wikipedia.org/wiki/RISC-V
4. (n.d.). What is RISC V Processor: Architecture, Working & Its Applications.
Electronics|Projects|Focus. Retrieved May 8, 2023, from
https://www.elprocus.com/risc-v-processor/
5. Atwell, C. (2022, March 11). What is RISC-V? Fierce Electronics. Retrieved May
8, 2023, from https://www.fierceelectronics.com/embedded/what-risc-v

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KU LEUVEN

FACULTY OF ENGINEERING TECHNOLOGY

Fig. 1 Comparison between CISC and RISC codes [2]

The execution pipeline of RISC-V includes six stages (Fig. 2) [4]:

Fig. 2 RISC-V architecture [4]

There are two types of cache [4]:

RISC-V found various applications, such as use in high-performance-based

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