74HCT4040

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4040
12-stage binary ripple counter
Product specification December 1990
File under Integrated Circuits, IC06
Philips Semiconductors Product specification
12-stage binary ripple counter 74HC/HCT4040
FEATURES (Q0 to Q11). The counter advances on the HIGH-to-LOW

transition of CP.
• Output capability: standard
• ICC category: MSI A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
GENERAL DESCRIPTION
The 74HC/HCT4040 are high-speed Si-gate CMOS
devices and are pin compatible with “4040” of the “4000B” APPLICATIONS
series. They are specified in compliance with JEDEC • Frequency dividing circuits
standard no. 7A.
• Time delay circuits
The 74HC/HCT4040 are 12-stage binary ripple counters • Control counters
with a clock input (CP), an overriding asynchronous
master reset input (MR) and twelve parallel outputs
QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V
CP to Q0 14 16 ns
Qn to Qn+1 8 8 ns
fmax maximum clock frequency 90 79 MHz
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 20 20 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990 2
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION

8 GND ground (0 V)
9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 Q0 to Q11 parallel outputs
10 CP clock input (HIGH-to-LOW, edge-triggered)
11 MR master reset input (active HIGH)
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
FUNCTION TABLE
INPUTS OUTPUTS
CP MR Qn
↑ L no change
↓ L count
X H L
Notes
1. H = HIGH voltage level
Fig.4 Functional diagram. L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock
transition
↓ = HIGH-to-LOW clock
transition
Fig.5 Logic diagram.
Fig.6 Timing diagram.
December 1990 4
DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C) TEST CONDITIONS

74HC
SYMBOL PARAMETER UNIT VCC WAVEFORMS
+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay 47 150 190 225 ns 2.0 Fig.7
CP to Q0 17 30 38 45 4.5
14 26 33 38 6.0
Qn to Qn+1 10 20 25 30 4.5
8 17 21 26 6.0
tPHL propagation delay 61 185 230 280 ns 2.0 Fig.7
MR to Qn 22 37 46 56 4.5
18 31 39 48 6.0
tTHL/ tTLH output transition time 19 75 95 110 ns 2.0 Fig.7
7 15 19 22 4.5
6 13 16 19 6.0
tW clock pulse width 80 14 100 120 ns 2.0 Fig.7
HIGH or LOW 16 5 20 24 4.5
14 4 17 20 6.0
tW master reset pulse 80 22 100 120 ns 2.0 Fig.7
width; HIGH 16 8 20 24 4.5
14 6 17 20 6.0
trem removal time 50 8 65 75 ns 2.0 Fig.7
MR to CP 10 3 13 15 4.5
9 2 11 13 6.0
fmax maximum clock pulse 6.0 27 4.8 4.0 MHz 2.0 Fig.7
frequency 30 82 24 20 4.5
35 98 28 24 6.0
December 1990 5
DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types

The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT

CP 0.85
MR 1.10
AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C) TEST CONDITIONS

74HCT
SYMBOL PARAMETER UNIT VCC WAVEFORMS
+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
CP to Q0
Qn to Qn+1
tPHL propagation delay 23 45 56 68 ns 4.5 Fig.7
MR to Qn
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.7
tW clock pulse width 16 7 20 24 ns 4.5 Fig.7

HIGH or LOW
tW master reset pulse 16 6 20 24 ns 4.5 Fig.7
width; HIGH
trem removal time 10 2 13 15 ns 4.5 Fig.7
MR to CP
fmax maximum clock pulse 30 72 24 20 MHz 4.5 Fig.7
frequency
December 1990 6
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock pulse frequency.
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and
the master reset to clock (CP) removal time.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990 7

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INTEGRATED CIRCUITS

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

12-stage binary ripple counter 74HC/HCT4040

FEATURES (Q0 to Q11). The counter advances on the HIGH-to-LOW

QUICK REFERENCE DATA

12-stage binary ripple counter 74HC/HCT4040

PIN NO. SYMBOL NAME AND FUNCTION

12-stage binary ripple counter 74HC/HCT4040

Fig.5 Logic diagram.

Fig.6 Timing diagram.

12-stage binary ripple counter 74HC/HCT4040

DC CHARACTERISTICS FOR 74HC

AC CHARACTERISTICS FOR 74HC

Tamb (°C) TEST CONDITIONS

12-stage binary ripple counter 74HC/HCT4040

DC CHARACTERISTICS FOR 74HCT

Note to HCT types

INPUT UNIT LOAD COEFFICIENT

AC CHARACTERISTICS FOR 74HCT

Tamb (°C) TEST CONDITIONS

tW clock pulse width 16 7 20 24 ns 4.5 Fig.7

12-stage binary ripple counter 74HC/HCT4040

(1) HC : VM = 50%; VI = GND to VCC.

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