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Wistron Catalina

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5 4 3 2 1

ĂƚĂůŝŶĂDͬůŽĐŬŝĂŐƌĂŵ;ĂůƉĞůůĂͿ Clarksfield option external GPU


SYSTEM DC/DC
INPUTS
TPS51125
OUTPUTS

+5VALW
Clock Generator DCBATOUT
Intel CPU AMD HDMI_OUT
+3VALW
SLG8SP585 DDRIII 800/1066/1333 MUX_B_1
D DDRIII Channel A Madison +3VL 40 D

Auburndale with internal Graphic VGA Non-ECC Slot 0 Auburndale W/Ͳdžϭϲh^ / SYSTEM DC/DC
AMD TMDS MUX_A_1 TPS51117/RT8209A
DDRIII 800/1066/1333 DDR III Channel B / Clarksfield PECI Park
Non-ECC Slot 1 INPUTS OUTPUTS
+1.5VU
FDI DMIx4 DCBATOUT
MUX_B_1 +1.05VS 41

Camera + Analog mic module /w


LED indicator SYSTEM DC/DC

HDMI_Level shift
ISL62881
INTEL
MUX_B
BLUETOOTH option (internal)
INPUTS OUTPUTS
same as Bali
HDMI_OUT Digital Display (Port B)
PCH RF module option (internal)
DCBATOUT +VCC_GFXCORE
43

14 USB 2.0/1.1 ports same as Bali


LED indicator ETHERNET (10/100/1000Mb)
C CPU DC/DC C

High Definition Audio h^Ϯ͘Ϭ USB x 6


6 SATA ports
ISL62883
USB 2.0 8 PCIE ports INPUTS OUTPUTS
Touch Panel ACPI 1.1 SATA eSATA CONN
Side
LPC I/F +VCC_CORE
DCBATOUT
RJ45 Intel 82577 LC PCI/PCI BRIDGE 0.844~1.3V
PCIE x1 SATA 3.5" SATA HDD 58A 38, 39
CONN 10/100/1000

Slim ODD
6-in-1 Flash VIA VT6325 PCIE x1
media reader Controller SYSTEM DC/DC
WLAN/WiMAX RT9025/RT9026
PCIE x1
802.11a/b/g/n INPUTS OUTPUTS
1394
Flash ROM SPI +3VS +1.8VS 44
B B
32MB
Headphone PCIE x1
TV-Tuner +1.5VU +0.75VS 44
PCB 8 LAYER
Digital+Analog (Worldwide)
HD AUDIO
L1: Signal 1
Digital Display (Port C)

MIC IN CODEC HD AUDIO SYSTEM DC/DC


ALC272 LPC Bus LPC debug port APW7138QAI L2: GND
SPIDIF
TMDS

MUX_A_1 INPUTS OUTPUTS L3: Signal 2


SPI_ROM HDCP
MUX_A
2MB 24LC02(R) DCBATOUT +1.1VS_VTT
L4: Signal 3
42
WƵĚŝŽ>ͬZ ITE L5: VCC
Scalar IC RTD 2663
ITE8758E L6: Signal 4
Scalar+Video Decode +MCU
6W AMP >s^;ƵĂůŚĂŶŶĞůͿ Audio codec L7: GND
TPA3113
L8: Signal 5
A A
<Core Design>
I2C

2CH SPEAKER 2.5W SYS CPU


AV-IN HDMI_IN (1.3) Wistron Corporation
Fan Fan 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
ϮϯΗ> Touch Button with White LED Title

sK>ͺd>
Block Diagram
Size Document Number Rev
Custom
Calpella M/B SA
Date: Tuesday, April 06, 2010 Sheet 1 of 59
5 4 3 2 1
5 4 3 2 1
Processor Strapping Power Sequence
Pin Name Strap Description Configuration (Default value for each bit is Default DCBATOUT
1 unless specified otherwise) Value
3D3V_AUX_S5
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
DisplayPort Embedded DisplayPort. 5V_AUX_S5
Presence 0: Enabled - An external Display Port device is
connected to the Embedded Display Port. S5_ENABLE (SIO)
CFG[3] PCI-Express Static 1: Normal Operation. 1
Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 5V_S5
D CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
3D3V_S5 >10ms D
Configuration 0: Bifurcation enabled
RSMRST#_SIO
Select
CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0 can power after power switch press
Temporarily used Connect to GND with 3.01K Ohm/5% resistor LAN_PWR_ON
for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
samples. 3D3V_LAN_S5
MoW and sighting report].
For a common motherboard design (for AUB and CFD),
the pull-down resistor should be used. Does not
SIO_PWRBTN#
impact AUB functionality.

PM_PWRBTN#

PM_SLP_S4#

PCH Strapping 1D5V_S3


DDR3_VREF_S3

Name Schematics Notes


PM_SLP_S3#
SPKR Reboot option at power-up
Default Mode: Internal weak Pull-down.
5V_S0
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kȍ
3D3V_S0
- 10-kȍ weak pull-up resistor.
1D8V_S0
INIT3_3V# Weak internal pull-down. Do not pull high. 1D5V_S0

C GNT3#/
GPIO55
Default Mode: Internal pull-up.
Low (0) = Top Block Swap Mode (Connect to ground with 4.7-kȍ weak
1D05V_S0
0D75V_S0 C
pull-down resistor). ALL_PWRGD
INTVRMEN High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled
1D05V_VTT
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1# required.
Boot from PCI: Connect GNT1# to ground with 1-kȍ pull-down VTT_PWRGD
resistor. Leave GNT0# Floating. (H_VTTPWRGD -->CPU, KBC)
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-kȍ
pull-down resistor. S0_PWR_GOOD
(IMVP_VR_EN)
GNT2#/ Default - Internal pull-up.
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers
only. Not for mobile/desktops). VCC_CORE
GPIO33 Default: Do not pull low.
Disable ME in Manufacturing Mode: Connect to ground with 1-kȍ VR_CLKEN#
pull-down resistor.
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-kȍ weak pull-up resistor. CORE_PWRGD
Disable iTPM: Left floating, no pull-down required. (SYS_PWROK, PCH_PWROK)
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-kȍ weak pull-up
resistor.
GFX_VR_EN
Disable Danbury: Connect to ground with 4.7-kȍ weak pull-down
resistor.
NC_CLE Weak internal pull-up. Do not pull low. VCC_GFXCORE
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.
/GPIO[33] High (1) : Flash Descriptor Security will be in effect. DIS

B HDA_SDO Weak internal pull-down. Do not pull high.


DGPU_PWR_EN# B
HDA_SYNC Weak internal pull-down. Do not pull high.
GPIO15 Weak internal pull-down. Do not pull high.
3D3V_S0_VGA
GPIO8 Weak internal pull-up. Do not pull low.
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for VGA_CORE_PWR
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails. DGPU_PWROK

1D0V_S0_VGA

1D5V_S0_VGA

1D8V_S0_VGA
N11M-GE Power Sequence
Platform controlled
VDD33
Sillicon controlled
PEX_VDD can ramp up any time PM_DRAM_PWRGD
PEX_VDD
tNVVDD
H_PWRGD
NVVDD
A tNV-IFPAB_IOVDD
PLT_RST#
A
IFPAB_IOVDD

tNV-FBVDDQ <Variant Name>


FBVDDQ
Wistron Corporation
>7ms 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
>10ms Taipei Hsien 221, Taiwan, R.O.C

Title
>99ms <Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Tuesday, April 06, 2010 Sheet 2 of 59

5 4 3 2 1
5 4 3 2 1

FOR CO-LAY SLG8LV595


D 1D5V_S0 1D5V_S0_CK505
D
1 (R) 2

R213
0R3J-0-U-GP 1221 (SC)

1
1D05V_S0 star trace 1D05V_CK505
DY R215
3D3V_S0 3D3V_CK505 1D5V_S0_CK505 0R3J-0-U-GP R221 close each pin
R226 3D3V_CK505 1D05V_CK505 1 2
1 2

1
0R0603-PAD-1-GP C625 C628 C129 C127
1

1
0R0603-PAD-1-GP C618 C623 C622 C624 C620 C128 C126

SC47P50V2JN-3GP
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP
2

2
SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SC47P50V2JN-3GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
Low voltage I/O power
2

2
supply for outputs.
place close place close

1221 (SC)

24

17

29

15

18
1

5
U9

VDD_27

VDD_SRC_IO

VDD_CPU_IO
VDD_CPU

VDD_SRC

VDD_REF

VDD_DOT
1225
DIS (S)
R1002 1 2 0R0402-PAD DREFCLK#_R 4 6 VGA_XIN1_L 4 1 RNT1
15 DREFCLK# DOT_96# 27MHZ VGA_XIN1 52
15 DREFCLK R1001 1 2 0R0402-PAD DREFCLK_R 3 7 OSC_SPREAD_L 3 2 SRN33J-5-GP-U OSC_SPREAD 52
DOT_96 27MHZ_SS
R998 1 2 0R0402-PAD CLKIN_DMI#_R 14
15 CLKIN_DMI# SRC_2#
R997 1 2 0R0402-PAD CLKIN_DMI_R 13 16 CPU_STOP#
15 CLKIN_DMI SRC_2 CPU_STOP#
25 CK_PWRGD TP2 TPAD28
R1000 1 CLK_PCIE_SATA#_R CKPWRGD/PD# REF_0/CPU_SEL
15 CLK_PCIE_SATA# 2 0R0402-PAD 11 30 R223 1 2 33R2J-2-GP CLK_ICH14 15
R999 1 CLK_PCIE_SATA_R SRC_1/SATA# REF_0/CPU_SEL
15 CLK_PCIE_SATA 2 0R0402-PAD 10
SRC_1/SATA

1
R996 1 2 0R0402-PAD CLK_CPU_BCLK#_R 22 28 GEN_XTAL_IN
15 CLK_CPU_BCLK# CPU_0# XTAL_IN
R995 1 2 0R0402-PAD CLK_CPU_BCLK_R 23 27 GEN_XTAL_OUT TP19 TPAD28 (R) C135
C 15 CLK_CPU_BCLK CPU_0 XTAL_OUT SC10P50V2JN-4GP
C

2
PCH_SMBDATA
19
CPU_1# SDA
31
PCH_SMBCLK
PCH_SMBDATA 12,13,15,29,58 DY
20 32 PCH_SMBCLK 12,13,15,29,58
CPU_1 SCL

VSS_SATA
VSS_CPU

VSS_SRC

VSS_DOT
VSS_REF

VSS_27
GND
SLG8SP585VTR-GP

33

26

21

12

9
2ND = 71.93197.003

1D05V_CK505 3D3V_CK505
3D3V_CK505
1 2 CPU_STOP#
R216 10KR2J-3-GP
2

R224 3.3V LVTTL input for CPU_STOP#. Contains


10KR2J-3-GP internal pull-up resistor.
DY 2K2R2J-2-GP
(R) it becomes a real time input for R219
asserting power down (active high).??
1

CK_PWRGD
REF_0/CPU_SEL
CL=20pF±0.2pF
Layout Notes:
D
2

FSC 0 1 C133
R225 SC33P50V2JN-3GP
10KR2J-3-GP 1 2 GEN_XTAL_IN Make sure that the stubs to the test points(CK_PWRGD,
2N7002-11-GP
133MHz G CLK_EN#, GEN_XTAL_OUT) in the layout are as short as

1
Q18 VR_CLKEN# 36 X6
SPEED 100MHz
1

(Default) X-14D3181MHZ-GP possible on the high speed signals.


S

82.30005.A11
C130 XTAL 14.3181M 20P30PPM HCX-5FA

2
B 1 2 GEN_XTAL_OUT
B
SC33P50V2JN-3GP

A A
<Variant Name>

Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C

Title
Ali Mountain

Size Document Number Rev


A2 <RevCode>
CK505_SLG8SP585
Date: Tuesday, April 06, 2010 Sheet 3 of 59

5 4 3 2 1
5 4 3 2 1

CPU1A 1 OF 9 R286
B26 PEG_IRCOMP_R 1 2 49D9R2F-GP
PEG_ICOMPI
A26
PEG_ICOMPO R287
16 DMI_TXN0 A24 B27

AUBURNDALE
DMI_RX0# PEG_RCOMPO EXP_RBIAS
16 DMI_TXN1 C23 A25 1 2 750R2F-GP
DMI_RX1# PEG_RBIAS
16 DMI_TXN2 B22
DMI_RX2# PEG_RXN15 PEG_RXN[15..0] 51
16 DMI_TXN3 A21 K35
DMI_RX3# PEG_RX0# PEG_RXN14
J34
PEG_RX1# PEG_RXN13
16 DMI_TXP0 B24 J33
DMI_RX0 PEG_RX2# PEG_RXN12
16 DMI_TXP1 D23 G35
DMI_RX1 PEG_RX3#

DMI
16 B23 G32 PEG_RXN11
DMI_TXP2 DMI_RX2 PEG_RX4#
A22 F34 PEG_RXN10
16 DMI_TXP3 DMI_RX3 PEG_RX5#
F31 PEG_RXN9
PEG_RX6#
D 16
16
DMI_RXN0
DMI_RXN1
D24
G24
F23
DMI_TX0#
DMI_TX1#
PEG_RX7#
PEG_RX8#
D35
E33
C33
PEG_RXN8
PEG_RXN7
PEG_RXN6
D
16 DMI_RXN2 DMI_TX2# PEG_RX9#
H23 D32 PEG_RXN5
16 DMI_RXN3 DMI_TX3# PEG_RX10#
B32 PEG_RXN4
PEG_RX11# PEG_RXN3
16 DMI_RXP0 D25 C31
DMI_TX0 PEG_RX12# PEG_RXN2
16 DMI_RXP1 F24 B28
DMI_TX1 PEG_RX13# PEG_RXN1
16 DMI_RXP2 E23 B30
DMI_TX2 PEG_RX14# PEG_RXN0
16 DMI_RXP3 G23 A31
DMI_TX3 PEG_RX15#
PEG_RXP15 PEG_RXP[15..0] 51
J35
PEG_RX0 PEG_RXP14
H34
PEG_RX1 PEG_RXP13
H33
PEG_RX2 PEG_RXP12
16 FDI_TXN0 E22 F35
FDI_TX0# PEG_RX3 PEG_RXP11
16 FDI_TXN1 D21 G33
FDI_TX1# PEG_RX4 PEG_RXP10
16 FDI_TXN2 D19 E34
FDI_TX2# PEG_RX5 PEG_RXP9
16 FDI_TXN3 D18 F32
FDI_TX3# PEG_RX6

Intel(R) FDI
G21 D34 PEG_RXP8
16 FDI_TXN4 FDI_TX4# PEG_RX7
16 E19 F33 PEG_RXP7
FDI_TXN5 FDI_TX5# PEG_RX8
F21 B33 PEG_RXP6
16 FDI_TXN6 FDI_TX6# PEG_RX9
16 G18 D31 PEG_RXP5
FDI_TXN7 FDI_TX7# PEG_RX10
A32 PEG_RXP4
PEG_RX11 PEG_RXP3
C30
PEG_RX12 PEG_RXP2
16 FDI_TXP0 D22 A28
FDI_TX0 PEG_RX13

PCI EXPRESS -- GRAPHICS


C21 B29 PEG_RXP1
16 FDI_TXP1 FDI_TX1 PEG_RX14
16 D20 A30 PEG_RXP0
FDI_TXP2 FDI_TX2 PEG_RX15
16 FDI_TXP3 C18 PEG_TXN[15..0] 51
FDI_TX3 PEG_TXN15_L C226 SCD1U10V2KX-5GP PEG_TXN15
16 FDI_TXP4 G22
FDI_TX4 PEG_TX0#
L33 DIS 1 2
16 E20 M35 PEG_TXN14_L DIS 1 2 C221 SCD1U10V2KX-5GP PEG_TXN14
FDI_TXP5 FDI_TX5 PEG_TX1#
F20 M33 PEG_TXN13_L DIS 1 (S) 2 C223 SCD1U10V2KX-5GP PEG_TXN13
16 FDI_TXP6 FDI_TX6 PEG_TX2#
16 G19 M30 PEG_TXN12_L DIS 1 (S) 2 C256 SCD1U10V2KX-5GP PEG_TXN12
FDI_TXP7 FDI_TX7 PEG_TX3#
L31 PEG_TXN11_L DIS 1 (S) 2 C255 SCD1U10V2KX-5GP PEG_TXN11

EKd͗
PEG_TX4# PEG_TXN10_L C248 SCD1U10V2KX-5GP PEG_TXN10
16 FDI_FSYNC0
F17
FDI_FSYNC0 PEG_TX5#
K32 DIS 1 (S) 2
E17 M29 PEG_TXN9_L DIS 1 (S) 2 C252 SCD1U10V2KX-5GP PEG_TXN9
16 FDI_FSYNC1 FDI_FSYNC1 PEG_TX6# PEG_TXN8_L C250 SCD1U10V2KX-5GP PEG_TXN8
PEG_TX7#
J31 DIS 1 (S) 2
C17 K29 PEG_TXN7_L DIS 1 (S) 2 C235 SCD1U10V2KX-5GP PEG_TXN7
16 FDI_INT FDI_INT PEG_TX8# PEG_TXN6_L C258 SCD1U10V2KX-5GP PEG_TXN6
DIS
W/ĞdžϭϲƌĞƐĞƌǀĞ
H30 1 (S) 2
PEG_TX9# PEG_TXN5_L C237 SCD1U10V2KX-5GP PEG_TXN5
16 FDI_LSYNC0
F18
FDI_LSYNC0 PEG_TX10#
H29 DIS 1 (S) 2
D17 F29 PEG_TXN4_L DIS 1 (S) 2 C260 SCD1U10V2KX-5GP PEG_TXN4
16 FDI_LSYNC1 FDI_LSYNC1 PEG_TX11# PEG_TXN3_L C239 SCD1U10V2KX-5GP PEG_TXN3
PEG_TX12#
E28 DIS 1 (S) 2
D29 PEG_TXN2_L DIS 1 (S) 2 C262 SCD1U10V2KX-5GP PEG_TXN2
PEG_TX13# PEG_TXN1_L C241 SCD1U10V2KX-5GP PEG_TXN1
D27 DIS 1 2
C [-1] 0317 FDI_FSYNC1 PEG_TX14#
PEG_TX15#
C26 PEG_TXN0_L DIS 1
(S)
(S)
(S)
2 C264 SCD1U10V2KX-5GP PEG_TXN0
PEG_TXP[15..0] 51
C
L34 PEG_TXP15_L DIS 1 (S) 2 C225 SCD1U10V2KX-5GP PEG_TXP15
1

PEG_TX0 PEG_TXP14_L C222 SCD1U10V2KX-5GP PEG_TXP14


PEG_TX1
M34 DIS 1 2
R786 M32 PEG_TXP13_L DIS 1 (S) 2 C224 SCD1U10V2KX-5GP PEG_TXP13
RN40 PEG_TX2 PEG_TXP12_L C257 SCD1U10V2KX-5GP PEG_TXP12
1KR2J-1-GP PEG_TX3
L30 DIS 1 (S) 2
5 4 FDI_LSYNC0 M31 PEG_TXP11_L DIS 1 (S) 2 C254 SCD1U10V2KX-5GP PEG_TXP11
FDI_LSYNC1 PEG_TX4 PEG_TXP10_L C249 SCD1U10V2KX-5GP PEG_TXP10
6 3 (R) K31 DIS 1 (S) 2
2

FDI_INT PEG_TX5 PEG_TXP9_L C247 SCD1U10V2KX-5GP PEG_TXP9


7
(R) 2
PEG_TX6
M28 DIS 1 (S) 2
8 1 FDI_FSYNC0 H31 PEG_TXP8_L DIS 1 (S) 2 C251 SCD1U10V2KX-5GP PEG_TXP8
PEG_TX7 PEG_TXP7_L C236 SCD1U10V2KX-5GP PEG_TXP7
PEG_TX8
K28 DIS 1 (S) 2
SRN1KJ-4-GP G30 PEG_TXP6_L DIS 1 (S) 2 C259 SCD1U10V2KX-5GP PEG_TXP6
PEG_TX9 PEG_TXP5_L C238 SCD1U10V2KX-5GP PEG_TXP5
PEG_TX10
G29 DIS 1 (S) 2
F28 PEG_TXP4_L DIS 1 (S) 2 C261 SCD1U10V2KX-5GP PEG_TXP4
PEG_TX11 PEG_TXP3_L C240 SCD1U10V2KX-5GP PEG_TXP3
PEG_TX12
E27 DIS 1 (S) 2
D28 PEG_TXP2_L DIS 1 (S) 2 C263 SCD1U10V2KX-5GP PEG_TXP2
PEG_TX13 PEG_TXP1_L C242 SCD1U10V2KX-5GP PEG_TXP1
PEG_TX14
C27 DIS 1 (S) 2
C25 PEG_TXP0_L DIS 1 (S) 2 C265 SCD1U10V2KX-5GP PEG_TXP0
PEG_TX15
(S)
For Graphics Disable , Pull-down to (S)

GND via 1-k ± 5% resistor

ϲϮ͘ϭϬϬϰϬ͘ϲϭϭ
ϮŶĚсϲϮ͘ϭϬϬϱϱ͘ϯϮϭ

B B

A A
<Variant Name>

Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C

Title
<Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Tuesday, April 06, 2010 Sheet 4 of 59

5 4 3 2 1
5 4 3 2 1

SM_RCOMP_0 1 2
R678 100R2F-L1-GP-U
SM_RCOMP_1 1 2
1D05V_VTT CPU1B 2 OF 9 R679 24D9R2F-L-GP
1 2 H_COMP3 AT23 SM_RCOMP_2 1 2
R671 20R2F-GP COMP3 BCLK_CPU_P R677 130R2F-1-GP
A16 BCLK_CPU_P 19
H_CATERR# H_COMP2 BCLK BCLK_CPU_N
1 2 1 2 AT24 B16 BCLK_CPU_N 19

AUBURNDALE
R681 49D9R2F-GP R672 20R2F-GP COMP2 BCLK# impedance compensation

MISC
CLOCKS
1 2 PROCHOT# 1 2 H_COMP1 G16 AR30
R662 68R2-GP R709 49D9R2F-GP COMP1 BCLK_ITP
AT30
H_COMP0 BCLK_ITP#
1 2 AT26
R673 49D9R2F-GP COMP0 PEG_CLK_R
E16 PEG_CLK_R 15
PEG_CLK PEG_CLK#_R
D16 PEG_CLK#_R 15
PEG_CLK#
D TPAD28 TP36

SKTOCC# (Socket Occupied)


SKTOCC#_R AH24
SKTOCC#
DPLL_REF_SSCLK
A18
A17
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
DPLL_REF_SSCLK 15 D
DPLL_REF_SSCLK# DPLL_REF_SSCLK# 15
H_CATERR# AK14
CATERR#

THERMAL
F6 DDR3_DRAMRST#
SM_DRAMRST# 1D05V_VTT DDR3_DRAMRST# 12,13
19 H_PECI AT15
PECI SM_RCOMP_0 RN26 SRN10KJ-5-GP
AL1
1225 SM_RCOMP0 SM_RCOMP_1
AM1 1 4
SM_RCOMP1 SM_RCOMP_2
AN1 2 3
PROCHOT# SM_RCOMP2
36 H_PROCHOT# 1 R663 2 AN26
0R0402-PAD PROCHOT#
AN15 PM_EXTTS#0_R 12
0814 PM_EXT_TS0#
AP15 PM_EXTTS#1_R 13
PM_EXT_TS1#

DDR3
MISC
19 PM_THRMTRIP-A# AK15
THERMTRIP#
130°C
AT28 XDP_PRDY# TP20 TPAD28
[-1] 0317
PRDY# XDP_PREQ#
PREQ#
AP27 2009/12/23
AN28 XDP_TCLK DPLL_REF_SCLK on CPU can be tied to GND if sno e-DP support
TPAD28 TP22 H_CPURST# TCK XDP_TMS
AP26 AP28
RESET_OBS# TMS

PWR MANAGEMENT
AT27 XDP_TRST#
TRST#

JTAG & BPM


AL15 AT29 XDP_TDI DPLL_REF_SSCLK
16 H_PM_SYNC PM_SYNC TDI XDP_TDO DPLL_REF_SSCLK#
AR27
TDO XDP_TDI_M
AR29
VCCPWRGOOD_1 TDI_M XDP_TDO_M
19 H_PWRGD 1 R669 2 AN14 AP29
0R0402-PAD VCCPWRGOOD_1 TDO_M
AN25 XDP_DBRESET#

1
VCCPWRGOOD_0 DBR#
1 R670 2 AN27
1225 0R0402-PAD VCCPWRGOOD_0 R949 R950
AJ22 Close to CPU side 0R2J-2-GP 0R2J-2-GP
16 PM_DRAM_PWRGD 1 R665 2 DRAMPWROK AK13
SM_DRAMPWROK
BPM0#
BPM1#
AK22 CHECK XDP
0R0402-PAD AK24

2
BPM2#
AJ24
H_VTTPWRGD BPM3#
AM15 AJ25
VTTPWRGOOD BPM4#
AH22
BPM5#
AK23
TPAD28 TP24 H_PWRGD_XDP BPM6#
AM26 AH23
TAPPWRGOOD BPM7#
C 18,27,28,33 PLT_RST# R667 1 2 PLT_RST#_R AL14
RSTIN#
C
1

1K5R2F-2-GP
R668
750R2F-GP
2

3D3V_S5
3D3V_S0
SB 1118

1
1D5V_S3
1

R660 1D05V_VTT
R659 100KR2J-1-GP
1

10KR2J-3-GP 84.2N702.A3F XDP_TMS 1 (R)DY 2


R664 2N7002KDW-GP R203 51R2J-2-GP
1K1R2F-GP 2 XDP_TDI 1 (R)DY 2 CPU JTAG
2

1 6 R201 51R2J-2-GP
XDP_PREQ# 1 (R)DY 2
2

VTT_PWRGD 2 5 H_VTTPWRGD_R R206 51R2J-2-GP XDP_TDO_M 3D3V_S0


33,35,39 VTT_PWRGD 1D05V_VTT
DRAMPWROK XDP_TDO 1 2

1
3 4 R204 51R2J-2-GP
1

C617 R200
1
SCD1U10V2KX-5GP

R666 Q63 0R2J-2-GP XDP_DBRESET# 1 2


3KR2F-GP R661 R674 1KR2J-1-GP
1

1KR2J-1-GP XDP_TCLK 1 (R)DY 2

2
R202 51R2J-2-GP XDP_TDI_M
2

XDP_TRST# 1 2
B H_VTTPWRGD R205 51R2J-2-GP
B

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (2/7)-HOST
Size Document Number Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 5 of 59

5 4 3 2 1
5 4 3 2 1

CPU1D 4 OF 9

CPU1C 3 OF 9

AUBURNDALE
AUBURNDALE
13 M_B_DQ[63..0] W8 M_CLK_DDR2 13
SB_CK0
D SA_CK0
AA6
AA7
M_CLK_DDR0 12
M_B_DQ0
M_B_DQ1
B5
A5
SB_DQ0
SB_CK0#
SB_CKE0
W9
M3
M_CLK_DDR#2 13
M_CKE2 13 D
12 M_A_DQ[63..0] SA_CK0# M_CLK_DDR#0 12 SB_DQ1
P7 M_B_DQ2 C3
SA_CKE0 M_CKE0 12 SB_DQ2
M_A_DQ0 A10 M_B_DQ3 B3 V7
SA_DQ0 SB_DQ3 SB_CK1 M_CLK_DDR3 13
M_A_DQ1 C10 M_B_DQ4 E4 V6
SA_DQ1 SB_DQ4 SB_CK1# M_CLK_DDR#3 13
M_A_DQ2 C7 M_B_DQ5 A6 M2
SA_DQ2 SB_DQ5 SB_CKE1 M_CKE3 13
M_A_DQ3 A7 Y6 M_B_DQ6 A4
SA_DQ3 SA_CK1 M_CLK_DDR1 12 SB_DQ6
M_A_DQ4 B10 Y5 M_B_DQ7 C4
SA_DQ4 SA_CK1# M_CLK_DDR#1 12 SB_DQ7
M_A_DQ5 D10 P6 M_B_DQ8 D1
SA_DQ5 SA_CKE1 M_CKE1 12 SB_DQ8
M_A_DQ6 E10 M_B_DQ9 D2
M_A_DQ7 SA_DQ6 M_B_DQ10 SB_DQ9
A8 F2 AB8 M_CS#2 13
M_A_DQ8 SA_DQ7 M_B_DQ11 SB_DQ10 SB_CS0#
D8 F1 AD6 M_CS#3 13
M_A_DQ9 SA_DQ8 M_B_DQ12 SB_DQ11 SB_CS1#
F10 AE2 M_CS#0 12 C2
M_A_DQ10 SA_DQ9 SA_CS0# M_B_DQ13 SB_DQ12
E6 AE8 M_CS#1 12 F5
M_A_DQ11 SA_DQ10 SA_CS1# M_B_DQ14 SB_DQ13
F7 F3
M_A_DQ12 SA_DQ11 M_B_DQ15 SB_DQ14
E9 G4 AC7 M_ODT2 13
M_A_DQ13 SA_DQ12 M_B_DQ16 SB_DQ15 SB_ODT0
B7 H6 AD1 M_ODT3 13
M_A_DQ14 SA_DQ13 M_B_DQ17 SB_DQ16 SB_ODT1
E7 AD8 M_ODT0 12 G2
M_A_DQ15 SA_DQ14 SA_ODT0 M_B_DQ18 SB_DQ17
C6 AF9 M_ODT1 12 J6
M_A_DQ16 SA_DQ15 SA_ODT1 M_B_DQ19 SB_DQ18
H10 J3
M_A_DQ17 SA_DQ16 M_B_DQ20 SB_DQ19
G8 G1 M_B_DM[7..0] 13
M_A_DQ18 SA_DQ17 M_B_DQ21 SB_DQ20 M_B_DM0
K7 G5 D4
M_A_DQ19 SA_DQ18 M_B_DQ22 SB_DQ21 SB_DM0 M_B_DM1
J8 J2 E1
M_A_DQ20 SA_DQ19 M_B_DQ23 SB_DQ22 SB_DM1 M_B_DM2
G7 J1 H3
M_A_DQ21 SA_DQ20 M_B_DQ24 SB_DQ23 SB_DM2 M_B_DM3
G10 M_A_DM[7..0] 12 J5 K1
M_A_DQ22 SA_DQ21 M_A_DM0 M_B_DQ25 SB_DQ24 SB_DM3 M_B_DM4
J7 B9 K2 AH1
M_A_DQ23 SA_DQ22 SA_DM0 M_A_DM1 M_B_DQ26 SB_DQ25 SB_DM4 M_B_DM5
J10 D7 L3 AL2
M_A_DQ24 SA_DQ23 SA_DM1 M_A_DM2 M_B_DQ27 SB_DQ26 SB_DM5 M_B_DM6
L7 H7 M1 AR4
M_A_DQ25 SA_DQ24 SA_DM2 M_A_DM3 M_B_DQ28 SB_DQ27 SB_DM6 M_B_DM7
M6 M7 K5 AT8
M_A_DQ26 SA_DQ25 SA_DM3 M_A_DM4 M_B_DQ29 SB_DQ28 SB_DM7
M8 AG6 K4
M_A_DQ27 SA_DQ26 SA_DM4 M_A_DM5 M_B_DQ30 SB_DQ29
L9 AM7 M4
M_A_DQ28 SA_DQ27 SA_DM5 M_A_DM6 M_B_DQ31 SB_DQ30
L6 AN10 N5
M_A_DQ29 SA_DQ28 SA_DM6 M_A_DM7 M_B_DQ32 SB_DQ31
K8 AN13 AF3
M_A_DQ30 SA_DQ29 SA_DM7 M_B_DQ33 SB_DQ32
N8 AG1 M_B_DQS#[7..0] 13
M_A_DQ31 SA_DQ30 M_B_DQ34 SB_DQ33 M_B_DQS#0
P9 AJ3 D5
M_A_DQ32 SA_DQ31 M_B_DQ35 SB_DQ34 SB_DQS0# M_B_DQS#1
AH5 AK1 F4
M_A_DQ33 SA_DQ32 M_B_DQ36 SB_DQ35 SB_DQS1# M_B_DQS#2
AF5 M_A_DQS#[7..0] 12 AG4 J4
M_A_DQ34 SA_DQ33 M_A_DQS#0 M_B_DQ37 SB_DQ36 SB_DQS2# M_B_DQS#3
AK6 C9 AG3 L4
M_A_DQ35 SA_DQ34 SA_DQS0# M_A_DQS#1 M_B_DQ38 SB_DQ37 SB_DQS3# M_B_DQS#4
AK7 F8 AJ4 AH2
M_A_DQ36 SA_DQ35 SA_DQS1# M_A_DQS#2 M_B_DQ39 SB_DQ38 SB_DQS4# M_B_DQS#5
AF6 J9 AH4 AL4
M_A_DQ37 SA_DQ36 SA_DQS2# M_A_DQS#3 M_B_DQ40 SB_DQ39 SB_DQS5# M_B_DQS#6
AG5 N9 AK3 AR5
C M_A_DQ38 AJ7
SA_DQ37
SA_DQ38
SA_DQS3#
SA_DQS4#
AH7 M_A_DQS#4 M_B_DQ41 AK4
SB_DQ40
SB_DQ41
SB_DQS6#
SB_DQS7#
AR8 M_B_DQS#7 C
DDR SYSTEM MEMORY A

M_A_DQ39 AJ6 AK9 M_A_DQS#5 M_B_DQ42 AM6


SA_DQ39 SA_DQS5# SB_DQ42

DDR SYSTEM MEMORY - B


M_A_DQ40 AJ10 AP11 M_A_DQS#6 M_B_DQ43 AN2
M_A_DQ41 SA_DQ40 SA_DQS6# M_A_DQS#7 M_B_DQ44 SB_DQ43
AJ9 AT13 AK5
M_A_DQ42 SA_DQ41 SA_DQS7# M_B_DQ45 SB_DQ44
AL10 AK2
M_A_DQ43 SA_DQ42 M_B_DQ46 SB_DQ45
AK12 AM4
M_A_DQ44 SA_DQ43 M_B_DQ47 SB_DQ46
AK8 AM3 M_B_DQS[7..0] 13
M_A_DQ45 SA_DQ44 M_B_DQ48 SB_DQ47 M_B_DQS0
AL7 M_A_DQS[7..0] 12 AP3 C5
M_A_DQ46 SA_DQ45 M_A_DQS0 M_B_DQ49 SB_DQ48 SB_DQS0 M_B_DQS1
AK11 C8 AN5 E3
M_A_DQ47 SA_DQ46 SA_DQS0 M_A_DQS1 M_B_DQ50 SB_DQ49 SB_DQS1 M_B_DQS2
AL8 F9 AT4 H4
M_A_DQ48 SA_DQ47 SA_DQS1 M_A_DQS2 M_B_DQ51 SB_DQ50 SB_DQS2 M_B_DQS3
AN8 H9 AN6 M5
M_A_DQ49 SA_DQ48 SA_DQS2 M_A_DQS3 M_B_DQ52 SB_DQ51 SB_DQS3 M_B_DQS4
AM10 M9 AN4 AG2
M_A_DQ50 SA_DQ49 SA_DQS3 M_A_DQS4 M_B_DQ53 SB_DQ52 SB_DQS4 M_B_DQS5
AR11 AH8 AN3 AL5
M_A_DQ51 SA_DQ50 SA_DQS4 M_A_DQS5 M_B_DQ54 SB_DQ53 SB_DQS5 M_B_DQS6
AL11 AK10 AT5 AP5
M_A_DQ52 SA_DQ51 SA_DQS5 M_A_DQS6 M_B_DQ55 SB_DQ54 SB_DQS6 M_B_DQS7
AM9 AN11 AT6 AR7
M_A_DQ53 SA_DQ52 SA_DQS6 M_A_DQS7 M_B_DQ56 SB_DQ55 SB_DQS7
AN9 AR13 AN7
M_A_DQ54 SA_DQ53 SA_DQS7 M_B_DQ57 SB_DQ56
AT11 AP6
M_A_DQ55 SA_DQ54 M_B_DQ58 SB_DQ57
AP12 AP8
M_A_DQ56 SA_DQ55 M_B_DQ59 SB_DQ58
AM12 AT9
M_A_DQ57 SA_DQ56 M_B_DQ60 SB_DQ59
AN12 M_A_A[15..0] 12 AT7
M_A_DQ58 SA_DQ57 M_A_A0 M_B_DQ61 SB_DQ60
AM13 Y3 AP9
M_A_DQ59 SA_DQ58 SA_MA0 M_A_A1 M_B_DQ62 SB_DQ61
AT14 W1 AR10 M_B_A[15..0] 13
M_A_DQ60 SA_DQ59 SA_MA1 M_A_A2 M_B_DQ63 SB_DQ62 M_B_A0
AT12 AA8 AT10 U5
M_A_DQ61 SA_DQ60 SA_MA2 M_A_A3 SB_DQ63 SB_MA0 M_B_A1
AL13 AA3 V2
M_A_DQ62 SA_DQ61 SA_MA3 M_A_A4 SB_MA1 M_B_A2
AR14 V1 T5
M_A_DQ63 SA_DQ62 SA_MA4 M_A_A5 SB_MA2 M_B_A3
AP14 AA9 V3
SA_DQ63 SA_MA5 M_A_A6 SB_MA3 M_B_A4
V8 R1
SA_MA6 M_A_A7 SB_MA4 M_B_A5
T1 13 M_B_BS0 AB1 T8
SA_MA7 M_A_A8 SB_BS0 SB_MA5 M_B_A6
Y9 13 M_B_BS1 W5 R2
SA_MA8 M_A_A9 SB_BS1 SB_MA6 M_B_A7
12 M_A_BS0 AC3 U6 13 M_B_BS2 R7 R6
SA_BS0 SA_MA9 M_A_A10 SB_BS2 SB_MA7 M_B_A8
12 M_A_BS1 AB2 AD4 R4
SA_BS1 SA_MA10 M_A_A11 SB_MA8 M_B_A9
12 M_A_BS2 U7 T2 R5
SA_BS2 SA_MA11 M_A_A12 SB_MA9 M_B_A10
U3 13 M_B_CAS# AC5 AB5
SA_MA12 M_A_A13 SB_CAS# SB_MA10 M_B_A11
AG8 13 M_B_RAS# Y7 P3
SA_MA13 M_A_A14 SB_RAS# SB_MA11 M_B_A12
T3 13 M_B_WE# AC6 R3
SA_MA14 M_A_A15 SB_WE# SB_MA12 M_B_A13
12 M_A_CAS# AE1 V9 AF7
SA_CAS# SA_MA15 SB_MA13 M_B_A14
12 M_A_RAS# AB3 P5
SA_RAS# SB_MA14 M_B_A15
12 M_A_WE# AE9 N1
SA_WE# SB_MA15

B B

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(3/7)
Size Document Number Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 6 of 59

5 4 3 2 1
5 4 3 2 1

CPU1F 6 OF 9

1D05V_S0

AUBURNDALE
VCC_CORE
PROCESSOR CORE POWER
30pcs : 10uF 6.3V X5R 1D05V_VTT

48A -->Arrandale AG35


VCC VTT0
AH14
AG34 AH12 C178 C161 C159 C156 C153 C164 C179

1
VCC VTT0
AG33 AH11
VCC VTT0

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
VCC_CORE AG32 AH10
VCC VTT0
D AG31 J14
D

2
VCC VTT0
AG30 J13
VCC VTT0
AG29 H14
VCC VTT0
AG28 H12
C165 C162 C160 C154 C157 C151 VCC VTT0
AG27 G14
1

1
VCC VTT0
AG26 G13
VCC VTT0
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
AF35 G12
VCC VTT0
AF34 G11
2

2
VCC VTT0
AF33 F14
VCC VTT0
AF32 F13
VCC VTT0
AF31 F12
VCC VTT0
AF30 F11
VCC VTT0
AF29
VCC VTT0
E14 The decoupling capacitors, filter
AF28 E12
AF27
VCC VTT0
D14 recommendations and sense resistors on the
VCC VTT0
AF26
VCC VTT0
D13 CPU/PCH Rails are specific to the CRB

1.1V RAIL POWER


AD35 D12
C144 C143 C142 C137 C141 C645 AD34
VCC VTT0
D11 Implementation. Customers need to follow the
1

1
VCC VTT0
AD33
VCC VTT0
C14 recommendations in the Calpella Platform
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
AD32 C13
AD31
VCC VTT0
C12 Design Guide.
2

VCC VTT0
AD30 C11
VCC VTT0
AD29 B14
VCC VTT0
AD28 B12
VCC VTT0
AD27 A14
AD26
VCC
VCC
VTT0
VTT0
A13 1D05V_S0
AC35 A12
VCC VTT0
AC34 A11
VCC VTT0
AC33
C627 C630 C633 C132 C134 C644 VCC 1D05V_VTT
AC32
1

VCC
AC31
VCC
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

AC30 AF10
VCC VTT0
AC29 AE10
2

VCC VTT0 C177 C176


AC28 AC10

1
VCC VTT0

CPU CORE SUPPLY


AC27 AB10
VCC VTT0 1D05V_S0

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
AC26 Y10
VCC VTT0
AA35 W10

2
VCC VTT0
AA34 U10
VCC VTT0
AA33 T10
VCC VTT0 1225 1D05V_VTT
AA32 J12
VCC VTT0
AA31 J11
VCC VTT0 +VTT_43 R1023
AA30 J16 1 2 0R0402-PAD
C C643 C641 C639 C169 C172 C168
AA29
AA28
VCC
VCC
VTT0
VTT0
J15 +VTT_44 R1022 1 2 0R0402-PAD C
1

VCC
AA27
VCC
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

AA26
VCC
Y35
Please note that the VTT Rail
2

VCC
Y34
VCC
Y33
Y32
VCC Values are Auburndale
VCC
Y31
Y30
VCC VTT=1.05V; Clarksfield
VCC
Y29
VCC VTT=1.1V
Y28
VCC
Y27
VCC
Y26
VCC
V35 AN33 PSI# 36
C166 C158 C635 C637 C152 C155 VCC PSI#
V34
1

VCC
V33 H_VID[6..0] 36
VCC
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

V32 AK35 H_VID0


VCC VID0 H_VID1
V31 AK33
2

VCC VID1 H_VID2


V30 POWER AK34
VCC VID2 H_VID3
V29 AL35
VCC VID3
V28
VCC CPU VIDS VID4
AL33 H_VID4
V27 AM33 H_VID5
VCC VID5 H_VID6
V26 AM35
VCC VID6
U35 AM34 PM_DPRSLPVR 36
VCC PROC_DPRSLPVR
U34
VCC
U33
VCC
U32
VCC H_VTTVID1
U31 G15 H_VTTVID1 39
VCC VTT_SELECT
U30
VCC
U29
VCC Clarksfield H_VTTVID1 = Low, VTT = 1.1V
U28
U27
VCC Arrandale H_VTTVID1 = High, VTT = 1.05V
VCC
U26
VCC
R35
VCC
R34
VCC
R33
VCC
R32 AN35 IMVP_IMON 36
VCC ISENSE
R31
VCC
R30
VCC
R29
B R28
VCC
AJ34
B
SENSE LINES

VCC VCC_SENSE VCC_SENSE 36


R27 AJ35 VSS_SENSE 36
VCC VSS_SENSE
R26
VCC
P35
VCC
P34 B15 VTT_SENSE 39
VCC VTT_SENSE TP_VSS_SENSE_VTT
P33 A15
VCC VSS_SENSE_VTT
P32
VCC TP47
P31
VCC TPAD28
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC

A A
<Variant Name>

Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C

Title
<Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Tuesday, April 06, 2010 Sheet 7 of 59

5 4 3 2 1
5 4 3 2 1

VCC_GFXCORE
CPU1G 7 OF 9

AT21

AUBURNDALE
VAXG1
AT19 AR22 VCC_AXG_SENSE 41
VAXG2 VAXG_SENSE

SENSE
LINES
AT18 AT22 VSS_AXG_SENSE 41
VAXG3 VSSAXG_SENSE
AT16
C149 C145 C150 C114 C116 C148 C147 C146 VAXG4
AR21

1
(R) (R) VAXG5
AR19
VAXG6

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
AR18
VAXG7 GFX_VID0
AR16 AM22

2
VAXG8 GFX_VID0 GFX_VID1
AP21 AP22
VAXG9 GFX_VID1

GRAPHICS VIDs
AP19 AN22 GFX_VID2
VAXG10 GFX_VID2 GFX_VID3
AP18 AP23 GFX_VID[6..0] 41
VAXG11 GFX_VID3
D AP16
AN21
VAXG12
VAXG13
GFX_VID4
GFX_VID5
AM23
AP24
GFX_VID4
GFX_VID5 D

GRAPHICS
AN19 AN24 GFX_VID6
VAXG14 GFX_VID6
AN18
VAXG15
AN16
VAXG16
AM21 AR25 GFX_VR_EN 41
VAXG17 GFX_VR_EN
AM19 AT25 GFX_DPRSLPVR 41
VAXG18 GFX_DPRSLPVR
SB 1209 AM18
AM16
VAXG19 GFX_IMON
AM24 GFX_IMON 41
VAXG20
AL21
VAXG21
AL19
VAXG22 1D5V_S3
AL18
VAXG23
AL16
AK21
AK19
VAXG24
VAXG25 VDDQ
AJ1
AF1
6A
C626 C652 C650 C629

1
VAXG26 VDDQ C634 C642 C632 C651

- 1.5V RAILS
AK18 AE7
VAXG27 VDDQ

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
AK16 AE4
VAXG28 VDDQ

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
AJ21 AC1

2
VAXG29 VDDQ
AJ19 AB7
VAXG30 VDDQ
AJ18 AB4
VAXG31 VDDQ
AJ16 Y1
VAXG32 VDDQ
AH21 W7
VAXG33 VDDQ
AH19 W4
VAXG34 VDDQ
AH18 U1
1D05V_S0 AH16
VAXG35
VAXG36
VDDQ
VDDQ
T7
T4
VDDQ

POWER
P1
VDDQ
N7
1D05V_VTT VDDQ
Please note that the VTT Rail VDDQ
N4

DDR3
L1
VDDQ
Values are Auburndale J24
VTT1 VDDQ
H1

FDI
J23
VTT=1.05V; Clarksfield C631 H25
VTT1 1D05V_S0
1

1
C646 VTT1
VTT=1.1V
SC10U6D3V3MX-GP

SC1U6D3V2KX-GP
P10
2

VTT1 1D05V_VTT
N10
VTT1
L10
1D05V_S0 VTT1
VTT1
K10
C648

1
C638

SC10U6D3V3MX-GP
C 1D05V_S0 C

SC1U6D3V2KX-GP
1D05V_VTT
18A

2
1.1V
J22
VTT1
K26 J20
VTT1 VTT1
J27 J18
VTT1 VTT1

PEG & DMI


C649 C647 C640 J26 H21 1D05V_VTT
1

TC21 (R) VTT1 VTT1


J25 H20
VTT1 VTT1
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

C636 H27 H19


VTT1 VTT1
ST220U2D5VBM-2GP

DY G28 C175
2

1
VTT1 C180
G27
VTT1
SC1U6D3V2KX-GP

SC10U6D3V3MX-GP
G26
VTT1

SC1U6D3V2KX-GP
F26

2
VTT1
E26 L26
VTT1 VTT1

1.8V
E25 L27
VTT1 VTT1
M26
VTT1
1D8V_S0

+V1.8S_VCCSFR
0.6A 1
R297
2
C220 C181

1
C217 C174 C231 0R0603-PAD-1-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP
2

2
B B

A A
<Variant Name>

Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C

Title
<Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Tuesday, April 06, 2010 Sheet 8 of 59

5 4 3 2 1
5 4 3 2 1

CPU1H 8 OF 9 CPU1I 9 OF 9

AT20 AE34
VSS VSS
AT17 AE33

AUBURNDALE

AUBURNDALE
VSS VSS
AR31 AE32 K27
VSS VSS VSS
AR28 AE31 K9
VSS VSS VSS
AR26 AE30 K6
VSS VSS VSS
AR24 AE29 K3
VSS VSS VSS
AR23 AE28 J32
VSS VSS VSS
AR20 AE27 J30
VSS VSS VSS
AR17 AE26 J21
VSS VSS VSS
AR15 AE6 J19
VSS VSS VSS
AR12 AD10 H35
VSS VSS VSS
AR9 AC8 H32
VSS VSS VSS
D AR6
AR3
AP20
VSS
VSS
VSS
VSS
AC4
AC2
AB35
H28
H26
H24
VSS
VSS
D
VSS VSS VSS
AP17 AB34 H22
VSS VSS VSS
AP13 AB33 H18
VSS VSS VSS
AP10 AB32 H15
VSS VSS VSS
AP7 AB31 H13
VSS VSS VSS
AP4 AB30 H11
VSS VSS VSS
AP2 AB29 H8
VSS VSS VSS
AN34 AB28 H5
VSS VSS VSS
AN31 AB27 H2
VSS VSS VSS
AN23 AB26 G34
VSS VSS VSS
AN20 AB6 G31
VSS VSS VSS
AN17 AA10 G20
VSS VSS VSS
AM29 Y8 G9
VSS VSS VSS
AM27 Y4 G6
VSS VSS VSS
AM25 Y2 G3
VSS VSS VSS
AM20 W35 F30
VSS VSS VSS
AM17 W34 F27
VSS VSS VSS
AM14 W33 F25
VSS VSS VSS
AM11 W32 F22
VSS VSS VSS
AM8 W31 F19
VSS VSS VSS
AM5 W30 F16
VSS VSS VSS
AM2 W29 E35
VSS VSS VSS
AL34 W28 E32
AL31
AL23
VSS
VSS
VSS
VSS VSS
VSS
VSS
W27
W26
E29
E24
VSS
VSS
VSS
VSS
AL20 W6 E21
VSS VSS VSS
AL17 V10 E18
VSS VSS VSS
AL12 U8 E13
VSS VSS VSS
AL9 U4 E11
VSS VSS VSS
AL6 U2 E8
VSS VSS VSS
AL3 T35 E5
VSS VSS VSS
AK29 T34 E2 AR34
VSS VSS VSS VSS_NCTF#AR34
AK27 T33 D33 B34
VSS VSS VSS VSS_NCTF#B34
AK25 T32 D30 B2
VSS VSS VSS VSS_NCTF#B2

AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35
AK20 T31 D26

A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35,
VSS VSS VSS
AK17 T30 D9
VSS VSS VSS TP_MCP_VSS_NCTF6 TP8 TPAD28
AJ31 T29 D6 B1
VSS VSS VSS VSS_NCTF#B1 TP_MCP_VSS_NCTF1 TP9 TPAD28
AJ23 T28 D3 A35
VSS VSS VSS VSS_NCTF#A35 TP_MCP_VSS_NCTF2 TP1 TPAD28
AJ20 T27 C34 AT1
VSS VSS VSS VSS_NCTF#AT1 TP_MCP_VSS_NCTF7 TP18 TPAD28
AJ17 T26 C32 AT35
C AJ14
AJ11
VSS
VSS
VSS
VSS
VSS
VSS
T6
R10
C29
C28
VSS
VSS
VSS
VSS_NCTF#AT35
RSVD_NCTF#AT33
RSVD_NCTF#AT34
AT33
AT34
C
AJ8 P8 C24 AP35
VSS VSS VSS RSVD_NCTF#AP35
AJ5 P4 C22 AR35
VSS VSS VSS RSVD_NCTF#AR35
AJ2 P2 C20 AT3
VSS VSS VSS RSVD_NCTF#AT3
AH35 N35 C19 AR1
VSS VSS VSS RSVD_NCTF#AR1
AH34 N34 C16 AP1
VSS VSS VSS RSVD_NCTF#AP1
AH33 N33 B31 AT2
VSS VSS VSS RSVD_NCTF#AT2
AH32 N32 B25 C1
VSS VSS VSS RSVD_NCTF#C1
AH31 N31 B21 A3

NCTF TEST PIN:


VSS VSS VSS RSVD_NCTF#A3
AH30 N30 B18 C35
VSS VSS VSS RSVD_NCTF#C35
AH29 N29 B17 B35
VSS VSS VSS RSVD_NCTF#B35
AH28 N28 B13 A34
VSS VSS VSS RSVD_NCTF#A34
AH27 N27 B11 A33
VSS VSS VSS RSVD_NCTF#A33
AH26 N26 B8
VSS VSS VSS
AH20 N6 B6
VSS VSS VSS
AH17 M10 B4
VSS VSS VSS
AH13 L35 A29
VSS VSS VSS
AH9 L32 A27
VSS VSS VSS
AH6 L29 A23
VSS VSS VSS
AH3 L8 A9
VSS VSS VSS
AG10 L5
VSS VSS
AF8 L2
VSS VSS
AF4 K34
VSS VSS
AF2 K33
VSS VSS
AE35 K30
VSS VSS

B B

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(6/7)
Size Document Number Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 9 of 59

5 4 3 2 1
5 4 3 2 1

CPU1E 5 OF 9

AJ13 CFG0 PCI-Express Configuration Select

AUBURNDALE
RSVD#AJ13
AJ12

1
RSVD#AJ12
AP25 (R) R207 1:Single PEG
SO-DIMM VREFDQ (M3) Circuit AL25
RSVD#AP25
RSVD#AL25 RSVD#AH25
AH25 DY 3KR2F-GP CFG0 0:Bifurcation enabled
AL24 AK26
for Clarksfield Processor AL22
RSVD#AL24 RSVD#AK26

2
RSVD#AL22
AJ33 AL26
RSVD#AJ33 RSVD#AL26
AG9 AR2
RSVD#AG9 RSVD_NCTF#AR2
M27
RN33 RSVD#M27
DY L28
RSVD#L28 RSVD#AJ26
AJ26

D 12 M_VREF_DQ_DIMM0
13 M_VREF_DQ_DIMM1
1
2
4
3
H_RSVD9_R
H_RSVD10_R
J17
H17
G25
SA_DIMM_VREF#
SB_DIMM_VREF#
RSVD#AJ27
AJ27
CFG3 CFG3 - PCI-Express Static Lane Reversal D

1
SRN0J-10-GP-U RSVD#G25
G17
RSVD#G17 R211
E31
RSVD#E31 1 :Normal Operation
E30 3KR2F-GP CFG3
(R) RSVD#E30 0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...

2
AL28
CFG0 RSVD#AL28
AM30 AL29
TPAD28 TP27 CFG1 CFG0 RSVD#AL29 CFG4
AM28
CFG1 RSVD#AP30
AP30 CFG4 - Display Port Presence
TPAD28 TP21 CFG2 AP31 AP32

1
CFG3 CFG2 RSVD#AP32
AL32 AL27
CFG4 CFG3 RSVD#AL27 (R) R208
AL30
CFG4 RSVD#AT31
AT31 1:Disabled; No Physical Display Port
TPAD28 TP28 CFG5 AM31
CFG5 RSVD#AT32
AT32 DY 3KR2F-GP CFG4 attached to Embedded Display Port
TPAD28 TP25 CFG6 AN29 AP33
CFG7 CFG6 RSVD#AP33 0:Enabled; An external Display Port
AM32 AR33

2
TPAD28 TP37 CFG8 CFG7 RSVD#AR33
AK32 device is connected to the Embedded
TPAD28 TP33 CFG9 CFG8
AK31

RESERVED
TPAD28 TP29 CFG10 AK28
CFG9 Display Port
TPAD28 TP31 CFG11 CFG10
AJ28
TPAD28 TP23 CFG12 CFG11
AN30 AR32
TPAD28 TP26 CFG13 CFG12 RSVD#AR32
AN32
TPAD28 TP34 CFG14 CFG13
AJ32
TPAD28 TP32 CFG15 CFG14 1225
AJ29 E15
TPAD28 TP35 CFG16 CFG15 RSVD_TP#E15
AJ30 F15
TPAD28 TP30 CFG17 CFG16 RSVD_TP#F15 CFG7
AK30
CFG17 KEY
A2 CFG7(Reserved) - Temporarily used for early
H16 D15
Clarksfield samples.

1
RSVD_TP#H16 RSVD#D15 SRN0J-10-GP-U
C15
RSVD#C15 RSVD64_R (R) R209
AJ15 2 3
RSVD#AJ15
RSVD#AH15
AH15 RSVD65_R 1 4 DY 3KR2F-GP CFG7 Clarksfield (only for early samples pre-ES1) -
1225
B19 RN25 Connect to GND with 3.01K Ohm/5% resistor.

2
RSVD#B19 (R)
A19
RN34 RSVD#A19
Note: Only temporary for early CFD sample
1 4 H_RSVD17_R A20
2 3 H_RSVD18_R B20
RSVD#A20 (rPGA/BGA) [For details please refer to the
RSVD#B20 WW33 MoW and sighting report].
AA5
C SRN0J-10-GP-U U9
T9
RSVD#U9
RSVD#T9
RSVD_TP#AA5
RSVD_TP#AA4
RSVD_TP#R8
AA4
R8
For a common M/B design (for AUB and CFD), C
(R) AD3 the pull-down resistor shouble be used. Does
RSVD_TP#AD3
AC9
RSVD#AC9 RSVD_TP#AD2
AD2 not impact AUB functionality.
AB9 AA2
RSVD#AB9 RSVD_TP#AA2
AA1
RSVD_TP#AA1
R9
RSVD_TP#R9
AG7
RSVD_TP#AG7
AE3
RSVD_TP#AE3

V4
RSVD_TP#V4
V5
RSVD_TP#V5
N2
RSVD_TP#N2
J29
RSVD#J29 RSVD_TP#AD5
AD5 VSS (AP34) can be left NC is
J28 AD7
RSVD#J28 RSVD_TP#AD7
W3 CRB implementation; EDS/DG
RSVD_TP#W3
RSVD_TP#W2
W2 recommendation to GND.
N3
RSVD_TP#N3
AE5
RSVD_TP#AE5
AD9
RSVD_TP#AD9

AP34 RSVD_VSS 1 2
VSS R199
0R2J-2-GP

B B

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number


CPU(7/7) Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 10 of 59

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A
<Variant Name>

Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C

Title
<Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Tuesday, April 06, 2010 Sheet 11 of 59

5 4 3 2 1
5 4 3 2 1

3D3V_S0

6 M_A_A[15..0] DIMM1

1
M_A_A0 98 NP1 (R) R624
A0 NP1 CHECK
D M_A_A1
M_A_A2
M_A_A3
97
96
A1
A2
NP2
NP2 DY 10KR2J-3-GP
D
95 110 M_A_RAS# 6 Note:

2
M_A_A4 A3 RAS#
92 113 M_A_WE# 6
M_A_A5 A4 WE# If SA0 DIM0 = 0, SA1_DIM0 = 0
91 115 M_A_CAS# 6
M_A_A6 A5 CAS# SA0_DIM0
90 SO-DIMMA SPD Address is 0xA0
M_A_A7 A6
86 114 M_CS#0 6
A7 CS0#
M_A_A8 89
A8 CS1#
121 M_CS#1 6
SA1_DIM0 SO-DIMMA TS Address is 0x30
M_A_A9 85
M_A_A10 A9
107 73 M_CKE0 6

1
A10/AP CKE0
M_A_A11 84
A11 CKE1
74 M_CKE1 6 If SA0 DIM0 = 1, SA1_DIM0 = 0
M_A_A12 83 R616 R625
M_A_A13 119
A12
101 10KR2J-3-GP 10KR2J-3-GP SO-DIMMA SPD Address is 0xA2
A13 CK0 M_CLK_DDR0 6
M_A_A14 80 103 SO-DIMMA TS Address is 0x32
A14 CK0# M_CLK_DDR#0 6
M_A_A15 78

2
A15
79 102 M_CLK_DDR1 6
6 M_A_BS2 A16/BA2 CK1
104 M_CLK_DDR#1 6
CK1#
109 M_A_DM[7..0] 6
6 M_A_BS0 BA0 M_A_DM0
108 11
6 M_A_BS1 BA1 DM0 M_A_DM1
6 M_A_DQ[63..0] 28
M_A_DQ0 DM1 M_A_DM2
5 46
M_A_DQ1 DQ0 DM2 M_A_DM3
7 63
M_A_DQ2 DQ1 DM3 M_A_DM4
15 136
M_A_DQ3 DQ2 DM4 M_A_DM5
M_A_DQ4
17
4
DQ3 DM5
153
170 M_A_DM6
1221 (SC)
M_A_DQ5 DQ4 DM6 M_A_DM7
6 187
M_A_DQ6 DQ5 DM7
16
M_A_DQ7 DQ6 SODIMM0_1_SMB_DATA_R
18 200 1 R614 2 0R0402-PAD-1-GP PCH_SMBDATA 3,13,15,29,58
M_A_DQ8 DQ7 SDA SODIMM0_1_SMB_CLK_R
21 202 1 R608 2 0R0402-PAD-1-GP PCH_SMBCLK 3,13,15,29,58
M_A_DQ9 DQ8 SCL 1225
23
M_A_DQ10 DQ9 TS#_DIMM0 3D3V_S0
33 198 1 R617 2 PM_EXTTS#0_R 5
M_A_DQ11 DQ10 EVENT# 0R0402-PAD
35
M_A_DQ12 DQ11
22 199
M_A_DQ13 DQ12 VDDSPD
24

2
M_A_DQ14 DQ13 SA0_DIM0 C573
34 197
M_A_DQ15 DQ14 SA0 SA1_DIM0 C574
36 201
DQ15 SA1

SCD1U10V2KX-5GP
M_A_DQ16 39 SC2D2U10V3KX-1GP

1
M_A_DQ17 DQ16
41 77
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 1D5V_S3
53 125
1D5V_S3 M_A_DQ20 DQ19 NC#/TEST
40
M_A_DQ21 DQ20
42 75
C M_A_DQ22 50
DQ21 VDD1
76 C
1

R675 M_A_DQ23 DQ22 VDD2


52 81
R639 M_A_DQ24 DQ23 VDD3
1 2 DDRVTT_REF_R 13,38 57 82
(R) 1KR2F-3-GP M_A_DQ25 DQ24 VDD4
59 87
0R2J-2-GP M_A_DQ26 DQ25 VDD5
67 88
M_A_DQ27 DQ26 VDD6
69 93 SODIMM A DECOUPLING
2

DIMM0_VREF_CADQ M_A_DQ28 DQ27 VDD7


56 94
M_A_DQ29 DQ28 VDD8
58 99
1

M_A_DQ30 DQ29 VDD9 1D5V_S3


68 100
(R) R633 M_A_DQ31 DQ30 VDD10
70 105
1KR2F-3-GP M_A_DQ32 DQ31 VDD11
129 106
M_A_DQ33 DQ32 VDD12
131 111
M_A_DQ34 DQ33 VDD13
141 112
2

M_A_DQ35 DQ34 VDD14 (R) (R)


143 117

1
M_A_DQ36 DQ35 VDD15 C610 C592 C603 C598 C591
130 118
DQ36 VDD16

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
M_A_DQ37 132 123
M_A_DQ38 DQ37 VDD17
140 124

2
M_A_DQ39 DQ38 VDD18
142
DIMM0_VREF_CADQ R636 1 M_VREF_CA_DIMM0 M_A_DQ40 DQ39
2 147 2
0R3J-0-U-GP M_A_DQ41 DQ40 VSS
149 3
1

M_A_DQ42 DQ41 VSS


157 8
C579 C581 M_A_DQ43 DQ42 VSS
159 9
SCD1U10V2KX-5GP M_A_DQ44 DQ43 VSS
SC2D2U10V3KX-1GP 146 13
2

M_A_DQ45 DQ44 VSS check layout spacing


148 14
M_A_DQ46 DQ45 VSS
158 19
M_A_DQ47 DQ46 VSS
160 20
M_A_DQ48 DQ47 VSS
163 25
DIMM0_VREF_CADQ R676 1 M_VREF_DQ_DIMM0 M_A_DQ49 DQ48 VSS C605 C599 C586 C612 C609 C601
2 165 26

1
DQ49 VSS

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
0R3J-0-U-GP M_A_DQ50 175 31 (R) (R)
1

M_A_DQ51 DQ50 VSS


177 32
C619 C621 M_A_DQ52 DQ51 VSS
164 37

2
SCD1U10V2KX-5GP M_A_DQ53 DQ52 VSS
SC2D2U10V3KX-1GP 166 38
2

M_A_DQ54 DQ53 VSS


174 43
M_A_DQ55 DQ54 VSS
176 44
M_A_DQ56 DQ55 VSS
181 48
M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
191 54
M_A_DQ59 DQ58 VSS
M_A_DQ60
193
DQ59 VSS
55 Place these Caps near SO-DIMMA.
180 60
M_A_DQ61 DQ60 VSS
182 61
M_A_DQ62 DQ61 VSS
192 65
B 6 M_A_DQS#[7..0]
M_A_DQ63

M_A_DQS#0
194
DQ62
DQ63
VSS
VSS
VSS
66
71 B
10 72
M_A_DQS#1 DQS0# VSS
27 127
M_A_DQS#2 DQS1# VSS
45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
135 134
M_A_DQS#5 DQS4# VSS
152 138
M_A_DQS#6 DQS5# VSS
169 139
0D75_S0 M_A_DQS#7 DQS6# VSS
186 144
DQS7# VSS
6 M_A_DQS[7..0] 145
M_A_DQS0 VSS
12 150
1

M_A_DQS1 DQS0 VSS


29 151
R601 M_A_DQS2 DQS1 VSS
47 155
0R0603-PAD-1-GP M_A_DQS3 DQS2 VSS
64 156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 162
2

M_A_DQS6 DQS5 VSS


171 167
MA_VTT M_A_DQS7 DQS6 VSS
Place these caps 188
DQS7 VSS
168
172
close to VTT1 and VSS
116 173
6 M_ODT0 ODT0 VSS
VTT2. 120 178
6 M_ODT1 ODT1 VSS
179
M_VREF_CA_DIMM0 VSS
126 184
M_VREF_DQ_DIMM0 VREF_CA VSS
1 185
10 M_VREF_DQ_DIMM0 VREF_DQ VSS
189
1

C569 C570 C562 C563 VSS


30 190
5,13 DDR3_DRAMRST# RESET# VSS
195
VSS
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

196
2

MA_VTT VSS
203 205
VTT1 VSS
204 206
VTT2 VSS

DDR3-204P-6-GP-U1

H = 9.2mm ϵ͘ϮŵŵZsZ^

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DIMM1
Size Document Number Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 12 of 59

5 4 3 2 1
5 4 3 2 1

6 M_B_A[15..0] DIMM2

M_B_A0 98 NP1
M_B_A1 A0 NP1 3D3V_S0
97 NP2
M_B_A2 A1 NP2
96
M_B_A3 A2
95 110 M_B_RAS# 6
M_B_A4 A3 RAS#
92 113 M_B_WE# 6

1
A4 WE#
D M_B_A5
M_B_A6
M_B_A7
91
90
86
A5
A6
CAS#
115

114
M_B_CAS# 6
R618
10KR2J-3-GP
D
A7 CS0# M_CS#2 6
M_B_A8 89 121
A8 CS1# M_CS#3 6
M_B_A9 85

2
M_B_A10 A9
107 73 M_CKE2 6
M_B_A11 A10/AP CKE0
84 74 M_CKE3 6
M_B_A12 A11 CKE1 SA1_DIM1
83
M_B_A13 A12
119 101 M_CLK_DDR2 6
M_B_A14 A13 CK0 SA0_DIM1
80 103 M_CLK_DDR#2 6
M_B_A15 A14 CK0#
78
A15
79 102 M_CLK_DDR3 6

1
6 M_B_BS2 A16/BA2 CK1
104 M_CLK_DDR#3 6
CK1# R72 (R) R615
109 M_B_DM[7..0] 6
6 M_B_BS0 BA0 M_B_DM0 10KR2J-3-GP DY 10KR2J-3-GP
108 11
6 M_B_BS1 BA1 DM0 M_B_DM1
6 M_B_DQ[63..0] 28
M_B_DQ0 DM1 M_B_DM2
5 46 1221 (SC)

2
M_B_DQ1 DQ0 DM2 M_B_DM3
7 63
M_B_DQ2 DQ1 DM3 M_B_DM4
15 136
M_B_DQ3 DQ2 DM4 M_B_DM5
17 153
M_B_DQ4 DQ3 DM5 M_B_DM6
4 170
M_B_DQ5 DQ4 DM6 M_B_DM7
6 187
M_B_DQ6 DQ5 DM7
16
M_B_DQ7 DQ6 SODIMM1_1_SMB_DATA_R
18 200 1 R606 2 0R0402-PAD-1-GP PCH_SMBDATA 3,12,15,29,58
M_B_DQ8 DQ7 SDA SODIMM1_1_SMB_CLK_R
21 202 1 R600 2 0R0402-PAD-1-GP PCH_SMBCLK 3,12,15,29,58
M_B_DQ9 DQ8 SCL 1225
23
M_B_DQ10 DQ9 TS#_DIMM1 3D3V_S0
33 198 1 R599 2 PM_EXTTS#1_R 5
M_B_DQ11 DQ10 EVENT# 0R0402-PAD
35
M_B_DQ12 DQ11
22 199
M_B_DQ13 DQ12 VDDSPD
24

2
M_B_DQ14 DQ13 SA0_DIM1 C44
34 197
M_B_DQ15 DQ14 SA0 SA1_DIM1 C51
36 201
DQ15 SA1

SCD1U10V2KX-5GP
M_B_DQ16 39 SC2D2U10V3KX-1GP

1
M_B_DQ17 DQ16
41 77
1D5V_S3 M_B_DQ18 DQ17 NC#1
51 122
M_B_DQ19 DQ18 NC#2 1D5V_S3
53 125
M_B_DQ20 DQ19 NC#/TEST
40
1

R212 M_B_DQ21 DQ20


42 75
R217 M_B_DQ22 DQ21 VDD1
1 2 DDRVTT_REF_R 12,38 50 76
(R) 1KR2F-3-GP M_B_DQ23 DQ22 VDD2
52 81
0R2J-2-GP M_B_DQ24 DQ23 VDD3
57 82
M_B_DQ25 DQ24 VDD4
59 87
C C
2

DIMM1_VREF_CADQ M_B_DQ26 DQ25 VDD5


67 88
M_B_DQ27 DQ26 VDD6
69 93
1

M_B_DQ28 DQ27 VDD7


56 94
R220 M_B_DQ29 DQ28 VDD8
58 99
(R) 1KR2F-3-GP M_B_DQ30 DQ29 VDD9
68 100
M_B_DQ31 DQ30 VDD10
70 105
M_B_DQ32 DQ31 VDD11
129 106
2

M_B_DQ33 DQ32 VDD12


131 111
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
130 118
DIMM1_VREF_CADQ R210 1 M_VREF_CA_DIMM1 M_B_DQ37 DQ36 VDD16
2 132 123
0R3J-0-U-GP M_B_DQ38 DQ37 VDD17
140 124
1

M_B_DQ39 DQ38 VDD18


142
C123 C125 M_B_DQ40 DQ39
147 2
SCD1U10V2KX-5GP M_B_DQ41 DQ40 VSS
SC2D2U10V3KX-1GP 149 3
2

M_B_DQ42 DQ41 VSS


157 8
M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
DIMM1_VREF_CADQ R222 1 M_VREF_DQ_DIMM1 M_B_DQ46 DQ45 VSS 1D5V_S3
2
M_B_DQ47
158
DQ46 VSS
19 SODIMM B DECOUPLING
0R3J-0-U-GP 160 20
1

M_B_DQ48 DQ47 VSS


163 25
C140 C138 M_B_DQ49 DQ48 VSS
165 26
SCD1U10V2KX-5GP M_B_DQ50 DQ49 VSS
SC2D2U10V3KX-1GP 175 31
2

M_B_DQ51 DQ50 VSS


177 32

1
M_B_DQ52 DQ51 VSS C602 C593 C113 C106 C94
164 37
DQ52 VSS

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
M_B_DQ53 166 38
M_B_DQ54 DQ53 VSS
174 43

2
M_B_DQ55 DQ54 VSS
176 44
M_B_DQ56 DQ55 VSS
181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 DQ61 VSS
192 65
M_B_DQ63 DQ62 VSS
194 66
DQ63 VSS
6 M_B_DQS#[7..0] 71
M_B_DQS#0 VSS C600 C608 C91 C119 C99 C110
10 72

1
DQS0# VSS

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
M_B_DQS#1 27 127
B M_B_DQS#2
M_B_DQS#3
45
62
DQS1#
DQS2#
VSS
VSS
128
133 B

2
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
6 M_B_DQS[7..0] 145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
M_B_DQS2 DQS1 VSS
47 155
M_B_DQS3 DQS2 VSS
64 156
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
0D75_S0 VSS
116 173
6 M_ODT2 ODT0 VSS
120 178
6 M_ODT3 ODT1 VSS
179
1

M_VREF_CA_DIMM1 VSS
126 184
R603 M_VREF_DQ_DIMM1 VREF_CA VSS
1 185
0R0603-PAD-1-GP 10 M_VREF_DQ_DIMM1 VREF_DQ VSS
189
VSS
30 190
5,12 DDR3_DRAMRST# RESET# VSS
195
2

VSS
196
MB_VTT VSS
203 205
MB_VTT VTT1 VSS
204 206
VTT2 VSS

Place these caps


1

close to VTT1 and C565 C568 C567 C566 DDR3-204P-7-GP-U1


VTT2.
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
2

Note:
SO-DIMMB SPD Address is 0xA4 SO-DIMMB is placed farther from
SO-DIMMB TS Address is 0x34 the Processor than SO-DIMMA

H =5.2mm ϱ͘ϮŵŵZsZ^
A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DIMM2
Size Document Number Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 13 of 59

5 4 3 2 1
5 4 3 2 1

ICH_RTCX2

X2

4 1 ICH_RTCX1 RTC_AUX_S5
RTC_AUX_S5 integrated VccSus1_05,VccSus1_5,VccCL1_5

R289 INTVRMEN High=Enable Low=Disable


3 2 20KR2J-L2-GP 1 2 SM_INTRUDER#

D X-32D768KHZ-38GPU
1
1
R273
2
2
R278
1MR2J-1-GP
INTVRMEN- Integrated SUS
1.1V VRM Enable
integrated VccLan1_05VccCL1_05
LAN100_SLP High=Enable Low=Disable
D

1
SMD 20KR2J-L2-GP C204 1 2 ICH_INTVRMEN High - Enable internal VRs
+- 10ppm CL:12.5P R277

SC1U6D3V2KX-GP
330KR2F-L-GP

2
R269 2 1 10MR3J-L1-GP 1221 (SC) PCH1A 1 OF 10
1

1
C188 C194 ICH_RTCX1 B13 D33
RTCX1 FWH0/LAD0 LPC_LAD0 33,34
SC12P50V3JN-LL-GP SC15P50V2JN-2-LL-GP ICH_RTCX2 D13 B33
RTCX2 FWH1/LAD1 LPC_LAD1 33,34
C32
2

2
FWH2/LAD2 LPC_LAD2 33,34
A32 LPC_LAD3 33,34
ICH_RTCRST# FWH3/LAD3
C14
SRTCRST# new signal Pin RTCRST#
C34 LPC_LFRAME# 33,34

2
SRTCRST# FWH4/LFRAME#
D17

1
C654 G4 SRTCRST#
A34

RTC

LPC
SM_INTRUDER# LDRQ0# PCH_GPIO23 TP50 TPAD28
GAP-OPEN A16 F34
INTRUDER# LDRQ1#/GPIO23

SC1U6D3V2KX-GP

2
ICH_INTVRMEN A14 AB9 INT_SERIRQ
INT_SERIRQ 33

1
INTVRMEN SERIRQ
0127 (1A)
ACZ_BIT_CLK A30
HDA_BCLK
AK7 SATA_RXN0 26
RN60 ACZ_SYNC SATA0RXN
D29 AK6
30 ACZ_RST#_AUDIO 3 2 ACZ_RST# HDA_SYNC SATA0RXP
SATA0TXN
AK11 SATA_TXN0_C C529 1 2 SCD01U50V2KX-1GP
SATA_RXP0
SATA_TXN0
26
26
HDD
4 1 ACZ_BIT_CLK ACZ_SPKR P1 AK9 SATA_TXP0_C C528 1 2 SCD01U50V2KX-1GP
30 ACZ_BITCLK_AUDIO 30 ACZ_SPKR SPKR SATA0TXP SATA_TXP0 26
SRN33J-5-GP-U ACZ_RST# C30
RN63 HDA_RST#
AH6 SATA_RXN1 26
ACZ_SDATAOUT SATA1RXN
4 1 AH5
30 ACZ_SDATAOUT_AUDIO
30 ACZ_SYNC_AUDIO 3 2 ACZ_SYNC 30 ACZ_SDATAIN0 G30
HDA_SDIN0
SATA1RXP
SATA1TXN
AH9 SATA_TXN1_C C957 1 2 SCD01U50V2KX-1GP
SATA_RXP1 26
SATA_TXN1 26
ODD
AH8 SATA_TXP1_C C959 1 2 SCD01U50V2KX-1GP
SATA1TXP SATA_TXP1 26
SRN33J-5-GP-U F30
HDA_SDIN1
AF11
TPAD28 TP51 HDA_SDIN2 SATA2RXN
E32 AF9

IHDA
HDA_SDIN2 SATA2RXP
SB 1211 F32
SATA2TXN
AF7
AF6
HDA_SDIN3 SATA2TXP
If Sample low ,the flash descriptor security will be overwrite
SB 1209 ACZ_SDATAOUT B29
SATA3RXN
AH3
AH1
C 8K2R2J-3-GP
R720
HDA_SDO SATA3RXP
SATA3TXN
SATA3TXP
AF3
AF1 SB 1118
C
MFG1 1 DY HDA_DOCK_EN#_GPIO33
NO REBOOT STRAP 2 H32

SATA
HDA_DOCK_EN#_GPIO33 (R) HDA_DOCK_EN#/GPIO33
1 AD9 SATA_RXN4 25
SOP_ENABLE_GP33_R TPAD28 TP71 HDA_DOCK_EN#_GPIO13 SATA4RXN
2 J30 AD8
3D3V_S0 HDA_DOCK_RST#/GPIO13 SATA4RXP
AD6
SATA_RXP4 25
SATA_TXN4 25
eSATA
1

SATA4TXN
AD5 SATA_TXP4 25
R513 DVD-CON2-15-GP SATA4TXP
ACZ_SPKR 1KR2J-1-GP PCH_JTAG_TCK
1
R250
DY 2 M3
JTAG_TCK SATA5RXN
AD3
1KR2J-1-GP AD1
PCH_JTAG_TMS SATA5RXP
(R) K3 AB3
2

JTAG_TMS SATA5TXN
AB1
PCH_JTAG_TDI SATA5TXP
K1
JTAG_TDI 1D05V_S0
No Reboot Strap R23

JTAG
Low = Default PCH_JTAG_TDO J2 AF16
JTAG_TDO SATAICOMPO
HDA_SPKR High = No Reboot
SPI_CS0#, SPI_MISO, SPI_MOSI, SPI_CLK: PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2
TRST# SATAICOMPI R708
No series resistor required if routing length is 1.5"-6.5"
37D4R2F-GP

PCH_SPI_CLK R258 1 2 15R2J-GP SPI_CLK_R BA2


SPI_CLK
PCH_SPI_CS#0 R243 1 2 15R2J-GP SPI_CS#0_R AV3
SPI_CS0#
AY3 T3 SATA_LED#
SPI_CS1# SATALED# SATA_LED# 26

PCH_SPI_MOSI R260 1 2 15R2J-GP SPI_MOSI_R AY1 Y9 SATA_DET#0_R 2 R246 1


1D05V_S0 SPI_MOSI SATA0GP/GPIO21 WIFI_RF_EN 29
0R0402-PAD

SPI
SPI_MISO_R AV1 V1 SATA_DET#1_R 2 R44 1
SPI_MISO SATA1GP/GPIO19 ODD_LED_EN# 34
0R0402-PAD
PCH_JTAG_TMS 1 R697 2
200R2J-L1-GP IBEXPEAK-M-GP-NF 0126 (1A)
PCH_JTAG_TDO 1 R255 2 (71.0HM55.00U)
200R2J-L1-GP

PCH_JTAG_TDI 1 R252 2 SPI_MOSI Enable iTPM: Connect to Vcc3_3 with


200R2J-L1-GP 8.2-kȍ weak pull-up resistor. 3D3V_S0
RN14
PCH_JTAG_RST# 1 DY 2 Disable iTPM: Left floating, no SATA_DET#0_R 5 4
B R694 (R) 10KR2J-3-GP pull-down required INT_SERIRQ
SATA_LED#
SATA_DET#1_R
6
7
3
2 B
8 1
3D3V_S0 3D3V_S5
SRN10KJ-6-GP
PCH_JTAG_TMS 1 R698 2 1 DY 2 SPI_MOSI_R RTC_AUX_S5 D15 RTC_BAT RTC_BAT
100R2J-2-GP R259 (R) 8K2R2J-3-GP 2

PCH_JTAG_TDO 1 R254 2 3
100R2J-2-GP
1

1 RTC_PWR 1 2

3
1
PCH_JTAG_TDI 1 R253 2 C347 R383
100R2J-2-GP SC1U10V2ZY-GP 1KR2J-1-GP BT1
2

BAS40CW-GP CR2032-3-GP
PCH_JTAG_RST# 1 DY 2 83.00040.E81
R695 (R) 51R2F-2-GP 2nd = 83.00040.M81

2
PCH_JTAG_TCK 1 2
R251 51R2F-2-GP

When unused all JTAG pins may be NC


CHECK PIN Define

ϯϮDďŝƚ 3D3V_S0
System BIOS Flash ROM DĂŝŶ͗Dy/
U10

PCH_SPI_CS#0 1 8
SPI_MISO_R 1 PCH_SPI_MISO CS# VCC PCH_SPI_HOLD#0
2 2 7
R230 33R2J-2-GP PCH_SPI_WP#0 DO HOLD# PCH_SPI_CLK
3 6
WP# CLK PCH_SPI_MOSI
4 5
VSS DI
1

C167

A W25Q32BVSSIG-1-GP
(72.25325.A01)
SCD1U16V2ZY-2GP
A
2

3D3V_S0
SPISKT1
<Core Design>
RN8 1 8
2 7
3 2 PCH_SPI_WP#0 3 6
4 1 PCH_SPI_HOLD#0 4 5 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SKT-G6179-GP-U Taipei Hsien 221, Taiwan, R.O.C.
SRN4K7J-8-GP
Title

PCH(1/9)
Size Document Number Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 14 of 59

5 4 3 2 1
5 4 3 2 1

0126 (1A)
3D3V_EUP

8
7
6
5
RN31
PCH1B 2 OF 10 SRN2K2J-2-GP

PCIE_RXN1 BG30 B9 PCH_GPIO11


29 PCIE_RXN1 PERN1 SMBALERT#/GPIO11 PCH_GPIO11 19
PCIE_RXP1 BJ30

1
2
3
4
29 PCIE_RXP1 SCD1U10V2KX-5GP 2 TXN1 PERP1
WLAN 29 PCIE_TXN1 1 C211 BF29 H14 SMB_CLK
PETN1 SMBCLK
D 29 PCIE_TXP1 SCD1U10V2KX-5GP 2

PCIE_RXN2
1 C215 TXP1 BH29

AW30
PETP1
SMBDATA
C8 SMB_DATA SML0_CLK SIO_SDA1
D
29 PCIE_RXN2 PCIE_RXP2 PERN2
BA30
29 PCIE_RXP2 SCD1U10V2KX-5GP 2 TXN2 PERP2 PCH_GPIO60 SML0_DATA SIO_SCL1
TV tuner 29 PCIE_TXN2 1 C218 BC30 J14 PCH_GPIO60 19
SCD1U10V2KX-5GP 2 TXP2 PETN2 SML0ALERT#/GPIO60
29 PCIE_TXP2 1 C227 BD30 SB 1206
PETP2 SML0_CLK
C6 SML0_CLK 27
SML0CLK
AU30

SMBus
27 PCIE_RXN3 PERN3
AT30 G8 SML0_DATA
27 PCIE_RXP3 PERP3 SML0DATA SML0_DATA 27 3D3V_EUP 3D3V_S0
SCD1U10V2KX-5GP 2 1 C234 TXN3 AU32
LAN 27 PCIE_TXN3
SCD1U10V2KX-5GP 2 1 C244 TXP3 AV32
PETN3
27 PCIE_TXP3

8
7
6
5
PETP3 PCH_GPIO74
M14
SML1ALERT#/GPIO74 RN28
28 PCIE_RXN4 BA32
PERN4 SIO_SCL1
28 PCIE_RXP4 BB32 E10 SIO_SCL1 33 SRN2K2J-2-GP
SCD1U10V2KX-5GP 2 TXN4 PERP4 SML1CLK/GPIO58
Cardreader 28 PCIE_TXN4 1 C232 BD32
SCD1U10V2KX-5GP 2 TXP4 PETN4 SIO_SDA1 3D3V_S0
28 PCIE_TXP4 1 C229 BE32 G12 SIO_SDA1 33
PETP4 SML1DATA/GPIO75

PCI-E*

1
2
3
4
BF33 SMB_CLK
PERN5 CL_CLK TP45 TPAD28 SMB_DATA
BH33 T13
PERP5 CL_CLK1

Controller
BG32
PETN5 CL_DATA TP43 TPAD28 84.2N702.A3F
BJ32 T11
PETP5 CL_DATA1
2N7002KDW-GP

Link
BA34 T9 CL_RST# TP42 TPAD28
PERN6 CL_RST1# SMB_DATA
AW34 3,12,13,29,58 PCH_SMBDATA 1 6
PERP6
BC34
PETN6 (R)
BD34 2 5
PETP6 PEG_CLKREQ# 1
PEG_A_CLKRQ#/GPIO47
H1
R262
DY 2
0R2J-2-GP
PEX_CLKREQ 52
SMB_CLK
AT34 3 4 PCH_SMBCLK 3,12,13,29,58
PERN7
AU34
PERP7 CLK_PCH_PEGA_N (S) 4 SRN0J-10-GP-U
AU36
PETN7 CLKOUT_PEG_A_N
AD43 1 DIS CLK_PCIE_PEG# 51 Q23
AV36 AD45 CLK_PCH_PEGA_P 2 3 RN38 CLK_PCIE_PEG 51
PETP7 CLKOUT_PEG_A_P 1225
BG34 AN4 CLK_EXP_N R1012 1 2 0R0402-PAD PEG_CLK#_R 5
PERN8 CLKOUT_DMI_N

PEG
BJ34 AN2 CLK_EXP_P R1013 1 2 0R0402-PAD
PERP8 CLKOUT_DMI_P PEG_CLK_R 5
BG36
PETN8
BJ36
PETP8 CLKOUT_DP_N (R) 1
AT1 4 DPLL_REF_SSCLK# 5
CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P
AT3 3 2 RN12 DPLL_REF_SSCLK 5
CLKOUT_DP_P/CLKOUT_BCLK1_P SRN0J-10-GP-U
AK48
CLKOUT_PCIE0N CHECK
AK47
CLKOUT_PCIE0P DY

From CLK BUFFER


AW24 CLKIN_DMI# CLKIN_DMI# 3
1225 PCIE_CLK_RQ0# CLKIN_DMI_N CLKIN_DMI PEG_CLKREQ#
P9 BA24 1 2
C PCIECLKRQ0#/GPIO73 CLKIN_DMI_P CLKIN_DMI 3
R261 10KR2J-3-GP C
R1016 1 2 0R0402-PAD CLK_PCH_SRC1_N AM43 AP3 CLK_CPU_BCLK#
29 CLK_PCIE_MINI1# CLKOUT_PCIE1N CLKIN_BCLK_N CLK_CPU_BCLK# 3
R1017 1 2 0R0402-PAD CLK_PCH_SRC1_P AM45 AP1 CLK_CPU_BCLK
29 CLK_PCIE_MINI1 CLKOUT_PCIE1P CLKIN_BCLK_P CLK_CPU_BCLK 3
1 DY 2 PCIE_CLK_RQ1# U4
29 MINI1_CLKREQ# R693 (R) 0R2J-2-GP PCIECLKRQ1#/GPIO18 DREFCLK#
F18 DREFCLK# 3
CLKIN_DOT_96N DREFCLK
E18 DREFCLK 3
R1020 CLK_PCH_SRC2_N CLKIN_DOT_96P
29 CLK_PCIE_MINI2# 1 2 0R0402-PAD AM47
R1021 CLK_PCH_SRC2_P CLKOUT_PCIE2N
29 CLK_PCIE_MINI2 1 2 0R0402-PAD AM48
CLKOUT_PCIE2P CLK_PCIE_SATA#
AH13 CLK_PCIE_SATA# 3
PCIE_CLK_RQ2# CLKIN_SATA_N/CKSSCD_N CLK_PCIE_SATA
29 MINI2_CLKREQ#
1 DY (R) 2 N4
PCIECLKRQ2#/GPIO20 CLKIN_SATA_P/CKSSCD_P
AH12 CLK_PCIE_SATA 3
R689 0R2J-2-GP

R1018 1 2 0R0402-PAD CLK_PCH_SRC0_N AH42 P41 CLK_ICH14


27 CLK_PCIE_LAN_N CLKOUT_PCIE3N REFCLK14IN CLK_ICH14 3
R1019 1 2 0R0402-PAD CLK_PCH_SRC0_P AH41
27 CLK_PCIE_LAN_P CLKOUT_PCIE3P
1 DY (R) 2 PCIE_CLK_RQ3# A8 J42 CLK_PCI_FB
27 LANCLK_REQ_N PCIECLKRQ3#/GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB 18
R264 0R2J-2-GP

R1014 1 2 0R0402-PAD CLK_PCH_SRC4_N AM51 AH51 XTAL25_IN


28 CLK_PCIE_CR_N CLKOUT_PCIE4N XTAL25_IN
R1015 1 2 0R0402-PAD CLK_PCH_SRC4_P AM53 AH53 XTAL25_OUT
28 CLK_PCIE_CR_P CLKOUT_PCIE4P XTAL25_OUT
TPAD28 TP5 1 DY (R) 2 PCIE_CLK_RQ4# M9 AF38 XCLK_RCOMP 1 2 1D05V_S0
R236 0R2J-2-GP PCIECLKRQ4#/GPIO26 XCLK_RCOMP R721 90D9R2F-1-GP
SB 1209
AJ50 T45 1 TP56 TPAD24 (M,P)
CLKOUT_PCIE5N CLKOUTFLEX0/GPIO64 XTAL25_IN
AJ52 1 2
CLKOUT_PCIE5P R324 0R2J-2-GP
PCIE_CLK_RQ5# H6 P43 1 TP54 TPAD24
Clock Flex
PCIECLKRQ5#/GPIO44 CLKOUTFLEX1/GPIO65

AK53 T42 1 TP52 TPAD24


1221 (SC)
CLKOUT_PEG_B_N CLKOUTFLEX2/GPIO66 XTAL25_IN
AK51 2 1

2
CLKOUT_PEG_B_P C294

2
PEG_B_CLKRQ# P13 N50 PCH_CLK48_R 1 2 SC18P50V2JN-1-GP
PEG_B_CLKRQ#/GPIO56 CLKOUTFLEX3/GPIO67 PCH_CLK48 33
33R2J-2-GP R319 X3 R986 (U)
XTAL-25MHZ-96GP 1MR2F-L-GP
SB 1206

1
IBEXPEAK-M-GP-NF DY (R) C301 (U) (U)

1
3D3V_EUP 3D3V_S0 3D3V_S0 3D3V_S0 XTAL25_OUT 2 1

SC4D7P50V2CN-1GP
(71.0HM55.00U) C300

2
B SB 1209 SC18P50V2JN-1-GP
B
2

(U)
(R) R257 (R) R690 (R) R691 (R) R234
DY 10KR2J-3-GP DY 10KR2J-3-GP DY 10KR2J-3-GP DY 10KR2J-3-GP
1

PCIE_CLK_RQ3# PCIE_CLK_RQ1# PCIE_CLK_RQ2# PCIE_CLK_RQ4#


SB 1206
1

1
2

R692 R688 R237 Delete!!


10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
R266
10KR2J-3-GP
2

2
1

3D3V_EUP

RN10
PCIE_CLK_RQ0# 1 8
SB 1206
PCH_GPIO74 2 7
PCIE_CLK_RQ5# 3 6
PEG_B_CLKRQ# 4 5

SRN10KJ-6-GP

A A
<Variant Name>

Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C

Title
<Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Tuesday, April 06, 2010 Sheet 15 of 59

5 4 3 2 1
5 4 3 2 1

PCH1C 3 OF 10
BA18
FDI_RXN0 FDI_TXN0 4
4 DMI_RXN0 BC24 BH17
DMI0RXN FDI_RXN1 FDI_TXN1 4
4 DMI_RXN1 BJ22 BD16
DMI1RXN FDI_RXN2 FDI_TXN2 4
4 DMI_RXN2 AW20 BJ16
DMI2RXN FDI_RXN3 FDI_TXN3 4
4 DMI_RXN3 BJ20 BA16
DMI3RXN FDI_RXN4 FDI_TXN4 4
BE14
FDI_RXN5 FDI_TXN5 4
4 DMI_RXP0 BD24 BA14
DMI0RXP FDI_RXN6 FDI_TXN6 4
4 DMI_RXP1 BG22 BC12
DMI1RXP FDI_RXN7 FDI_TXN7 4
4 DMI_RXP2 BA20
DMI2RXP
4 DMI_RXP3 BG20 BB18
DMI3RXP FDI_RXP0 FDI_TXP0 4
BF17
FDI_RXP1 FDI_TXP1 4
4 DMI_TXN0 BE22 BC16
DMI0TXN FDI_RXP2 FDI_TXP2 4
4 DMI_TXN1 BF21 BG16
DMI1TXN FDI_RXP3 FDI_TXP3 4
D 4
4
DMI_TXN2
DMI_TXN3
BD20
BE18
DMI2TXN
DMI3TXN
FDI_RXP4
FDI_RXP5
AW16
BD14
BB14
FDI_TXP4
FDI_TXP5
4
4
D
FDI_RXP6 FDI_TXP6 4
4 DMI_TXP0 BD22 BD12
DMI0TXP FDI_RXP7 FDI_TXP7 4
4 DMI_TXP1 BH21
DMI1TXP
4 DMI_TXP2 BC20
DMI2TXP
4 DMI_TXP3 BD18 BJ14 FDI_INT 4
DMI3TXP FDI_INT

DMI
FDI
BF13 FDI_FSYNC0 4
1D05V_S0 FDI_FSYNC0
BH25
DMI_ZCOMP
BH13 FDI_FSYNC1 4
DMI_IRCOMP_R FDI_FSYNC1
1 2 BF25
R290 49D9R2F-GP DMI_IRCOMP
BJ12 FDI_LSYNC0 4
FDI_LSYNC0
3D3V_S0 BG14
FDI_LSYNC1 FDI_LSYNC1 4

1
19,27 LAN_DISABLE_N 1 (R) 2 LAN_RST#1 R702
R705 0R2J-2-GP 10KR2J-3-GP

2
PM_SYSRST#_R T6 J12 PCIE_WAKE#
SYS_RESET# WAKE# PCIE_WAKE# 29

SB 1201 M6 Y1 PM_CLKRUN#
R285 1 (R) SYS_PWROK CLKRUN#/GPIO32
33,36 PWRGD3V_150MS 2 0R2J-2-GP

System Power Management


36,42,43 CORE_PWRGD 1 R284 2 PM_PWROK_1 B17
0R0402-PAD 1225 PWROK
R283 1 2 10KR2J-3-GP 1 R687 2
0R0402-PAD ME_PWROK K5 P8 PM_SUS_STAT# TP44 TPAD28
ALL_PWRGD 1 (R) MEPWROK SUS_STAT#/GPIO61
37,38,39,40,43 ALL_PWRGD 2
R686 0R2J-2-GP 1225
1 R704 2 LAN_RST#1 A10 F3 PM_SUS_CLK TP7 TPAD28
0R0402-PAD LAN_RST# SUSCLK/GPIO62

5 PM_DRAM_PWRGD PM_DRAM_PWRGD D9 E4 PM_SLP_S5# TP39 TPAD28


DRAMPWROK SLP_S5#/GPIO63
1225
PM_RSMRST# C16 H7 PM_SLP_S4#_R 1 R683 2 PM_SLP_S4# 25,33,38
RSMRST# SLP_S4# 0R0402-PAD
C 1 1 (R) 2 SUS_PWR_DN_ACK_R M1
SUS_PWR_DN_ACK/GPIO30 SLP_S3#
P12 PM_SLP_S3#_R 1 R701 2 PM_SLP_S3# 33,35,43
C
TPAD24 TP4 R233 0R2J-2-GP 0R0402-PAD
1225
1 2 PM_PWRBTN#_R P5 K8 PM_SLP_M# TP97 TPAD28
33 SIO_PWNBTN_N PWRBTN# SLP_M#
R231 0R0402-PAD

1 1 (R) 2 AC_PRESENT_R P7 N2 PM_SLP_DSW# TP6 TPAD28


TPAD24 TP3 R232 0R2J-2-GP ACPRESENT/GPIO31 TP23

PCH_GPIO72 A6 BJ10 H_PM_SYNC


BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 5

PM_RI# F14 F6 PM_SLP_LAN#


RI# SLP_LAN#/GPIO29 PM_SLP_LAN# 27,39

IBEXPEAK-M-GP-NF

(71.0HM55.00U) SB 1206
3D3V_EUP
,<͊͊
RN9
3D3V_S5 PM_RI# 1 8
SUS_PWR_DN_ACK_R 2 7
AC_PRESENT_R 3 6
PM_PWRBTN#_R 4 5
1225 SRN10KJ-6-GP
1

R282 R279 3D3V_S0 3D3V_EUP


1 2 (R) 10KR2J-3-GP
0R0402-PAD
PM_CLKRUN# 1 2
SB 1206
2

R247 PCH_GPIO72 1 2
(R) D26 8K2R2J-3-GP R256 8K2R2J-3-GP
1 PM_RSMRST#
PCIE_WAKE# 1 2
33 RSMRST#_SIO 3 R685 1KR2J-1-GP
1

R281
B 2 (R)
B
100KR2J-1-GP

BAT54PT-GP
83.00054.T81
2

2ND = 83.BAT54.D81

A A
<Variant Name>

Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C

Title
<Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Tuesday, April 06, 2010 Sheet 16 of 59

5 4 3 2 1
5 4 3 2 1

D D
PCH1D 4 OF 10
T48 BJ46
L_BKLTEN SDVO_TVCLKINN
R722 T47 BG46
L_VDD_EN SDVO_TVCLKINP
2 (R) 1 LIBG Y48 BJ48
L_BKLTCTL SDVO_STALLN PCH_HDMI_HPD
BG48
2K37R2F-GP SDVO_STALLP
AB48

2
L_DDC_CLK
Y45 BF45
L_DDC_DATA SDVO_INTN R809
SB 1209 BH45
SDVO_INTP 100KR2J-1-GP (U)
AB46
L_CTRL_CLK
V48
L_CTRL_DATA

1
LIBG AP39 T51
L_LVBG LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK 24
TPAD28 TP55 AP41 T53 PCH_HDMI_DATA 24

,D/
LVD_VBG SDVO_CTRLDATA
2 (R) 1 LVDS_VREF AT43
R724 LVD_VREFH DPB_AUXN TP61 TPAD28
AT42 BG44
0R2J-2-GP LVD_VREFL DDPB_AUXN DPB_AUXP TP59 TPAD28 3D3V_S0
BJ44
DDPB_AUXP PCH_HDMI_HPD RN42 (U)
AU38
DDPB_HPD PCH_HDMI_HPD 24

LVDS
AV53 2 3 PCH_HDMI_CLK
SB 1209 AV51
LVDSA_CLK#
BD42 PCH_HDMI_DATA2-_L 1 2 1 4 PCH_HDMI_DATA
LVDSA_CLK DDPB_0N PCH_HDMI_DATA2- 24
BC42 PCH_HDMI_DATA2+_L C2771 SCD1U10V2KX-5GP
2 PCH_HDMI_DATA2+ 24
DDPB_0P
BB47 BJ42 PCH_HDMI_DATA1-_L C2811 (U)SCD1U10V2KX-5GP
2 PCH_HDMI_DATA1- 24
LVDSA_DATA#0 DDPB_1N
BA52 BG42 PCH_HDMI_DATA1+_L C2721 (U)SCD1U10V2KX-5GP
2 SRN2K2J-1-GP

Digital Display Interface


LVDSA_DATA#1 DDPB_1P PCH_HDMI_DATA1+ 24
AY48 BB40 PCH_HDMI_DATA0-_L C2741 SCD1U10V2KX-5GP
(U) 2 PCH_HDMI_DATA0- 24
LVDSA_DATA#2 DDPB_2N
AV47 BA40 PCH_HDMI_DATA0+_L C2531 SCD1U10V2KX-5GP
(U) 2 PCH_HDMI_DATA0+ 24
LVDSA_DATA#3 DDPB_2P
AW38PCH_HDMI_CLK-_L C2671 SCD1U10V2KX-5GP
(U) 2 PCH_HDMI_CLK- 24
DDPB_3N
BB48 BA38 PCH_HDMI_CLK+_L C2431 (U)SCD1U10V2KX-5GP
2 PCH_HDMI_CLK+ 24
LVDSA_DATA0 DDPB_3P C245
BA50
LVDSA_DATA1 (U)SCD1U10V2KX-5GP
AY49 (U)
LVDSA_DATA2
AV48 Y49 PCH_TMDS_CLK 24
LVDSA_DATA3 DDPC_CTRLCLK
AB49

s/
DDPC_CTRLDATA PCH_TMDS_DATA 24
AP48
LVDSB_CLK# DPC_AUXN TP58 TPAD28
AP47 BE44
LVDSB_CLK DDPC_AUXN DPC_AUXP TP57 TPAD28 3D3V_S0
BD44
DDPC_AUXP PCH_TMDS_HPD RN41 (U)
AY53 AV40
C AT49
AU52
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
DDPC_HPD

DDPC_0N
BE40 PCH_TMDS_DATA2-_L 1 2
PCH_TMDS_HPD 24

PCH_TMDS_DATA2- 24
1
2
4
3
PCH_TMDS_CLK
PCH_TMDS_DATA
C
AT53 BD40 PCH_TMDS_DATA2+_L C2841 SCD1U10V2KX-5GP
2 PCH_TMDS_DATA2+ 24
LVDSB_DATA#3 DDPC_0P
BF41 PCH_TMDS_DATA1-_L C2861 (U)SCD1U10V2KX-5GP
2 PCH_TMDS_DATA1- 24 SRN2K2J-1-GP
DDPC_1N
AY51 BH41 PCH_TMDS_DATA1+_L C2791 (U)SCD1U10V2KX-5GP
2 PCH_TMDS_DATA1+ 24
LVDSB_DATA0 DDPC_1P
AT48 BD38 PCH_TMDS_DATA0-_L C2821 SCD1U10V2KX-5GP
(U) 2 PCH_TMDS_DATA0- 24
LVDSB_DATA1 DDPC_2N
AU50 BC38 PCH_TMDS_DATA0+_L C2901 (U)SCD1U10V2KX-5GP
2 PCH_TMDS_DATA0+ 24
LVDSB_DATA2 DDPC_2P
AT51 BB36 PCH_TMDS_CLK-_L C2951 (U)SCD1U10V2KX-5GP
2 PCH_TMDS_CLK- 24
LVDSB_DATA3 DDPC_3N
BA36 PCH_TMDS_CLK+_L C2711 (U)SCD1U10V2KX-5GP
2 PCH_TMDS_CLK+ 24
DDPC_3P C273 (U)SCD1U10V2KX-5GP
(U)
150R2J-L1-GP-U R315 1 2 PCH_BLUE 23 PCH_BLUE AA52 U50 PCH_TMDS_HPD
150R2J-L1-GP-U R314 PCH_GREEN CRT_BLUE DDPD_CTRLCLK
1 2 23 PCH_GREEN AB53 U52
150R2J-L1-GP-U R313 PCH_RED CRT_GREEN DDPD_CTRLDATA
1 2 23 PCH_RED AD53
CRT_RED

1
BC46
DDPD_AUXN R725
23 PCH_DDCCLK V51 BD46
CRT_DDC_CLK DDPD_AUXP (U) 100KR2J-1-GP
23 PCH_DDCDATA V53 AT38
CRT_DDC_DATA DDPD_HPD
UMA
BJ40

2
DDPD_0N
23 PCH_HSYNC Y53 BG40
CRT_HSYNC DDPD_0P
23 PCH_VSYNC Y51 BJ38
CRT_VSYNC DDPD_1N
BG38
DDPD_1P

CRT
BF37
CRT_IREF DDPD_2N
1 2 AD48 BH37
R732 DAC_IREF DDPD_2P
AB51 BE36
1KR2D-1-GP CRT_IRTN DDPD_3N
BD36
DDPD_3P

1K 0.5% ohm IBEXPEAK-M-GP-NF

(71.0HM55.00U)

B B

A A
<Variant Name>

Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C

Title
<Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Tuesday, April 06, 2010 Sheet 17 of 59

5 4 3 2 1
5 4 3 2 1

1226 (SC)
3D3V_S0
RN37
INT_PIRQG# 8 1
PCI_TRDY# 7 2
PCI_DEVSEL# 6 3
PCI_PLOCK# 5 4

SRN8K2J-4-GP
3D3V_S0
D PCI_STOP# 8
RN36
1
D
PCI_FRAME# 7 2
INT_PIRQD# 6 3
PCI_IRDY# 5 4
PCH1E 5 OF 10 +V_NVRAM_VCCQ
SRN8K2J-4-GP H40 AY9
AD0 NV_CE#0
N34 BD1
AD1 NV_CE#1 DMI Termination Voltage
C44 AP15

1
AD2 NV_CE#2
A38 BD8
AD3 NV_CE#3 (R) R249
C36
AD4
NV_CLE Set to Vss when low.
J34
AD5 NV_DQS0
AV9 Set to Vcc when high. DY 1KR2J-1-GP
A40 BG8
AD6 NV_DQS1
D45

2
AD7
E36 AP7
AD8 NV_DQ0/NV_IO0 NV_CLE
H48 AP6
E40
AD9 NV_DQ1/NV_IO1
AT6
These pins are left as NC,
AD10 NV_DQ2/NV_IO2
C40
M48
AD11 NV_DQ3/NV_IO3
AT9
BB1
because the function is disable.
AD12 NV_DQ4/NV_IO4
3D3V_S0 These pins are left as NC, M45
F53
AD13 NV_DQ5/NV_IO5
AV6
BB3
AD14 NV_DQ6/NV_IO6 +V_NVRAM_VCCQ
because the function is disable. M40
AD15 NV_DQ7/NV_IO7
BA4

NVRAM
M43 BE4
INT_PIRQB# AD16 NV_DQ8/NV_IO8
1 2 J36 BB6
R323 8K2R2J-3-GP PCI_REQ3# AD17 NV_DQ9/NV_IO9
1 2 K48 BD6

1
R321 8K2R2J-3-GP AD18 NV_DQ10/NV_IO10
F40
AD19 NV_DQ11/NV_IO11
BB7 Danbury Technology:
C42 BC8 Disabled when Low. (R) R248
AD20 NV_DQ12/NV_IO12
K46
AD21 NV_DQ13/NV_IO13
BJ8 Enable when High. DY 1KR2J-1-GP
M51 BJ6
3D3V_S0 AD22 NV_DQ14/NV_IO14
J52 BG6

2
AD23 NV_DQ15/NV_IO15
K51
AD24 NV_ALE NV_ALE
L34 BD3
PCI_PERR# AD25 NV_ALE NV_CLE
1 2 F42 AY6
R738 8K2R2J-3-GP AD26 NV_CLE
J40
INT_PIRQF# AD27
1 2 G46
R322 8K2R2J-3-GP AD28 NV_RCOMP (R)
F44 AU2 1 2
AD29 NV_RCOMP R263
M47
AD30

PCI
H36 AV7 32D4R2F-GP
AD31 NV_RB#
DY
J50 AY8
3D3V_S0 3D3V_S0 C/BE0# NV_WR#0_RE#
G42 AY5
C 1
RN35
8 INT_PIRQA# 1
RN39
8 PCI_REQ0#
H47
G34
C/BE1#
C/BE2#
C/BE3#
NV_WR#1_RE#

NV_WE#_CK0
AV11 USB
C
2 7 PCI_SERR# 2 7 INT_PIRQH# BF5
INT_PIRQC# PCI_REQ1# INT_PIRQA# NV_WE#_CK1
3 6 3 6 G38
INT_PIRQE# PCI_REQ2# INT_PIRQB# PIRQA#
4 5 4 5 H51
INT_PIRQC# PIRQB#
B37
PIRQC# USBP0N
H18 USBPN0 25 Pair Device
SRN8K2J-4-GP SRN8K2J-4-GP INT_PIRQD# A44 J18 USB0
PIRQD# USBP0P USBPP0 25
A18 USBPN1 0 USB0
USBP1N USBPN1 29
PCI_REQ0# USBPP1
0126 (1A) PCI_REQ1#
F51
REQ0# USBP1P
C18 USBPP1 29 MINI1 [-1] 0317
A46
REQ1#/GPIO50 USBP2N
N20 USBPN2 49 1 MINI1
PCI_REQ2# B45 P20 USB2
REQ2#/GPIO52 USBP2P USBPP2 49
PCI_REQ3# M53 J20 2 USB2
REQ3#/GPIO54 USBP3N USBPN3 49
PCI_GNT0# 1 (R)DY 2 L20 USB3
USBP3P USBPP3 49
R736 1KR2J-1-GP PCI_GNT0# F48 F20 3 USB3
GNT0# USBP4N USBPN4 49
PCI_GNT1# 1 DY 2 USE SPI PCI_GNT1# K45 G20 USB4
GNT1#/GPIO51 USBP4P USBPP4 49
R730 (R) 1KR2J-1-GP PCI_GNT2# F36 A20 USBPN5 25 4 USB4
PCI_GNT3# GNT2#/GPIO53 USBP5N
H53
GNT3#/GPIO55 USBP5P
C20 USBPP5 25 Touch panel
M22 USBPN6 1 TP49 TPAD24 5 Touch panel
INT_PIRQE# USBP6N USBPP6 TP48 TPAD24
B41
PIRQE#/GPIO2 USBP6P
N22 1 Reserve
INT_PIRQF# K53 B21 USBPN7 1 TP72 TPAD24 6 Reserve
INT_PIRQG# A36
PIRQF#/GPIO3 USBP7N
D21 USBPP7 1 TP74 TPAD24 Reserve
[-1] 0317
INT_PIRQH# PIRQG#/GPIO4 USBP7P
A48
PIRQH#/GPIO5 USBP8N
H22 USBPN8 25 7 Reserve
USBP8P
J22 USBPP8 25 USB8

USB
BOOT BIOS Strap 34 PCI_RST# PCI_RST# K6 E22 USBPN9 49 8 USB8
PCIRST# USBP9N
USBP9P
F22 USBPP9 49 USB9
PCI_GNT#0 PCI_GNT#1 BOOT BIOS Location PCI_SERR# E44 A22 9 USB9
SERR# USBP10N USBPN10 34
PCI_PERR# E50 C22 Reserve USB
PERR# USBP10P USBPP10 34
0 0 LPC(Default) G24 USBPN11 10 Reserve USB
USBP11N USBPN11 29
USBPP11 MINI2
1 0 Reserved PCI_IRDY# USBP11P
H24 USBPP11 29 [-1] 0317
A42
IRDY# USBP12N
L24 USBPN12 26 11 MINI2
H44 M24 USBPP12 26 Bluetooth (SB 1204)
PCI_DEVSEL# PAR USBP12P
0 1 PCI F46
DEVSEL# USBP13N
A24 USBPN13 26 12 Bluetooth
PCI_FRAME# C46 C24 Camera
FRAME# USBP13P USBPP13 26
1 1 SPI 13 Camera
PCI_PLOCK# D49
PLOCK# USB_RBIAS_PN
B25 1 2
PCI_STOP# USBRBIAS# R291
D41
PCI_TRDY# STOP# 22D6R2F-L1-GP
C48 D25 SB 1206
TRDY# USBRBIAS
LPC_PME_N M7
33 LPC_PME_N PME#
N16 3D3V_EUP
B 5,27,28,33 PLT_RST#
PLT_RST#

CLK_PCI_SIO_R
D5
PLTRST#
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
J16
F16
OC*08
OC*23
OC*49
25
49
49 OC*67
B
R320 1 2 22R2J-2-GP N52 L16 R707 1 2
33 CLK_PCI_SIO
15 CLK_PCI_FB R318 1 2 51R2J-2-GP CLK_PCI_FB_R P53
CLKOUT_PCI0
CLKOUT_PCI1
OC3#/GPIO42
OC4#/GPIO43
E14 Check!!
34 CLK_PCI_PORT80 R731 1 2 47R2J-2-GP CLK_PCI_PORT80_R P46 G16 10KR2J-3-GP
CLK_PCI_3 CLKOUT_PCI2 OC5#/GPIO9 OC*67
P51 F12
TPAD28 TP11 CLK_PCI_4 CLKOUT_PCI3 OC6#/GPIO10
P48 T15
TPAD28 TP60 CLKOUT_PCI4 OC7#/GPIO14

IBEXPEAK-M-GP-NF

(71.0HM55.00U)

PCI_GNT2# 1 DY 2 PCI_GNT3# 1 DY 2
R718 4K7R2J-2-GP R316 4K7R2J-2-GP
(R) (R)

A16 swap override Strap/Top-Block


Swap Override jumper

PCI_GNT#3 Low = A16 swap


override/Top-Block
Swap Override enabled
High = Default

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH(5/9)
Size Document Number Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 18 of 59

5 4 3 2 1
GPIO8 has a weak[20K] internal pull up.
No need to have external pull down/up.
5 4 3 2 1
GPIO8 pin set to high at reset.

GPIO15 has a weak[20K] internal pull down.


PCH1F 6 OF 10
No need to have external pull up/down.
GPIO 15 pin is set to low at reset. RISER_DET# Y3 AH45
49 RISER_DET# BMBUSY#/GPIO0 CLKOUT_PCIE6N
Low : ME Crypto TLS with no confidentiality AH46
CLKOUT_PCIE6P
High : ME Crypto TLS with confidentiality 47 COM_Disable# C38
TACH1/GPIO1
[-1] 0401 MB_ID0 D37
TACH2/GPIO6
GPIO27 has a weak[20K] internal pull up. CLKOUT_PCIE7N
AF48

MISC
To enable on-die PLL Voltage regurator, MB_ID1 J32 AF47
TACH3/GPIO7 CLKOUT_PCIE7P
should not place external pull down. SB 1206 ODD_REJECT_OUT# F10
48 ODD_REJECT_OUT# GPIO8
3D3V_EUP LAN_DISABLE_N K9 U2
16,27 LAN_DISABLE_N LAN_PHY_PWR_CTRL/GPIO12 A20GATE KA20GATE 33
D PCH_GPIO28 5
RN32
4
CMOS_IN T7
GPIO15 1225
D
PCH_GPIO60 6 3 TPAD28 TP62 DGPU_HOLD_RST# AA2 AM3 BCLK_CPU_N_R R1011 1 2 0R0402-PAD
15 PCH_GPIO60 SATA4GP/GPIO16 CLKOUT_BCLK0_N/CLKOUT_PCIE8N BCLK_CPU_N 5
LAN_DISABLE_N 7 2 R1010 1 2 0R0402-PAD BCLK_CPU_P 5
PCH_GPIO11 8 1 DGPU_PWROK F38 AM1 BCLK_CPU_P_R
15 PCH_GPIO11 42,43,58 DGPU_PWROK TACH0/GPIO17 CLKOUT_BCLK0_P/CLKOUT_PCIE8P
SRN10KJ-6-GP 26 WEBCAM_DET# WEBCAM_DET# Y7 BG10
SCLOCK/GPIO22 PECI H_PECI 5

GPIO
RN15
PCH_GPIO45 1 4 TPAD28 TP40 PCH_GPIO24 H10 T1
GPIO24 RCIN# KBRCIN# 33
PCH_GPIO46 2 3
TPAD28 TP46 PCH_GPIO27 AB12 BE10 1D05V_VTT
GPIO27 PROCPWRGD H_PWRGD 5

CPU
SRN8K2J-6-GP 1 2
PCH_GPIO28 V13 BD10 R270
CMOS_IN GPIO28 THRMTRIP# 56R2J-4-GP
1 2
R276 10KR2J-3-GP STP_PCI#
0126 (1A) M11
STP_PCI#/GPIO34 PCH_THERMTRIP_R 1 2 PM_THRMTRIP-A# 5
TOUCH_CABLE_DET# 1 2 WEBCAM_EN V6 R274
26 WEBCAM_EN SATACLKREQ#/GPIO35
R943 10KR2J-3-GP 54D9R2F-L1-GP
DGPU_PWR_EN# AB7 BA22
SATA2GP/GPIO36 TP1
dGPU_PRSNT# AB13 AW22 Placed Within 2" from PCH
PSW_CLR# SATA3GP/GPIO37 TP2

29 TV_EN R723 1 (R) 2 PCH_GPIO38 V3 BB22


2

SLOAD/GPIO38 TP3
GAP-OPEN

0R0402-PAD
25 TP_DET# P3 AY45
TP_DET# SDATAOUT0/GPIO39 TP4
G24
PCH_GPIO45 H3 AY46
PCIECLKRQ6#/GPIO45 TP5
1

PCH_GPIO46 F1 AV43
PCIECLKRQ7#/GPIO46 TP6
PCH_GPIO48 AB6 AV45
SDATAOUT1/GPIO48 TP7
3D3V_S0 PSW_CLR# AA4 AF13
SATA5GP/GPIO49 TP8
RN30 48 TOUCH_CABLE_DET# F8 M18
GPIO57 TP9
5 4
TP_DET# 6 3 N18
PCH_GPIO48 TP10
7 2 B4
PSW_CLR# VSS_NCTF_8
8 1 B52 AJ24
VSS_NCTF_9 TP11
BH2

NCTF
VSS_NCTF_16

RSVD
SRN10KJ-6-GP BH52 AK41
C 3D3V_S0
D2
VSS_NCTF_17
VSS_NCTF_28
TP12

TP13
AK42
C
A4
DGPU_HOLD_RST# VSS_NCTF#A4
UMA

BJ49,BJ5,BJ50,BJ52,BJ53,D1,D53,E1,E53
2 1 A49 M32
2

R699 10KR2J-3-GP VSS_NCTF#A49 TP14


A5

BE53,BF1,BF53,BH1,BH53,BJ1,BJ2,BJ4,
R696 VSS_NCTF#A5
A50 N32
VSS_NCTF#A50 TP15

A4,A49,A5,A50,A52,A53,B2,B53,BE1,
(U) 10KR2J-3-GP A52
VSS_NCTF#A52
A53 M30
DGPU_PWR_EN# VSS_NCTF#A53 TP16
1 2 B2
1

10KR2J-3-GP R703 dGPU_PRSNT# VSS_NCTF#B2


B53 N30
VSS_NCTF#B53 TP17
BE1
2

VSS_NCTF#BE1
BE53 H12
R700 VSS_NCTF#BE53 TP18
BF1
(S) VSS_NCTF#BF1
10KR2J-3-GP BF53 AA23
3D3V_S0 VSS_NCTF#BF53 TP19
BH1
VSS_NCTF#BH1
DIS BH53 AB45
1

RN7 VSS_NCTF#BH53 NC_1


BJ1
WEBCAM_DET# VSS_NCTF#BJ1
5 4 BJ2 AB38
STP_PCI# VSS_NCTF#BJ2 NC_2
6 3 BJ4
VSS_NCTF#BJ4

NCTF TEST PIN:


RISER_DET# 7 2 BJ49 AB42
VSS_NCTF#BJ49 NC_3
8 1 BJ5
VSS_NCTF#BJ5
BJ50 AB41
SRN10KJ-6-GP VSS_NCTF#BJ50 NC_4
BJ52
VSS_NCTF#BJ52
BJ53 T39
VSS_NCTF#BJ53 NC_5
D1
VSS_NCTF#D1
D53
VSS_NCTF#D53 INIT3_3V# TP41 TPAD28
E1 P6
3D3V_S0 VSS_NCTF#E1 INIT3_3V#
E53
VSS_NCTF#E53
C10
TP24
2

IBEXPEAK-M-GP-NF
R716
(M) 10KR2J-3-GP (71.0HM55.00U)

MB_ID1 MB_ID0
1

MB_ID0
0 0 UMA
2

R715 0 1 MADISON Header color: RED


(U,P) 10KR2J-3-GP CMOS1
1 0 PARK 1
B Clear CMOS by GPIO B
1

CMOS_IN 2
3

DVD-CON3-S8-GP

3D3V_S0
2

1-2 NORMAL(DEFAULT)
R240
(P) 10KR2J-3-GP 2-3 CLR CMOS
1

MB_ID1
2

R239
(U,M) 10KR2J-3-GP
1

A A
<Variant Name>

Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C

Title
<Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Tuesday, April 06, 2010 Sheet 19 of 59

5 4 3 2 1
5 4 3 2 1

D D
SB 1204
1D05V_S0
PCH1G POWER 7 OF 10
69mA L35
1.432A AB24
AB26
VCCCORE VCCADAC
AE50 3D3V_S0_DAC 1 2 3D3V_S0

1
C216 C207 VCCCORE (R) C296 FCM1608KFG-301T05-GP
AB28 AE52
VCCCORE VCCADAC

SC10U6D3V3MX-GP

SCD1U10V2KX-5GP
AD26 (R) R325 C291
VCCCORE

SC1U6D3V2KX-GP

SCD01U50V2KX-1GP
CRT
AD28 AF53 DY 0R2J-2-GP

2
VCCCORE VSSA_DAC
AF26
VCCCORE

VCC CORE
AF28 AF51

2
VCCCORE VSSA_DAC
AF30
VCCCORE
AF31
VCCCORE
AH26
VCCCORE
AH28
VCCCORE +3VS_VCCA_LVD
AH30
VCCCORE
AH31 AH38 1 (R) 2
VCCCORE VCCALVDS R719
AJ30
VCCCORE >s^ŝƐĂďůĞ
AJ31 AH39 0R0603-PAD
VCCCORE VSSA_LVDS
SB 1209
1D05V_S0 AP43 +1.8VS_VCCTX_LVDS 1 (R) 2
VCCTX_LVDS R729
AP45
VCCTX_LVDS 0R0603-PAD
AT46

LVDS
VCCTX_LVDS
AK24 AT45
1D05V_S0 VCCIO VCCTX_LVDS
(R) >s^ŝƐĂďůĞ
42mA 1
L14
DY 2 +1.05VS_VCCAPLL_EXP BJ24
VCCAPLLEXP
AB34

1
IND-1UH-2-GP (R) C202 VCC3_3

SC10U6D3V3MX-GP
DY AN20
VCCIO VCC3_3
AB35
AN22 3D3V_S0
357mA

HVCMOS
2
VCCIO
AN23 AD35
VCCIO VCC3_3
AN24

1
VCCIO C655
AN26
VCCIO

SCD1U10V2KX-5GP
1D05V_S0 AN28
VCCIO
BJ26
3.062A

2
VCCIO
BJ28
VCCIO
AT26
C C
1

1
C303 C302 C307 C309 C313 C310 VCCIO
AT28
1

VCCIO
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

TC10 (R) AU26


VCCIO
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
AU28 1D5V_S0_1D8V_S0
2

2
VCCIO
ST220U2D5VBM-2GP

DY AV26
196mA
2

VCCIO
AV28 AT24
VCCIO VCCVRM
AW26
VCCIO
AW28
VCCIO 1D05V_VTT

DMI
BA26 AT16 1225
VCCIO VCCDMI +1.1VS_VCC_DMI
BA28
BB26
VCCIO
VCCIO VCCDMI
AU16 1 R267 2
0R0603-PAD
61mA 1D8V_S0 3D3V_S0
BB28

1
3D3V_S0 VCCIO C191 1D05V_S0
BC26 DY

1
VCCIO

PCI E*
BC28 1 (R) 2 DY
VCCIO SC1U6D3V2KX-GP R268 0R3J-0-U-GP 0R3J-0-U-GP
BD26

2
VCCIO 0R3J-0-U-GP
BD28
1

VCCIO +V_NVRAM_VCCQ R241 (R) R244


BE26 AM16
C171 VCCIO VCCPNAND
BE28 AK16
156mA

2
VCCIO VCCPNAND
SCD1U10V2KX-5GP

BG26 AK20
2

VCCIO VCCPNAND
BG28 AK19

1
VCCIO VCCPNAND C182
BH27
VCCIO VCCPNAND
AK15 VCCPNAND which power the DC NAND interface must be powered even if dual channel
AK13 SCD1U10V2KX-5GP
1D05V_S0 VCCPNAND NAND interface is not connected since it also supplies power to other functions inside
AN30 AM12

2
VCCIO VCCPNAND PCH.

NAND / SPI
AN31 AM13
VCCIO VCCPNAND
1 (R)DY 2 AM15
L12 C198 VCCPNAND
357mA
1

IND-1UH-2-GP AN35
VCC3_3
DY(R) SC10U6D3V3MX-GP
/ŶƚĞƌŶĂůƉŽǁĞƌ
2

VCCAFDI_VRM AT22
VCCVRM[1]
1D05V_S0 +1.05VS_VCCAPLL_FDI BJ18 AM8
VCCFDIPLL VCCME3_3 1225 3D3V_S0
AM9
VCCME3_3
FDI

AM23 AP11
VCCIO VCCME3_3
VCCME3_3
AP9 85mA VCCME3_3 1 R242 2
0R0603-PAD
1

1
C311 C312 C212 C209 C233 C183
SC10U6D3V3MX-GP

SCD1U10V2KX-5GP
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

IBEXPEAK-M-GP-NF
2

2
(71.0HM55.00U)

B B
1225
1D5V_S0_1D8V_S0

VCCAFDI_VRM 1 R272 2
0R0603-PAD

1D5V_S0_1D8V_S0
1D8V_S0

1 R271 2
0R0603-PAD
1D5V_S0

1 2
(R)
R275
0R3J-0-U-GP
CHECK?? DY

A A
<Variant Name>

Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C

Title
<Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Tuesday, April 06, 2010 Sheet 20 of 59

5 4 3 2 1
5 4 3 2 1

D 1D05V_S0 +1.05VS_VCCA_CLK
D
L18

SC1U10V2KX-1GP
DY POWER
52mA 1 (R) 2
IND-10UH-125-GP (R)
PCH1J 10 OF 10 1D05V_S0

1
(R) C299 C293 AP51 V24
VCCACLK VCCIO

SC10U6D3V3MX-GP
DY DY V26

1
VCCIO C199
AP53 Y24

2
VCCACLK VCCIO
Y26
VCCIO SC1U6D3V2KX-GP

2
1D05V_S0 AF23 V28 3D3V_EUP
1225 VCCLAN VCCSUS3_3
U28
R245 1 +1.05VS_VCCLAN VCCSUS3_3
2 0R0402-PAD AF24 U26
VCCLAN VCCSUS3_3
U24
VCCSUS3_3
P28

1
C185 DCPSUSBYP VCCSUS3_3 C658 C662
Y20 P26
DCPSUSBYP VCCSUS3_3 C661
VccLAN may be N28

1
VCCSUS3_3

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
N26 SC1U6D3V2KX-GP
grounded if Intel LAN is

2
C657 VCCSUS3_3
AD38 M28
disabled VCCME VCCSUS3_3
M26

2
VCCSUS3_3

SCD1U10V2KX-5GP
AD39 L28

USB
VCCME VCCSUS3_3
L26
VCCSUS3_3 3D3V_EUP
AD41 J28
1D05V_S0 VCCME VCCSUS3_3
J26
VCCSUS3_3
AF43 H28
1.849A VCCME VCCSUS3_3
H26

1
C219 C230 VCCSUS3_3
AF41 G28

1
C205 VCCME VCCSUS3_3 C210
G26
VCCSUS3_3
AF42 F28 SCD1U10V2KX-5GP

2
VCCME VCCSUS3_3

SC1U6D3V2KX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP F26

2
VCCSUS3_3 3D3V_EUP
V39 E28
VCCME VCCSUS3_3

Clock and Miscellaneous


E26
VCCSUS3_3
V41 C28
VCCME VCCSUS3_3
C26

A
VCCSUS3_3 3D3V_S0
V42 B27
VCCME VCCSUS3_3 D27
A28
VCCSUS3_3
Y39 A26 RB751V-40-2-GP

1
C200 VCCME VCCSUS3_3
1D05V_S0 SC1U10V2KX-1GP
DY 1D05V_S0
Y41 U23

A
K
L17 VCCME VCCSUS3_3
(R)

2
1 2 +1.05VS_VCCA_A_DPL Y42 V23 5V_EUP D28
C IND-10UH-125-GP C298 VCCME VCCIO
1mA RB751V-40-2-GP C
1

C289 F24 +5VALW_PCH_VCC5REFSUS 1 2


V5REF_SUS R710 10R2J-2-GP

K
1
SC10U6D3V3MX-GP SC1U6D3V2KX-GP +VCCRTCEXT V9
2

DCPRTC C660 5V_S0

1
1D5V_S0_1D8V_S0 SCD1U10V2KX-5GP
1mA

2
C653 K49 +5VS_PCH_VCC5REF 1 2
L16 V5REF
SCD1U10V2KX-5GP AU24 R737 10R2J-2-GP

PCI/GPIO/LPC
2

1
+1.05VS_VCCA_B_DPL VCCVRM
1 2
IND-10UH-125-GP C297 J38 C668
1

C288 VCC3_3
BB51 SCD1U10V2KX-5GP
68mA +1.05VS_VCCA_A_DPL

2
VCCADPLLA 3D3V_S0
BB53 L38
VCCADPLLA VCC3_3
SC1U6D3V2KX-GP

SC10U6D3V3MX-GP
2

M36
69mA +1.05VS_VCCA_B_DPL BD51
VCCADPLLB
VCC3_3
BD53 N36

1
VCCADPLLB VCC3_3
AH23 P36 C664
VCCIO VCC3_3

SCD1U10V2KX-5GP
AJ35 3D3V_S0

2
1D05V_S0 VCCIO SCD1U10V2KX-5GP
AH35 U35
VCCIO VCC3_3 C665 1 2
AF34
VCCIO
AD13
VCC3_3
AH34
1

C203 C201 C208 VCCIO 1D05V_S0


+1.05VS_VCCAPLL L11
SC1U6D3V2KX-GP AF32 DY
SC1U6D3V2KX-GP SC1U6D3V2KX-GP VCCIO
AK3 1 2 32mA
2

VCCSATAPLL IND-10UH-125-GP
V12 AK1

1
DCPSST VCCSATAPLL C184 C186
+VCCSST SC1U10V2KX-1GP DY DY SC1U10V2KX-1GP (R) 1D05V_S0

2
1

+1.1VALW_INT_VCCSUS Y22
C656 DCPSUS
AH22
1

SCD1U10V2KX-5GP VCCIO (R) (R)


2

1
C659 1D5V_S0_1D8V_S0 C197
SCD1U10V2KX-5GP P18 AT20
2

VCCSUS3_3 VCCVRM SC1U6D3V2KX-GP

2
3D3V_EUP U19
SATA
VCCSUS3_3
PCI/GPIO/LPC

AH19
163mA U20
VCCSUS3_3
VCCIO
AD20
B B
1

VCCIO
U22
C213 VCCSUS3_3
AF22
SCD1U10V2KX-5GP 3D3V_S0 VCCIO
2

AD19
VCCIO
V15 AF20
VCC3_3 VCCIO
AF19
1

VCCIO
V16 AH20
CHECK C287 VCC3_3 VCCIO
SCD1U10V2KX-5GP Y16 AB19
2

VCC3_3 VCCIO
AB20
1D05V_VTT 1225 VCCIO R711
AB22
VCCIO 1D05V_S0 +3VS_+1.5VS_HDA_IO 0R0603-PAD
AD22
1 R265 2 1mA +1.1VS_PCH_CPU_IO AT18
V_CPU_IO
VCCIO 1225 1 2 3D3V_EUP
SCD1U10V2KX-5GP

0R0603-PAD AA34 PCH_VCC_1_1_20 R714 1 2 0R0402-PAD


CPU
1

C190 C192 VCCME PCH_VCC_1_1_21 R712 1 0R0402-PAD


Y34 2
C187 VCCME PCH_VCC_1_1_22 R713 1 0R0402-PAD
AU18 Y35 2
SC4D7U6D3V3KX-GP V_CPU_IO VCCME PCH_VCC_1_1_23 R717 1 0R0402-PAD
SCD1U10V2KX-5GP AA35 2
2

VCCME +3VS_+1.5VS_HDA_IO

6mA
RTC

A12 L30
RTC_AUX_S5 VCCRTC VCCSUSHDA
HDA

1225
1

C663
1 R280 2
0R0603-PAD
2mA +1.1VS_PCH_VCCRTC IBEXPEAK-M-GP-NF
SC1U6D3V2KX-GP
2
1

(71.0HM55.00U)
C195 C196
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH(8/9)
Size Document Number Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 21 of 59

5 4 3 2 1
5 4 3 2 1

PCH1I 9 OF 10
AY7 VSS VSS H49
B11 VSS VSS H5
B15 VSS VSS J24
B19 VSS VSS K11
B23 VSS VSS K43
B31 VSS VSS K47
B35 VSS VSS K7
B39 VSS VSS L14
B43 VSS VSS L18
D B47
B7
VSS VSS L2
L22
D
PCH1H 8 OF 10 VSS VSS
BG12 VSS VSS L32
AB16 VSS BB12 VSS VSS L36
BB16 VSS VSS L40
AA19 VSS VSS AK30 BB20 VSS VSS L52
AA20 VSS VSS AK31 BB24 VSS VSS M12
AA22 VSS VSS AK32 BB30 VSS VSS M16
AM19 VSS VSS AK34 BB34 VSS VSS M20
AA24 VSS VSS AK35 BB38 VSS VSS N38
AA26 VSS VSS AK38 BB42 VSS VSS M34
AA28 VSS VSS AK43 BB49 VSS VSS M38
AA30 VSS VSS AK46 BB5 VSS VSS M42
AA31 VSS VSS AK49 BC10 VSS VSS M46
AA32 VSS VSS AK5 BC14 VSS VSS M49
AB11 VSS VSS AK8 BC18 VSS VSS M5
AB15 VSS VSS AL2 BC2 VSS VSS M8
AB23 VSS VSS AL52 BC22 VSS VSS N24
AB30 VSS VSS AM11 BC32 VSS VSS P11
AB31 VSS VSS BB44 BC36 VSS VSS AD15
AB32 VSS VSS AD24 BC40 VSS VSS P22
AB39 VSS VSS AM20 BC44 VSS VSS P30
AB43 VSS VSS AM22 BC52 VSS VSS P32
AB47 VSS VSS AM24 BH9 VSS VSS P34
AB5 VSS VSS AM26 BD48 VSS VSS P42
AB8 VSS VSS AM28 BD49 VSS VSS P45
AC2 VSS VSS BA42 BD5 VSS VSS P47
AC52 VSS VSS AM30 BE12 VSS VSS R2
AD11 VSS VSS AM31 BE16 VSS VSS R52
C AD12
AD16
VSS VSS AM32
AM34
BE20
BE24
VSS VSS T12
T41
C
VSS VSS VSS VSS
AD23 VSS VSS AM35 BE30 VSS VSS T46
AD30 VSS VSS AM38 BE34 VSS VSS T49
AD31 VSS VSS AM39 BE38 VSS VSS T5
AD32 VSS VSS AM42 BE42 VSS VSS T8
AD34 VSS VSS AU20 BE46 VSS VSS U30
AU22 VSS VSS AM46 BE48 VSS VSS U31
AD42 VSS VSS AV22 BE50 VSS VSS U32
AD46 VSS VSS AM49 BE6 VSS VSS U34
AD49 VSS VSS AM7 BE8 VSS VSS P38
AD7 VSS VSS AA50 BF3 VSS VSS V11
AE2 VSS VSS BB10 BF49 VSS VSS P16
AE4 VSS VSS AN32 BF51 VSS VSS V19
AF12 VSS VSS AN50 BG18 VSS VSS V20
Y13 VSS VSS AN52 BG24 VSS VSS V22
AH49 VSS VSS AP12 BG4 VSS VSS V30
AU4 VSS VSS AP42 BG50 VSS VSS V31
AF35 VSS VSS AP46 BH11 VSS VSS V32
AP13 VSS VSS AP49 BH15 VSS VSS V34
AN34 VSS VSS AP5 BH19 VSS VSS V35
AF45 VSS VSS AP8 BH23 VSS VSS V38
AF46 VSS VSS AR2 BH31 VSS VSS V43
AF49 VSS VSS AR52 BH35 VSS VSS V45
AF5 VSS VSS AT11 BH39 VSS VSS V46
AF8 VSS VSS BA12 BH43 VSS VSS V47
AG2 VSS VSS AH48 BH47 VSS VSS V49
AG52 VSS VSS AT32 BH7 VSS VSS V5
AH11 VSS VSS AT36 C12 VSS VSS V7
AH15 AT41 C50 V8
B AH16
VSS
VSS
VSS
VSS AT47 D51
VSS
VSS
VSS
VSS W2 B
AH24 VSS VSS AT7 E12 VSS VSS W52
AH32 VSS VSS AV12 E16 VSS VSS Y11
AV18 VSS VSS AV16 E20 VSS VSS Y12
AH43 VSS VSS AV20 E24 VSS VSS Y15
AH47 VSS VSS AV24 E30 VSS VSS Y19
AH7 VSS VSS AV30 E34 VSS VSS Y23
AJ19 VSS VSS AV34 E38 VSS VSS Y28
AJ2 VSS VSS AV38 E42 VSS VSS Y30
AJ20 VSS VSS AV42 E46 VSS VSS Y31
AJ22 VSS VSS AV46 E48 VSS VSS Y32
AJ23 VSS VSS AV49 E6 VSS VSS Y38
AJ26 VSS VSS AV5 E8 VSS VSS Y43
AJ28 VSS VSS AV8 F49 VSS VSS Y46
AJ32 VSS VSS AW14 F5 VSS VSS P49
AJ34 VSS VSS AW18 G10 VSS VSS Y5
AT5 VSS VSS AW2 G14 VSS VSS Y6
AJ4 VSS VSS BF9 G18 VSS VSS Y8
AK12 VSS VSS AW32 G2 VSS VSS P24
AM41 VSS VSS AW36 G22 VSS VSS T43
AN19 VSS VSS AW40 G32 VSS VSS AD51
AK26 VSS VSS AW52 G36 VSS VSS AT8
AK22 VSS VSS AY11 G40 VSS VSS AD47
AK23 VSS VSS AY43 G44 VSS VSS Y47
AK28 VSS VSS AY47 G52 VSS VSS AT12
AF39 VSS VSS AM6
IBEXPEAK-M-GP-NF H16 AT13
VSS VSS
H20 VSS VSS AM5
H30 AK45
A (71.0HM55.00U)
H34
VSS
VSS
VSS
VSS AK39
<Core Design>
A
H38 VSS VSS AV14
H42 VSS Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

IBEXPEAK-M-GP-NF Title

(71.0HM55.00U)
PCH(9/9)
Size Document Number Rev
A3
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 22 of 59
8 7 6 5 4 3 2 1

CRT header for debug RED_CONN

5V_S0
R534 CRT1
GREEN_CONN 1 (R) 2 2 1
0R2J-2-GP
D D
4 X 3
RED_CONN 6 5 5VDDCCLK_CON
GREEN_CONN 8 7 5VDDCDA_CON
BLUE_CONN BLUE_CONN 10 9 VSYNC_5V_CON
12 11 HSYNC_5V_CON

1
DVD-CONN12D-FP12GP
&ƌŽŵW, R536 R537 R535
21.62698.206,
PCH_HSYNC
17 PCH_HSYNC PCH_VSYNC 11pin -1#3, 3D3V_S0

2
17 PCH_VSYNC 150R2J-L1-GP-U 150R2J-L1-GP-U 2.0mm pitch
PCH_DDCCLK 150R2J-L1-GP-U
17 PCH_DDCCLK PCH_DDCDATA
17 PCH_DDCDATA

1
R922
PCH_RED 10KR2J-3-GP R920
17 PCH_RED 10KR2J-3-GP
PCH_GREEN
17 PCH_GREEN
PCH_BLUE
17 PCH_BLUE

2
UMARN22 (U)

2
17 PCH_DDCDATA PCH_DDCDATA 1 4 DDC_DATA_VGA
(U) 17 PCH_DDCCLK PCH_DDCCLK 2 3 DDC_CLK_VGA
RN56 UMA
PCH_RED 2 3 RED_CONN SRN0J-10-GP-U
C 17 PCH_RED C
PCH_GREEN1 4 GREEN_CONN
17 PCH_GREEN
DIS RN55 (S)
&ƌŽŵDyD SRN0J-10-GP-U 52 MXM_DDCDATA MXM_DDCDATA
MXM_DDCCLK
1
2
4
3
52 MXM_DDCCLK
(S) RN57 DIS
52,58 MXM_HSYNC MXM_RED 1 4 SRN0J-10-GP-U
52 MXM_RED
52,58 MXM_VSYNC MXM_GREEN 2 3
52 MXM_GREEN

52 MXM_DDCDATA MXM_DDCDATA SRN0J-10-GP-U


52 MXM_DDCCLK MXM_DDCCLK
RN23
MXM_RED SRN0J-10-GP-U
52 MXM_RED
MXM_GREEN 17 PCH_HSYNC 1 4 HSYNC_3P3V
52 MXM_GREEN
MXM_BLUE (U) UMA 17 PCH_VSYNC 2 3 VSYNC_3P3V
52 MXM_BLUE
PCH_BLUE 1 2 BLUE_CONN
17 PCH_BLUE
R921 (U) UMA
0R2J-2-GP
(S) RN54 DIS
MXM_BLUE 1 2 52,58 MXM_HSYNC 1 4
52 MXM_BLUE
R923 (S) 52,58 MXM_VSYNC 2 3
0R2J-2-GP
SRN0J-10-GP-U
DIS
B B

5V_S0 5V_S0

A
1

D20
1

C530 1N4148W-1-GP
3D3V_S0 SCD1U16V2ZY-2GP U31 C524
2

SCD1U16V2ZY-2GP

K
2

1 8 BYP VCC5_DDC_PH
VCC_SYNC BYP
1

2 VCC_VIDEO VIDEO_1 3 BLUE_CONN 1


4 GREEN_CONN R517 R519
VIDEO_2 RED_CONN 2K2R2J-2-GP 2K2R2J-2-GP
3D3V_S0 7 VCC_DDC VIDEO_3 5
1

C532 14 HSYNC_5V_CON
<Core Design>
2

SCD1U16V2ZY-2GP HSYNC_3P3V SYNC_OUT1 VSYNC_5V_CON


13 16
2

VSYNC_3P3V SYNC_IN1 SYNC_OUT2


15 SYNC_IN2
A 9 5VDDCDA_CON_1 R515 1 2 100R2J-2-GP 5VDDCDA_CON A
DDC_DATA_VGA 10 DDC_IN1
DDC_OUT1
DDC_OUT2 12 5VDDCCLK_CON Wistron Corporation
DDC_CLK_VGA 11 DDC_IN2 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
6 C501 Taipei Hsien 221, Taiwan, R.O.C.
GND SC470P50V2KX-3GP
2

(R) Title
IP4772CZ16-1-GP

Size Document Number


VGA header Rev
B
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 23 of 59
8 7 6 5 4 3 2 1
5 4 3 2 1
,<hDE/^͊͊
U46
(S)
HDMI_OUT_TXD2 HDMI_OUT_TXD2 1 8 HDMI_OUT_TXD2
HDMI_OUT_TXD2 49 L1#1L1#8
HDMI_OUT_TXD2# HDMI_OUT_TXD2# 49 HDMI_OUT_TXD2# 2 7 HDMI_OUT_TXD2#
L2#2L2#7
G1 G2
HDMI_OUT_TXD1 HDMI_OUT_TXD1 GNDGND HDMI_OUT_TXD1
HDMI_OUT_TXD1 49 3 6
HDMI_OUT_TXD1# HDMI_OUT_TXD1# L3#3L3#6 HDMI_OUT_TXD1#
HDMI_OUT_TXD1# 49 4 5
L4#4L4#5
HDMI_OUT_TXD0 HDMI_OUT_TXD0 49
HDMI_OUT_TXD0#
HDMI_OUT_TXD0# 49 RCLAMP0524P-GP
HDMI_OUT_TXC
HDMI_OUT_TXC 49
HDMI_OUT_TXC#
HDMI_OUT_TXC# 49
D HDMI_OUT_SCL U50
D
HDMI_OUT_SCL 49
HDMI_OUT_SDA (S)
HDMI_OUT_SDA 49
HDMI_OUT_TXD0 1 8 HDMI_OUT_TXD0
HDMI_OUT_HPD HDMI_OUT_TXD0# L1#1L1#8 HDMI_OUT_TXD0#
HDMI_OUT_HPD 49 2 7
L2#2L2#7
G1 G2
HDMI_OUT_TXC GNDGND HDMI_OUT_TXC
3 6
HDMI_OUT_TXC# L3#3L3#6 HDMI_OUT_TXC#
4 5
L4#4L4#5

RCLAMP0524P-GP

3D3V_S0

3D3V_S0

R840 4K7R2J-2-GP

4K7R2J-2-GP
3D3V_S0
ZĞƐĞƌǀĞ

R822 4K7R2J-2-GP

4K7R2J-2-GP
1

1
C918 (R) C828 (R) C841 (R) C794 (R) C432 (U) C427 (U) C916 (U) C852 (U)
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

2
R863 2
SCD1U10V2KX-4GP

5V_S0 3D3V_S0 5V_S0


2

2
(R) (R)
ZĞƐĞƌǀĞ SB 1208

2
R823 2
DY DY

8101_NC351
8101_NC341

1
UMA UMA UMA UMA For PS8171 RN50 C845 (R) C921 (R) C851 (R) C912 (R) C898 (U) C920 (U) C882 (U) C853 (U) (R) (R) RN49

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
HDMI_OUT_SDA 1 4 2 TMDS_IN2_SDA 1 4 D29

SCD1U10V2KX-4GP
R862 HDMI_OUT_SCL 2 3 3 DY DY TMDS_IN2_SCL 2 3 K A

1
1
(R) 1
2 DY 1 SRN1K5J-GP SRN47K-2-GP-U 1N4148W-1-GP
D31

8101_NC35_2
8101_NC34_2
4K7R2J-2-GP CH461FPT-GP-U UMA UMA UMA UMA

11
15
21
26
33
40
46

35
34
2
U47

NC#35
NC#34
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
38 23 HDMI_OUT_TXC#
C 17 PCH_HDMI_CLK- IN_D1- OUT_D1- HDMI_OUT_TXC C

11
15
21
26
33
40
46

35
34
39 22

2
17 PCH_HDMI_CLK+ IN_D1+ OUT_D1+ U48
41 20 HDMI_OUT_TXD0#

NC#35
NC#34
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
17 PCH_HDMI_DATA0- IN_D2- OUT_D2- HDMI_OUT_TXD0
42 19
17 PCH_HDMI_DATA0+ IN_D2+ OUT_D2+
44 17 HDMI_OUT_TXD1# 38 23 TMDS_IN2_CLK-
17 PCH_HDMI_DATA1- IN_D3- OUT_D3- 17 PCH_TMDS_CLK- IN_D1- OUT_D1- TMDS_IN2_CLK- 47
45 16 HDMI_OUT_TXD1 39 22 TMDS_IN2_CLK+
17 PCH_HDMI_DATA1+ IN_D3+ OUT_D3+ 17 PCH_TMDS_CLK+ IN_D1+ OUT_D1+ TMDS_IN2_CLK+ 47
ZĞĐŽŵŵĞŶĚĞĚƋƵĂůŝnjĂƚŝŽŶ͗ HDMI_OUT_TXD2# TMDS_IN2_DATA0-
47 14 41 20 TMDS_IN2_DATA0- 47
΀Wϭ͕WϬ΁сϬϭ͕ϰĚ 17 PCH_HDMI_DATA2- IN_D4- OUT_D4- HDMI_OUT_TXD2 17 PCH_TMDS_DATA0- IN_D2- OUT_D2- TMDS_IN2_DATA0+
48 13 42 19 TMDS_IN2_DATA0+ 47
17 PCH_HDMI_DATA2+ IN_D4+ OUT_D4+ CHECK 17 PCH_TMDS_DATA0+ IN_D2+ OUT_D2+
(U) R813 44 17 TMDS_IN2_DATA1-
17 PCH_TMDS_DATA1- IN_D3- OUT_D3- TMDS_IN2_DATA1- 47
2 UMA 1 4K7R2J-2-GP PC0 3 8 PCH_HDMI_DATA 17 45 16 TMDS_IN2_DATA1+
3D3V_S0 PC0 SDA 17 PCH_TMDS_DATA1+ IN_D3+ OUT_D3+ TMDS_IN2_DATA1+ 47
2 1 4K7R2J-2-GP PC1 4 9 PCH_HDMI_CLK 17 ZĞĐŽŵŵĞŶĚĞĚƋƵĂůŝnjĂƚŝŽŶ͗
R812 PC1 SCL TMDS_IN2_DATA2-
DY HPD
7 PCH_HDMI_HPD 17
΀Wϭ͕WϬ΁сϬϭ͕ϰĚ 17 PCH_TMDS_DATA2-
47
IN_D4- OUT_D4-
14
TMDS_IN2_DATA2+
TMDS_IN2_DATA2- 47
48 13 TMDS_IN2_DATA2+ 47
(R) REXT_HDMI 17 PCH_TMDS_DATA2+ IN_D4+ OUT_D4+
6
1

REXT HDMI_OUT_HPD (U) R831


10 30
R811 8101_OE# RT_EN# HPD_SINK HDMI_OUT_SDA 8101_PC0
25 29 3D3V_S0 2 UMA 1 4K7R2J-2-GP 3 8 PCH_TMDS_DATA 17
(U) 5K1R2F-2-GP DDC_EN_PS8101 OE# SDA_SINK HDMI_OUT_SCL 8101_PC1 PC0 SDA
3D3V_S0 2 (U) 1 32 28 2 1 4K7R2J-2-GP 4 9 PCH_TMDS_CLK 17
DDC_EN SCL_SINK R842 PC1 SCL
UMA DY HPD
7 PCH_TMDS_HPD 17
R865
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2

4K7R2J-2-GP (R) 8101_REXT_HDMI 6

1
REXT TMDS_IN2_HPD
UMA 10 30 TMDS_IN2_HPD 47
2

5V_S0 R839 8101_OE#2 RT_EN# HPD_SINK TMDS_IN2_SDA


UMA 25 29 TMDS_IN2_SDA 47
1
5
12
18
24
27
31
36
37
43
49

OE# SDA_SINK

5K1R2F-2-GP
R810 (U) (U) 2 (U) 1 DDC_EN_PS8101_2 32 28 TMDS_IN2_SCL
3D3V_S0 DDC_EN SCL_SINK TMDS_IN2_SCL 47
(U)499R2F-2-GP UMA
UMA PS8101-GP R841

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
2 4K7R2J-2-GP
1

71.P8101.003 UMA

2
2ND = 71.03411.B03 HDMI_OUT_HPD 3 UMA

1
5
12
18
24
27
31
36
37
43
49
R843 (U)
(S) 1 (U) 499R2F-2-GP
UMA PS8101-GP
D30

1
71.P8101.003 3D3V_S0
BAV99PT-GP-U 2ND = 71.03411.B03
RN17 (S)
1 4 HDMI_OUT_TXD1
52 NV_HDMI_DATA1+ HDMI_OUT_TXD1#
2 3
DIS

1
52 NV_HDMI_DATA1-

B SRN0J-6-GP
RN58 (S)
HDMI_OUT_TXD2
3D3V_S0 3D3V_S0 (U)
R873
20KR2J-L2-GP B
1 4
52 NV_HDMI_DATA2+ HDMI_OUT_TXD2#
2 3
DIS

2
52 NV_HDMI_DATA2- 8101_OE#2
SRN0J-6-GP Q78 (S)

1
RN18 (S) NV_HDMI_DATA_R 1 6 HDMI_OUT_SDA
1 4 HDMI_OUT_TXC R851

D
52 NV_HDMI_CLK+ HDMI_OUT_TXC# (U) 20KR2J-L2-GP (U)
2 3 2 5
52 NV_HDMI_CLK- DIS Q74
SRN0J-6-GP HDMI_OUT_SCL 3 4 NV_HDMI_CLK_R 2N7002-11-GP
2

RN59 (S) 8101_OE# TMDS_IN2_HPD G


1 4 HDMI_OUT_TXD0 2N7002KDW-GP 84.27002.W31
52 NV_HDMI_DATA0+ HDMI_OUT_TXD0#
2
DIS 3 84.2N702.A3F 2ND = 84.27002.Y31

S
52 NV_HDMI_DATA0-
D

SRN0J-6-GP DIS (U)


Q77
2N7002-11-GP
DIS HDMI_OUT_HPD G
1 (S) 2 NV_HDMI_DATA_R 84.27002.W31
52 NV_HDMI_DATA
R882 DIS 0R2J-2-GP 2ND = 84.27002.Y31
S

1 2 NV_HDMI_CLK_R
52 NV_HDMI_CLK
R875 (S) 0R2J-2-GP

DIS
1 (S) 2 HDMI_OUT_HPD
52 NV_HDMI_DETECT R484 0R2J-2-GP

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HDMI OUT
Size Document Number Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 24 of 59

5 4 3 2 1
5 4 3 2 1

Side 2 USB PORT USB Power


USB PORT (0/1)
Use 69.50007.801 (Littelfuse)
F3
VCC5_USB 1 2 USBVCC08

1
FUSE-1D5A6V-7GP
DCBATOUT 5V_S5 --> VCC5_USB

1
(69.50007.801) R6 (R) TC1 (R) C560

1
470KR2J-2-GP C13
D D

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
R493

1 2

2
47KR2J-2-GP

SE330U6D3VM-3GP
5V_S5 OC*08 18

1
C14 R7

2
R488 Q44 SC1000P50V3JN-GP-U 560KR2J-GP

1
USB_EN2 1 2 USB_EN 4 5 (R)

2
G D
R876 10KR2J-3-GP 3 6

2
1
S D
100KR2J-1-GP 2 7

1
S D
1 8 R627

D
S D
C486 C482 1KR2J-1-GP
2

1
(R) AO4468-GP VCC5_USB

2
SCD1U25V3ZY-1-LL-GP
Q79 R899

2
USB_EN1 G 2N7002-11-GP 100KR2J-1-GP VCC5_USB
SCD1U50V3KX-GP

1
D

1
Q75 R492
1

2N7002-11-GP 4K7R2J-2-GP C490 C488


R881 (R) (R)
SB 1204

2
PM_SLP_S4#G 100KR2J-1-GP
16,33,38 PM_SLP_S4# [-1] 0401

2
USB2
6
h^džϭ
S

SC10U10V5ZY-1GP USBVCC08 1
SCD1U16V2ZY-2GP
C
USBP0N_EXT 2 C
USBP0P_EXT

SC10U10V5ZY-1GP
3

SC22U10V6ZY-2GP
4

1
D9 IP4220CZ6-GP C7 C12 5

USBP0P_EXT 1 6 USBP0N_EXT SKT-USB-130-GP

2
ESD I/O1 ESD I/O4 USBVCC08
2 GND VP 5
R12 20R0402-PAD R26 2 0R0402-PAD
1 1 3 ESD I/O2 ESD I/O3 4
dLJĐŽϮϮ͘ϭϬϮϭϴ͘Eϭϭ

1
(R)C
C16
16
2007/11/23,

SCD1U16V2ZY-2GP
SB 1210 Add for 4L USB1

2
2

3
ACM2012H-900-GP-DUMMY ACM2012H-900-GP-DUMMY 6
USBVCC08 1 h^džϭ
USBP0P_EXT USBP8P_EXT D10 IP4220CZ6-GP USBP8N_EXT 2
18 USBPP0 18 USBPP8
(R) USBP8P_EXT

SC10U10V5ZY-1GP
3
18 USBPN0 USBP0N_EXT 18 USBPN8 USBP8N_EXT 1 6 4
ESD I/O1 ESD I/O4

1
(R)

SC22U10V6ZY-2GP
2 5 USBVCC08 C559 C17 5
TR3 TR4 USBP8P_EXT GND VP USBP8N_EXT
3 ESD I/O2 ESD I/O3 4
SKT-USB-130-GP
1

2
1
(R)C
C561
561

SCD1U16V2ZY-2GP
68.00201.141 Murata dLJĐŽϮϮ͘ϭϬϮϭϴ͘Eϭϭ

2
B R15 1 20R0402-PAD R25 1 2 0R0402-PAD68.00201.141 Murata B
69.10087.011 Chilisin
69.10087.011 Chilisin

eSATA PORT Touch panel


R124 1 (R) 2 0R3J-0-U-GP

F1 USBVCCTP
VCC5_USB 1 2 USBVCCTP
ESATA1
SB 1118 FUSE-1D5A6V-8GP

1
14 SATA_RXP4 SATA_RXP4SCD01U16V2KX-3GP 2 1 C11 SATA_RXP4_C 2 1 (69.42001.291)
SATA_RXN4SCD01U16V2KX-3GP C10 SATA_RXN4_C A+ GND C89
14 SATA_RXN4 2 1 3 A- GND 4
14 SATA_TXN4 SATA_TXN4SCD01U16V2KX-3GP 2 1 C9 SATA_TXN4_C 5 7 SC10U10V5ZY-1GP

2
SATA_TXP4SCD01U16V2KX-3GP C8 SATA_TXP4_C B- GND
14 SATA_TXP4 2 1 6 B+ GND 8
GND 9 <Core Design>
NP1 10 USBVCCTP MULTITP1
NP1 GND
NP2 NP2 GND 11
A TP_DET# 1 A
19 TP_DET#
Wistron Corporation
SKT-ESATA-7P-4-GP 2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
18 USBPP5 USBPP5 3 Taipei Hsien 221, Taiwan, R.O.C.
18 USBPN5 USBPN5 4
5 Title

USB IO/eSATA/TP
DVD-CON5-14-GP Size Document Number Rev
B
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 25 of 59
5 4 3 2 1
DZ Z&ͲхtŝƌĞůĞƐƐ<ͬD^
3D3V_W EBCAM 3D3V_S5
3D3V_S0
U3 (R)
ZDKs͊͊

2
0R0402-PAD (R) C32
18 USBPN13 R69 1 2 USBP13N_INT 3D3V_BT_S0 1 5 1 2 R607

SCD1U16V2ZY-2GP
OUT IN SC4D7U10V3KX-GP 10KR2J-3-GP
2 GND SB 1204
18 USBPP13 R76 1 2 USBP13P_INT 3 4
NC#3 EN

1
0R0402-PAD EC3 W EBCAM_EN 19

1
G5240B1T1U-GP 1225 100R2J-2-GP

2
74.05240.A7F PW RSW 1 R613
3D3V_W EBCAM 3D3V_S0 1 2 PW R_BTN#_11 R602 2PW R_BTN# 1
0R0402-PAD
2 PW RBTN_N 33 ůƵĞƚŽŽƚŚ

1
5 C564
1 R67 2 SCD1U16V2ZY-2GP 18 USBPN12 R336 1 (R) 20R0402-PADUSBP12N_INT
3 4 BT_POW ER

2
0R0603-PAD 18 USBPP12 R340 1 (R) 20R0402-PADUSBP12P_INT
SW -TACT-172-GP BTRF1
SC 1229 1
[-1] 0401
3D3V_EUP
SC 1229 WƵƚŽŶdŽƉƐŝĚĞĨŽƌĚĞďƵŐ 2
USBP12P_INT

SIO_PWRLED_LED*1
G1 3
4 USBP12N_INT

2
3D3V_W EBCAM 3D3V_EUP PW R_BTN# 1 2 5 BT_LED_PW R
R612 6 W LAN_ACT
W EBCAM1 4K7R2J-2-GP (R)
SB 1204 7 BT_RESET_OUT
W LAN_ACT 29
GAP-OPEN BT_RESET_OUT 49
USBP13N_INT 2 1 USBP13P_INT 8

2
4 3
W EBCAM_DET# 6 5 2 R611 1 1 PMBS3906-GP JW T-CON8-S1-GP
19 W EBCAM_DET# 33 SIO_PW RLED_N Q61
1KR2J-1-GP
R598

3
DVD-CONN6D-S2-GP PW RLED1
PW R_LED#_PA K PW R_LED#_N 1 2

LED-W -38-GP 100R3J-4-GP

[-1] 0401

ͲZKDKEEdKZ 3D3V_S0
ůƵĞdŽŽƚŚWŽǁĞƌ
BT_POW ER

SC1U10V3ZY-6GP
ŚĞĐŬ,ƉŽǁĞƌ;нϭϮsͿĂŶĚĐŽŶŶĞĐƚŽƌƚLJƉĞ

1
3D3V_S0 C708

WLAN_LED#1
R631 3D3V_S5
4K7R2J-2-GP (R) (R)
Check connection!!

2
2
3D3V_S5

2
R758
SATAODD1 2 R629 1 1 PMBS3906-GP 10KR2J-3-GP
29 W LAN_LED# Q62
8
1 SCD01U50V2KX-1GP 1KR2J-1-GP
R628

S
C952 W LANLED1 BT_POW ER_CTL#1
2 SATA_RXP1_C 1 2 SATA_RXP1 14 W LAN_LED#_P A K W LAN_LED#_N 1 2 G
3 SATA_RXN1_C 1 2 Q67 BT_POW ER
4 C954
SATA_RXN1 14 3D3V_S0 LED-W -38-GP 100R3J-4-GP ĞĨĂƵůƚсх,ŝŐŚ

D
5 SCD01U50V2KX-1GP SATA_TXN1 14 AO3413-GP
6 SATA_TXP1 14 ^ϱсх>Žǁ Q69

D
2
7 3D3V_S0 2N7002-11-GP
[-1] 0401

SATA_LED#1
9 R28 33 BT_PW R_EN G
4K7R2J-2-GP
SKT-SATA7P-19-GP-U

S
1

2
2 R27 1 1 PMBS3906-GP
14 SATA_LED# Q3
1KR2J-1-GP
R16

3
HDDLED1

D/E,ŽŶŶĞĐƚŽƌ SATA_LED#_P
A K SATA_LED#_N

LED-W -38-GP
1

100R3J-4-GP
2

BT_POW ER
Check connection!! SB 1204
SATAHDD1
[-1] 0401
,WŽǁĞƌŽŶŶĞĐƚŽƌ

2
8
1 SCD01U50V2KX-1GP R754
C527 4K7R2J-2-GP (R)
2 SATA_RXP0_C 1 2
3 SATA_RXN0_C 1 2
SATA_RXP0 14
SATA_RXN0 14
Layout: Please put them together R619

1
4 C526 BTLED1
5 SCD01U50V2KX-1GP SATA_TXN0 14 BT_LED_PW R A K BT_LED_N 1 2
6 SATA_TXP0 14 Pin1(VCC12) V_5HDD V_5HDD
7 LED-W -38-GP 100R3J-4-GP
9 SATAPW R1
>ŽƚĞƐ͗ϮϬ͘ϴϭϭϭϮ͘ϬϬϳ
K
SKT-SATA7P-19-GP-U 1 +12V_S0 [-1] 0401
1

D24
Black DŽůĞdž͗ϮϬ͘ϴϬϲϭϴ͘ϬϬϳ 2
3
C555
SC10U10V5ZY-1GP
SMAJ6D0A-13-F-GP
2

4
A

5 V_5HDD

DVD-CON5-26-GP
5V_S0 [-1] 0401 (21.61192.105)
POLYSW -3A6V-GP-U V_5HDD
<Core Design>
F2
1 2 V_5HDD V_5HDD +12V_S0 +12V_S0

(R) Wistron Corporation


R574 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SC10U10V5ZY-1GP

1 2 C553 C550 Taipei Hsien 221, Taiwan, R.O.C.


0R5J-5-GP (R) C554 C551
SC1U16V3KX-2GP

R573 SC10U25V6KX-1GP Title


2

1 2 SC1U16V3KX-2GP (R)
0R5J-5-GP HDD/ODD IF+USB device
Size Document Number Rev
A3
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 26 of 59
A B C D E

5,18,28,33 PLT_RST# V_3P3_LAN R476 1 2 10KR2J-3-GP CLK_REQ_N


U25
15 CLK_PCIE_LAN_P LANCLK_REQ_N R473 1 2 0R2J-2-GP
15 CLK_PCIE_LAN_N (R) 48 13 LAN_MDI0_DP
PLT_RST# R459 LAN_RST_N CLK_REQ# MDI_PLUS0 LAN_MDI0_DN
2 1 0R0402-PAD 36 PE_RST# MDI_MINUS0 14
V_3P3_LAN
15 PCIE_RXN3
CLK_PCIE_LAN_P 44 17 LAN_MDI1_DP >EͺD/ͺWͬ>EͺD/ͺE
15 PCIE_RXP3 PE_CLKP MDI_PLUS1
CLK_PCIE_LAN_N LAN_MDI1_DN
45 18 ƌŽƵƚŝŶŐŐƵŝĚĞůŝŶĞ͗ϰŵŝůƐŽŶ

PCIE
PE_CLKN MDI_MINUS1

MDI
C465 C474

1
PCIE_RXP3 HSI1_C_DP LAN_MDI2_DP SC10U10V5ZY-1GP
15 PCIE_TXN3
PCIE_RXN3
C441 1
C443 1
2 SCD1U10V2KX-4GP
2 SCD1U10V2KX-4GP HSI1_C_DN
38
39
PETP MDI_PLUS2 20
21 LAN_MDI2_DN
ϭϬŵŝůƐƐƉĂĐŝŶŐ SCD1U16V2ZY-2GP
15 PCIE_TXP3 PETN MDI_MINUS2
4 WĂŝƌƚŽƉĂŝƌƐŚŽƵůĚŬĞĞƉĂǁĂLJ 4

2
PCIE_TXP3 41 23 LAN_MDI3_DP
PERP MDI_PLUS3
15 SML0_CLK
PCIE_TXN3 42 PERN MDI_MINUS3 24 LAN_MDI3_DN ǁŝƚŚϮϱŵŝůƐ
15 SML0_DATA Place near Pin5
SML0_CLK 28 6
15 LANCLK_REQ_N

SMBUS
SML0_DATA SMB_CLK VCT
31 SMB_DATA
1 LAN_RSVD1 R477 1 2 3KR2J-2-GP V_3P3_LAN
RSVD#1_VCC3P3 LAN_RSVD2 R474
Low: Power down mode 2 1 2 3KR2J-2-GP
16,19 LAN_DISABLE_N RSVD#2_VCC3P3
VDD3P3 5 V_3P3_LAN
Place near IC
LAN_DISABLE_N 3
RJ45_LED0 LAN_DISABLE# V_3P3_C
49 RJ45_LED0 CTRL_2P5 4
C927 V_1P0_LAN

1
49 RJ45_LED1 RJ45_LED1 15 SC1U6D3V2KX-GP
RJ45_LED0 AVDD2P5
26 LED0 AVDD2P5 19
49 RJ45_LED2 RJ45_LED2 RJ45_LED1 27 29 R471 1 2 0R0603-PAD V_1P0_LAN

2
LED1 DVDD2P5

LED
V_3P3_LAN RJ45_LED2 25 C917 C901
LED2

1
SCD1U16V2ZY-2GP SC1U10V3ZY-6GP
LAN_MDI0_DN 47
49 LAN_MDI0_DN DVDD1P2
LAN_MDI0_DP 46
49 LAN_MDI0_DP

2
R453 1 DVDD1P2
2 10KR2J-3-GP (R) TP_LAN_JTDI 32 JTAG_TDI DVDD1P2 37 V_1P0_FILTERED R469 1 2 0R0603-PAD
LAN_MDI1_DN TPAD28 TP13 TP_LAN_JTDO 34
49 LAN_MDI1_DN JTAG_TDO

JTAG
LAN_MDI1_DP R452 1 2 10KR2J-3-GP (R) TP_LAN_JTMS 33 43 V_1P0_FILTERED1
49 LAN_MDI1_DP JTAG_TMS AVDD1P2
R451 1 2 10KR2J-3-GP (R) TP_LAN_JTCK 35
LAN_MDI2_DN JTAG_TCK V_1P0_FILTERED2 R878
49 LAN_MDI2_DN AVDD1P2 11 1 2 0R0603-PAD
LAN_MDI2_DP
49 LAN_MDI2_DP
C468 1 2 SC10P50V3JN-GP LAN_XTALO 9 40
LAN_MDI3_DN LAN_XTALI XTAL_OUT AVDD1P2 1D05V_LAN
49 LAN_MDI3_DN 10 XTAL_IN AVDD1P2 22
LAN_MDI3_DP SMD 16
49 LAN_MDI3_DP AVDD1P2
3 +- 30ppm CL:18P AVDD1P2 8 3
LAN_TEST_EN 30 V_1P0_LAN 1225
X5 TEST_EN
LAN_RBIAS 12 7 1 R830 2
RBIAS CTRL_1P2 0R0805-PAD
1 4

SC10U6D3V3MX-GP
49 C923
VSS_EPAD

1
SCD1U16V2ZY-2GP
C857 C847

SCD1U16V2ZY-2GP
WG82578DC-GP C895

SC10U6D3V3MX-GP
2 3 R455 R478 (71.82577.D03) (R)

2
1KR2J-1-GP 3K01R2F-3-GP
WůĂĐĞŶĞĂƌ>E

2
1

1
XTAL-25MHZ-129-GP
C479 C466
SC33P50V2JN-3GP SC33P50V2JN-3GP
2

2
3D3V_EUP 3D3V_EUP
3D3V_EUP
0126 (1A)
Layout note
Keep LAN chip at least 1" from the RJ45

1
C493
SC1U16V3KX-2GP

2
R565

2
Right LED Left LED Giga 100 10 1 2PM_SLP_LAN#1
1 PMBS3906-GP
2 16,39 PM_SLP_LAN# Q52 2
10KR2J-3-GP
Green Orange
X

3
Left LED Link Orange Green

S
SLP_PN1_M G Q45
Right LED Act Blink Blink Blink AO3413-GP

1
Green
V_3P3_LAN

D
R498
10KR2J-3-GP
11 12 5 1 2 3 4 7 8 9 10 6 13 14

2
1 <Core Design> 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

INTEL Gb LAN-WG82577LC
Size Document Number Rev
Custom
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 27 of 59
A B C D E
A B C D E

3D3V_S0

V_3_1394_O
From VT6325
CLK_PCIE_CR_P <F7>
15 CLK_PCIE_CR_P CLK_PCIE_CR_N R71 Internal LDO

S
15 CLK_PCIE_CR_N 4K7R2J-2-GP

1
CRIO18 2CRIO18_R
PCIE_RXP4
1 G
R111 (R)
Layout: Close to Card
15 PCIE_RXP4 AO3413-GP 0R3J-0-U-GP
15 PCIE_RXN4
PCIE_RXN4
Q7
connector
PCIE_TXP4 V_3_CARD MEM_CARD1
15 PCIE_TXP4 Layout: Close

2
D
PCIE_TXN4 V_3_CARD V_3_CARD
15 PCIE_TXN4
PLT_RST#
to VT6325 12
VCC SDIO/DATA0
22 CRIO5
CRIO6
24
5,18,27,33 PLT_RST# DATA1 CRIO4
38 20
XD_VCC DATA2

1
<F7> <F7> 16 CRIO3

1
4
<F7> <F7> R91 C59 C42 C45 DATA3 4
21
C54 C70 10KR3J-L1-GP <F7> (R) <F7> C62 SD_VDD CRIO7_SDWP
41
C61 <F7> SD_W/P CRIO15
39

2
SCD1U16V2ZY-2GP SC10U10V5ZY-1GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP CRIO17 SD_C/D CRIO11_SD
2 15

2
SC1U10V3ZY-6GP SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP CRIO10 XD_CARD_DETECT SD_CMD
3
CRIO9 XD_R/B# CRIO12
4 25
CRIO11_XD_CE 5 XD_RE# SD_CLK
<F7> CRIO13 XD_CE# CRIO14
6 31
CRIO19 XD_CLE SD_DAT0 CRIO8
7 34
<F7> CRIO8 XD_ALE SD_DAT1 CRIO10
8 9
V_3_1394_O 3D3V_S0 <F7> V_3_1394_A CRIO11 CRIO11_SD CRIO14 XD_WE# SD_DAT2 CRIO9
1 R54 2 13 11
L6 0R0402-PAD XD_WP# SD_CD/DAT3
1 2
+3.3V <F7> CRIO0 23 NP1
<F7> FCM1608KFG-301T05-GP R60 CRIO11_XD_CE CRIO1 XD_D0 NP1
1 2 27 NP2
XD_D1 NP2

1
C80 <F7> <F7> <F7> 0R0402-PAD CRIO2_XD 30
C79 C55 C81 C82 C52 C43 C69 C85 CRIO3 XD_D2
32 10
<F7> <F7> (R) <F7> <F7> <F7> CRIO4 XD_D3 VSS
33 28

2
SCD1U16V2ZY-2GP CRIO7 XD_D4 VSS
1 R55 2 CRIO7_SDWP CRIO5 35 29
SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP 0R0402-PAD CRIO6 XD_D5 SD_VSS
36 19
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC1U10V3ZY-6GP <F7> CRIO7 XD_D6 SD_VSS
37
CRIO7_MSBS XD_D7
1 R57 2 40
0R0402-PAD CRIO16 SD_GND
18 1
CRIO7_MSBS INS XD_GND
26 17
<F7> CRIO2_SCLK BS XD_GND
14 42
CRIO2 SCLK GND
1 R52 2 CRIO2_XD 43
VCORE_1394_A 0R0402-PAD GND
VCORE_1394 <F7> <F7>
L5 1 R53 CRIO2_SCLK CARD-PUSH-38P-GP-U
+1.2V 1 2
+1.2V 0R0402-PAD
2

1 FCM1608KFG-301T05-GP

1
<F7> <F7> <F7> <F7> <F7> <F7> <F7> V_3_CARD
C46 C67 C83 C84 C36 C47 C48
CRIO14 R51 1 <F7> 2 4K7R2J-2-GP
2

2
CRIO8 R56 1 <F7> 2 4K7R2J-2-GP
SC1U10V3ZY-6GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP SCD1U16V2ZY-2GP CRIO10 R59 1 <F7> 2 4K7R2J-2-GP
SCD1U16V2ZY-2GP SC1U10V3ZY-6GP SCD1U16V2ZY-2GP CRIO9 R58 1 <F7> 2 4K7R2J-2-GP
3 CRIO11 R61 1 <F7> 2 4K7R2J-2-GP 3

CRIO13 R63 1 (R) 2 4K7R2J-2-GP


CRIO19 R62 1 (R) 2 4K7R2J-2-GP
CRIO14 R66 1 (R) 2 4K7R2J-2-GP

1394 port Common Choke Front 4pin SB 1210


U5 R5 1 2 R3 1 2 FIRE1
0R2J-2-GP 0R2J-2-GP 5
VIA VT6325 3D3V_S0 22
VCC1 CRIO0
45 CRIO0 TPB0- TPBN0 TPA0- TPAN0 NP1
1 46 CRIO1 TPBN0 1
VCC2 CRIO1 CRIO2
43 47
Close to FIRE1

3
VCC3 CRIO2 CRIO3 TPBP0
48 2
CRIO3 CRIO4 TPAN0
42 49 3
VDD33I CRIO4 CRIO5 TPAP0
V_3_1394_O 41 50 4
VDD33O CRIO5 CRIO6 TR1
52 NP2
CRIO6 CRIO7 ACM2012H-900-GP-DUMMY
V_3_CARD 51 53 (R) 6
VCCCR1 CRIO7 CRIO8
58 54
VCCCR2 CRIO8 CRIO9 ACM2012H-900-GP-DUMMY (R) SKT-1394-4P-53-GP
CRIO9
55
TR2
68.00201.141Murata
VCORE_1394 23 56 CRIO10
VDDC1 CRIO10 CRIO11 69.10087.011 Chilisin
2 57

4
VDDC2 CRIO11 CRIO12
44 59
VDDC3 CRIO12 CRIO13 TPB0+ TPBP0 TPA0+ TPAP0
CRIO13
60 If using 6pin CONN, please
28 61 CRIO14
VDDC4 CRIO14 CRIO15 separate shielding GND and
62 1 2 1 2
CRIO15 CRIO16 R4 0R2J-2-GP R2 0R2J-2-GP
V_3_1394_A 29 63 signal GND.
VDDA CRIO16 CRIO17
35 3
VDDAP0 CRIO17 CRIO18
4
CRIO18 CRIO19
10 5
VCCAH_RX CRIO19 NC_CRIO20
14
VCCAH_MAIN CRIO20
17 Pin17 is floating
VCORE_1394_A 6
2 VCCA_TX TPA0- 2
9 38
VCCA_RX XTPAM0 TPA0+ TPBIAS0 C86
39 1 2
XTPAP0 TPB0- SCD33U16V3KX-1GP
XTPBM0
36 XCPS Definition:
PCIE_RXP4 SCD1U16V2ZY-2GP2 1 C50 PCIE_1394_TXP 7 37 TPB0+
PETP0 XTPBP0

1
PCIE_RXN4 SCD1U16V2ZY-2GP2 1 C49 PCIE_1394_TXN 8 For 6pin type of 1394, mount 11kohm res to +12V.
PCIE_TXP4 PETN0 XI_1394 R107 R105
11
PERP0 XI
31 For 4pin type, unmount 11kohm res.
PCIE_TXN4 12 30 XO_1394 R110 54D9R2F-L1-GP 54D9R2F-L1-GP
PERN0 XO XREXT_1394 Both of type need mount 1kohm to GND.
33 1 2
5K6R2F-2-GP R68 PEX_REXT XREXT XCPS_1394 5K6R2F-2-GP
1 2 13 34

2
PLT_RST# PEX_REXT XCPS0 TPBIAS0 XCPS_1394
18 40
CLKREQ_N_1394 PERST# XTPBIAS0 TPB0-
3D3V_S0 1 2 19

1
4K7R2F-GP R77 CLKREQ# SDA_1394 TPB0+
26
CLK_PCIE_CR_P SDA SCL_1394 R109
15 27
CLK_PCIE_CR_N REFCLK+ SCL 1KR2F-3-GP
16
REFCLK- VT6325_REG_EN TPA0-
32 1 2
NC#32 R103 TPA0+

2
4K7R2F-GP
1 2 EE_EN
20
21
GPIO1
64
Near the chip

1
EE_EN VSS
Disable EEPROM 24
TEST
Mount 4.7kohm R80 (R) GRSTZ_1394 25 65 R106 R108
function 4K7R2F-GP GRST# GND 54D9R2F-L1-GP 54D9R2F-L1-GP
1

C64
EEPROM Enable Unmount VT6325-GP C88

2
SC1U10V3ZY-6GP 1 2
2

SC270P50V2JN-2GP

CLOSE TO connector D8 3D3V_S0 1394_PD1 1 R112


SB 1204 2

TPA0+ 1 6 TPA0- 4K99R2F-L-GP


ESD I/O1 ESD I/O4
2 5

1
TPB0+ GND VP TPB0- C558
3 4
XI_1394 ESD I/O2 ESD I/O3
SCD1U16V2ZY-2GP

2
XO_1394 3D3V_S0 1 2 C78 <F7> IP4220CZ6-GP

SCD1U16V2ZY-2GP
X1
1 2 U4
1 1
XTAL-24D576MHZ-4-GP R102 8 1
WP_1394 VCC E0
2 1 7 2
1

C72 C77 510R2J-1-GP SCL_1394 WC# E1


6 3
SC15P50V2JN-2-GP SC15P50V2JN-2-GP SDA_1394 SCL E2
5 4 <Core Design>
SDA VSS
2

M24C02-WMN6TP-GP-U
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1221 (SC) Taipei Hsien 221, Taiwan, R.O.C.

Title
VT6325 1394/CARD READER
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 28 of 59
A B C D E
A B C D E

Mini PCI-E Connector


TV-TUNER Card Wireless Card(Present support EP/SP)
4 4

3D3V_S0 3D3V_S0

MINI2 MINI1
53 53
NP1 NP1 0R2J-2-GP
1D5V_S0_EP 1D5V_S0_SP MINI1_WAKE# R23 1 (R)
2 1 SC 1216_Eric 2 1 2 PCIE_WAKE# 16
4 3 TV_CVBS+ R970 1 (R) 2 0R2J-2-GP 2663_C15 47 4 3
6 5 TV_CVBS- R971 1 (R) 2 0R2J-2-GP 2663_C14 47 6 5
BC_PWR WLAN_ACT 26
8 7 MINI2_CLKREQ# 15 8 7 MINI1_CLKREQ# 15
BC_DATA
SC 1230 BC_CLK
10
12
9
11
10
12
9
11
CLK_PCIE_MINI2# 15 CLK_PCIE_MINI1# 15
BC_RESET 14 13 CLK_PCIE_MINI2 15 14 13 CLK_PCIE_MINI1 15
R1038 1 (R) 2 0R2J-2-GP TV_IR_Card 16 15 16 15
47 TV_IR (R) R43
SC 1230 DY 2 (R)
1
R472
DY 10KR2J-3-GP
2
BC_DETECT
1
10KR2J-3-GP
18 17 18 17
20 19 TV_IRQ_Card R1039 1 (R) 20R2J-2-GP 20 19
19 TV_EN R850 0R0402-PAD TV_IRQ 47 14 WIFI_RF_EN R596 (R) 0R0402-PAD
22 21 22 21
33 MINIPCIE_RST# MINI2_3D3V_S0 24 PCIE_C_RXN2 33 MINIPCIE_RST#
3D3V_S0 1 2 23 1 (R) 2 PCIE_RXN2 15 3D3V_S0 R48 1 (R) 2 0R0603-PADMINI3_3D3V_S0 24 23 PCIE_C_RXN1 1 2 PCIE_RXN1 15
3
R872 0R0603-PAD 26 25 PCIE_C_RXP2 1 2 PCIE_RXP2 15 26 25 PCIE_C_RXP1 1 2 PCIE_RXP1 15 3
(R) 28 27 R849 (R) 0R0402-PAD 28 27 R597 (R) 0R0402-PAD
3,12,13,15,58 PCH_SMBCLK 30 29 3,12,13,15,58 PCH_SMBCLK 30 29
3,12,13,15,58 PCH_SMBDATA 32 31 PCIE_TXN2 15 3,12,13,15,58 PCH_SMBDATA 32 31 PCIE_TXN1 15
34 33 PCIE_TXP2 15 34 33 PCIE_TXP1 15
[-1] 0317 18 USBPN11 36 35 [-1] 0317 18 USBPN1 36 35
SC 1230 18 USBPP11 38 37 18 USBPP1 38 37
40 39 3D3V_S0 40 39 MINI1_PIN_3D3V 1 2 3D3V_S0
3D3V_EUP_M R975 1 (R) 2 0R3J-0-U-GP TV_Power 42 41 42 41 R19
0R0603-PAD
R972 2 (R) 1 0R2J-2-GP TV_RST#
44
46
43
45 TV_Audio_R_Card R984 1 (R) 2 0R2J-2-GP
SC 1216_Eric 26 WLAN_LED# 44
46
43
45
47 HW_TV_RST# TV_Audio_R 47 (R)
48 47 TV_Audio_L_Card R985 1 (R) 2 0R2J-2-GP TV_Audio_L 47 48 47
50 49 TV_SMBCLK R973 1 (R) 2 0R2J-2-GP 50 49
Touch_SMBCLK 47,48
3D3V_S0 52 51 TV_SMBDATAR974 1 (R) 2 0R2J-2-GP 3D3V_S0 52 51
Touch_SMBDATA 47,48
NP2 NP2
54 54
SC 1216_Eric MINIPCI52P-GP-U MINIPCI52P-GP-U
(62.10043.511)
(62.10043.511)
3D3V_EUP_M Tyco 1759544-1 (62.10043.511)

2
SC 1230 2
1

BCAS1
C970 C971 NP1
SC10U10V5ZY-1GP SCD1U16V2ZY-2GP BC_PWR 1 2 BC_RESET
2

(R) (R)
BC_CLK 3 4 BC_DETECT 3D3V_S0 1D5V_S0_SP
5 6 1 TP16 TPAD24
BC_DATA 7 8 1 TP17 TPAD24
NP2

1
SPD-CONN8A-3-GP
C37 C41 C38
SCD1U16V2ZY-2GP SC10U10V5ZY-1GP SCD1U16V2ZY-2GP

2
1D5V_S0 1D5V_S0_EP 3D3V_S0 1D5V_S0_EP

1D5V_S0 1D5V_S0_SP
<Core Design>
G33
1

1 2 G17
1 C458 C461 C460 C928 1 2 1
GAP-CLOSE-PWR-2U-GP SC10U10V5ZY-1GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP SCD1U16V2ZY-2GP Wistron Corporation
2

(R) GAP-CLOSE-PWR-2U-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


G32 G18 Taipei Hsien 221, Taiwan, R.O.C.
1 2 1 2
Title
GAP-CLOSE-PWR-2U-GP GAP-CLOSE-PWR-2U-GP
MINI CARD CONN(1/2) .
Size Document Number Rev
B
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 29 of 59
A B C D E
A B C D E

dŽW, ACZ_RST#_AUDIO
5V_S5
14 ACZ_RST#_AUDIO

A
ACZ_SYNC_AUDIO (R)
14 ACZ_SYNC_AUDIO +12V_S0 D12
ACZ_SDATAIN0 ŶĞĂƌĐŽĚĞĐ 5VA_S0
14 ACZ_SDATAIN0 5VA_S0 WƵƚŶĞĂƌWŝŶϯϴ U1 500mA
SSM5817SPT-GP

ACZ_BITCLK_AUDIO AUD_AGND 1

K
VOUT

1
14 ACZ_BITCLK_AUDIO ALC272_AVDD 2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C19SC2D2U10V3ZY-1GP
GND

1
ACZ_SDATAOUT_AUDIO AUD_AGND R29 D11 3
14 ACZ_SDATAOUT_AUDIO VIN

1
1N4148W-1-GP
(R) C15 (R)
SB 1209 0R0603-PAD

1
C23

C29
ACZ_SPKR (R) APL78L05EC-TRLGPU SC10U10V5ZY-1GP C18
ŶĞĂƌĐŽĚĞĐ

2
14 ACZ_SPKR 1225 SC10U10V5ZY-1GP
4 4

2
K
ALC272_HP_OUT_R 2 (R) R32 1 AUD_PIN32

C20 SC2D2U10V3ZY-1GP
2

2
32 ALC272_HP_OUT_R

2
0R0402-PAD V_12_CODEC AUD_AGND AUD_AGND AUD_AGND
C22 C24
D/:</E

1
ALC272_HP_OUT_L 2 (R) R33 1 AUD_PIN31 SC4D7U10V5ZY-3GP (R)

1
AUD_AGNDAUD_AGND 32 ALC272_HP_OUT_L 0R0402-PAD SCD1U16V2ZY-2GP C21 C28
MIC_R_JACK ϲϰ͘ϱϭϬϭϱ͘ϲ>;ϱ͘ϭŬͿ (R) SC1U16V3KX-2GP SC4D7U25V5KX-GP
32 MIC_R_JACK

2
32 MIC_L_JACK MIC_L_JACK 32 HP_OUT_JD R24 1 2 5K1R2F-2-GP
AUD_AGND

ALC272_MIC1_VREFR
^W/& AUDIO OUT TO SCALAR

2
PC_AUDIO_L ALC272_MIC1_VREFR
ŶĞĂƌĐŽĚĞĐ

ALC272_SENSEB

ALC272_AVDD
CODEC_VREF
32 PC_AUDIO_L

1
ALC272_CPVEE

ALC272_CBN
D7

ALC272_CBP 1

2 ALC272_MIC1_VREFRR
SPDIF C25 BAW56-3-GP
49 SPDIF

2ALC272_MIC2_VREFRR
3
PC_AUDIO_R SC4D7U10V5ZY-3GP

2
32 PC_AUDIO_R

AUD_AGND

:ĂĐŬĞƚĞĐƚ

1
36

35

34

33

32

31

30

29

28

27

26

25
32 MIC_IN_JD MIC_IN_JD U2
HP_OUT_JD

MIC1-VREFO
HPOUT-L/PORT-I-L

AVSS1

AVDD1
LOUT1-L/PORT-D-L

VREF
SENSE-B

CPVEE

CBP
LOUT1-R/PORT-D-R

HPOUT-R/PORT-I-R

CBN
32 HP_OUT_JD

R13 R14
37 24 4K7R2J-2-GP 4K7R2J-2-GP
DWŵƵƚĞůŽŐŝĐƵƐĞ 64.51015.6DL (5.1k) MONO-OUT LINE1-R/PORT-C-R

1
3 ALC272_AVDD 38 23 EXT_MIC 3

1
AVDD2 LINE1-L/PORT-C-L
EAPD# ŶĞĂƌĐŽĚĞĐ 39 22 AUD_PIN22 C26 1 2 PORT_B_R 1 R17 2 1KR2J-1-GP MIC_R_JACK 32
32 EAPD# R31 LOUT2-L/PORT-A-L MIC1-R/PORT-B-R SC10U10V5KX-2GP
2 1 CODEC_JDREF 40 21 AUD_PIN21 1 2 PORT_B_L 1 R18 2 1KR2J-1-GP MIC_L_JACK 32
JDREF MIC1-L/PORT-B-L C27 SC10U10V5KX-2GP
20KR2F-L-GP 41 20
LOUT2-R/PORT-A-R LINE2-VREFO
42 AVSS2 MIC2-VREFO 19

43 18
AUD_AGND NC#43 ALC272 LINE1-VREFO
44 DMIC-CLK3/4 MIC2-R/PORT-F-R 17

45 SPDIFO2
(LQFP-48) MIC2-L/PORT-F-L 16

46 15 SB 1209

GPIO0/DMIC-DATA1/2

GPIO1/DMIC-DATA3/4
DMIC-CLK1/2 LINE2-R/PORT-E-R

^W/&Khd EAPD 47 EAPD LINE2-L/PORT-E-L 14 DELETE!!


48 13 ALC272_SENSEA 1 2

SDATA-OUT
MIC_IN_JD 32

PCBEEP-IN
49 SPDIF SPDIFO1 SENSE-A R38

SDATA-IN

DVDD-IO
2

RESET#
20KR2F-L-GP

BITCLK
2

DVDD

SYNC
DVSS

DVSS
R41
10KR2J-3-GP R35
(R) 10KR2J-3-GP
ALC272-GR-GP
[-1] 0317
1

10

11

12
3D3V_S0
1

2 2
AUD_PC_BEEP

HDA_SDIN1_RES
SC4D7U10V5ZY-3GP

SCD1U16V2ZY-2GP

ACZ_RST#_AUDIO 14
2

1
C39

C34

ACZ_SYNC_AUDIO 14
(R) ACZ_SDATAIN_RTL_ALC272 2 R42 1 33R2J-2-GP
1

ACZ_SDATAIN0 14

ACZ_BITCLK_AUDIO 14

ACZ_SDATAOUT_AUDIO 14 C33
48 HP_DET_MUTE# R49
2

3D3V_S0 2 1 AUD_BEEP 1 2 AUD_PC_BEEP


EC1 14 ACZ_SPKR
2 1 SCD1U16V2ZY-2GP R587

2
(R) 10KR2J-3-GP 10KR2J-3-GP SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1
EC2 2 1 SCD1U16V2ZY-2GP

C35
(R) R50 C40
1

SC220P50V2KX-3GP
R40 1 2 0R2J-2-GP 5V_EUP [4.7k) 10KR2J-3-GP

2
2

1
2

3D3V_S0 AUD_AGND
AUD_AGND
AUD_AGND R47
10KR2J-3-GP
1

EC4 2 1 SCD1U16V2ZY-2GP EAPD#


1 (R) 1
<Core Design>
D

1225 Q5
R1 1 2 0R0402-PAD 2N7002-11-GP
Wistron Corporation
R20 1 2 0R2J-2-GP EAPD G 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
(R)
S

Title
AUD_AGND AUDIO CODEC-ALC272
Size Document Number Rev
Custom
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 30 of 59
A B C D E
A B C D E

4 4

3 3

2 2

<Core Design>

1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserve
Size Document Number Rev
B
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 31 of 59
A B C D E
5 4 3 2 1

5V_EUP AUD_AGND
HP JACK (14/15)
D//E ,WKhd Cehck Jack Spec

2
HPOUT1

1
SHIELDING
R65
SB 1209 R10 Impedance=60 ohm 1
30 MIC_L_JACK
30 MIC_R_JACK
10KR2J-3-GP DELETE!! 1KR2J-1-GP
R8
L3 GND_1
R70 GND_2

1
2
ALC272_HP_OUT_L 1 2 1 2 HP_OUT_L_C 2

2
MUTE_LO#1 2 MUTE_LO*_1 1 Q8 FCM1608KF-1-GP 6
,WKhd 4K7R2J-2-GP
PMBS3906-GP
R9
100R2J-2-GP
L4
HP_OUT_R_C
HP_OUT_JD
3
4

3
D ALC272_HP_OUT_R 1 2 1 2 5 D

1
ALC272_HP_OUT_L FCM1608KF-1-GP C1 (R)
30 ALC272_HP_OUT_L

SC100P50V2JN-3GP
ALC272_HP_OUT_R 100R2J-2-GP NP1
30 ALC272_HP_OUT_R

1
C5 D1 D2 NP2

2
1

SC100P50V2JN-3GP
R11 C6 (R) (R)

SC100P50V2JN-3GP
1KR2J-1-GP AUDIO-JK132-GP
JACK DETECT

2
AUD_AGND AUD_AGND

MLVG04025R0QV05BP-GP

MLVG04025R0QV05BP-GP
1

2
AUD_AGND

2
MIC_IN_JD D6
30 MIC_IN_JD SB 1209 R22

3
AUD_AGND AUD_AGND
AUD_AGND
30 HP_OUT_JD
HP_OUT_JD DELETE!! 1 2 1 Q2
PMBS3904-1-GP
AUD_AGND AUD_AGND 2 HP_OUT_L_C

ALC272_MUTE
4K7R2J-2-GP 3

2
EAPD# 5V_EUP 1 HP_OUT_R_C
30 EAPD#
AUD_AGND
AUD_AGND

3
R21 AZ2025-02S-GP
R64 1 2 1 Q1
100KR2J-1-GP PMBS3904-1-GP /ĨƵƐĞ͗ϴϯ͘ϬϮϬϮϱ͘Ϭϭ
TPA3113_SD# 4K7R2J-2-GP
47,48 TPA3113_SD# D25

2
2
K A MUTE_LO#
AUD_AGND
FRONT MIC JACK (21/22)

3
R46
EAPD# 1 Q6 1N4148W -1-GP
2 1
>/EKhdƚŽ^ĐĂůĂƌ PMBS3904-1-GP MICJK1
10KR2J-3-GP
D//E SHIELDING

2
Impedance=60 ohm 1
C GND_1 C
L1
GND_2

3
R84 MIC_L_JACK 1 2 MIC_IN_L_JK 2
TPA3113_SD# 1 2 1 Q9 FCM1608KF-1-GP 6
MMBT3904-7-F-GP MIC_IN_R_JK 3
L2
10KR2J-3-GP (R) MIC_IN_JD 4

2
MIC_R_JACK 1 2 5

1
PC_AUDIO_R (R) FCM1608KF-1-GP C4 (R)
30 PC_AUDIO_R

SC100P50V2JN-3GP
PC_AUDIO_L NP1
30 PC_AUDIO_L
D4 D3 NP2

2
1

1
47 PC_AUDIO_R_C PC_AUDIO_R_C C2 C3 (R) (R)

SC100P50V2JN-3GP

SC100P50V2JN-3GP
47 PC_AUDIO_L_C PC_AUDIO_L_C AUDIO-JK132-GP
AUD_AGND AUD_AGND

MLVG04025R0QV05BP-GP

MLVG04025R0QV05BP-GP
2

2
AUD_AGND D5
AUD_AGND AUD_AGND
AUD_AGND AUD_AGND 2 MIC_L_JACK

3
Speaker Out (35/36) Placement Near Scalar 1 MIC_R_JACK
1225 AUD_AGND
C572
PC_AUDIO_R 2 R605 1 PC_AUDIO_R_1 2 1 PC_AUDIO_R_C AZ2025-02S-GP
0R0402-PAD
SC22U6D3V5MX-2GP
/ĨƵƐĞ͗ϴϯ͘ϬϮϬϮϱ͘Ϭϭ
ŶĞĂƌĐŽĚĞĐ
B B

SB 1209
C571
PC_AUDIO_L 2 R604 1 PC_AUDIO_L_1 1 2 PC_AUDIO_L_C
0R0402-PAD
SC22U6D3V5MX-2GP
ŶĞĂƌĐŽĚĞĐ
1223
1225

SB 1209

1223

SC 1226

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

AUDIO HP_JK/ MIC_JK


Size Document Number Rev
A3
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 32 of 59

5 4 3 2 1
5 4 3 2 1

3D3V_S5
SuperIO Power-Save
SuperIO power monitoring inputs
Fan Controller 3D3V_S0
CPU_FAN_TACH1 BT_PWR_EN R759 1 /ŶƐƚĂůůEͲDŽƐĂŶĚƵƌƌĞŶƚͲ>ŝŵŝƚ Please set R value depend on what you need.
34 CPU_FAN_TACH1 2 10KR2J-3-GP
CPU_FAN_PWM1
34 CPU_FAN_PWM1 ZĞƐŝƐƚŽƌǁŚĞŶŝŶ^ϱĨŽƌƉŽǁĞƌͲƐĂǀŝŶŐ͘

1
SYS_FAN_TACH1 5V_S0
34 SYS_FAN_TACH1
34 SYS_FAN_PWM1 SYS_FAN_PWM1 3D3V_S0 SIO_PSON_N R787 1 2 10KR2J-3-GP L37
FCM1608KFG-301T05-GP R771
SIO_VIN1 1 2
SRN10KJ-6-GP
WůĞĂƐĞĐŚĞĐŬŝƚΖƐƉƵůůͲŚŝŐŚůŽĐĂƚŝŽŶ

1
RN44 (R) 3D3V_EUP 6K8R2F-2-GP

2
LPC interface LPC_LAD3 1 8 AVCC3 C743 R766
LPC_LAD2 2 7 SCD1U16V2ZY-2GP 10KR2F-2-GP

1
14,34 LPC_LFRAME# LPC_LFRAME# LPC_LAD1 3 6 RSMRST#_SIO R782 1 2 4K7R2J-2-GP

D
14,34 LPC_LAD0 LPC_LAD0 LPC_LAD0 4 5

2
2

1
14,34 LPC_LAD1 LPC_LAD1 Q70
D 2N7002-11-GP D
14,34 LPC_LAD2 LPC_LAD2 C724 C712 1D5V_S3
LPC_LAD3 SRN10KJ-5-GP SIO_PSON_N G SCD1U16V2ZY-2GP SC22U6D3V5MX-2GP SIO_GND
14,34 LPC_LAD3 R767

2
KBRCIN# LPC_LFRAME# 2 3
19 KBRCIN#
KA20GATE KBRCIN# 1 4 LPC_PME_N R785 1 (R) 2 4K7R2J-2-GP SIO_VIN4 1 2
19 KA20GATE

S
18 CLK_PCI_SIO CLK_PCI_SIO
PLT_RST# RN43
5,18,27,28 PLT_RST#

2
INT_SERIRQ R789 10KR2F-2-GP
14 INT_SERIRQ
INT_SERIRQ 2 R756 1 SIO_PWRLED_N 1 2 4K7R2J-2-GP R760 C741
1KR2J-1-GP 330R3J-L-GP SCD1U16V2ZY-2GP

1
KA20GATE 2 R762 1 R784

2
(R) SIO_PWNBTN_N 1 2 4K7R2J-2-GP
15 PCH_CLK48 PCH_CLK48 1KR2J-1-GP SIO_GND
PWRGD3V_150MS 2 R799 1 1D05V_S0
RSMRST#_SIO
16 RSMRST#_SIO R775
1KR2J-1-GP KA20GATE G28

1
SIO_PSON_N SIO_VIN5 1 2HM_V_1P1 2 1
35,44,47 SIO_PSON_N
MINIPCIE_RST# 2 R45 1 R1052

2
PWRGD3V_150MS 680R2J-3-GP GAP-CLOSE-PWR
16,36 PWRGD3V_150MS 10KR2F-2-GP
1KR2J-1-GP C747
SIO_PWRLED_N SCD1U16V2ZY-2GP
26 SIO_PWRLED_N [-1] 0406

1
SIO_PWNBTN_N 3D3V_S0
16 SIO_PWNBTN_N 1226 (SC) AVCC3
0126 (1A)
R764
26 PWRBTN_N PWRBTN_N RN45 SIO_VIN1 SIO_GND VCC_CORE
1 8 RTS1_N 1 2
VTT_PWRGD 5,35,39 R776
LPC_PME_N 2 7 SOUT1 SIO_VIN4 G29
18 LPC_PME_N
5V_S0 3 6 DTR1_N SIO_VIN5 SIO_VIN6 1 2HM_V_CPU 2 1
PM_SLP_S3# RI1_N SIO_VIN6 0R0402-PAD
16,35,43 PM_SLP_S3# RN46 4 5

2
HWM_REF GAP-CLOSE-PWR
10KR2F-2-GP

ATXPG
16,25,38 PM_SLP_S4# PM_SLP_S4# SIO_MCLK 1 8 SRN10KJ-6-GP GPU_DPLUS C754
SIO_MDAT 2 7 SCD1U16V2ZY-2GP

1
CORE_PWRGD SIO_KCLK 3 6 HWM_REF
16,36,42,43 CORE_PWRGD SIO_KDAT 4 5 SIO_SIN1 GPU_DPLUS
47 SIO_SIN1

2
GPU_DPLUS

1
52 GPU_DPLUS GPU_DMINUS C756 C772 SIO_GND
SRN2K2J-2-GP

SC2200P50V3KX-LL-GP
52 GPU_DMINUS
[-1] 0317

1
PLT_RST_ATI# SC1U16V3ZY-GP

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
C C

2
51,52 PLT_RST_ATI#
U43 GPU_DMINUS
1228 (SC)

RI1#
DCD1#
DTR1#
SIN1
SOUT1
DSR1#
RTS1#

ATXPG/VIN3
VIN4
VIN5
VIN6

TMPIN1
GNDD
AVCC3
VIN1/VCC

VREF
SIO_GND
SOUT1
47 SOUT1 SuperIO power monitoring inputs
SIO_SIN1
[-1] 0317 3D3V_S5
47 SIO_SIN1
1 48 SYS_TEMP_HDD
CTS1# TMPIN2 GPU_DMINUS
2 47
CPU_FAN_TACH1 3VSB TSD-
34 CPU_FAN_TACH1 3 46 SIO_GND
FAN_TAC1 GNDA
2

34 CPU_FAN_PWM1 CPU_FAN_PWM1 4 45 RSMRST#_SIO


C713 SYS_FAN_TACH1 FAN_CTL1 RSMRST#/CIRRX1/GP55 PLT_RST_ATI#
34 SYS_FAN_TACH1 5
FAN_TAC2/GP52 PCIRST3#/GP10
44 0126 (1A)
SCD1U16V2ZY-2GP

34 SYS_FAN_PWM1 SYS_FAN_PWM1 6 43 SIO_MCLK


1

FAN_CTL2/GP51 MCLK/GP56 SIO_MDAT


7 42
[-1] 0402 SIO_EUP_EN
PC_SYNC_INT#_R
8
GNDD
5VSB_CTRL
64-LQFP MDAT/GP57
KCLK/GP60
41 SIO_KCLK
SIO_KDAT
9 40
BT_PWR_EN GP21 KDAT/GP61 SIO_PWRLED_N
26 BT_PWR_EN 10 39
GP20 3VSBSW#/GP40

PCHSM_C/PECI/AMDTSI_C
R1030 3D3V_S5 SIO_IRTX 11 38 PWRGD3V_150MS
TPAD28 TP53 PC_SYNC_INT#_R MINIPCIE_RST# CIRTX1 PWRGD3_150MS PM_SLP_S4#
2 1 29 MINIPCIE_RST# 12 37
PCIRST2#/GP11 SUSC#/GP53 SIO_PSON_N

PCHSM_D/AMDTSI_D
13 36
0R2J-2-GP 3VSB PSON#/GP42 PWRBTN_N HWM_REF
14 35 PWRBTN_N 26
2

(R) C740 PLT_RST# VCORE PANSHW#/GP43 LPC_PME_N


15 34
LRESET PME#/GP54

1
SCD1U16V2ZY-2GP

INT_SERIRQ 16 33 SIO_PWNBTN_N
2

SERIRQ PWRON#/GP44 R783


1

SYS_3VSB
SCD022U16V2KX-3-LL-GP G30 (R) 7K68R2F-GP

LFRAME#
C709

PCICLK
1 2 SC 1216_Eric

SUSB#
KRST#
1

CLKIN
GNDD

VBAT
3VSB
GA20
LAD0
LAD1
LAD2
LAD3
SB 1201

2
GAP-CLOSE-PWR SYS_TEMP_HDD TP14 TPAD28
TP38 TPAD28
IT8758E-GP 17 Near Together
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SIO_GND

If without use these pins, Please pull-up. Don't let it floating


If not use PECI, pin 27 28 could be SIO_GND
1.Pin 54:VIN3/ATXPG confiqured as SMBus. Placement Near Venting Hole
2.Pin 32:SUSB# R1049 RTC_AUX_S5 3D3V_EUP
3.Pin 23/ Pin 58/ Pin 60/ Pin 62 LPC_LFRAME# PM_SLP_S3# 4K7R2J-2-GP SYS_TEMP_HDD 1 R235 2 SYS_TEMP_VENTING
4.Pin55 need 2.8V LPC_LAD0 3VSB_DET 1 2 0R0402-PAD

3
B B
LPC_LAD1

1
LPC_LAD2 3D3V_S5 C761 1

1
LPC_LAD3 C746 C751 SC2200P50V3KX-LL-GP Q22
[-1] 0317 SB 1201

SC1U16V3ZY-GP
Note:use EUP function:Pin32/Pin33/Pin34/Pin37/Pin39/Pin45 pull high to SYS_3VSB. KBRCIN# SCD1U16V2ZY-2GP

2
KA20GATE PMBS3904-1-GP

2
CLK_PCI_SIO Layout Note: GPU_DMINUS 1 R238 2 SYS_TEMP_VENTING_G
PCH_CLK48 The trace between IT8758(Pin25) & oscillator 0R0402-PAD
[-1] 0401 (output) must Thicken and Shorten. In addition to
SIO_SDA1 that, the trace spacing must broaden.
15 SIO_SDA1
SIO_SCL1 1225
15 SIO_SCL1
R1026
[-1] 0401 CAP close to ITE8758
1 2 R1027
1 2
0R0805-PAD
0R0805-PAD
R744 1 2 0R5J-5-GP
(R) R752 1 2 0R5J-5-GP
(R)
Q65 3D3V_EUP
5V_S5 AO3413-GP 5V_EUP Q64
3D3V_S5 AO3413-GP 3D3V_EUP
EuP Controller signal S D

1
EuP Controller signal S D
R794
47KR2J-2-GP PWRGD3V_150MS
G
1

(R)
G
1

R757 5V_EUP_M 3D3V_EUP_M

2
1

3
100KR2J-1-GP C706 R753
1
SC1U10V3ZY-6GP

S D 100KR2J-1-GP C701 S D PM_SLP_S3#_2 1 Q72


SC1U10V3ZY-6GP

3D3V_S5 PMBS3904-1-GP
2

Q92 Q90 (R)


SC 1226
2

2
3
AO3413-GP AO3413-GP R778
G

R755 (R) (R) PM_SLP_S3# 2PM_SLP_S3#_1 1 Q71


SC 1226 16,35,43 PM_SLP_S3# 1
1

5V_EUP_EN# 1 2 5V_EUP_EN#_G R751 PMBS3904-1-GP


R947 3V_EUP_EN# 1 2 3V_EUP_EN#_G 10KR2J-3-GP (R)

2
A 10KR2J-3-GP 10KR2J-3-GP (R) A
5V_EUP 5V_EUP_M 10KR2J-3-GP 3D3V_EUP 3D3V_EUP_M
D

R1029
1

Q66 C704
SB 1210 SB 1210
D
2

2N7002-11-GP 2 R1028 1 Q68 C702 2 1


(R) 2N7002-11-GP
<Core Design>
2

SIO_EUP_EN G SC1U10V3ZY-6GP 0R5J-5-GP


2

SIO_EUP_EN SC1U10V3ZY-6GP 0R5J-5-GP


G
(R)
Wistron Corporation
S

5VSB_CTRL(EUP control) 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
High : Enable (default) SC 1226 Title
LOW : Disable (EUP Enable] SIO ITE8758
SC 1226 Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 33 of 59
5 4 3 2 1
5 4 3 2 1

CPU FAN MXM_SYS FAN


5V_S0
3D3V_S0 3D3V_S0 5V_S0

2
CPUFAN1 4K7R2J-2-GP SYSFAN1
R292 1 R485 1
4K7R2J-2-GP
2 2

1
R288 3 R486 3
1 2 4 3D3V_S0 1 2 4
33 CPU_FAN_PWM1 33 SYS_FAN_PWM1 3D3V_S0
100R2J-2-GP 100R2J-2-GP

1
JWT-CON4-S10-GP JWT-CON4-S10-GP

1
D D
(21.61143.104) (21.61143.104)

2
R295
ϭ͘ϱŵŵƉŝƚĐŚ

SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

2
4K7R2J-2-GP R487

C206

C500
4K7R2J-2-GP
D13

2
D19

2
K A CPU_FAN_TACH1 33
K A SYS_FAN_TACH1 33
1N4148W-1-GP
1N4148W-1-GP

LPC DEBUG PORT LIGHT BAR CONTROL 5V_S5

LIGHTBAR1
R952 1

LIGHT_BAR_PWR
2 1LIGHT_BAR_PWR_R 2

33R5J-2-GP JWT-CON2-S5-GP

DEBUGH1
3D3V_S0 2 1 CLK_PCI_PORT80
CLK_PCI_PORT80 18

D
4 3 PCI_RST#
PCI_RST# 18
6 5 LPC_LAD0 Q48
LPC_LAD0 14,33
8 7 LPC_LAD1 2N7002-11-GP
LPC_LAD1 14,33
C 10 9 LPC_LAD2 48 LIGHT_BAR_ON# LIGHT_BAR_ON# G C
LPC_LAD2 14,33
12 11 LPC_LAD3
LPC_LAD3 14,33
14 13 LPC_LFRAME#
LPC_LFRAME# 14,33

S
1
DVD-CONN14D-S7-GP
R948
10KR2J-3-GP

Pin height 2.3mm

2
USB RESERVE ODD REJECTION
1226 (SC)

USBDEBUG1 3D3V_EUP_M
1 VCC5_USB

2 USBPN10 18

1
3 USBPP10 18
4 R542
100KR2J-1-GP
B B
JWT-CON4-S10-GP
R533

2
(21.61143.104) ODDREJ1
1 2 ODD_REJECT_IN#_1 1
48 ODD_REJECT_IN#
SB 1206

1
2
C523 100R2F-L1-GP-U ODD_LED_EN#_P1 3

SC1U16V3KX-2GP
4

2
JWT-CON4-S10-GP
(21.61143.104)

ODD_LED_EN#1 3D3V_S0

2
2 R904 1 1 PMBS3906-GP
14 ODD_LED_EN# Q80
1

1KR2J-1-GP C935
3

R906
ODD_LED_EN#_P 1 2
2
SC4D7U10V5ZY-3-LL-GP

100R3J-4-GP
A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Fan control
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 34 of 59
5 4 3 2 1
5 4 3 2 1

5V_S0 5V_S5

Run Power 5A
1
2
S
S
U34
D
D
8
7
3 S D 6
G D
2nd = 84.00610.C31 4 5
D +12V_S0 Q32
NDS0610-NL-GP RUN_POW ER_ON AO4468-GP
D
84.04468.037
1 2 Z_12V S D 2nd = 84.04800.D37
R334 10KR2J-3-GP

K
1

1
1 C317
84.S0610.B31R343 R337 D14

G
3D3V_S0

10KR2J-3-GP

SCD22U25V3KX-GP

330KR2J-L1-GP
PDZ9D1B-GP 3D3V_S5
2 83.9R103.C3F U15
2 1 Z_12V_G3 2ND = 83.9R103.F3F 1 S D 8

A
R335 330KR2J-L1-GP 2 S D 7

1
3 S D 6
R338 4 G D 5
100KR2J-1-GP 6.5A
AO4468-GP
Z_12V_D4 84.04468.037

2
2nd = 84.04800.D37
Q33
4 3
Z_12V_D3

1D05V_S0 1D05V_LAN
5 2 U41
PM_SLP_S3# 16,33,43 S D
1 8
6 1 2 S D 7
3 S D 6
G D
2N7002KDW -GP 1221 (SC) 4 5

84.2N702.A3F AO4468-GP
C 84.04468.037
2nd = 84.04800.D37
C

[-1] 0319
U39
1D5V_S0 AO3400A-GP 1D5V_S3

S D
1.65A
1221 (SC)

G
MXM Thermal protect circuit

D17
1 VTT_PW RGD 5,33,39

42,52 GPU_THRM# 2 (S)

BAT54-7-F-GP

B B

Reserved for Discharge


5V_S0 3D3V_S0
1

DY DY
R544 R30
100R5J-3-GP (R) 100R5J-3-GP (R)
2

2
3D3V_RUNPWR
5V_RUNPWR

Q49 Q4
A A
D

2N7002-11-GP 2N7002-11-GP <Core Design>


DY DY
(R)
(R) G SIO_PSON_N G SIO_PSON_N
SIO_PSON_N 33,44,47
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
S

Title

Run Power
Size Document Number Rev
A3
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 35 of 59
A B C D E

5V_S5
VCC_CORE
R142
DCBATOUT DCBATOUT_62883
R227
1 2 VCC5B_ADP3212
1 2
HCB2012KF-800T80-GP 10R3F-GP C613
1225 5V_S5

SC1U10V2KX-1GP
R228

1
(R)

7K32R2F-GP

ST330U2D5VDM-17GP

ST330U2D5VDM-17GP

ST330U2D5VDM-17GP

ST330U2D5VDM-17GP

ST330U2D5VDM-17GP

ST330U2D5VDM-17GP
1
1 2 7 PM_DPRSLPVR R184 1 2 0R0402-PAD

1
HCB2012KF-800T80-GP R130 (R)
R657 DCBATOUT_62883
SB 1203 TC20 TC7 TC8 TC6 TC5 TC9
R229

2
(R) 7 PSI# R180 1 2 0R0402-PAD 0R0402-PAD

2
1 2
HCB2012KF-800T80-GP 7 H_VID[6..0] C173 C170 C163

1
SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP
1

5
6
7
8
3212_PVCC

0R2J-2-GP

D
D
D
D
4 4
Q21

2
3212_AGND R134 SIR474DP-T1-GE3-GP
Panasonic

1
C122

SCD01U25V2KX-3GP
2
3D3V_S0 SC4D7U10V5ZY-3-LL-GP ESR = 4.5m-ohm

3212_DPRSLPVR

G
S
S
S
3212_TTSNS_NTC

2
2009/10/06 C103

4
3
2
1
1
C120 R680

NTC-220K-2-GP

2
L9

3212_PSI
SCD33U10V3KX-3GP 10R2J-2-GP

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6
RT1 1 2 1 2 1 2
Q19
3212_BST1_1 Q20 SIR840DP-GP

2
IND-D36UH-19-GP

5
6
7
8

5
6
7
8
R188 SIR840DP-GP

3KR2J-2-GP

D
D
D
D

D
D
D
D
(74.03212.D73)

48

47

46

45

44

43

42

41

40

39

38

37
3KR2J-2-GP

1R3J-L1-GP
R143 U8

2
3212_AGND R137

VID0

VID1

VID2

VID3

VID4

VID5

VID6

PSI#

PH0

PH1

VCC
DPRSLP
G22
SB 1201

2
3212_TTSNS GAP-CLOSE-PWR

S
S
S

S
S
S
G

G
1225

1
16,33 PWRGD3V_150MS R140 1 2 0R0402-PAD 3212_EN 1 36 3212_BST1

4
3
2
1

4
3
2
1
EN BST1
2 35 3212_DRVH1 3212_DRVL1
16,42,43 CORE_PWRGD PWRGD DRVH1
3 34 3212_SW1
7 IMVP_IMON IMON SW1 R186
4 33 3212_SWFB1 1 2100R2F-L1-GP-U 3212_SWFB1_1
3 VR_CLKEN# CLKEN# SWFB1
3212_FBRTN 5 32 3212_PVCC DCBATOUT_62883
FBRTN PVCC
C101 1 2 SC150P50V2JN-3GP 3212_FB 6 31 3212_DRVL1
FB DRVL1 C139 C136 C131
SC18P50V2JN-1-GP

1
3212_COMP 7 ADP3212MNR2G-3-GP 30

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP
COMP PGND

5
6
7
8
R136

D
D
D
D
1 23212_TREDT# 8 29 3212_DRVL2

2
TREDT# DRVL2
1

5V_S5 R187
3212_COMP_1

C588 5K1R2F-2-GP 9 28 3212_SWFB2


1 2100R2F-L1-GP-U
VARFREQ SWFB2
2

3 R638 10 27 3212_SW2 3
VRTT SW2

G
S
S
S
1K65R2F-GP
C587 R642 11 26 3212_DRVH2

4
3
2
1
TTSNS DRVH2 Q24 R706
2 1 1 2 1 2

SCD33U10V3KX-3GP
L10
12 25 3212_BST2 SIR474DP-T1-GE3-GP 10R2J-2-GP
SC220P50V2KX-3-LL-GP
34K8R2F-1-GP GND BST2
1 2 1 2

CSCOMP
R189

CSSUM
1221 (SC)

SWFB3
CSREF

PWM3

2
RAMP
3212_VCCSENSE_1

LLINE

OD3#
Q26

IREF

1R3J-L1-GP
RPM

GND
SCD1U10V2KX-4GP

ILIM

5
6
7
8

5
6
7
8
C590 SIR840DP-GP IND-D36UH-19-GP

RT
SB 1203
1

D
D
D
D

D
D
D
D
Q25

1
2

R645 3212_AGND SIR840DP-GP

C121
3212_RPM
13

14

15

3212_RAMP 16

3212_LLINE 17

3212_CSREF18

3212_CSSUM19

20

21

3212_OD3# 22

3212_PWM3 23

3212_SWFB324

49
3212_CSCOMP
5K49R2F-GP

1
3212_BST2_1
1

2
3212_ILIM
3212_RT
1 80K6R2F-GP 3212_IREF
2
1

S
S
S

S
S
S
G

G
R218 G23
[-1] 0317 100R2F-L1-GP-U 3212_AGND R181 GAP-CLOSE-PWR

4
3
2
1

4
3
2
1
1 2100R2F-L1-GP-U

1
3212_DRVL2
1 140KR2F-1-GP
1 48D7KR2F-GP

7 VSS_SENSE 1 R135 2 2009/10/06

1SC1U10V2KX-1GP
2

0R0402-PAD 1 562KR2F-GP
C95
1 R129 SC1KP50V2KX-1GP
3212_VRTT

2
2
1

7 VCC_SENSE 0R0402-PAD
3212_SWFB2_1
SB 1203

2KR2F-3-GP
R214

1
100R2F-L1-GP-U 3212_AGND 3212_SWFB3_1 DCBATOUT_62883

R177
2

3212_BST3_1
5V_S5 C214 C193 C189

SCD33U10V3KX-3GP
2

1
VCC_CORE

1R3J-L1-GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP
2

5
6
7
8
R154

R153

R157

C115

D
D
D
D
R162

G25

SC270P50V2KX-1GP

SC1200P50V2KX-1GP

2
5 H_PROCHOT#

R299
C280 GAP-CLOSE-PWR

NTC-220K-2-GP
1

1
SC4D7U10V5ZY-3-LL-GP

75KR2F-GP

1
1

1
(R)
D

1
R132 C118 C117 R174 RT2

C228
2
U11

G
S
S
S
0R0603-PAD Q17 2 3212_BST3

2
3212_RAMP_1

1 2 2N7002-11-GP 3212_AGND

4
3
2
1
2 2
G 1 10 Q27 R682
IN BST L13
2 9 3212_DRVH3 SIR474DP-T1-GE3-GP 10R2J-2-GP
DCBATOUT_62883 SD# DRVH
1 23212_CSSUM_1 3 8 3212_SW3 1 2 1 2
S

3212_AGND DRVLSD# SW
4 7
R169 CROWBAR GND
SB 1203 5 6
1

5
6
7
8

5
6
7
8
R161 143KR2F-GP VCC DRVL IND-D36UH-19-GP

D
D
D
D

D
D
D
D
0R2J-2-GP Q29 Q28
1 2 R655 ADP3611JRMZ-REEL-1-GP SIR840DP-GP SIR840DP-GP
3212_AGND 0R0402-PAD 3212_DRVL3
SB 1203
2
SC1KP50V2KX-1GP

S
S
S

S
S
S
G

G
R191 1 2 160KR3F-GP
1

4
3
2
1

4
3
2
1
C112
R190 1 2 160KR3F-GP 3212_DRVL3
2

R185 1 2 160KR3F-GP
1D05V_VTT SB 1201
3212_AGND
1

1D05V_VTT
RN61
R160 R171 R176 R179 R183
1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP H_VID0 1 8
(R) (R) (R) (R) H_VID1 2 7
H_VID2 3 6
2

H_VID0 H_VID3 4 5
H_VID1
H_VID2
H_VID3 SRN1KJ-4-GP
H_VID4
RN62
H_VID5
H_VID6 3212_PSI 1 8
3212_PSI H_VID6 2 7
3212_DPRSLPVR H_VID5 3 6 1D05V_VTT
1 H_VID4 4 5 1
1

R147 R150 R155 R172 R182 SRN1KJ-4-GP


1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP
<Core Design>
(R) (R) (R) (R) (R)
1226 (SC)
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_VCORE
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 36 of 59
A B C D E
5 4 3 2 1

D D

DCBATOUT DCBATOUT_51125_1

R547
1 2 HCB2012KF-800T80-GP

+3VSB/+5VSB R561
1 (R) 2 HCB2012KF-800T80-GP DCBATOUT

R555
1 (R) 2 HCB2012KF-800T80-GP
84.04468.037 AO4468

1
DCBATOUT_51125_1
84.04468.037 AO4468 Vgs @ 4.5V,
Vgs @ 4.5V, 1225
R507 Id = 10A,
2D2R5J-1-GP
Id = 10A, DCBATOUT_51125_1 Rds(on) = 17.4~22mohm,

2
Rds(on) = 17.4~22mohm,
1225 Qg = 9~12nC
V_19_3_5V_VIN
Qg = 9~12nC
1

1
C542 C516 C515

1
C503 C541 C540 C517
SCD01U50V2KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP
SCD1U50V3KX-GP SCD01U50V2KX-1GP
SB 1203
2

D 8
D 7
D 6
D 5

5
6
7
8

SC10U25V6KX-1GP

SC10U25V6KX-1GP
SB 1203

2
D
D
D
D
Q50 Q51
SI4128DY-T1-GE3-GP SI4128DY-T1-GE3-GP

16
U30

VIN

G
S
S
S
C489 SCD1U50V3KX-GP R489 R529 C518

1 S
2 S
3 S
4 G
2D2R5J-1-GP 2D2R5J-1-GP SCD1U50V3KX-GP

4
3
2
1
Iomax=4A 1 2 8205A_BOOT2_R 1 2 8205A_BOOT2 9 22 8205A_BOOT1 1 2 8205A_BOOT1_R 1 2 Iomax=8.5A
3D3V_S5 3D3V_PWR BOOT2 BOOT1 5V_PWR 5V_S5
R458 8205A_UGATE2_R R541 1 2 2D2R5J-1-GP 8205A_UGATE2 10 21 8205A_UGATE1 R538 1 2 2D2R5J-1-GP 8205A_UGATE1_R R590
0R0603-PAD L28 UGATE2 UGATE1 L30 C557 0R0603-PAD
C 1 2 1 2 8205A_PHASE2 11 20 8205A_PHASE1 1 2 SC1U10V3ZY-6GP 1 2 C
IND-3D3UH-135-GP PHASE2 PHASE1 IND-3D3UH-135-GP R589
R462 8205A_LGATE2_R R503 1 2 0R0805-PAD 8205A_LGATE2 12 19 8205A_LGATE1 R570 1 2 8205A_LGATE1_R 0R0603-PAD
1

1
0R0603-PAD C437 TC14 LGATE2 LGATE1 0R0805-PAD TC18 1 2
D 8
D 7
D 6
D 5
SC1U10V3ZY-6GP

1 2 ST220U6D3VDM-20GP ST220U6D3VDM-20GP R583

5
6
7
8
Q46 8205A_VO2 7 24 8205A_VO1 G34 0R0603-PAD
2

2
1

1
D
D
D
D
R467 SI4712DY-T1-GE3-GP VO2 VO1 Q56
SB 1203 1 2

GAP-CLOSE-PWR-3-GP
0R0603-PAD G31 8205A_FB2 8205A_FB1 SI4712DY-T1-GE3-GP R580
1 2
5
FB2 FB1
2 SB 1203 0R0603-PAD
SB 1209
GAP-CLOSE-PWR-3-GP

R502 1 2 820KR2F-GP (R) 1 2


2

2
R499 1 2 100KR2J-1-GP 8205A_EN 8205A_PGOOD R592
S
S
S
G

DCBATOUT_51125_1 13 23
EN PGOOD

G
S
S
S
0R0603-PAD
SB 1209
1
2
3
4

8205A_ENTIP2 6 1 8205A_ENTIP1 1 2

4
3
2
1
ENTRIP2 ENTRIP1 R593
8205A_VREF 3 15 0R0603-PAD
8205A_VREF VREF PGND
1 2
C505 SCD22U6D3V2KX-1GP 8205A_TONSEL 4 25 R594
TONSEL GND 0R0603-PAD
2 1
1 2
8205A_SKIPSEL 14 18 R595
R511 1 SKIPSEL NC#18
+3VL 2 0R2J-2-GP 0R0603-PAD
1

(R) 1 2

VREG3

VREG5
1

Close to VFB 8205A_VREF R509 1 2 0R2J-2-GP

1
R497
Pin (pin5) Close to VFB

1
R496 0R2J-2-GP R508 1 2 0R2J-2-GP (R)
6K65R2F-GP (R) (R) RT8205AGQW-GP R531 Pin (pin2)
2

17
8205A_FB2_R 0R2J-2-GP R525
2

+3VL R915 1 2 0R2J-2-GP 30KR2F-GP

2
1

C495 8205A_FB1_R

2
SC18P50V2JN-1-GP 8205A_VREF R917 1 2 0R2J-2-GP
(R) (R)
2

1
R911 1 2 0R2J-2-GP C522
(R) SC18P50V2JN-1-GP
1

(R)
G9

2
R504 G8 1 2 3D3V_AUX_8205A 5V_AUX_8205A 1 2
+3VL +5VL

1
10KR2F-2-GP GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
2

1
C484 C507 R532
SC10U10V5ZY-1GP SC10U10V5ZY-1GP 20KR2F-L-GP

2
B B

3D3V_S0
GND VREF VREG3 VREG5
OCP

1
8205A_ENTIP1 R524 1 2 249KR2F-GP
R526
SKIPSEL PWM SKIP 00A AUTOSKIP 00A AUTOSKIP 10KR2F-2-GP
1225
8205A_ENTIP2 R491 1 2 150KR2F-L-GP

2
8205A_PGOOD 1 R527 2 ALL_PWRGD 16,38,39,40,43
TONSEL 200k/CH1 330k/CH1 400k/CH1 400k/CH1 SB 1203 0R0402-PAD
250k/CH2 375k/CH2 500k/CH2 500k/CH2

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8205A_3V&5V
Size Document Number Rev
A2
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 37 of 59
5 4 3 2 1
5 4 3 2 1

DCBATOUT

DCBATOUT_51117

+1.5V_S3 C292 R328 2 1 HCB2012KF-800T80-GP


SCD1U50V3KX-GP
R329 2 1 HCB2012KF-800T80-GP
Q31
SIR474DP-T1-GE3-GP (R)

1
C315

5
6
7
8
5V_S5 SC10U25V6KX-1GP

D
D
D
D

2
C246
SC1U16V3KX-2GP 8209A_1D5UGATE R743 1 2 1.5V_UG12
2D2R5J-1-GP
D D
C314

G
S
S
S
SC10U25V6KX-1GP
R311 1 2 249KR2F-GP

4
3
2
1
1

1
R735
R727 2D2R5J-1-GP C666 +1.5V_PWR 1D5V_S3

2
2D2R3J-2-GP U40 RT8209AGQW-GP SCD1U50V3KX-GP
8209A_1D5TON 16 13 8209A_1D5BOOT 1 2 1D5BOOT_1 2 1

2
TON BOOT 8209A_1D5UGATE
12
UGATE 8209A_1D5PHASE L15
9 11 1 2 IND-1D5UH-52-GP R740 1 2 0R0805-PAD
8209A_1D5VDD VDDP PHASE 8209A_1D5LGATE
2 8
VDD LGATE R739 1
7 2 0R0805-PAD
PGND

1
C667

1
SC1U16V3KX-2GP 8209A_1D5_PGOOD 4 3 8209A_1D5FB R310 1 210KR2F-2-GP Q30 C705 C707 R734 1 2 0R0805-PAD
PGOOD FB

5
6
7
8
2 8209A_1D5CS 10 1 8209A_1D5VOUT SIR840DP-GP R300 TC22 TC23

NC#17

D
D
D
D
CS VOUT

SCD1U16V2ZY-2GP

ST330U2D5VDM-9GP

ST330U2D5VDM-9GP
SC10U25V6KX-1GP
14 2D2R6J-3-GP R741 1 2 0R0805-PAD

GND

2
1
NC#14 C278 (R) R728 G5
15 5
EN/DEM NC#5 SCD1U16V2KX-3GP 1.5V_LG12 GAP-CLOSE-PWR R742 1
2 1 2 0R0805-PAD

2
1
2 1

1D5V_PWR_EN

6
17
R308 0R0805-PAD R746 1 2 0R0805-PAD

11D5V_LX1_SNB

2
S
S
S
G
18KR2F-GP C275

2
(R) R750 1 2 0R0805-PAD
SB 1203

4
3
2
1
1
SCD1U16V2KX-3GP
1225 R307 C276

2
10KR2F-2-GP (R) R733 1 2 0R0805-PAD

SCD1U16V2KX-3GP
2
16,37,39,40,43 ALL_PWRGD 2 R726 1

1
0R0402-PAD
C266 1.5V
SC1500P50V3KX-GP
Imax=15A

2
16,25,33 PM_SLP_S4# PM_SLP_S4# R312 1 2 1KR2J-1-GP
Vout=1.5V

1
C283
SCD1U16V2KX-3GP
(R) Vout = 0.75*(1+R_Top/R_GND)

C 2 C

+0.75V_MEM_VTT

1D5V_S3 U37

1 9 5V_S5
VIN GND
2 8
1

1
C589 C596 GND NC#8
3 7
REFEN NC#7
4 6
VOUT VCNTL
SC10U10V5ZY-1GP 5
2

1
NC#5 C577
SCD1U16V2KX-3-LL-GP

SCD1U16V2ZY-2GP
B B

2
1D5V_S3 RT9045GSP-GP

Iout=1A
1

DDR_VREF_PWR
1KR2F-3-GP 0D75_S0
R644
1225
2

0R0805-PAD 2 1 R632
12,13 DDRVTT_REF_R 2 R637 1 DDRVTT_REF
0R0402-PAD

1
C582 C580 C578 C576
1

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
2

2
R641
1KR2F-3-GP
2

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

+1.5V/+0.75V
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 38 of 59
5 4 3 2 1
5 4 3 2 1

DCBATOUT

DCBATOUT_7138_1D05V_VTT

+1.05V(V_1D05_VTT) C53
SCD1U50V3KX-GP
R75 2 1 HCB2012KF-800T80-GP

R79 2 1 HCB2012KF-800T80-GP
(R)
D D
Q11

5
6
7
8

1
SIR474DP-T1-GE3-GP C65

D
D
D
D
5V_S5 SC10U25V6KX-1GP

2
8209A_1D1UGATE R86 1 2 1.1V_UG12
2D2R5J-1-GP

G
S
S
S
C63 C66
SC10U25V6KX-1GP

4
3
2
1
SC1U10V3ZY-6GP
R626 1 2 249KR2F-GP

2
1
R88
R630 2D2R5J-1-GP C60 1.1V +1.05VS_VTT_PWR 1D05V_VTT
2D2R3J-2-GP U6 RT8209AGQW-GP SCD1U50V3KX-GP
8209A_1D1TON 16 13 8209A_1D1BOOT 1 2 1D1BOOT_1 2 1 Imax=13A

2
TON BOOT 8209A_1D1UGATE
12
UGATE 8209A_1D1PHASE L7 1
9
VDDP PHASE
11 2 IND-1D5UH-52-GP R193 1 2 0R0805-PAD
8209A_1D1VDD 2 8 8209A_1D1LGATE
VDD LGATE R194 1
PGND 7 2 0R0805-PAD

1
C575 Q15

1
SC1U10V3ZY-6GP 4 3 8209A_1D1FB R101 1 2 4K7R2F-GP SIR840DP-GP C124 C109 TC3 TC4 R195 1 2 0R0805-PAD
PGOOD FB

5
6
7
8

ST330U2D5VDM-9GP

ST330U2D5VDM-9GP
8209A_1D1CS 10 1 8209A_1D1VOUT R117

NC#17
2
CS VOUT

D
D
D
D

SCD1U16V2ZY-2GP

SC10U25V6KX-1GP
14 2D2R6J-3-GP R196 1 2 0R0805-PAD

GND

2
NC#14

1
15 5 C74 R93 G21
EN/DEM NC#5 SCD1U16V2KX-3GP 2 1 1.1V_LG12 GAP-CLOSE-PWR R197 1 2 0R0805-PAD

2
1
2 1 0R0805-PAD

6
17
R82 (R) R198 1 2 0R0805-PAD

8209A_1D1EN

2
11.1V_LX1_SNB
S
S
S
12KR2F-L-GP

G
SB 1203

4
3
2
1
1
R99 R192 1 2 0R0805-PAD

2
11K5R2F-GP (R)

2
C75

2
5,33,35 VTT_PWRGD VTT_PWRGD SCD1U16V2KX-3GP C76

2
(R) SCD1U16V2KX-3GP
SB 1203 C87
SC1500P50V3KX-GP

2
Vout=1.1V
Vout = 0.75*(1+R_Top/R_GND)

1
1225
R97 1 2 0R0402-PAD C68
16,37,38,40,43 ALL_PWRGD
SCD1U16V2KX-3GP

2
(R) R104
(R)
1 2
Clarksfield H_VTTVID1 = Low, VTT = 1.1V
0R2J-2-GP Arrandale H_VTTVID1 = High, VTT = 1.05V

1
R100
C 75KR2F-GP C

2
7 VTT_SENSE 5V_S0
VID_SEL

1
R95
10KR2J-3-GP

2
Q14
2N7002-11-GP G VTT5
Q13A 6

2
C71 MMBT3904DW-GP

1
SCD033U16V2KX-GP R92 (R) 2 VTT3 4K7R2J-2-GP 1 2 R85 VTT_PWRGD VTT_PWRGD 5,33,35
(R) 0R0402-PAD (R)

2
1

1
5V_S0
VTT4

1
R78
10KR2J-3-GP
(R)

2
Q10 1 VTT2 1KR2J-1-GP 1 2 R81 H_VTTVID1 H_VTTVID1 7
PMBS3904-1-GP

2
Q13B 3
MMBT3904DW-GP
(R) 5VTT1 1KR2J-1-GP 1 2 R87
(R)

1
4
R90
0R2J-2-GP
(R)

2
B B

DCBATOUT

DCBATOUT_8209A

+1.05V(V_1D05_PCH) C728
SCD1U50V3KX-GP
R772 2 1 HCB2012KF-800T80-GP

R768 2 1 HCB2012KF-800T80-GP
(R)

SB 1203

1
C342
5
6
7
8
5V_S5 SC10U25V6KX-1GP
D
D
D
D
Q36

2
8209A_1D05UGATE R777 1 2 1.05V_UG12 SI4128DY-T1-GE3-GP
2D2R5J-1-GP
1

C830 C752
G
S
S
S

SC10U25V6KX-1GP
SC1U10V3ZY-6GP

R440 1 2 249KR2F-GP
2

4
3
2
1
1

R423
R816 2D2R5J-1-GP C407 1.05V 1D05V_PWR 1D05V_LAN
2D2R3J-2-GP U23 RT8209AGQW-GP SCD1U50V3KX-GP
8209A_1D05TON 16 13 8209A_1D05BOOT 1 2 1D05BOOT_1 2 1 Imax=7A, OCP>10.5A
2

TON BOOT 8209A_1D05UGATE


UGATE 12
9 11 8209A_1D05PHASE L20 1 2 R331 1 2 0R0805-PAD
8209A_1D05VDD VDDP PHASE 8209A_1D05LGATE IND-1D5UH-53-GP
2 VDD LGATE 8
7 R332 1 2 0R0805-PAD
PGND
1

C863
1

1
SC1U10V3ZY-6GP 8209A_1D05PGOOD 4 3 8209A_1D05FB R442 1 2 4K7R2F-GP SI4712DY-T1-GE3-GP C318 C322 TC13 R333 1 2 0R0805-PAD
PGOOD FB
5
6
7
8

8209A_1D05CS 10 1 8209A_1D05VOUT R392


NC#17
2

CS VOUT
D
D
D
D

SCD1U16V2ZY-2GP

SC10U25V6KX-1GP

ST330U2D5VDM-9GP
14 Q37 2D2R6J-3-GP R330 1 2 0R0805-PAD
GND

2
NC#14 C433 R422 G6
1
15 EN/DEM NC#5 5
SCD1U16V2KX-3GP 2 1 1.05V_LG12 GAP-CLOSE-PWR
2
1

1225 2 1 0R0805-PAD
8209A_1D05EN

6
17

R418 (R)
SB 1203
11.05V_LX1_SNB

2
G
S
S
S

16,37,38,40,43 ALL_PWRGD 2 R438 1 11K5R2F-GP


1

0R0402-PAD
4
3
2
1
1

3D3V_EUP R444
2

A 11K5R2F-GP (R) A
2

C430
0126 (1A)
2
1

SCD1U16V2KX-3GP C435
SB 1209
2

R905 (R) SCD1U16V2KX-3GP


10KR2J-3-GP
SB 1203 C389
SC1500P50V3KX-GP
2

Vout=1.05V
2

16,27 PM_SLP_LAN# PM_SLP_LAN# 1 2


R437 1KR2J-1-GP
Vout = 0.75*(1+R_Top/R_GND)
1

C419
<Core Design>
SCD1U16V2KX-3GP
2

(R)
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

V_1P1_VTT/ V_1P05_PCH
Size Document Number Rev
Custom
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 39 of 59
5 4 3 2 1
5 4 3 2 1

1D8V_S0 (RT9025)
3D3V_S5

5V_S5 R651 1D8V_S0


(R) 0R0805-PAD

1
D C611 C607 D
1 2
SC10U10V5KX-2GP SC10U10V5KX-2GP

1
R653

2
1225 C616 0R0805-PAD
SC1U16V3KX-2GP 1 2

2
R656
0R0805-PAD
1 2
+1.8V_LDO
Vo(cal.)=1.8069V R658
0R0805-PAD

9
U38 1 2

GND
4 5 (R)
VDD NC#5

1
3 6 C606 (R)
9025_EN_1D8 VIN VOUT
2 R650 1 2 EN ADJ 7 R654 C615 C614
44 1589_PGOOD

SC100P50V2JN-3GP
0R0402-PAD 1 8 18KR2J-GP

2
PGOOD GND

SC10U10V5KX-2GP

SC10U10V5KX-2GP
(R)

2
1
C604 RT9025-25PSP-GP
SCD1U25V3KX-GP 74.09025.03D 9025_ADJ_1D8

1
C C
R652
R649 14K3R2F-GP
1 2 9025_PGOOD_1D8
16,37,38,39,43 ALL_PWRGD
0R0402-PAD

2
Vo=0.8*((R1+R2)/R2)
SC 1226 1225

B B

<Core Design>

A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number


1D8V POWER Rev
B
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 40 of 59
5 4 3 2 1
A B C D E

62881_AGND

SCD1U16V2KX-3-LL-GP 1225

2
C90
R113
4K7R2J-2-GP 2 1 R1005 1 2 0R0402-PAD GFX_VID6
R1004 1 2 0R0402-PAD GFX_VID5
R1003 1 2 0R0402-PAD GFX_VID4 GFX_VID[6..0] 8

1
1225

8 GFX_VR_EN R116 1 2 0R0402-PAD

R115 1 2 0R0402-PAD R1009 1 2 0R0402-PAD GFX_VID3 DCBATOUT DCBATOUT_62881


8 GFX_DPRSLPVR
R1008 1 2 0R0402-PAD GFX_VID2
R1007 1 2 0R0402-PAD GFX_VID1 R73

62881_DPRSLPVR
1
4 4
R1006 1 2 0R0402-PAD GFX_VID0 HCB2012KF-800T80-GP 1 2

62881_VR_ON
R114

62881_VID6

62881_VID5

62881_VID4

62881_VID3

62881_VID2

62881_VID1

62881_VID0
3D3V_S0 4K7R2J-2-GP
DCBATOUT_62881 R74
5V_S0 HCB2012KF-800T80-GP 1 2

2
(R)

2
R121 R120
10KR2F-2-GP 62881_AGND (74.62881.A73) 0R0402-PAD

28

27

26

25

24

23

22
U7 1225

/ŵĂdžсϭϮ

VID6

VID5

VID4

VID3

VID2
DPRSLPVR

VR_ON
2

C92 C58 C57 C56

1
SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP
SC1U10V2KX-1GP

5
6
7
8
1225
KWхϭϴ

D
D
D
D
62881_AGND R119 1 20R2J-2-GP 62881_CLK_EN# 1 21 Q12

2
CLK_EN# VID1 SIR474DP-T1-GE3-GP
62881_PGOOD 2 20 2009/10/09

1
PGOOD VID0
R122 1 2 47KR2F-GP 62881_RBIAS 3 19 62881_VCCP VCC_GFXCORE
RBIAS VCCP

G
S
S
S
R635
8K06R2F-GP 62881_VW 4 ISL62881HRZ-T-GP 18 62881_LGATE 1 R98 2VGX_UG1

4
3
2
1
VW LGATE
SC1KP50V2KX-1GP

0R0805-PAD
C583 62881_COMP 5 17 L8
1

COMP VSSP
1

62881_FB 6 16 62881_PHASE 1 2
(R) FB PHASE
R634 7 15 62881_UGATE Q16 2009/10/09
2

VSEN UGATE IND-D88UH-3-GP

5
6
7
8
0R2J-2-GP 62881_VSEN SIR840DP-GP
2

1
D
D
D
D
ISUM+

BOOT
ISUM-

IMON
1 2 2009/10/09 29 (R) R94

VDD
RTN

1
GND

VIN
C93 2D2R6J-3-GP
C585 2009/10/09 R123 SC470P50V2JN-GP C111

1
2009/10/09 SC22P50V2JN-4GP 4K02R2F-GP SCD1U10V2KX-4GP

62881_BOOT
8

62881_ISUM- 9

62881_ISUM+10

62881_VDD 11

12

13

14

2
S
S
S
G
C98 TC25 TC2
R118

ST330U2D5VDM-9GP

ST330U2D5VDM-9GP
62881_VSEN_1 1 R133 SCD22U16V3KX-2-GP 62881_SN

62881_RTN
1 2 1 2 2 SB 1210

62881_VIN

4
3
2
1

2
62881_AGND 1 2 2D2R2F-GP (R)

1
R640 0R0402-PAD
C73
SC1500P50V3KX-GP
DELETE!!
3 1 262881_BOOT_1 3
820KR2F-GP

2
C584 4K32R2F-GP 2009/10/09
GFX_IMON 8

1
1 2 62881_FB_1 1 2 R125 1 2

1
R647
62881_AGND 26K1R2F-2-GP C595
SC100P50V2JN-3GP SCD015U25V2KX-GP
SB 1210

2
2
62881_AGND DCBATOUT_62881

1
1 2
R643 0R2J-2-GP G19 G20
1

C96 5V_S5 GAP-CLOSE-PWR GAP-CLOSE-PWR


SC330P50V2KX-3GP 1 2

2
R646 1R2F-GP
2

8 VCC_AXG_SENSE R127 1 2 0R0402-PAD C594


1

1
SC1U10V2KX-1GP
2

C597
1225 C97 SCD22U16V3KX-2-LL-GP
2

SC330P50V2KX-3GP
1

8 VSS_AXG_SENSE R141 1 2 0R0402-PAD


62881_AGND 62881_AGND
1

C100 C105 SCD15U10V2KX-GP R144 1 2 62881_ISUM+_4


SCD22U10V2KX-1GP

SC1KP50V2KX-1GP
1

1
2009/10/09
2

2KR3F-L-GP
1

R128 R138 R139 C104 R149

1
10R3F-GP 10R3F-GP 82D5R2F-1-GP (R) 2K61R2F-1-GP
62881_AGND 1 G2 G3
SCD01U25V2KX-3GP

R145 GAP-CLOSE-PWR GAP-CLOSE-PWR


2

2
1

C107 62881_ISUM+_2 11KR2F-L-GP

2
62881_ISUM+_1 62881_ISUM+_3
2

1
2

2
1

SCD047U16V2KX-1-GP

C102 R152 R158


2009/10/09 0R2J-2-GP NTC-10K-9-GP
2

1 2 62881_ISUM-_4
1

2 2
R146
3K48R2F-GP C108
SCD1U50V3KX-LL-GP
2

62881_AGND

VSS_AXG_SENSE_OUTCAP

VCC_AXG_SENSE_OUTCAP

1 1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GFX_Vcore
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 41 of 59
A B C D E
A B C D E

VDDC_PWR VDDC
R350
5V_S0 0R0603-PAD
For GPU Core and GPIO15/20 relationship as below: 1 2
DCBATOUT DCBATOUT_62872_VGA_CORE R349

1
0R0603-PAD
VID1(GPIO20) VID0(GPIO15) Core R389
(S) 2D2R3J-2-GP R396 1 (S) HCB2012KF-800T80-GP
1
R348
2
2
0 0 1.22V 0R0603-PAD
1 2

2
0 1 1.02V R403 1 (R) 2 HCB2012KF-800T80-GP R346
0R0603-PAD
1 0 1.12V 1 2
C362 C365 R410 1 (R) 2 HCB2012KF-800T80-GP R347
1 1 0.92V

SC1U16V3KX-2GP

SCD1U10V2KX-4GP
0R0603-PAD
1 2

1
(S) (S) R363
4 4
0R0603-PAD
2009/10/09 DCBATOUT_62872_VGA_CORE 1 2

2
C367 R365
SC1U16V3KX-2GP 0R0603-PAD
(S) 1 2
1 2 R359
C371 C359 C357 0R0603-PAD

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP
1 2

1
(S) (S) (S)
DY R431(R) 62872_AGND
35,52 GPU_THRM# 1 2 SB 1209

2
0R2J-2-GP

5
6
7
8

5
6
7
8
D
D
D
D

D
D
D
D
62872_LGATE

R397
2G7
GAP-CLOSE-PWR
(S)
Q35
(R)
Q88
Ϭ͘ϵsΕϭ͘ϮsΛϮϬ
(R) 2 SIR474DP-T1-GE3-GP SIR474DP-T1-GE3-GP
KWхϯϬ

62872_VCC
16,36,43 CORE_PWRGD 1

62872_BOOT_1
0R2J-2-GP

20
1

G
S
S
S

G
S
S
S
DY U20
VDDC_PWR

PVCC
LGATE
1

4
3
2
1

4
3
2
1
R384 C366
2 19 2R3J-GP (S) SCD22U25V3KX-GP
62872_AGND PGND VCC 62872_BOOT (S) 62872_UGATE
3 18 1 2

2
L19

1
62872_EN GND BOOT 62872_UGATE
4 17
AMD_GPIO20 5 EN UGATE 62872_PHASE (S)
16 1 2
AMD_GPIO15 6 VID1 PHASE
62872_SREF 7 VID0 NC#15
15
62872_OCSET
SB 1209 IND-D56UH-22-GP
VGA power sequence modify!! 14

5
6
7
8

5
6
7
8
62872_SET0 8 SREF OCSET 62872_VO
13
SET0 VO

D
D
D
D

D
D
D
D
PGOOD
62872_SET1 9 12 62872_FB
1

SET1 FB (S) (S)

SET2
C396 R406 Q34 Q87 2009/10/09
R399
1

1
SCD068U10V2KX-1GP

DIS (S) (S) 32K4R2F-1-GP SIR840DP-GP SIR840DP-GP (S) C319 (S) TC12 (S) TC11

ST330U2D5VDM-9GP

ST330U2D5VDM-9GP
3D3V_VGA 1 (S) 2 ISL62872HRUZ-T-GP
10

11

S
S
S

S
S
S
(S)

G
2

2
4
3
2
1

4
3
2
1
1

10KR2J-3-GP 62872_PGOOD
62872_SET2

SCD1U16V2KX-3-LL-GP
3D3V_VGA
3 C377 62872_LGATE 3
1

(R) 2009/10/09
2

1
SCD1U25V3KX-GP R413
(S) 26K7R2F-GP R411 R394 1 (S) 2 6K19R2F-GP

2
(S) 10KR2J-3-GP C381(S)
62872_AGND
SB 1201 1 2 G26
2

GAP-CLOSE-PWR
2

DGPU_PWROK 19,43,58 R398 1 (S) 2 6K19R2F-GP

1
1

SCD1U50V3KX-LL-GP
R409
(S) 22K1R2F-L-GP 1 262872_FB_1 1 (S) 2

3D3V_VGA
SB 1201 C402 (S) R405
2

SC1200P50V2KX-1GP 100R2F-L1-GP-U
2009/10/09
4
3

RN47 2009/10/09
SRN10KJ-5-GP R415 R412
(S) 249KR2F-GP 30K9R2F-GP
1 (S) 2 1 (S) 2 1 (S) 2 62872_FB_2
1
2

R404
SB 1201 SB 1201 24K9R2F-L-GP
[Park]R412=30.9k
AMD_GPIO15
62872_AGND [Madison]R412=28k
52 AMD_GPIO15

52 AMD_GPIO20 AMD_GPIO20
1
1

R1051 R1050
10KR2J-3-GP 10KR2J-3-GP
2
2

2 2
[-1] 0317

1 1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

MXM_GFX_Vcore
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 42 of 59
A B C D E
A B C D E

AO4468, SO-8
Id=11.6A, Qg=9~12nC
3D3V_S0 to 3D3V_DELAY Transfer 1D5V_S3
Rdson=17.4~22m ohm
+1.5V_REG
DIS
(S) U16
8 D S 1
7 D S 2
6 D S 3 DIS (S) DIS

1
5 D G 4 C508 TC15

1
C320 (S)
R430

SCD1U16V2KX-3GP
SC10U6D3V3MX-GP DIS AO4468-GP (S) ST330U2D5VDM-9GP

2
1 2 84.04468.037

2
0R5J-5-GP (R)
4 4
Q40
3D3V_VGA AO3413-GP 3D3V_S0 RUN_POWER_ON

D S Q47 (S)
84.03413.A31
S D RUNON_R
(S)

G
DIS NDS0610-NL-GP
R439 84.S0610.B31

G
2ND = 84.00610.C31
1 (S) 2 R514
1 (S) 2 DIS_EN_1D5_RUN_R

1
100KR2J-1-GP 330KR2J-L1-GP
DIS R919 DIS R530
100KR2J-1-GP 100KR2J-1-GP DIS (S) 330KR2J-L1-GP

3
(S)
16,36,42 CORE_PWRGD 1 R435 2 1

2
(R) Q42 (S) 3D3V_VGA
1

(S)

2
C425 PMBS3904-1-GP DIS_EN_1D5_RUN

1
SCD01U16V2KX-3GP
2

100KR2J-1-GP (S) R925

D
10KR2J-3-GP (S)
16,37,38,39,40 ALL_PWRGD 1 R447 2 Q81
(R) R926 2N7002-11-GP

2
19,42,58 DGPU_PWROK DGPU_PWROK 1 (R) 2DGPU_PWROK_R G 84.27002.W31
0R2J-2-GP 2ND = 84.27002.N31
100KR2J-1-GP DIS

S
DIS

1
16,33,35 PM_SLP_S3# 1 R443 2 R924 (R)
(S) CORE_PWRGD 1 (R) 2 C949
16,36,42 CORE_PWRGD 0R2J-2-GP
0126 (1A) DY

2
DY SCD1U10V2KX-4GP

3 3

Iout=1.5A sŽƵƚсϭsͺs'
1D5V_S3
5V_S5
1.0V_REG 3D3V_VGA
C304
SC1U10V3ZY-6GP
1

1
C316 1 R747 3D3V_VGA
DIS SC10U10V5ZY-1GP DIS DIS
(S) 2K2R2J-2-GP
0126 (1A)
2

1
(S) (S)
2

U13 R749

2
DIS R352 9025_PGOOD_1V 10KR2J-3-GP
0R0805-PAD 5 (R)
(S) 1V_VGA_OUT VIN#5 DY
2 1 4 6

2
VOUT#4 VCNTL R748
3 7
R351 VOUT#3 POK
1 DIS 2 1V_VGA_FB 2 8 1V_VGA_EN 1 (R) 2 DGPU_PWROK 19,42,58
0R0805-PAD R354 (S) 4K7R2F-GP FB EN 0R2J-2-GP
1 9 1D5V_S3
GND VIN#9
2 1
1

DIS (S) DIS


APL5930KAI-TRG-GP C703 R745
SCD022U16V2KX-3GP
2 1 DIS (S) (S) 2 (R) 1
2

0R2J-2-GP CORE_PWRGD 16,36,42


1

C321 DY
Vo=0.8*(1+(R1/R2))
1

C324
SC10U6D3V3MX-GP SCD01U16V2KX-3GP R345
2

DIS 18K7R2F-GP
(R)
2009/08/14 (S) (S) DIS
2

2 2

1226 (SC)

3D3V_S0
1D8V_VGA
5V_S0
(R) (RT9025)
1

C269 C270
SC10U10V5KX-2GP SC10U10V5KX-2GP
1

(S) 1.8V_REG
2

(S) C285
SC1U16V3KX-2GP
2

(S) R342
0R0805-PAD
1226 (SC) 1 2
1D8V_LDO_VGA
Vo(cal.)=1.8069V R341
R303 0R0805-PAD
9

9025_PGOOD_1V 1 2 9025_EN_VGA U12 (S) 1 2


(S)
GND

0R0402-PAD-1-GP (R) 4 5 (R)


1

C268 VDD NC#5 C306 (S) (R)


3 6
R306 SCD1U25V3KX-GP VIN VOUT R327 C308 C305
2 7
EN ADJ
SC100P50V2JN-3GP

1 CORE_PWRGD 1 (R) 2 1 8 (S) 18KR2J-GP 1


2

16,36,42 CORE_PWRGD PGOOD GND


SC10U10V5KX-2GP

SC10U10V5KX-2GP

0R2J-2-GP
DY
2

3D3V_VGA RT9025-25PSP-GP
74.09025.03D 9025_ADJ_VGA
<Core Design>
1

R302 R326
(R) 10KR2J-3-GP (S) 14K3R2F-GP Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2

TPAD28 TP10 1D8V_S0_VGA_PG 1 (R) 2 9025_PGOOD_VGA Title

R304
Vo=0.8*((R1+R2)/R2) 1.8V_REG/1V_PCIE
0R2J-2-GP Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 43 of 59
A B C D E
DCBATOUT DCBATOUT_1589

HCB2012KF-800T80-GP R528
1226 (SC) 1 2
12V_PW R +12V_S0
HCB2012KF-800T80-GP 1 (R) 2 R539
G16
5V_EUP 1 2
DCBATOUT_1589
GAP-CLOSE-PW R

3D3V_S0
G15

A
1
SB 1210 1 2

1
R567 D21 (R)
R965 2D2R5J-1-GP RB751V-40-2-GP C520 C519 GAP-CLOSE-PW R (R)

1
10KR2J-3-GP SC10U25V6KX-1GP SC10U25V6KX-1GP C556

2
G14 SC10U25V6KX-1GP

1589_BT1 K
1 2

2
1
1589_PGOOD C543 GAP-CLOSE-PW R
40 1589_PGOOD
SC1U16V3KX-2GP

1589_VCC

1
R552
U35 2D2R3J-2-GP
SB 1203 Design Current = 4.2A
1589_FB 8 6

2
1589_VOS FB VCC U33 12V_PW R
9 VOS

1
1589_PGOOD 10 PGOOD
R554 1 S1 D1 8
L29
1 1589_BOOT C535 1 2SCD1U50V3KX-GP 10KR2J-3-GP
BOOT
1

LX 2 1589_LX 1589_LG12 2 G1 D1 7 1 2
1

R550 R548 (R) 3 1589_UG


158R2F-GP C534 UG 1589_LG 1589_LG12 IND-10UH-197-GP
2K21R2F-GP 5 4 2 1

2
GND LG
SCD01U16V2KX-3GP 11 7 1589_COMP R559 1589_LX 3 S2 D2 6
2

GND COMP/EN#

1
0R0805-PAD
2

2 1 1589_UG1 4 G2 D2 5 R543 TC19


NCP1589AMNTW G-GP-U R558 2D2R6J-3-GP E100U16VM-32-GP
SB 1203

2
1
2D2R5J-1-GP

1589_LX1_SNB
R562 SI4214DDY-GP

2
R564 20KR2F-L-GP
3K3R2F-2-GP
SB 1203 DCBATOUT_1589
C538 1 2 SCD22U16V3KX-2-GP 1589_CP1 1 2

1
C539 1 2 SC1KP-GP
SB 1203 R546

1
10R3F-GP

1
C531 C537
SCD1U50V3KX-GP

2
2
SC1500P50V3KX-GP

C536 SCD01U16V2KX-3GP R549


75R2F-2-GP
1 2 1589_FB1 1 2
R553
1 2 12V_PW R_SENSE

2K21R2F-GP
R1
1

R557 Vout=0.8*(R1+R2)/R2
158R2F-GP CWH
D
2

Q53
33,35,47 SIO_PSON_N G 2N7002-11-GP
S

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
+12V
Size Document Number Rev
Custom
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 44 of 59
5 4 3 2 1

Adaptor in to generate DCBATOUT


ĚĚĂůƚĞƌŶĂƚĞϴϰ͘ϬϭϰϬϯ͘ϯϳ
DCBATOUT
AD_JK
D

U42
AD_JK 1 S D 8

1
2 S D 7 C718

SCD01U50V2ZY-1GP
3 S D 6 SCD1U50V3ZY-GP

K
C710 AD+_2 4 G D 5 (R)
DC in

2
1

1
D16 (R)

SC1U50V5ZY-1-GP
C373 P4SMA24A-GP
DY AO4433-GP

1
SCD1U50V3KX-LL-GP R763 U44

C727
100KR2J-1-GP
1 S D 8

1
S D
2
3 S D
7
6
11A,11mohm <14mohm
AD+_2 4 G D 5
Vgs=-20 , 14mohm <18

2
AO4433-GP
(R) mohm Vgs=-10

1
R770

C 56KR3F-GP

2
B

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C.
A
Title

DC IN
Size Document Number Rev
A4
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 45 of 59
5 4 3 2 1

Mini PCIE holder


D

H9 H14 H3 H11 H5
3

2
HOLE HOLE
4 (R) 4 (R) 4 (R)
1 1 1

5 8 5 8 5 8

1
GEN315R158-8-F-A GEN315R158-8-F-A GEN315R158-8-F-A
6

7
C H13 H8 H2
3

2
4 (R) 4 (R) 4 (R)
1 1 1

5 8 5 8 5 8
FAN holder

GEN315R158-8-F-A GEN315R158-8-F-A GEN315R158-8-F-A


6

7
H12 H6 H7 H10
HOLE HOLE HOLE HOLE

1
B H1 H4
HOLE HOLE

1
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C.
A
Title

Screw hole
Size Document Number Rev
A4
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 46 of 59
5 4 3 2 1

VENDER ID Close to U22 3D3V_EUP_M


SC 1226 SRN4K7J-8-GP SB 1202

1 2663_C16

2663_C17
Samsung LED xx 3.3v 3D3V_EUP_M 3D3V_EUP_M

1
LG LED x0 1.1v R982 1 (R) 2 0R2J-2-GP TV_Audio_L TP96 3D3V_EUP_M (R)
SC 1226 3D3V_EUP_M 2 3

1
LG CCFL 0x 1.65v TPAD28 C934 R886
GPIO FUNCTION 1 4

TV_Audio_R_1
TV_Audio_L_1
Samsung CCFL 00 0.825v R571 R983 1 (R) 2 0R2J-2-GP TV_Audio_R TP95 SC1U10V3ZY-6GP 4K7R2J-2-GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

RTD2663_HDMI_SDA
20KR2J-L2-GP TPAD28 C904 C914 C906

RTD2663_HDMI_SCL
0126 (1A) RN52 1 2

1
3D3V_EUP_M

C452

C462
LCDVDD_EN VCM_BB
SC 1216_Eric

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
LCDVDD_EN 48

2
R579 2 R894 1

2
BL_PWM LCD_ID_0 Panel_SEL AV_AUDIO_R

RTD2663_HPD_SINK
BL_PWM 48 1 2 SB 1209

1
AV_AUDIO_L AMP_OUT_L 10KR2J-3-GP

SDA_SINK
SCL_SINK
BL_ON 1 2 10KR2J-3-GP PC_AUDIO_R_C AMP_OUT_R C459 C455 DELETE!!

HCK+

HD0+

HD1+

HD2+
BL_ON 48

HCK-

HD0-

HD1-

HD2-

SDA_CTL
SCL_CTL
PC_AUDIO_L_C BB3_3V SC1U16V3KX-2GP 1225

2
SCD1U16V2ZY-2GP
COM_Disable# C408 SCD1U16V2ZY-2GP LCD_ID_1 1 R578 2 D1_2V
COM_Disable# 19

1
1 2 20KR2J-L2-GP R993
R980 R981
BB3_3V
1 0R0402-PAD
2 /ϮͺĚĚƌсϬƚƌůZĞŐ͗ϵϰͬϵϱ͕/^ŚĂĚŽǁ͗ϵϲͬϵϳ
C444 SCD1U16V2ZY-2GP RTD2663_HDMI_SDA
1 2
0R2J-2-GP 0R2J-2-GP
RTD2663_HDMI_SCL 3D3V_EUP_M
1
R994
2
/ϮͺĚĚƌсϭƚƌůZĞŐ͗ϰͬϱ͕/^ŚĂĚŽǁ͗ϲͬϳ
0R0402-PAD

2
R897

HW_TV_RST#
TPA3113_SD# C388 SCD1U16V2ZY-2GP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TPA3113_SD# 32,48 3D3V_EUP_M

2663_C16
2663_C17
D 1 2 1 2 RTD2663_HPD_SINK U52 D
D1_2V
LCD_ID_0 D1_2V

Z1
Y1

Z2
Y2

Z3
Y3

Z4
Y4

SCL_CTL
SDA_CTL
GND

VCC

I2C_ADDR
SDA_SINK
SCL_SINK

HPD_SINK
LCD_ID_0 48 3D3V_EUP_M

TV_IRQ
LCD_ID_1 LCD_ID_1 48 C445 SCD1U16V2ZY-2GP 4K7R2J-2-GP

TOUCH_ID0 TOUCH_ID0 48
1
L24
2 3D3V_EUP_M C394 C438 C449
džƚĞƌŶĂůͺ,D/ͺ/EͺKEE;ϯͿ SB 1208 0126 (1A)
BB3_3V R902

1
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
TPAD24 TP94 1 49 32
POW_SINK POWDN

129

128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
SCD1U16V2ZY-2GP
HDMI_IN_HPD C454 C447 HDMI_IN_HPD 2 1HPD3_O 50 31 2 R874 1
HDMI_IN_HPD 49 SBK160808T-301Y-N-GP U22 HPD3 REXT

4
3
HDMI_IN_SDA 51 30 TMDS_IN2_DATA2+

2
TOUCH_INT# SC2D2U16V3KX-GP RN21 1KR2J-1-GP HDMI_IN_SCL SDA3 A14 TMDS_IN2_DATA2- 499R2F-2-GP
52 29

DDC0_SCL

AIN_2L

AIN_1L

AOUT_L

HPOUT_L

I2C_M0_SCL
V3.3IO

AIN_MONO
AOUT_MONO

G3.3IO
V3.3IO
GND

AIN_2R

AIN_1R

AOUT_R

HPOUT_R
V1.2CORE

DDC0_SDA
V3.3BB
G3.3BB

VCM_BB
G3.3BB

V3.3BB
G1.2CORE
V1.2CORE

I2C_M0_SDA

G1.2CORE
TOUCH_INT# 48 SCL3 B14
SRN4K7J-8-GP HDMI_IN_TXC# 53 28
SIO_PSON_N R907 HDMI_IN_TXC B31 NC#28 TMDS_IN2_DATA1+
SIO_PSON_N 33,35,44 54 27
HDMI_IN1_CON5V R1PWR5V A31 A13 TMDS_IN2_DATA1-
2 1 55 26
L22
RTD2663_HPD_SINK 1 102 HDMI_IN_TXD0# 56
POW3 B13
25 W,ͺdD^ͺ/E;ϭͿ

1
2
CEC V1.2CORE B32 GND

1
34K8R2F-1-GP HDMI_IN_TXD0 TMDS_IN2_DATA0+ 3D3V_EUP_M
I2C FUNCTION 1 2 VD3_3V 2
G3.3TMDS V1.2CORE
101 57
A32 A12
24

1
SBK160808T-301Y-N-GP TV_IRQ HCK- 3 100 BL_ON R569 58 23 TMDS_IN2_DATA0-
C352 HW_TV_RST# HCK+ RXCN0 EJTAG_TMS BL_PWM 10KR2J-3-GP HDMI_IN_TXD1# GND B12
SMB_CLK 15 4 99 59 22
RXCP0 EJTAG_TDO B33 VCC

1
SCD1U16V2ZY-2GP HD0- 5 98 LCDVDD_EN HDMI_IN_TXD1 TMDS_IN2_CLK+
SB 1210 3D3V_EUP_M 60 21

2
SMB_DATA 15 RX0N0 EJTAG_TDI A33 A11
HD0+ 6 97 RF_AGC_OUT 61 20 TMDS_IN2_CLK- C925

2
HD1- RX0P0 EJTAG_TCLK WP_SPI HDMI_IN_TXD2# VCC B11 TMDS_IN2_SCL SC1U10V3ZY-6GP
7 96 SC 1216_Eric 62 19

2
RX1N0 EJTAG_TRST# B34 SCL1

2
YPP3_3V HD1+ 8 95 RTD2663_IRRX HDMI_IN_TXD2 63 18 TMDS_IN2_SDA
RX1P0 IRRX A34 SDA1

1
HD2- 9 94 SCL_CTL R989 1 2 0R0402-PAD TOUCH_SMBCLK C938 64 17
C340 C404 HD2+ RX2N0 I2C_M1_SCL SDA_CTL R990 1 TOUCH_SMBDATA CEXT I2C_RST
Master 10 93 2 0R0402-PAD SC1U10V3ZY-6GP

1
Touch_SMBDATA 29,48 RX2P0 I2C_M1_SDA

2
SC2D2U16V3KX-GP SCD1U16V2ZY-2GP R991 1 R441 2 11 92 VGA_TXBOUT0-

2
Touch_SMBCLK 29,48 HDMI_REXT TEAN

POW2

POW1
HPD2

HPD1
TOUCH_INT# TOUCH_INT_2# VGA_TXBOUT0+ 1225

SDA2
HW TV Card 1KR2F-3-GP C936

SCL2
1 2 12 91

GND

VCC
TMDS3_3V V3.3TMDS TEAP

B21
A21

B22
A22

B23
A23

B24
A24
D1_2V 13 90 VGA_TXBOUT1- SC2D2U10V3KX-1GP

1
0R2J-2-GP V1.2CORE TEBN VGA_TXBOUT1+ 3D3V_EUP_M
AV_IN 14
15
G1.2CORE TEBP
89
88 VGA_TXBOUT2-
IFADC3_3V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
G3.3LSADC TECN
1
10KR2F-2-GP1
10KR2F-2-GP 2R436 16 87 VGA_TXBOUT2+ R1035 3D3V_S0 PS331TQFP64G-GP 3D3V_S0
LSADC_REF TECP R900 R879
AV_CVBS+ C348 Panel_SEL VGA_TXBCLK- BL_ON
AV_CVBS-
AV_CVBS+ 49
SCD1U16V2ZY-2GP
[-1] 0402 SIO_PSON_N
17
18
LSADC0 TECLKN
86
85 VGA_TXBCLK+
1 2
1 2 R2PWR3V R1PWR3V 2 1
2

AV_CVBS- 49 LSADC1 TECLKP

MXM_DDCDATA_TMDS
MXM_UMA_SEL 19 84 VGA_TXBOUT3- 10KR2J-3-GP

ATI_TMDS_CLKN
MXM_DDCCLK_TMDS

ATI_TMDS_CLKP
LSADC2 TEDN VGA_TXBOUT3+ 4K7R2J-2-GP 4K7R2J-2-GP
AUDIO_OUTPUT 20 83

ATI_TMDS_00N

ATI_TMDS_01N

ATI_TMDS_02N
ATI_TMDS_00P

ATI_TMDS_01P

ATI_TMDS_02P
LSADC3_3V V3.3LSADC TEDP R909
VDAC3_3V TOUCH_INT_2# 21 82 R1036
AHS0 G3.3LVDS R846
1

AMP_OUT_R TPA3113_SD# 22 81 3D3V_EUP_M BL_PWM 1 2 MXM_TMDS_HPD 2 1 HPD2_O


AMP_OUT_R 48 AVS0 V3.3LVDS
AMP_OUT_L C349 YPP3_3V 23 80 VGA_TXAOUT0- HPD1_O 2 1 TMDS_IN2_HPD
AMP_OUT_L 48 V3.3YPPADC TOAN
SCD1U16V2ZY-2GP 2663_C0 VGA_TXAOUT0+ (R) 10KR2J-3-GP
24 79 SC 1226
2

3D3V_EUP_M 2663_C1 BIN0N TOAP VGA_TXAOUT1- 1KR2J-1-GP


L21 25 78
2663_C2 BIN0P TOBN VGA_TXAOUT1+ SRN10KJ-5-GP 1KR2J-1-GP
AUDIO_INPUT ,ŝŐŚс'WhKŶŽĂƌĚ 26
GIN0N TOBP
77

1
1 2 PLL3_3V 2663_C3 27 76 VGA_TXAOUT2- LCDVDD_EN 4 1
GIN0P TOCN
1

AV_AUDIO_R AV_AUDIO_R 49 R818 2663_C4 28 75 VGA_TXAOUT2+ TOUCH_INT# 3 2


C AV_AUDIO_L C337 C354 10KR2J-3-GP 2663_C5 RIN0N TOCP VGA_TXACLK- C
AV_AUDIO_L 49 SBK160808T-301Y-N-GP 29 74
SCD1U16V2ZY-2GP (S) 2663_C6 RIN0P TOCLKN VGA_TXACLK+
30 73 RN48
2

PC_AUDIO_R_C SC2D2U16V3KX-GP MXM_UMA_SEL 2663_C7 BIN1N TOCLKP VGA_TXAOUT3-


PC_AUDIO_R_C 32 31 72 1 2

1 2
BIN1P TODN RN51
PC_AUDIO_L_C 2663_C8 32 71 VGA_TXAOUT3+
PC_AUDIO_L_C 32
1
L23
2 R814
2663_C9
2663_C10
33
34
GIN1N
GIN1P
TODP
G1.2CORE
70
69
SCL_CTL
SDA_CTL
1
2
4
3 Dy/ŽŶůLJ d/ͺdD^ͺ/E;ϮͿ C924
SC1U10V3ZY-6GP
TMDS3_3V RIN1N V1.2CORE D1_2V
1
SCD1U16V2ZY-2GP

10KR2J-3-GP 2663_C11 3D3V_EUP_M


RTD2663 LVDS_OUTPUT C423 (U)
35
36
RIN1P V3.3IO
68
67
3D3V_EUP_M
SBK160808T-301Y-N-GP G3.3YPPADC SPI_DO SRN4K7J-8-GP 3D3V_EUP_M 3D3V_EUP_M
37 66
>ŽǁсhD YPP1_2V
2

V1.2YPPADC SPI_DI

SCD1U16V2ZY-2GP
VGA_TXBOUT0-

VDAC_REXT
38 65

G3.3VDADC
3D3V_EUP_M

V3.3VDADC
VGA_TXBOUT0- 48 L38 G1.2CORE SPI_SCK

G3.3IFADC
V3.3IFADC
G3.3VDAC
V1.2CORE
VGA_TXBOUT0+

V3.3VDAC
G3.3APLL
V3.3APLL
VGA_TXBOUT0+ 48

SPI_CS#

1
RF_AGC
G3.3PLL

RESET#
V3.3PLL
VGA_TXBOUT1- 1 2

AVOUT
VGA_TXBOUT1- 48 LSADC3_3V
1

1
VIN2N

VIN1N

VIN0N
VIN2P

VIN1P

VIN0P
+12V_S0

XOUT
VGA_TXBOUT1+ R395 R385 for ESD R445 R461 R380

IF1N
IF1P
VGA_TXBOUT1+ 48

XIN
VGA_TXBOUT2- C834 C413 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP U18 C356 4K7R2J-2-GP
VGA_TXBOUT2- 48 SBK160808T-301Y-N-GP [-1] 0317 protection

1
VGA_TXBOUT2+ SCD1U16V2ZY-2GP (72.25165.A01)
2

2
VGA_TXBOUT2+ 48 1225
VGA_TXBCLK- SC2D2U16V3KX-GP R1033 RTD2663-GP

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

2
VGA_TXBCLK- 48
VGA_TXBCLK+ 10KR2J-3-GP SPI_CS R3761 222R2J-2-GP CS 1 8
VGA_TXBCLK+ 48 CS# VCC
VGA_TXBOUT3- 1 R774 2 SPI_MISOR7611 222R2J-2-GP MISO 2 7
VGA_TXBOUT3- 48 1D2V_S5 84.2N702.A3F DO HOLD#
VGA_TXBOUT3+ D1_2V 0R0402-PAD SPI_MOSIR3901 222R2J-2-GP 3 6 SCK
VGA_TXBOUT3+ 48 L26

2
2N7002KDW-GP SPI_SCKR3821 WP# CLK MOSI
PLL3_3V 1 R388 2 222R2J-2-GP 4 5
GND DIO

2663_C12
2663_C13
2663_C14
2663_C15
ALOG1_2V1 0R0402-PAD C372 1
2 SB 1226 2
SC10U10V5ZY-1GP SC10U10V5ZY-1GP

D1_2V
VGA_TXAOUT0- RTD2663_HDMI_SDA 1 6 SIO_SIN1 1 2 (R) SC10P50V3JN-GP
VGA_TXAOUT0- 48
1

1
C405

VGA_TXAOUT0+ 4K7R2J-2-GP R377 C725 1 W25X16VSSIG-GP

10KR2F-2-GP
VGA_TXAOUT0+ 48 SBK160808T-301Y-N-GP 2

1
VGA_TXAOUT1- C355 R373 BURN_SINK (R) SC10P50V3JN-GP
VGA_TXAOUT1- 48 2 5 SB 1202

R378
VGA_TXAOUT1+ SCD1U16V2ZY-2GP 0R0402-PAD PLL3_3V
2

VGA_TXAOUT1+ 48

3
VGA_TXAOUT2- SOUT1 RTD2663_HDMI_SCL R446

75R2F-2-GP
VGA_TXAOUT2- 48 3 4 VD3_3V

1
VGA_TXAOUT2+ AV_CVBS+ WP_SPI 1 2 1 Q43

2
VGA_TXAOUT2+ 48 L27 PMBS3904-1-GP
VGA_TXACLK- Q93 R374 AV_CVBS- U17 (R)

2
VGA_TXACLK- 48
VGA_TXACLK+ DIG1_2V 1 2K2R2J-2-GP
VGA_TXACLK+ 48 2 YPP1_2V 0126 (1A)

2
VGA_TXAOUT3- XTAL-27MHZ-66-GP X4 1 3D3V_EUP_M
VGA_TXAOUT3- 48 RESET
1

SCD1U16V2ZY-2GP
C363

VGA_TXAOUT3+ 1 2 2

2
VGA_TXAOUT3+ 48 SBK160808T-301Y-N-GP R1032 GND
3

C370
VCC
3 SB 1202

1
SCD1U16V2ZY-2GP BURN_SINK 1 2 1 Q94 C344 C346 TUN_IF-
2

1
PMBS3904-1-GP TUN_IF+ (R)
PCH_TMDS_OUTPUT (Level Shift} 4K7R2J-2-GP STL8110PCH300-GP C332 R370

SC15P50V2JN-2-LL-GP

SC15P50V2JN-2-LL-GP
2

2
IFADC3_3V 4K7R2J-2-GP

2
TMDS_IN2_DATA0-
TMDS_IN2_DATA0+
TMDS_IN2_DATA0- 24 1228 (SC) VDAC3_3V 0126 (1A)

1 2
TMDS_IN2_DATA0+ 24
RESET
TMDS_IN2_DATA1-
TMDS_IN2_DATA1- 24

2663_C11

2663_C12

2663_C13

2663_C14

2663_C15
TMDS_IN2_DATA1+ C343

2663_C0

2663_C1

2663_C2

2663_C4

2663_C5

2663_C6

2663_C7

2663_C9
2663_C3

2663_C8

2663_C10
B TMDS_IN2_DATA1+ 24 B
BURN_SINK 1 2 3D3V_EUP_M SC1U16V3KX-2GP

2
TMDS_IN2_DATA2-
TMDS_IN2_DATA2- 24
TMDS_IN2_DATA2+ R942
TMDS_IN2_DATA2+ 24

C410

C406

C399

C393

C401

C391

C383

C382

C378

C379

C374

C369

C339

C338

C350

C351
10KR2J-3-GP
TMDS_IN2_CLK-
TMDS_IN2_CLK+
TMDS_IN2_CLK- 24 SC 1226 0126 (1A) [-1] 0401 WůĂĐĞŵĞŶƚEĞĂƌZŝƐĞƌ

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP
TMDS_IN2_CLK+ 24

SCD047U10V2KX-2-LL-GP
5V_54331 5V_EUP_M L25 1D2V_PWR 1D2V_S5
SC 1226

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP
SCD1U25V3ZY-1GP

TMDS_IN2_SDA R475 1 2 1 2 HDMI_5V

1
TMDS_IN2_SDA 24 3D3V_EUP_M
TMDS_IN2_SCL 0R0603-PAD IND-4D7UH-173-GP D23
TMDS_IN2_SCL 24
1

1 2 R480 1
K

C456 C448 C497 0R0805-PAD


1

1
SCD1U16V2ZY-2GP

TMDS_IN2_HPD R479 D18 2 HDMI_IN1_CON5V

SCD1U16V2ZY-2GP
TMDS_IN2_HPD 24
2

1
C480

0R0603-PAD U27 SMB_5A


SC47U6D3V6MX-1GP

SC47U6D3V6MX-1GP

ATI_TMDS_OUTPUT 1 2 SBM54PT R951 3


2

1
10KR2J-3-GP

C546
1 8 0126 (1A)
A

BOOT PH

1
1
R556

R560
C547 R563
SC820P50V2KX-1GP

BAT54-7-F-GP
ATI_TMDS_00P
2
VIN GND
7
Kс,ͲхƐŚŽƌƚ SC1KP-GP (R)
348KR2F-GP

ATI_TMDS_00P 52 3 6

2
EN COMP
1

ATI_TMDS_00N C481 C469 U59 (R) 3D3V_S0 R372

4K7R2J-2-GP
4 5
Kс>ͲхŽƉĞŶ

2
ATI_TMDS_00N 52 SS VSENSE
SC10U25V6KX-1GP

SC10U25V6KX-1GP

R494

C485 R505 RF_AGC_OUT TOUCH_ID0

47KR2J-2-GP

47KR2J-2-GP
1 2

2
1

ATI_TMDS_01P 10KR2F-2-GP RTD2663_HDMI_SDA 1 5 3D3V_S0 U36


2

2
2
ATI_TMDS_01P 52 A VCC
1
SCD01U16V2KX-3LLGP

ATI_TMDS_01N TPS54331D-GP SIO_SIN1 2 C521 0R0402-PAD


ATI_TMDS_01N 52 B
1

2
SCD1U16V2ZY-2GP
C492

C496 3 4 (R) 8 1
2

ATI_TMDS_02P GND OE VCC E0


7 2
2

ATI_TMDS_02P 52 WC# E1
1

ATI_TMDS_02N R581 TUN_IF+ HDMI_IN_SCL 6 3


121KR2F-L-GP

2
ATI_TMDS_02N 52 SCL E2
1

C487 NC7SZ66P5X-1GP 4K7R2J-2-GP TUN_IF- HDMI_IN_SDA


SC 1216_Eric 5
SDA VSS
4
1
SCD01U16V2KX-3LLGP

ATI_TMDS_CLKP SC10P50V3JN-LL-GP R506


51K1R2F-GP

1
ATI_TMDS_CLKP 52
R500

C360

C368
ATI_TMDS_CLKN 19K6R2F-GP U60 (R)
ATI_TMDS_CLKN 52

2
M24C02-WMN6TP-GP-U

SCD047U10V2KX-2-LL-GP

SCD047U10V2KX-2-LL-GP
R501

RTD2663_HDMI_SCL 1 5 2N7002-11-GP (R)


2

D
A VCC

1
MXM_DDCCLK_TMDS SOUT1 2 Q91
2

1
MXM_DDCCLK_TMDS 52 B
MXM_DDCDATA_TMDS 3 4 COM_Disable# R568
MXM_DDCDATA_TMDS 52 GND OE (R) 10KR2J-3-GP
[-1] 0401

2
MXM_TMDS_HPD G BURN_SINK
MXM_TMDS_HPD 52 PMBS3906-GP
WP_EDID
NC7SZ66P5X-1GP [-1] 0401 1

2
Q57

S
RTD2663 HDMI_IN (R)

3
HDMI EDID Debug
HDMI_IN_TXD0 &Žƌ,tds SC 1216_Eric 3D3V_EUP_M 5V_EUP_M CN4
HDMI_IN_TXD0 49 JWT-CON4-S10-GP
HDMI_IN_TXD0#
A HDMI_IN_TXD0# 49 A
1

HDMI_IN_TXD1 (R) CN3


HDMI_IN_TXD1 49
HDMI_IN_TXD1# 2663_C14 RTD2663_IRRX R978 1 2 0R2J-2-GP TOUCH_INT# R976 (R) R977 1
2663_C14 29 &ŽƌdsKŶůLJ

4
3
2

1
HDMI_IN_TXD1# 49 100R2J-2-GP
2663_C15 10KR2J-3-GP WP_EDID
HDMI_IN_TXD2
2663_C15 29 [-1] 0401 1 2 TV_IR (R)
SB 1208 2
HDMI_IN_TXD2 49
HDMI_IN_TXD2# HW_TV_RST# TV_IR1 TUN_IF+ 1 TP89 TPAD24 RTD2663_HDMI_SDA
2

HDMI_IN_TXD2# 49 HW_TV_RST# 29 <Core Design>


R979 0R0402-PAD 4 R379 TUN_IF- 1 TP90 TPAD24 RTD2663_HDMI_SCL DVD-CON2-15-GP
HDMI_IN_TXC IR_Header_VCC 1 0R0402-PAD (R)
HDMI_IN_TXC 49
HDMI_IN_TXC# TV_Audio_L TOUCH_SMBCLK 1 2 SCL_tuner 1 TP91 TPAD24 3D3V_EUP_M
HDMI_IN_TXC# 49
TV_Audio_R
TV_Audio_L
TV_Audio_R
29
29 2 TOUCH_SMBDATA 1 2 SDA_tuner 1 TP92 TPAD24 Wistron Corporation
TV_IR 3 R375 RF_AGC_OUT 1 TP93 TPAD24 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
HDMI_IN_SCL 5 0R0402-PAD Taipei Hsien 221, Taiwan, R.O.C.
HDMI_IN_SDA
HDMI_IN_SCL 49
TV_IR
[-1] 0401
HDMI_IN_SDA 49 TV_IR 29
1

C972 C973 MLX-CON3-9-GP Title


SC1U16V3KX-2GP SC47U6D3V6MX-1GP (R)
SIO_SIN1 TV_IRQ (R) (R) Scaler IC
2

33 SIO_SIN1 TV_IRQ 29
Size Document Number Rev
SOUT1 Custom
33 SOUT1 Catalina SA
Date: Tuesday, April 06, 2010 Sheet 47 of 59
5 4 3 2 1
5 4 3 2 1

VGA_TXBOUT0- RUN_POWER_ON 3D3V_EUP 3D3V_S5 3D3V_S5


VGA_TXBOUT0+
VGA_TXBOUT0- 47
VGA_TXBOUT0+ 47 Touch Key

2
VGA_TXBOUT1-
VGA_TXBOUT1- 47 +19V_S5_INV Power

1
VGA_TXBOUT1+ R575
VGA_TXBOUT1+ 47

1
VGA_TXBOUT2- R1024 4K7R2J-2-GP
VGA_TXBOUT2- 47 1228
VGA_TXBOUT2+ 10KR2J-3-GP R576 DCBATOUT G12 +19V_S5_INV
VGA_TXBOUT2+ 47
VGA_TXBCLK- Q86 S 20KR2J-L2-GP 1 2

G
VGA_TXBCLK- 47

1
VGA_TXBCLK+ 3D3V_EUP_M 5V_EUP_M 2N7002-7F-GP INVERTER_EN
VGA_TXBCLK+ 47

2
VGA_TXBOUT3- LVDS1 GAP-CLOSE-PWR-2U-GP
VGA_TXBOUT3- 47

2
VGA_TXBOUT3+ ODD_REJECT_OUT_S# D S 31 G13
ODD_REJECT_OUT# 19

D
VGA_TXBOUT3+ 47

1
C548 5V_S5_LCD 1 1 2
R987 R988 0126 (1A) Q54

SC100P50V2JN-3GP
2N7002-11-GP
VGA_TXAOUT0- 0R0603-PAD 0R0603-PAD 2 GAP-CLOSE-PWR-2U-GP
VGA_TXAOUT0- 47

2
VGA_TXAOUT0+ INVERTER_EN# G 3 G11
VGA_TXAOUT0+ 47
VGA_TXAOUT1- 4 1 2
VGA_TXAOUT1- 47

1
VGA_TXAOUT1+ 5

D
VGA_TXAOUT1+ 47

S
VGA_TXAOUT2- TOUCHBTN1 6 GAP-CLOSE-PWR-2U-GP
VGA_TXAOUT2- 47
D VGA_TXAOUT2+ 5VS5_TOUCH 1 Q55 7 G10 D
VGA_TXAOUT2+ 47 2N7002-11-GP
VGA_TXACLK- VGA_TXBOUT3+ 8 1 2
VGA_TXACLK- 47
VGA_TXACLK+ 2 47 BL_ON G VGA_TXBOUT3- 9
VGA_TXACLK+ 47
VGA_TXAOUT3- Touch_SMBCLK 3 VGA_TXBCLK+ 10 GAP-CLOSE-PWR-2U-GP
VGA_TXAOUT3- 47
VGA_TXAOUT3+ Touch_SMBDATA 4 H: Enable VGA_TXBCLK- 11
VGA_TXAOUT3+ 47 TP15

S
TOUCH_INT# 5 VGA_TXBOUT2+ 12
AMP_OUT_L
AMP_OUT_L 47 1 6 L: Disable VGA_TXBOUT2- 13
AMP_OUT_R ODD_REJECT_IN# 7 14
AMP_OUT_R 47
ODD_REJECT_OUT_S# 8 VGA_TXBOUT1+ 15
TPAD24 LIGHT_BAR_ON# VGA_TXBOUT1-
ODD_REJECT_IN# 3VS5_TOUCH
9
10 DCBATOUT
16
17
INVERTER BOARD CONNECTOR
ODD_REJECT_IN# 34
TOUCH_ID0 11 G27 VGA_TXBOUT0+ 18
ODD_REJECT_OUT# TOUCH_CABLE_DET# 12 5V_S5 1 2 +19V_S5_LOGIC_PWR VGA_TXBOUT0- 19
ODD_REJECT_OUT# 19 +19V_S5_INV
TOUCH_INT# +19V_S5_LOGIC_PWR VGA_TXAOUT3+ 20
GAP-CLOSE-PWR-2U-GP VGA_TXAOUT3- 21
L: Touch any key JWT-CON12-S-GP VGA_TXACLK+ 22

1
-->PCH H: Normal (21.61143.112) VGA_TXACLK- 23

1
24 INV_CN1
R936 R932 5V_S5 VGA_TXAOUT2+ 25 2 1
BT_RESET_IN# BT_RESET_OUT 10KR2J-3-GP 20KR2J-L2-GP U57 5V_S5_LCD VGA_TXAOUT2- 26
TOUCH_CABLE_DET# 1 D D 6 VGA_TXAOUT1+ 27 4 3
TOUCH_CABLE_DET# 19 (Mechical Key] S

2
L: BT_RESET_IN# 2 D D 5 L43 VGA_TXAOUT1- 28 6 5

1
H: BT_RESET 3 G S 4 V_5_LCD1 1 2 VGA_TXAOUT0+ 29 LCD_ID_1 8 7 LCD_ID_0
L: RESET_BT C968 HCB2012KF600-GP VGA_TXAOUT0- 30 INVERTER_EN 10 9 BL_PWM

2
H: Normal SC4D7U10V5ZY-3GP AO6402A-GP 32

2
Main: 84.06402.B3D R931 DVD-CONN10D-S9-GP
Q83 Alt: 84.00655.B3D 330R3J-L-GP PTWO-CON30-3-GP-U
2N7002-11-GP
BL_CTL_OFF R934 G LCD_ENAVDD_GATE1

1
3
10KR2J-3-GP High: Enable 5V_S5_LCD_DOWN
Power ON: High (Default]

1
LCDVDD_EN 1 2 1 Q84 C964
Low: Disable

S
Touch: Low/High/Low... PMBS3904-1-GP SCD1U25V3ZY-1GP

D
TPA3113_SD# High: Enable S
TPA3113_SD# 32,47

2
1
Q82
LIGH_BAR_ON
Low: Disable R933 2N7002-11-GP Odd: channel A
1KR2J-1-GP LCD_ENAVDD_GATE2 G
LIGH BAR Off : High (Default] Even: channel B
BL_ON
BL_ON
Touch: Low/High/Low... Low: Enable
47

S
High: Disable
C
BL_PWM
[-1] 0401 C
BL_PWM 47
LCDVDD_EN
LCDVDD_EN 47

Touch_SMBDATA 29,47
Touch_SMBCLK 29,47
LIGHT_BAR_ON#
LIGHT_BAR_ON# 34 +19V_AMP_PVCC
DCBATOUT
R566
1 2
LCD_ID_0
LCD_ID_0 47
LCD_ID_1 0R0805-PAD
LCD_ID_1 47
TOUCH_ID0
TOUCH_ID0 47 +19V_AMP_AVCC
DCBATOUT
L42
1 2
HP_DET_MUTE#
HP_DET_MUTE# 30
HCB1608KF-181-GP
(R)
TOUCH_INT#
TOUCH_INT# 47 R937
AMP_OUT_L 1 2 0R0402-PAD AMP_SPKR_L
R927
AMP_OUT_R 1 2 0R0402-PAD AMP_SPKR_R
2

R935 R928
4K32R3F-L-GP 4K32R3F-L-GP TPA3113_SD1#
[-1] 0401 (R) (R)
LPF for fc(-3dB)=500Hz
1

2
1225
3113_AGND 3113_AGND C967 R938
SC3900P50V2KX-2GP 0R0402-PAD U56
+19V_AMP_PVCC 29 +19V_AMP_PVCC
GND
1 2
1

TPA3113_SD_L# 1 28 TC16 09.10712.C8L


SD# PVCCL

1
B (R) 09.10712.A9L B
1

C969 TPA3113_FAULT# 2 27 C552 E100U25VM-10-GP 09.10712.D8L


R577 R572 SC1U16V3KX-2GP FAULT# PVCCL SCD1U25V3ZY-1GP Internal Speaker x 2

2
100KR2J-1-GP 100KR2J-1-GP AMP_SPKR_L 2 1 SPKR_IN_L 3 26 TPA3113_BSPL1 2 SPKR_OUT_L+
(R) (R) C965 LINP BSPL SCD22U16V3KX-2-GP C966
2 1 TPA3113_LINN 4 25 SPKPL_TPA3113
2

TPA3113_GAIN0 TPA3113_GAIN1 3113_AGND LINN OUTPL


SC1U16V3KX-2GP TPA3113_GAIN0 L31 (68.00206.121)
5 GAIN0 PGND 24 [-1] 0319
2

SPKR_OUT_L+ 1 2 HCB2012KF-600T30-GP SPKR_L+_C 1


R584 R582 +19V_AMP_AVCC C962 TPA3113_GAIN1 6 23 SPKNL_TPA3113 SPKR_OUT_L- L32 (68.00206.121) SPKR_L-_C 2 SPKL1
0R0402-PAD SCD1U25V3ZY-1GP 3113_AGND GAIN1 OUTNL SPKR_OUT_L+ SPKR_OUT_L- 1 HCB2012KF-600T30-GP JWT-CON2-S11-GP
0R0402-PAD 2
2

7 22 TPA3113_BSNL1 2C963 SPKR_OUT_L- L40 (68.00206.121) SPKR_R+_C 1


1225 AVCC BSNL SCD22U16V3KX-2-GP SPKR_OUT_R+ 1 HCB2012KF-600T30-GP SPKR_R-_C SPKR1
2 2
1

TC17 3113_AGND 8 21 TPA3113_BSNR1 2C961 SPKR_OUT_R- SPKR_OUT_R- L41 JWT-CON2-S11-GP


E100U25VM-10-GP R930 R929 AGND BSNR SCD22U16V3KX-2-GP SPKR_OUT_R+ SPKR_OUT_R- 1 HCB2012KF-600T30-GP
2
SPKNR_TPA3113 (68.00206.121)
1 2 1 2 9 20 SB 1204
2

GVDD OUTNR

1
10KR2F-2-GP 10KR2F-2-GP C544 C950
3113_AGND C960 SC1KP-GP SC1KP-GP
2 1 C956
10 PLIMIT PGND 19 SB 1208
3113_AGND

2
2 1TPA3113_RINN 11 18 SPKPR_TPA3113
SC1U16V3KX-2GP C953 SC1U16V3KX-2GP RINN OUTPR
AMP_SPKR_R 2 1 SPKR_IN_R 12 17 TPA3113_BSPR1 2C955 SPKR_OUT_R+
RINP BSPR

1
SCD22U16V3KX-2-GP 3113_AGND 3113_AGND
SC1U16V3KX-2GP 13 16 +19V_AMP_PVCC C549 C958
NC#13 PVCCR
SHUTDOWN TPA3111D2 SC1KP-GP

2
3113_AGND 14 15 SC1KP-GP
C951 1 PBTL PVCCR
2
1

L ( 0V~0.8V ) SHUTDOWN SC3900P50V2KX-2GP 3D3V_S5


(R) TPA3113D2PWPR-GP C545 HCB2012KF-600T30-GP

2
3113_AGND SCD1U25V3ZY-1GP Z=60 ohm,Rdc=0.04 ohm
2

H ( 2V ~ VDD ) ACTIVE R939 I=3A ,0805


4K7R2J-2-GP
3D3V_S5
SB 1202

1
TPA3113_SD1#
1

GAIN1 GAIN0 GAIN ( dB ) R941 1 (R) 2 0R0402-PAD


R591

D
R940 1 2 0R2J-2-GP SC 1226 20KR2J-L2-GP
0 0 20 (R) Q59
A SB 1210 2N7002-11-GP A
2

TPA3113_SD G
3113_AGND 3D3V_S0 3D3V_EUP_M
1 0 26
S
3

R586
<Core Design>
2

TPA3113_SD# 1 2 1 Q60
R946 10KR2J-3-GP PMBS3904-1-GP
0 1 32 4K7R2J-2-GP
Wistron Corporation
2
G

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


1

R588 Taipei Hsien 221, Taiwan, R.O.C.


1 1 36 HP_DET_MUTE# S D 1 2 1 Q58
10KR2J-3-GP PMBS3904-1-GP Title

PANEL OUTPUT & AMP


2

Q89 Size Document Number Rev


2N7002-11-GP Custom
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 48 of 59
5 4 3 2 1
A B C D E

ZZh^ ϭϵ͘ϱs/E AD_JK


RISER1
AD_JK

18 USBPN2 B1 A1
18 USBPP2
18 USBPN3 B2 A2
18 USBPP3 B3 A3
18 USBPN4 B4 A4
18 USBPP4 B5 A5
18 USBPN9 B6 A6
18 USBPP9 B7 A7
B8 A8
B9 A9
B10 A10 V_3P3_LAN
B11 A11
NP1
4
>E HDMI_OUT_TXD2
HDMI_OUT_TXD2#
B12
B13
A12
A13 LAN_MDI3_DN
LAN_MDI3_DP
4

B14 A14
HDMI_OUT_TXD1 B15 A15
HDMI_OUT_TXD1# B16 A16 LAN_MDI2_DN
27 RJ45_LED0 RJ45_LED0 B17 A17 LAN_MDI2_DP
HDMI_OUT_TXD0 B18 A18
27 RJ45_LED1 RJ45_LED1 HDMI_OUT_TXD0# B19 A19 LAN_MDI1_DN
B20 A20 LAN_MDI1_DP 5V_S0 5V_SPDIF
27 RJ45_LED2 RJ45_LED2 HDMI_OUT_TXC B21 A21 R490
HDMI_OUT_TXC# B22 A22 LAN_MDI0_DN 1 2
5V_S0 B23 A23 LAN_MDI0_DP 0R0603-PAD
LAN_MDI0_DN HDMI_OUT_SCL B24 A24
27 LAN_MDI0_DN
LAN_MDI0_DP HDMI_OUT_SDA B25 A25 RJ45_LED0
27 LAN_MDI0_DP
HDMI_OUT_HPD B26 A26 RJ45_LED1

1
LAN_MDI1_DN C463 B27 A27 RJ45_LED2
27 LAN_MDI1_DN
LAN_MDI1_DP SCD1U16V2ZY-2GP HDMI_IN_TXD2 B28 A28 5V_SPDIF
27 LAN_MDI1_DP
HDMI_IN_TXD2# B29 A29 SPDIF

2
LAN_MDI2_DN SPDIF 30
27 LAN_MDI2_DN B30 A30
LAN_MDI2_DP HDMI_IN_TXD1 B31 A31 VCC5_USB
27 LAN_MDI2_DP
HDMI_IN_TXD1# B32 A32 USBPP2
LAN_MDI3_DN B33 A33 USBPN2
27 LAN_MDI3_DN
LAN_MDI3_DP HDMI_IN_TXD0 B34 A34
27 LAN_MDI3_DP
HDMI_IN_TXD0# B35 A35 USBPP3
B36 A36 USBPN3
HDMI_IN_TXC B37 A37
HDMI_IN_TXC# B38 A38 VCC5_USB
HDMI_5V B39 A39 USBPP4
HDMI_IN_SCL B40 A40 USBPN4
,D/Khd HDMI_IN_SDA
HDMI_IN_HPD
AV_CVBS-
B41
B42
A41
A42 USBPP9
USBPN9
HDMI_OUT_TXD2
SWAP AV_CVBS+
B43
B44
A43
A44
HDMI_OUT_TXD2 24
HDMI_OUT_TXD2# HDMI_OUT_TXD2# 24 B45 A45
AV_AUDIO_R B46 A46 OC*49 18 BT_POWER
HDMI_OUT_TXD1 OC*23 18
HDMI_OUT_TXD1#
HDMI_OUT_TXD1 24 SB 1210 AV_AUDIO_L
B47
B48
A47
A48 BT_RESET_IN#
HDMI_OUT_TXD1# 24
3 B49 A49 RISER_DET# 3

1
HDMI_OUT_TXD0 (R) RISER_DET# 19
HDMI_OUT_TXD0 24 NP2
HDMI_OUT_TXD0# HDMI_OUT_TXD0# 24 1 R356 2 C525
0R0402-PAD MLX-CONN98-4R5-GP U32 SCD1U16V2ZY-2GP

2
HDMI_OUT_TXC BT_POWER 1 5
HDMI_OUT_TXC 24 NC#1 VCC (R)
HDMI_OUT_TXC# HDMI_OUT_TXC# 24
(R) 2
A

2
EC5 2 1 SCD1U16V2ZY-2GP AVIN_AGND
HDMI_OUT_SCL HDMI_OUT_SCL 24 R551 3 4 BT_RESET_OUT
HDMI_OUT_SDA 4K7R2J-2-GP GND Y BT_RESET_OUT 26
HDMI_OUT_SDA 24 R1045
(R) SNAHC1G14DBVR-GP
HDMI_OUT_HPD HDMI_OUT_HPD 24 1 2 (R)

1
AVIN_AGND BT_RESET_IN# 22R2J-2-GP

1
1 R1044 2 BT_POWER

1
R89
U51 (R) 0R0402-PAD C533 4K7R2J-2-GP
HDMI_IN_TXC# 1 8 HDMI_IN_TXC# SCD1U10V2KX-5GP

2
HDMI_IN_TXC L1#1 L1#8 HDMI_IN_TXC (R) Q85
2 7
,D//E

2
L2#2 L2#7 PMBS3906-GP
G1 G2 1
HDMI_IN_TXD0# GNDGND HDMI_IN_TXD0#
3 6 R1042 R1043
HDMI_IN_TXD0 L3#3 L3#6 HDMI_IN_TXD0
4 5

1 3
L4#4 L4#5
1 2 1 2
HDMI_IN_TXD2 HDMI_IN_TXD2 47
HDMI_IN_TXD2# HDMI_IN_TXD2# 47 RCLAMP0524P-GP R545 1K5R2F-2-GP

1
10KR2J-3-GP 100R2J-2-GP
HDMI_IN_TXD1 HDMI_IN_TXD1 47 C976
HDMI_IN_TXD1# HDMI_IN_TXD1# 47 SCD1U10V2KX-5GP

2
HDMI_IN_TXD0 HDMI_IN_TXD0 47
HDMI_IN_TXD0# HDMI_IN_TXD0# 47
U53 (R)
HDMI_IN_TXC HDMI_IN_TXC 47 HDMI_IN_TXD1# 1 8 HDMI_IN_TXD1#
HDMI_IN_TXC# HDMI_IN_TXD1 L1#1 L1#8 HDMI_IN_TXD1
HDMI_IN_TXC# 47 2 7
L2#2 L2#7
HDMI_IN_TXD2#
G1
3
GNDGND
G2
6 HDMI_IN_TXD2#
0126 (1A)
HDMI_IN_TXD2 L3#3 L3#6 HDMI_IN_TXD2
4 5
2
HDMI_IN_SCL L4#4 L4#5 2
HDMI_IN_SCL 47
HDMI_IN_SDA HDMI_IN_SDA 47
RCLAMP0524P-GP
HDMI_IN_HPD HDMI_IN_HPD 47

s/E
47 AV_CVBS+ AV_CVBS+
47 AV_CVBS- AV_CVBS-

47 AV_AUDIO_R AV_AUDIO_R

47 AV_AUDIO_L AV_AUDIO_L

1 1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Riser slot
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 49 of 59
A B C D E
5 4 3 2 1

D D

POWER REGULATORS

+3.3V 190 mA VDDR3 60 mA


A2VDD 130 mA

+0.95/+1V 33 A VDDC 29 A
VDDCI 4 A
C C

+1.5V VDDR1 TBD


MVDDQ/C
VDD_CT 17 mA
DP[F:A]_PVDD 20 mA
DP[D:A]_VDD18 130 mA
DP[F:E]_VDD18 130 mA
SPV18 50 mA
MPV18 150 mA
DPLL_PVDD 75 mA
+1.8V 1.384 A PCIE_PVDD 40 mA
PCIE_VDDR 400 mA
TSVDD 5 mA
VDDR4
AVDD TBD
70 mA
VDD1DI 45 mA
VDD2DI 50 mA
A2VDDQ
1.5 mA

+1.0V 1.42 A
DP[D:A]_VDD10 110 mA
DP[F:E]_VDD10 110 mA
SPV10
DPLL_VDDC 100 mA
B B
PCIE_VDDC 1.1 A

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI_Power rail
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 50 of 59
5 4 3 2 1
5 4 3 2 1

W/ͺdžϭϲ
4 PEG_TXP[15..0]

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
D D
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12 U21A 1 OF 8
PEG_TXP13
PEG_TXP14
PEG_TXP15

4 PEG_TXN[15..0] PEG_TXP0 PEG_T_TXP0 2 C699 SCD1U10V2KX-4GP PEG_RXP0


PEG_TXN0
AA38
PCIE_RX0P PCIE_TX0P
Y33
PEG_T_TXN0
DIS 1
Y37 Y32 DIS 1 2 C700 SCD1U10V2KX-4GP PEG_RXN0
PEG_TXN0 PCIE_RX0N PCIE_TX0N
(S)
PEG_TXN1 (S)
PEG_TXN2 PEG_TXP1 Y35 W33 PEG_T_TXP1 DIS 1 2 C673 SCD1U10V2KX-4GP PEG_RXP1
PEG_TXN3 PEG_TXN1 PCIE_RX1P PCIE_TX1P PEG_T_TXN1 PEG_RXN1
W36 W32 DIS 1 2 C674 SCD1U10V2KX-4GP
PEG_TXN4 PCIE_RX1N PCIE_TX1N
(S)
PEG_TXN5 (S)
PEG_TXN6 PEG_TXP2 W38 U33 PEG_T_TXP2 DIS 1 2 C687 SCD1U10V2KX-4GP PEG_RXP2
PEG_TXN7 PEG_TXN2 PCIE_RX2P PCIE_TX2P PEG_T_TXN2 PEG_RXN2
V37 U32 DIS 1 2 C688 SCD1U10V2KX-4GP
PEG_TXN8 PCIE_RX2N PCIE_TX2N
(S)
PEG_TXN9 (S)
PEG_TXN10 PEG_TXP3 V35 U30 PEG_T_TXP3 DIS 1 2 C675 SCD1U10V2KX-4GP PEG_RXP3
PEG_TXN11 PEG_TXN3 PCIE_RX3P PCIE_TX3P PEG_T_TXN3
U36 U29 DIS 1 2 C676 SCD1U10V2KX-4GP PEG_RXN3
PEG_TXN12 PCIE_RX3N PCIE_TX3N
(S)
PEG_TXN13 (S)
PEG_TXN14 PEG_TXP4 U38 T33 PEG_T_TXP4 DIS 1 2 C689 SCD1U10V2KX-4GP PEG_RXP4
PEG_TXN15 PEG_TXN4 PCIE_RX4P PCIE_TX4P PEG_T_TXN4 PEG_RXN4
T37 T32 DIS 1 2 C690 SCD1U10V2KX-4GP
PCIE_RX4N PCIE_TX4N
(S)
(S)
PEG_TXP5 T35 T30 PEG_T_TXP5 DIS 1 2 C677 SCD1U10V2KX-4GP PEG_RXP5
PEG_TXN5 PCIE_RX5P PCIE_TX5P PEG_T_TXN5
R36 T29 DIS 1 2 C678 SCD1U10V2KX-4GP PEG_RXN5
PCIE_RX5N PCIE_TX5N

PCI EXPRESS INTERFACE


(S)
(S)
PEG_TXP6 R38 P33 PEG_T_TXP6 DIS 1 2 C691 SCD1U10V2KX-4GP PEG_RXP6
PEG_TXN6 PCIE_RX6P PCIE_TX6P PEG_T_TXN6 PEG_RXN6
P37 P32 DIS 1 2 C694 SCD1U10V2KX-4GP
PCIE_RX6N PCIE_TX6N
C (S) C
(S)
4 PEG_RXP[15..0] PEG_TXP7 PEG_T_TXP7 2 C679 SCD1U10V2KX-4GP PEG_RXP7
PEG_RXP0 PEG_TXN7
P35
PCIE_RX7P PCIE_TX7P
P30
PEG_T_TXN7
DIS 1
PEG_RXN7
N36 P29 DIS 1 2 C680 SCD1U10V2KX-4GP
PEG_RXP1 PCIE_RX7N PCIE_TX7N
(S)
PEG_RXP2 (S)
PEG_RXP3 PEG_TXP8 N38 N33 PEG_T_TXP8 DIS 1 2 C695 SCD1U10V2KX-4GP PEG_RXP8
PEG_RXP4 PEG_TXN8 PCIE_RX8P PCIE_TX8P PEG_T_TXN8
M37 N32 DIS 1 2 C692 SCD1U10V2KX-4GP PEG_RXN8
PEG_RXP5 PCIE_RX8N PCIE_TX8N
(S)
PEG_RXP6 (S)
PEG_RXP7 PEG_TXP9 M35 N30 PEG_T_TXP9 DIS 1 2 C681 SCD1U10V2KX-4GP PEG_RXP9
PEG_RXP8 PEG_TXN9 PCIE_RX9P PCIE_TX9P PEG_T_TXN9 PEG_RXN9
L36 N29 DIS 1 2 C682 SCD1U10V2KX-4GP
PEG_RXP9 PCIE_RX9N PCIE_TX9N
(S)
PEG_RXP10 (S)
PEG_RXP11 PEG_TXP10 L38 L33 PEG_T_TXP10 DIS 1 2 C693 SCD1U10V2KX-4GP PEG_RXP10
PEG_RXP12 PEG_TXN10 PCIE_RX10P PCIE_TX10P PEG_T_TXN10
K37 L32 DIS 1 2 C696 SCD1U10V2KX-4GP PEG_RXN10
PEG_RXP13 PCIE_RX10N PCIE_TX10N
(S)
PEG_RXP14 (S)
PEG_RXP15 PEG_TXP11 K35 L30 PEG_T_TXP11 DIS 1 2 C683 SCD1U10V2KX-4GP PEG_RXP11
PEG_TXN11 PCIE_RX11P PCIE_TX11P PEG_T_TXN11 PEG_RXN11
J36 L29 DIS 1 2 C684 SCD1U10V2KX-4GP
PCIE_RX11N PCIE_TX11N
(S)
(S)
PEG_TXP12 J38 K33 PEG_T_TXP12 DIS 1 2 C697 SCD1U10V2KX-4GP PEG_RXP12
PEG_TXN12 PCIE_RX12P PCIE_TX12P PEG_T_TXN12 PEG_RXN12
H37 K32 DIS 1 2 C698 SCD1U10V2KX-4GP
PCIE_RX12N PCIE_TX12N
(S)
4 PEG_RXN[15..0] (S)
PEG_RXN0 PEG_TXP13 H35 J33 PEG_T_TXP13 DIS 1 2 C669 SCD1U10V2KX-4GP PEG_RXP13
PEG_RXN1 PEG_TXN13 PCIE_RX13P PCIE_TX13P PEG_T_TXN13
G36 J32 DIS 1 2 C670 SCD1U10V2KX-4GP PEG_RXN13
PEG_RXN2 PCIE_RX13N PCIE_TX13N
(S)
PEG_RXN3 (S)
PEG_RXN4 PEG_TXP14 G38 K30 PEG_T_TXP14 DIS 1 2 C685 SCD1U10V2KX-4GP PEG_RXP14
PEG_RXN5 PEG_TXN14 PCIE_RX14P PCIE_TX14P PEG_T_TXN14 PEG_RXN14
F37 K29 DIS 1 2 C686 SCD1U10V2KX-4GP
PEG_RXN6 PCIE_RX14N PCIE_TX14N
(S)
PEG_RXN7 (S)
PEG_RXN8 PEG_TXP15 F35 H33 PEG_T_TXP15 DIS 1 2 C672 SCD1U10V2KX-4GP PEG_RXP15
PEG_RXN9 PEG_TXN15 PCIE_RX15P PCIE_TX15P PEG_T_TXN15
E37 H32 DIS 1 2 C671 SCD1U10V2KX-4GP PEG_RXN15
PEG_RXN10 PCIE_RX15N PCIE_TX15N
(S)
PEG_RXN11
B
PEG_RXN12
SB 1202 (S) B
PEG_RXN13 CLOCK
PEG_RXN14 CLK_PCIE_PEG AB35
15 CLK_PCIE_PEG PCIE_REFCLKP
PEG_RXN15 CLK_PCIE_PEG# AA36
15 CLK_PCIE_PEG# PCIE_REFCLKN

CALIBRATION (S) 1.0V_REG


R821 AJ21 Y30 1 R798 2 1K27R2F-L-GP
NC#AJ21 PCIE_CALRP
AK21
(S) 2 PWRGOOD_ATI AH16 NC#AK21
1 Y29 1 R792 2 2KR2F-3-GP
10KR2J-3-GP PWRGOOD PCIE_CALRN (S)
CLK_PCIE_PEG#
15 CLK_PCIE_PEG#
CLK_PCIE_PEG ATI_RST# 1 R353 2 PLT_RST1#_M92_1 AA30
15 CLK_PCIE_PEG PERST#
0R0402-PAD
1

C325 MADISON-PRO-GP
ATI_RST# (R) SC47P50V2JN-3GP
52 ATI_RST#
(M71.MDSON.M03, P71.0PARK.M05)
2

33,52 PLT_RST_ATI# PLT_RST_ATI# 1 R344 2 ATI_RST#


0R0402-PAD

[-1] 0401
A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI_Mad_PCIE
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 51 of 59
5 4 3 2 1
5 4 3 2 1

HSYNC/VSYNC are transmitted on TX0P/M_DP[A, C]2P/N,


TX3P/M_DP[B, D]2P/N, TXOUT_L0P/N_DPE2P/N,
or TXOUT_U0P/N_DPF2P/N (Blue) channel during blank

U21G 7 OF 8 09/09/28
U21B 2 OF 8
>ĂLJŽƵƚŶŽƚŝĐĞ͗ delete
D /ƚƐŚŽƵůĚďĞƉůĂĐĞŶĞĂƌ,D/ĐŽŶŶĞĐƚŽƌ LVDS CONTROL AK27 do not need LVDS D
DdžD,D/Khd sWd΀ϯ͗Ϭ΁ AU24 TX2P_DPAP3 (S)C400
(S)C400 1DIS 2
,D/ VARY_BL
DIGON
AJ27
TXCAP_DPA3P NV_HDMI_CLK+ 24
TX2P_DPAN3 SCD1U16V2KX-3GP C4031 DIS2 (S)
,LJŶŝdžͲ,ϱdYϭ'ϲϯ&ZͲϭϮ;ϴϬϬD,njͿ TXCAM_DPA3N
AV23
SCD1U16V2KX-3GP
NV_HDMI_CLK- 24
NV_HDMI_CLK+ 24
NV_HDMI_CLK- 24 ^ĂŵƐƵŶŐͲ<ϰtϭ'ϭϲϰϲͲ,ϭϮ;ϴϬϬD,njͿ MUTI GFX TX0P_DPA2P
AT25
AR24
TX2P_DPAP2
TX2P_DPAN2
(S)C392
(S)C392
SCD1U16V2KX-3GP
1DIS 2
C3971 DIS2 (S)
NV_HDMI_DATA0+ 24
AK35
TX0M_DPA2N NV_HDMI_DATA0- 24 TXCLK_UP_DPF3P
DPA SCD1U16V2KX-3GP AL36
NV_HDMI_DATA0+ 24 TXCLK_UN_DPF3N
NV_HDMI_DATA0- 24 1.8V_REG AU26 TX2P_DPAP1 (S) C386 1DIS 2 NV_HDMI_DATA1+ 24
TX1P_DPA1P TX2P_DPAN1 SCD1U16V2KX-3GP C3901
TX1M_DPA1N
AV25 DIS2 (S) NV_HDMI_DATA1- 24 TXOUT_U0P_DPF2P
AJ38
NV_HDMI_DATA1+ 24 SCD1U16V2KX-3GP AK37
TX2P_DPAP0 (S) C380 1DIS 2 TXOUT_U0N_DPF2N
NV_HDMI_DATA1- 24 AR8 AT27 NV_HDMI_DATA2+ 24
DVPCNTL_MVP_0 TX2P_DPA0P

1
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP
AU8 AR26 TX2P_DPAN0 SCD1U16V2KX-3GP C3841 DIS2 (S) NV_HDMI_DATA2- 24 AH35
R449 R466 R450 R456 DVPCNTL_MVP_1 TX2M_DPA0N SCD1U16V2KX-3GP TXOUT_U1P_DPF1P
NV_HDMI_DATA2+ 24 AP8 AJ36
(R) (R) (R) (R) DVPCNTL_0 TXOUT_U1N_DPF1N
NV_HDMI_DATA2- 24 AW8 AR30 5V_S0
DVPCNTL_1 TXCBP_DPB3P

2
AR3 AT29 AG38

1
NV_HDMI_CLK DVPCNTL_2 TXCBM_DPB3N R419 R420 R428 R429 R416 R417 R425 R426 TXOUT_U2P_DPF0P
NV_HDMI_CLK 24 AR1 AH37

2
DVPCLK TXOUT_U2N_DPF0N

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP
NV_HDMI_DATA NV_HDMI_DATA 24 MEM_ID0 AU1 AV31 R804 (S) (S) (S) (S) (S) (S) (S) (S)
MEM_ID1 DVPDATA_0 TX3P_DPB2P 100KR2J-1-GP 2N7002-11-GP
AU3 AU30 DIS AF35

G
MEM_ID2 DVPDATA_1 DPB TX3M_DPB2N (S) Q73 TXOUT_U3P
AW3 AG36

1
NV_HDMI_DETECT MEM_ID3 DVPDATA_2 (S) TXOUT_U3N
NV_HDMI_DETECT 24 AP6 AR32

2
DVPDATA_3 TX4P_DPB1P
AW5 AT31 S D
DVPDATA_4 TX4M_DPB1N LVTMDP
AU5
DVPDATA_5
AR6 AT33
AW6
AU6
DVPDATA_6
DVPDATA_7
TX5P_DPB0P
TX5M_DPB0N
AU32 dD^ƚŽ^ĐĂůĂƌ TXCLK_LP_DPE3P
AP34
AR34
DVPDATA_8 TX2P_DPCP3 C429 (S)1DIS 2 TXCLK_LN_DPE3N
AT7 AU14 ATI_TMDS_CLKP 47
DVPDATA_9 TXCCP_DPC3P TX2P_DPCN3 SCD1U16V2KX-3GP C4341
AV7
DVPDATA_10 TXCCM_DPC3N
AV13 DIS2(S) ATI_TMDS_CLKN 47 TXOUT_L0P_DPE2P
AW37
AN7 SCD1U16V2KX-3GP AU35
DVPDATA_11 TX2P_DPCP2 C424 (S)1DIS 2 TXOUT_L0N_DPE2N
AV9 AT15 ATI_TMDS_00P 47
DVPDATA_12 TX0P_DPC2P TX2P_DPCN2 SCD1U16V2KX-3GP C4281
AT9
DVPDATA_13 TX0M_DPC2N
AR14 DIS2(S) ATI_TMDS_00N 47 TXOUT_L1P_DPE1P
AR37
AR10 SCD1U16V2KX-3GP AU39
DdžDs'Khd AW10
AU10
DVPDATA_14
DVPDATA_15
DPC
TX1P_DPC1P
AU16
AV15
TX2P_DPCP1
TX2P_DPCN1
C421 1DIS 2(S)
SCD1U16V2KX-3GP C4221 DIS2(S)
ATI_TMDS_01P 47
TXOUT_L1N_DPE1N
AP35
DVPDATA_16 TX1M_DPC1N ATI_TMDS_01N 47 TXOUT_L2P_DPE0P
MXM_DDCCLK AP10 SCD1U16V2KX-3GP AR35
MXM_DDCCLK 23 DVPDATA_17 TXOUT_L2N_DPE0N
MXM_RED MXM_DDCDATA AV11 AT17 TX2P_DPCP0 C415 1DIS 2(S) ATI_TMDS_02P 47
MXM_RED 23 MXM_DDCDATA 23 3D3V_S0 DVPDATA_18 TX2P_DPC0P
AT11 AR16 TX2P_DPCN0 SCD1U16V2KX-3GP C4181 DIS2(S) ATI_TMDS_02N 47 AN36
DVPDATA_19 TX2M_DPC0N SCD1U16V2KX-3GP TXOUT_L3P
AR12 AP37
MXM_GREEN DVPDATA_20 TXOUT_L3N
MXM_GREEN 23 AW12 AU20 5V_S0
DVPDATA_21 TXCDP_DPD3P

2
MXM_HSYNC AU12 AT19
MXM_HSYNC 23,58 DVPDATA_22 TXCDM_DPD3N

1
MXM_VSYNC R432 3D3V_VGA 3D3V_VGA AP12 R883 R880 R895 R893 R898 R896 R903 R901
MXM_VSYNC 23,58 DVPDATA_23

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP

499R2F-2-GP
MXM_BLUE 100KR2J-1-GP AT21 R866 (S) (S) (S) (S) (S) (S) (S) (S)
MXM_BLUE 23 TX3P_DPD2P
AR20 100KR2J-1-GP DIS 2N7002-11-GP MADISON-PRO-GP

G
TX3M_DPD2N (S) Q76
09/09/28

1
2

2
DPD AU22 (S) (M71.MDSON.M03, P71.0PARK.M05)

2
35,42 GPU_THRM# Must be tied high if not used. R791 (R) TX4P_DPD1P
AV21 S D
10KR2J-3-GP (R) R800 TX4M_DPD1N
10KR2J-3-GP I2C AT23

D
TX5P_DPD0P
AR22

1
TPAD24 TP69 I2C_CLK TX5M_DPD0N
1 AK26
C Q41 TPAD24 TP67 I2C_DAT SCL C
1 AJ26
2N7002-11-GP GPIO19_CTF SDA
G
AD39 MXM_RED
GPIOS GENERAL PURPOSE I/O R
AD37 2 R364 1 150R2F-1-GP

S
GPIO_7_BLON GPIO0 R# (S)
AH20
GPIO1 GPIO_0 MXM_GREEN
AH18 AE36
GPIO2 GPIO_1 G R367 1 150R2F-1-GP
58 GPIO0 AN16 AD35 2
GPIO_2 G#

2
GPU_SMBDAT AH23 (S)
58 GPIO1 GPIO_3_SMBDATA
R817 GPU_SMBCLK AJ23 AF37 MXM_BLUE
58 GPIO2 GPIO_4_SMBCLK B
10KR2J-3-GP GPIO5 AH17 AE38 2 R366 1 150R2F-1-GP
58 GPU_SMBDAT GPIO_5_AC_BATT DAC1 B#
TPAD24 TP79 1 GPIO6 AJ17 (S) B8 1.8V_REG
58 GPU_SMBCLK GPIO_6
GPIO_7_BLON AK17 AC36 MXM_HSYNC 1 (S) 2
58 GPIO5

1
09/10/07 GPIO8 GPIO_7_BLON HSYNC MXM_VSYNC PBY201209T-221Y-N-GP
AJ13 AC38
do not need GPIO9 GPIO_8_ROMSO VSYNC 220ohm@100MHz 3A
AH15
GPIO_9_ROMSI

2
58 GPIO8 3D3V_VGA GPIO10 AJ16 (S) (R) (S)
GPIO11 GPIO_10_ROMSCK
58 GPIO9 AK16 AB34 1 R765 2 499R2F-2-GP AVDD C722 C738 C731

2
GPIO12 GPIO_11 RSET (S) SC10U6D3V3MX-GP SC1U10V2MX-GP SCD1U16V2ZY-2GP
AL16

1
09/10/07 R852 GPIO13 GPIO_12
58 GPIO11 AM16 AD34
pull high,OD (S)10KR2J-3-GP MXM_TMDS_HPD GPIO_13 AVDD
58 GPIO12 47 MXM_TMDS_HPD AM14 AE34
(R) AMD_GPIO15 GPIO_14_HPD2 AVSSQ VDD1DI B5 1.8V_REG
58 GPIO13 AM13
3D3V_VGA R448 2 OSC_SPREAD_1 GPIO_15_PWRCNTL_0 (S) 2
3 OSC_SPREAD DY 1 AK14 AC33 1

1
MB_ALERTB 0R2J-2-GP GPIO_16_SSIN VDD1DI PBY201209T-221Y-N-GP
AG30 AC34
GPIO_17_THERMAL_INT VSS1DI
1

TPAD24 TP83 1 GPIO18 AN14 220ohm@100MHz 3A

2
09/09/28 R360 GPIO19_CTF GPIO_18_HPD3 (S) (R) (S)
AM17
Reserved for CLKREQ (R) 100KR2J-1-GP AMD_GPIO20 GPIO_19_CTF C716 C739 C732
AL13 AC30
can unconnect if not use TPAD24 TP82 GPIO21 GPIO_20_PWRCNTL_1 R2 SC10U6D3V3MX-GP SC1U10V2MX-GP SCD1U16V2ZY-2GP
1 AJ14 AC31

1
GPIO22 GPIO_21_BB_EN R2#
AK13
2

GPIO_22_ROMCS#
15 PEX_CLKREQ AN13 AD30
GPIO24_TRSTB GPIO_23_CLKREQ# G2
AM23 AD31
GPIO25_TDI JTAG_TRST# G2#
AN23
58 GPIO22 GPIO26_TCK JTAG_TDI
AK23 AF30
GPIO27_TMS JTAG_TCK B2
AL24 AF31
GPIO28_TDO JTAG_TMS B2#
AM24
1.8V_REG TPAD24 TP81 JTAG_TDO
1 AJ19
TPAD24 TP80 GENERICA
58 GENERICC 1 AK19 AC32
GENERICB C
2

TPAD24 TP77 1 GENERICC AJ20 AD32


R828 TPAD24 TP78 GENERICC Y
1 AK20 AF32
(S) TPAD24 TP73 GENERICD COMP
499R2F-2-GP 1 AJ24
AMD_GPIO15 TPAD24 TP70 HPD5 GENERICE_HPD4 DAC2
42 AMD_GPIO15 PLACE VREFG DIVIDER AND CAP 1 AH26
GENERICF
VREFG TPAD24 TP68 1 09/10/07 AH24 AD29 H2SYNC
CLOSE TO ASIC
21

AMD_GPIO20 add TP GENERICG H2SYNC V2SYNC


AC29
2

42 AMD_GPIO20 R824 (S) V2SYNC 3D3V_VGA


249R2F-GP C870 NV_HDMI_DETECT AK24 3D3V_VGA
PEX_CLKREQ (S) SCD1U10V2KX-5GP HPD1
AG31 SB 1202
1

15 PEX_CLKREQ VDD2DI
AG32
1

VSS2DI

1
R877
ϬϵͬϬϵͬϮϴ

1
4K7R2J-2-GP
R892 (R)
A2VDD
AG33
4K7R2J-2-GP (R)
ϯͲ<ĞdžƚĞƌŶĂůƉƵůůͲƵƉ;ϯ͘ϯsͿŝƐƌĞƋƵŝƌĞĚ
1.8V_REG AD33 ŝĨĂŶĞdžƚĞƌŶĂů/K^ZKDĐŚŝƉŝƐƵƐĞĚ͘

2
B B11 DPLL_PVDD VREFG A2VDDQ B
(1.8V@150mA DPLL_PVDD) AH13

2
(S) 2 VREFG NV_HDMI_CLK
1 AF33
PBY201209T-221Y-N-GP A2VSSQ NV_HDMI_DATA 3D3V_VGA
2

2
220ohm@100MHz 3A (S) (R) (S)
C748 C750 C749 AA29
SC10U6D3V3MX-GP SC1U10V2MX-GP SCD1U16V2ZY-2GP R2SET
AM32
1

1
DPLL_PVDD
AN32
DPLL_PVSS R868
1.0V_REG B12 (S) DPLL_VDDC DDC/AUX MXM_DDCCLK
s' 4K7R2J-2-GP (R)
(1.1V@300mA DPLL_VDDC) DDC1CLK
AM26 MXM_DDCCLK 23
1 2 AN31 AN26 MXM_DDCDATA
DPLL_VDDC DDC1DATA MXM_DDCDATA 23
PBY201209T-221Y-N-GP

2
2

2
220ohm@100MHz 3A (S) (R) (S) AM27
C753 C757 C758 XTALIN PLL/CLOCK AUX1P GPIO22
AV33 AL27
SC10U6D3V3MX-GP SC1U10V2MX-GP SCD1U16V2ZY-2GP XTALOUT AU34 XTALIN AUX1N

OTHERS
1

1
XTALIN XTALOUT
AM19
DDC2CLK
AL19
R3861 DY (R) 2 XTALOUT VGA_XIN1_ATI DDC2DATA
3 VGA_XIN1 1 R371(S) 2 AW34
1MR2J-1-GP 0R2J-2-GP XO_IN
H2SYNC 58 AN20
AUX2P
V2SYNC 58 Y1 1 R369 2 0R2J-2-GP AW35 AM20
(R) (S) XO_IN2 AUX2N
MXM_DDCCLK_TMDS
dD^ƚŽ^ĐĂůĂƌ
3 2 AL30
DDCCLK_AUX3P
DDCDATA_AUX3N
AM30 MXM_DDCDATA_TMDS
MXM_DDCCLK_TMDS 47
MXM_DDCDATA_TMDS 47
SERIAL EEPROM 512K/1M
DY
4 1
DDCCLK_AUX4P
AL29 A 256MB MEMORY APERTURE SIZE
GPU_DPLUS AF29 AM29
33 GPU_DPLUS
GPU_DMINUS DPLUS THERMAL DDCDATA_AUX4N CAN BE DEFINED USING A SEPARATE
33 GPU_DMINUS AG29 ,D/
1

DY XTAL-27MHZ-74-GP DY (R) DMINUS NV_HDMI_CLK ROM OR STRAPPING


AN21 NV_HDMI_CLK 24
(R) C375 C361 09/10/07 DDCCLK_AUX5P NV_HDMI_DATA
SC18P50V2JN-1-GP SC18P50V2JN-1-GP add TP TPAD24 TP66 1TS_FDO AK32
DDCDATA_AUX5N
AM21 NV_HDMI_DATA 24 SB 1202
2

TS_FDO
AJ30
DDC6CLK
AL31 AJ31
TSVDD TS_A DDC6DATA
1.8V_REG B9 (1.8V@15mA TSVDD) AK30
(S) 1 DDCCLK_AUX7P 5V_S0
2
FCM1608KFG-301T05-GP
AJ32
AJ33
TSVDD DDCDATA_AUX7N
AK29 SB 1202 5V_S0
TSVSS
2

2
300ohm@100MHz 0.5A (S) (R) (S)
C720 C729 C736

1
SC10U6D3V3MX-GP SC1U10V2MX-GP SCD1U16V2ZY-2GP MADISON-PRO-GP
1

1
(M71.MDSON.M03, P71.0PARK.M05) R945 R944
0126 (1A) 47KR2J-2-GP 47KR2J-2-GP

2
2
MXM_DDCCLK_TMDS
GPIO24_TRSTB MXM_DDCDATA_TMDS
3D3V_VGA
3D3V_S0 U61 (R)
2

14 3 1 R1047 2 R871
VCC 1Y PERST#_BUF (R) 10KR2J-3-GP
6
2Y
1

A 8 8K2R2J-3-GP C978 (R) JTAG A


3Y
33,51 PLT_RST_ATI# 1 R1046 2 2 11 SC100P50V2JN-3-LL-GP NP1
1

(R) 1A 4Y (R) GPIO26_TCK TESTEN_1


5 1 2
2
1

8K2R2J-3-GP C977 2A
9
SC100P50V2JN-3-LL-GP 3A R870 GPIO27_TMS
12 3 4
(R) 4A
1 R1048 2 10KR2J-3-GP GPIO25_TDI 5 6
2

1 (R) (R) GPIO28_TDO 7 8 3D3V_VGA


1OE#
1

4 8K2R2J-3-GP C979 NP2


1

2OE# SC100P50V2JN-3-LL-GP
10
3OE# TESTEN_1 (R) SPD-CONN8A-3-GP
13 7
2

4OE# GND (R)


<Core Design>
SN74LV125APWR-1-GP
PERST#_Delay
Wistron Corporation
51 ATI_RST# 1 R355 2 PERST#_BUF 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
(R) Taipei Hsien 221, Taiwan, R.O.C.
0R2J-2-GP
Title

ATI_Mad_IO
Size Document Number Rev
D
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 52 of 59
5 4 3 2 1
5 4 3 2 1

U21E 5 OF 8

+1.5V_REG MEM I/O 1.8V_REG


PCIE PCIE_VDDR (1.8V@504mA PCIE_VDDR) L36
AC7 AA31 1 (S) 2
VDDR1 PCIE_VDDR

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SCD1U16V2ZY-2GP

SC1U10V2MX-GP

SC2D2U6D3V2MX-GP
AD11 AA32 PBY201209T-221Y-N-GP
VDDR1 PCIE_VDDR

2
AF7 AA33 (S) (R) (S) (S) 220ohm@100MHz 3A
VDDR1 PCIE_VDDR

SC10U6D3V3MX-GP
C803 C868 C886 C875 C881 C876 C815 AG10 AA34 C762 C723 C763 C715
VDDR1 PCIE_VDDR
AJ7 V28

1
VDDR1 PCIE_VDDR
AK8 W29
VDDR1 PCIE_VDDR
AL9 W30
VDDR1 PCIE_VDDR
G11 Y31
VDDR1 PCIE_VDDR 1.0V_REG

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP
G14

1
VDDR1
G17
VDDR1 (1.1V@1920mA PCIE_VDDC) For M96/M92 PCIE_VDDC = 1.1V
C345 C364 C941 C353 C943 C398 C884 C908 G20 G30
VDDR1 PCIE_VDDC For M97/RV8xx PCIE_VDDC = 1.0V

SCD1U16V2ZY-2GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC2D2U6D3V2MX-GP
G23 G31

2
VDDR1 PCIE_VDDC

2
G26 H29 (S) (S) (S) (S) (S)
D (S) (S) (S) (S) (S) (S) (S) VDDR1 PCIE_VDDC D

SC10U6D3V3MX-GP
G29 H30 C771 C783 C775 C776 C767
VDDR1 PCIE_VDDC
H10 J29

1
VDDR1 PCIE_VDDC
J7 J30
VDDR1 PCIE_VDDC
J9 L28
VDDR1 PCIE_VDDC
SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP
1 K11 M28

2
VDDR1 PCIE_VDDC
K13 N28
VDDR1 PCIE_VDDC

SC10U6D3V3MX-GP
C911 C878 C782 C755 C504 C387 C420 C502 C915 K8 R28
(S) (S) (S) (S) (S) (S) (S) (S) VDDR1 PCIE_VDDC
L12 T28
2

1
VDDR1 PCIE_VDDC
L16 U28
VDDR1 PCIE_VDDC
L21
VDDR1 VDDC
L23
VDDR1
L26 AA15
VDDR1 VDDC

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP
L7 CORE AA17

1
VDDR1 VDDC
M11 AA20
VDDR1 VDDC C846 C797 C790 C854 C804 C810 C823 C812 C802
N11 AA22
VDDR1 VDDC
(S) (S) (S) (S) (S) (S) (S) (S) P7 AA24

2
VDDR1 VDDC
(S) R11 AA27
VDDR1 VDDC
U11 AB16
VDDR1 VDDC
U7 AB18
VDDR1 VDDC

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP SC2D2U6D3V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP
Y11 AB21

1
VDDR1 VDDC
Y7 AB23
VDDR1 VDDC C768 C829 C809 C844 C843 C848 C786
AB26
VDDC (S) (S) (S) (S) (S) (S) (S) (S) (S)
AB28

2
1.8V_REG VDDC
AC17
VDDC
AC20
VDDC_CT VDDC

SC2D2U6D3V2MX-GP
LEVEL AC22
VDDC

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP
B4 (1.8V@110mA VDD_CT) TRANSLATION AC24
VDDC

1
POWER
1 2 AF26 AC27
PBY201209T-221Y-N-GP VDD_CT VDDC C855 C801 C818 C781 C798 C831 C822
AF27 AD18
VDD_CT VDDC (S) (S) (S) (S) (S) (S) (S)
2

1
220ohm@100MHz 3A (S) C765 (S) C777 (S) C773 (S) C780 (S) AG26 AD21

2
VDD_CT VDDC
SC10U6D3V3MX-GP

(S) C711 AG27 AD23


VDD_CT VDDC
SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP
AD26
1

2
3D3V_VGA VDDC
AF17
VDDC

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP
I/O AF20
VDDC

SC2D2U6D3V2MX-GP
AF23 AF22

1
VDDR3 VDDC (S) (S) (S)
AF24 AG16
2

1
C726 C805 (S) C800 (S) C796 (S) VDDR3 VDDC C817 C824 C813 C842 C835 C839
AG23 AG18
VDDR3 VDDC
SC10U6D3V3MX-GP

C AG24 AG21 C

2
VDDR3 VDDC (S) (S) (S) (S) (S) (S) (S)
SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP
(S) AH22 (S) (S) (S)
1

2
VDDC
AH27
VDDC
AF13 AH28
VDDR4 VDDC
AF15 M26
VDDR4 VDDC

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
AG13 N24

1
VDDR4 VDDC (S) (S) (S) (S) (S)
AG15 N27
VDDR4 VDDC/BIF_VDDC C323 C806 C795 C836 C833
R18
B26 VDDR4 VDDC
R21

2
VDDC
1 2 AD12 R23
PBY201209T-221Y-N-GP VDDR4 VDDC
AF11 R26
2

220ohm@100MHz 3A C869 (S) C864 VDDR4 VDDC


AF12 T17
VDDR4 VDDC
SC10U6D3V3MX-GP

(S) C922 AG11 T20


VDDR4 VDDC
SC1U10V2MX-GP

SC1U10V2MX-GP

(S) T22
1

(S) 09/10/07 VDDC


T24
add TP VDDC
T27
VDDC/BIF_VDDC
U16
TPAD14-GP TP64 VDDC
1 M20 U18
TPAD14-GP TP63 NC_VDDRHA VDDC
1 M21 U21
NC_VSSRHA VDDC
U23
VDDC
U26
TPAD14-GP TP85 VDDC
1 V12 V17
TPAD14-GP TP84 NC_VDDRHB VDDC
1 U12 V20
NC_VSSRHB VDDC
V22
VDDC
V24
VDDC
V27
VDDC
Y16
B3 PCIE_PVDD PLL VDDC
(1.8V@40mA PCIE_PVDD) VDDC
Y18
2 1 AB37 Y21
FCM1608KFG-301T05-GP MPV18 PCIE_PVDD VDDC
Y23
VDDC
2

300ohm@100MHz 0.5A (S) (S) (S) H7 Y26


MPV18 VDDC
SC10U6D3V3MX-GP

(S) C330 C333 C334 H8 Y28


MPV18 VDDC
SC1U10V2MX-GP

SC1U10V2MX-GP
1

SPV18
AM10
1.0V_REG L39 SPV18
AA13
VDDCI
1 2 AN9 AB13
PBY201209T-221Y-N-GP SPV10 VDDCI
AC12
2

B
220ohm@100MHz 3A VDDCI B
AN10 AC15
SPVSS VDDCI
SC10U6D3V3MX-GP

SPV18 C891 C893 C894 AD13


(S) VDDCI
SC1U10V2MX-GP

SCD1U16V2ZY-2GP

B24 (1.8V@75mA SPV18) AD16


1

VDDCI
1 2 M15
PBY201209T-221Y-N-GP VDDCI
M16
2

220ohm@100MHz 3A (S) (S) (S) VOLTAGE VDDCI


M18
VDDCI
SC10U6D3V3MX-GP

C896 C902 C903 SENESE M23 B1 (R)


(S) VDDCI
SC1U10V2MX-GP

SCD1U16V2ZY-2GP

N13 1 2
1

VDDCI PBY201209T-221Y-N-GP
AF28 N15
FB_VDDC VDDCI 220ohm@100MHz 3A VDDC
N17
VDDCI
N20
(S) VDDCI
(S) AG28 N22 1 (S) 2
FB_VDDCI VDDCI

SC1U10V2MX-GP

SC1U10V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP
(S) ISOLATED R12 R820 0R5J-5-GP

1
MPV18 CORE I/O VDDCI (S) (S) (S) (S) (S) (S) (S) (S) Dual footprint
R13
B25 VDDCI C867 C873 C861 C862 C897 C889 C890 C900
(1.8V@500mA MPV18) AH29
FB_GND VDDCI
R16
1 2 T12

2
PBY201209T-221Y-N-GP VDDCI
T15
220ohm@100MHz 3A VDDCI
V15
2

(S) (S) (S) VDDCI


(S) Y13
VDDCI
SC10U6D3V3MX-GP

C892 C907 C909


SC1U10V2MX-GP

SCD1U16V2ZY-2GP
1

MADISON-PRO-GP

(M71.MDSON.M03, P71.0PARK.M05)

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI_Mad_POWER
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 53 of 59
5 4 3 2 1
5 4 3 2 1

U21F 6 OF 8
D D

AB39 A3
PCIE_VSS GND
E39 A37
PCIE_VSS GND
F34 AA16
PCIE_VSS GND
F39 AA18
PCIE_VSS GND
G33 AA2
PCIE_VSS GND
G34 AA21
PCIE_VSS GND
H31 AA23
PCIE_VSS GND
H34 AA26
PCIE_VSS GND
H39 AA28
PCIE_VSS GND
09/09/28 J31
J34
PCIE_VSS GND
AA6
AB12
PCIE_VSS GND
For dual-link TMDS, the associated power supply rails can K31
PCIE_VSS GND
AB15
K34 AB17
share the filters/decoupling capacitors. K39
PCIE_VSS
PCIE_VSS
GND
GND
AB20
L31 AB22
we use single HDMI, share or ? L34
PCIE_VSS GND
AB24
PCIE_VSS GND
need check! M34
PCIE_VSS GND
AB27
M39 AC11
PCIE_VSS GND
N31 AC13
1.8V_REG PCIE_VSS GND
N34 AC16
PCIE_VSS GND
P31 AC18
PCIE_VSS GND
P34 AC2
B19 DPA_VDD18 PCIE_VSS GND
(1.8V@130mA DPA_VDD18) P39
PCIE_VSS GND
AC21
1 2 U21H 8 OF 8 R34 AC23
PBY201209T-221Y-N-GP PCIE_VSS GND
T31 AC26

2
220ohm@100MHz 3A (S) (S) (S) DPC_VDD18 DP C/D POWER DP A/B POWER DPA_VDD18 PCIE_VSS GND
T34 AC28
C816 C808 C807 PCIE_VSS GND
(S) T39 AC6
SC10U6D3V3MX-GP SCD1U16V2ZY-2GP PCIE_VSS GND
AP20 AN24 U31 AD15

1
DPC_VDD18 DPA_VDD18 PCIE_VSS GND
AP21 AP24 U34 AD17
SC1U10V2MX-GP DPC_VDD18 DPA_VDD18 PCIE_VSS GND
V34 AD20
DPC_VDD10 PCIE_VSS GND
V39 AD22
1.0V_REG B23 DPA_VDD10 B13 1.0V_REG PCIE_VSS GND
(1.0V@200mA DPC_VDD10) (1.0V@200mA DPA_VDD10) W31
PCIE_VSS GND
AD24
B16 (1.8V@130mA DPB_VDD18) DPB_VDD18 1 2 AP13 AP31 1 2 W34 AD27
PBY201209T-221Y-N-GP DPC_VDD10 DPA_VDD10 PBY201209T-221Y-N-GP PCIE_VSS GND
1 2 AT13 AP32 Y34 AD9
DPC_VDD10 DPA_VDD10 PCIE_VSS GND

2
PBY201209T-221Y-N-GP 220ohm@100MHz 3A (S) (S) (S) 220ohm@100MHz 3A Y39 AE2

2
220ohm@100MHz 3A (S) (R) (S) C880 C872 C871 C760 C769 C770(S) PCIE_VSS GND
(S) AE6
C793 C791 C792 SC10U6D3V3MX-GP SCD1U16V2ZY-2GP SC10U6D3V3MX-GP SCD1U16V2ZY-2GP GND
(S) AN17 AN27 AF10

1
SC10U6D3V3MX-GP SCD1U16V2ZY-2GP DPC_VSSR DPA_VSSR GND
AP16 AP27 AF16

1
SC1U10V2MX-GP DPC_VSSR DPA_VSSR SC1U10V2MX-GP GND
AP17 AP28 AF18
SC1U10V2MX-GP DPC_VSSR DPA_VSSR (S) (S) GND
AW14 AW24 AF21
AW16
DPC_VSSR
DPC_VSSR
DPA_VSSR
DPA_VSSR
AW26
(S) F15
GND
GND GND
GND
GND
AG17
AG2
DPD_VDD18 DPB_VDD18 F17 AG20
GND GND
F19 AG22
GND GND
AP22 AP25 F21 AG6
B18 DPC_VDD18 DPD_VDD18 DPB_VDD18 GND GND
(1.8V@130mA DPC_VDD18) AP23
DPD_VDD18 DPB_VDD18
AP26 F23
GND GND
AG9
1 2 F25 AH21
C PBY201209T-221Y-N-GP DPD_VDD10 DPB_VDD10 GND GND C
F27 AJ10
2

2
220ohm@100MHz 3A (S) (S) (S) 1.0V_REG B22 B10 (S) 1.0V_REG GND GND
(1.0V@200mA DPD_VDD10) (1.0V@200mA DPB_VDD10) F29
GND GND
AJ11
(S) C821 C826 C825 1 2 AP14 AN33 1 2 F31 AJ2
SC10U6D3V3MX-GP SCD1U16V2ZY-2GP PBY201209T-221Y-N-GP DPD_VDD10 DPB_VDD10 PBY201209T-221Y-N-GP GND GND
AP15 AP33 F33 AJ28
1

1
DPD_VDD10 DPB_VDD10 GND GND

2
220ohm@100MHz 3A (R) (R) (R) (R) (R) (R) 220ohm@100MHz 3A F7 AJ6
SC1U10V2MX-GP C858 C859 C860 C733 C735 C742 GND GND
(S) F9 AK11
SC10U6D3V3MX-GP SCD1U16V2ZY-2GP SC10U6D3V3MX-GP SCD1U16V2ZY-2GP GND GND
G2 AK31

1
GND GND
AN19 AN29 G6 AK7
SC1U10V2MX-GP DPD_VSSR DPB_VSSR SC1U10V2MX-GP GND GND
AP18 AP29 H9 AL11
DPD_VSSR DPB_VSSR GND GND
AP19 AP30 J2 AL14
B17 DPD_VDD18 DPD_VSSR DPB_VSSR 1.8V_REG GND GND
(1.8V@130mA DPD_VDD18) AW20
DPD_VSSR DPB_VSSR
AW30 J27
GND GND
AL17
1 2 AW22 AW32 DPA_PVDD (1.8V@20mA DPA_PVDD) B15 J6 AL2
PBY201209T-221Y-N-GP DPD_VSSR DPB_VSSR GND GND
2 1 J8 AL20
2

220ohm@100MHz 3A (S) (R) (S) FCM1608KFG-301T05-GP GND GND


R391 K14 AL21
GND GND/PX_EN

2
C814 C819 C811 300ohm@100MHz 0.5A K7 AL23
(S) GND GND
SC10U6D3V3MX-GP SCD1U16V2ZY-2GP 2 R427 1 AW18 AW28 2 (S) 1 C787 C788 C789 (S) L11 AL26
1

DPCD_CALR DPAB_CALR SC10U6D3V3MX-GP SCD1U16V2ZY-2GP GND GND


L17 AL32

1
SC1U10V2MX-GP 150R2F-1-GP DPE_VDD18 GND GND
L2 AL6
150R2F-1-GP SC1U10V2MX-GP GND GND
(S) DP E/F POWER DP PLL POWER L22 AL8
(S) (S) GND GND
AH34 AU28 L24 AM11
DPE_VDD18 DPA_PVDD GND GND
AJ34 AV27 L6 AM31
DPE_VDD18 DPA_PVSS (S) GND GND
M17 AM9
DPE_VDD10 GND GND
M22 AN11
DPB_PVDD B14 GND GND
(1.8V@20mA DPA_PVDD) M24
GND GND
AN2
(1.8V@130mA DPE_VDD18) AL33
DPE_VDD10 DPB_PVDD
AV29 2 1 N16
GND GND
AN30
B7 (1.8V@130mA DPF_VDD18) DPE_VDD18 AM33 AR28 FCM1608KFG-301T05-GP N18 AN6

2
DPE_VDD10 DPB_PVSS 300ohm@100MHz 0.5A GND GND
1 2 N2 AN8
PBY201209T-221Y-N-GP C778 C779 C774 (S) GND GND
N21 AP11
2

220ohm@100MHz 3A (S) (R) (R) (S) SC10U6D3V3MX-GP SCD1U16V2ZY-2GP GND GND


N23 AP7

1
C721 C737 C745 C730 1.0V_REG GND GND
(S) AN34 AU18 N26 AP9
SC10U6D3V3MX-GP SCD1U16V2ZY-2GP B6 (S) DPE_VDD10 DPE_VSSR DPC_PVDD SC1U10V2MX-GP GND GND
AP39 AV17 N6 AR5
1

SC1U10V2MX-GP DPE_VSSR DPC_PVSS DPC_PVDD (S) (S) B21 GND GND


1 2 AR39
DPE_VSSR (1.8V@20mA DPC_PVDD) R15
GND GND
B11
SC1U10V2MX-GP SC1U10V2MX-GP PBY201209T-221Y-N-GP AU37 2 1 R17 B13

2
220ohm@100MHz 3A (R) (R) (R) (R) DPE_VSSR DPD_PVDD (S) FCM1608KFG-301T05-GP GND GND
R2 B15
GND GND

2
C714 C717 C734 C719 AV19 300ohm@100MHz 0.5A R20 B17
SC10U6D3V3MX-GP SCD1U16V2ZY-2GP DPE_VDD18 DPD_PVDD C856 C849 C850 GND GND
09/09/28 AR18 (S) R22 B19

1
LVDS MODE DPD_PVSS SC10U6D3V3MX-GP SCD1U16V2ZY-2GP GND GND
R24 B21
CHECK

1
SC1U10V2MX-GP GND GND
(1.8V@200mA DPE_VDD18) AF34
DPF_VDD18
R27
GND GND
B23
do not support LVDS (1.8V@200mA DPF_VDD18) (1.0V@170mA DPE_VDD10) AG34 SC1U10V2MX-GP R6 B25
DPF_VDD18 (S) (S) GND GND
AM37 T11 B27
DPE_VDD10 DPE_PVDD B20 GND GND
DPE_PVSS
AN38 (1.8V@20mA DPA_PVDD) T13
GND GND
B29
(S) 2 1 T16 B31
DPEF_PVDD FCM1608KFG-301T05-GP GND GND
AK33 T18 B33

2
DPF_VDD10 300ohm@100MHz 0.5A GND GND
AK34 T21 B7
DPF_VDD10 C840 C837 C838 (S) GND GND
AL38 T23 B9
DPF_PVDD SC10U6D3V3MX-GP SCD1U16V2ZY-2GP GND GND
AM35 T26 C1

1
DPF_PVSS GND GND
U15 C39
SC1U10V2MX-GP GND GND
AF39 U17 E35
DPF_VSSR (S) (S) GND GND
AH39 U2 E5
DPF_VSSR GND GND
AK39 U20 F11
B DPF_VSSR DPEF_PVDD (S) B2 GND GND B
AL34
DPF_VSSR (1.8V@20mA DPE_PVDD) U22
GND GND
F13
AM34 2 1 U24
DPF_VSSR FCM1608KFG-301T05-GP GND
U27

2
300ohm@100MHz 0.5A GND
R368 U6
C329 C331 C335 GND
(S) V11
(S) 1 SC10U6D3V3MX-GP SCD1U16V2ZY-2GP GND
2 AM39 V16

1
DPEF_CALR GND
V18
SC1U10V2MX-GP GND
V21
150R2F-1-GP MADISON-PRO-GP (S) (S) GND
V23
GND
V26
(S) GND
(M71.MDSON.M03, P71.0PARK.M05) W2
GND
W6
GND
Y15
GND
Y17
GND
Y20
GND VSS_MECH1 TP12 TPAD14-GP
Y22 A39 1
GND VSS_MECH VSS_MECH2 TP86 TPAD14-GP
Y24 AW1 1
GND VSS_MECH VSS_MECH3
Y27 AW39 1 (S) TP65 TPAD14-GP
GND VSS_MECH
U13 (S)
GND
V13 (S)
GND
MADISON-PRO-GP

(M71.MDSON.M03, P71.0PARK.M05)

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI_DP POWER
Size Document Number Rev
D
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 54 of 59
5 4 3 2 1
5 4 3 2 1

U21C 3 OF 8
DDR2 DDR2 U21D 4 OF 8
GDDR3/GDDR5 GDDR5/GDDR3 DDR2 DDR2
D DDR3 DDR3 GDDR3/GDDR5 GDDR5/GDDR3 D
RASA0#
56 RASA0# RASA1# MDA0 MAA0 DDR3 DDR3
C37 G24
56 RASA1# MDA1 DQA0_0/DQA_0 MAA0_0/MAA_0 MAA1 MDB0 MAB0
C35 J23 C5 P8
CASA0# MDA2 DQA0_1/DQA_1 MAA0_1/MAA_1 MAA2 MDB1 DQB0_0/DQB_0 MAB0_0/MAB_0 MAB1
A35 H24 C3 T9
56 CASA0# DQA0_2/DQA_2 MAA0_2/MAA_2 DQB0_1/DQB_1 MAB0_1/MAB_1

MEMORY INTERFACE A
CASA1# MDA3 E34 J24 MAA3 MDB2 E3 P9 MAB2
56 CASA1# DQA0_3/DQA_3 MAA0_3/MAA_3 DQB0_2/DQB_2 MAB0_2/MAB_2

MEMORY INTERFACE B
MDA4 G32 H26 MAA4 MDB3 E1 N7 MAB3
WEA0# MDA5 DQA0_4/DQA_4 MAA0_4/MAA_4 MAA5 MDB4 DQB0_3/DQB_3 MAB0_3/MAB_3 MAB4
D33 J26 F1 N8
56 WEA0# WEA1# MDA6 DQA0_5/DQA_5 MAA0_5/MAA_5 MAA6 MDB5 DQB0_4/DQB_4 MAB0_4/MAB_4 MAB5
F32 H21 F3 N9
56 WEA1# MDA7 DQA0_6/DQA_6 MAA0_6/MAA_6 MAA7 MDB6 DQB0_5/DQB_5 MAB0_5/MAB_5 MAB6
E32 G21 F5 U9
CKEA0 MDA8 DQA0_7/DQA_7 MAA0_7/MAA_7 MAA8 MDB7 DQB0_6/DQB_6 MAB0_6/MAB_6 MAB7
D31 H19 G4 U8
56 CKEA0 CKEA1 MDA9 DQA0_8/DQA_8 MAA1_0/MAA_8 MAA9 MDB8 DQB0_7/DQB_7 MAB0_7/MAB_7 MAB8
F30 H20 H5 Y9
56 CKEA1 MDA10 DQA0_9/DQA_9 MAA1_1/MAA_9 MAA10 MDB9 DQB0_8/DQB_8 MAB1_0/MAB_8 MAB9
C30 L13 H6 W9
CSA0#_0 MDA11 DQA0_10/DQA_10 MAA1_2/MAA_10 MAA11 MDB10 DQB0_9/DQB_9 MAB1_1/MAB_9 MAB10
A30 G16 J4 AC8
56 CSA0#_0 CSA1#_0 MDA12 DQA0_11/DQA_11 MAA1_3/MAA_11 MAA12 MDB11 DQB0_10/DQB_10 MAB1_2/MAB_10 MAB11
F28 J16 K6 AC9
56 CSA1#_0 MDA13 DQA0_12/DQA_12 MAA1_4/MAA_12 A_BA2 MDB12 DQB0_11/DQB_11 MAB1_3/MAB_11 MAB12
C28 H16 K5 AA7
MDA14 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 A_BA0 MDB13 DQB0_12/DQB_12 MAB1_4/MAB_12 B_BA2
A28 J17 L4 AA8
MDA15 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 A_BA1 MDB14 DQB0_13/DQB_13 MAB1_5/BA2 B_BA0
E28 H17 M6 Y8
MDA16 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 MDB15 DQB0_14/DQB_14 MAB1_6/BA0 B_BA1
D27 M1 AA9
MDA17 DQA0_16/DQA_16 DQMA#0 MDB16 DQB0_15/DQB_15 MAB1_7/BA1
F26 A32 M3
CLKA0 MDA18 DQA0_17/DQA_17 WCKA0_0/DQMA_0 DQMA#1 MDB17 DQB0_16/DQB_16 DQMB#0
C26 C32 M5 H3
56 CLKA0 CLKA0# MDA19 DQA0_18/DQA_18 WCKA0#_0/DQMA_1 DQMA#2 MDB18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 DQMB#1
A26 D23 N4 H1
56 CLKA0# MDA20 DQA0_19/DQA_19 WCKA0_1/DQMA_2 DQMA#3 MDB19 DQB0_18/DQB_18 WCKB0#_0/DQMB_1 DQMB#2
F24 E22 P6 T3
CLKA1 MDA21 DQA0_20/DQA_20 WCKA0#_1/DQMA_3 DQMA#4 MDB20 DQB0_19/DQB_19 WCKB0_1/DQMB_2 DQMB#3
C24 C14 P5 T5
56 CLKA1 CLKA1# MDA22 DQA0_21/DQA_21 WCKA1_0/DQMA_4 DQMA#5 MDB21 DQB0_20/DQB_20 WCKB0#_1/DQMB_3 DQMB#4
A24 A14 R4 AE4
56 CLKA1# MDA23 DQA0_22/DQA_22 WCKA1#_0/DQMA_5 DQMA#6 MDB22 DQB0_21/DQB_21 WCKB1_0/DQMB_4 DQMB#5
E24 E10 T6 AF5
QSA#[7..0] MDA24 DQA0_23/DQA_23 WCKA1_1/DQMA_6 DQMA#7 MDB23 DQB0_22/DQB_22 WCKB1#_0/DQMB_5 DQMB#6
C22 D9 T1 AK6
56 QSA#[7..0] MDA25 DQA0_24/DQA_24 WCKA1#_1/DQMA_7 MDB24 DQB0_23/DQB_23 WCKB1_1/DQMB_6 DQMB#7
A22 U4 AK5
QSA[7..0] MDA26 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 QSA0 MDB25 DQB0_24/DQB_24 WCKB1#_1/DQMB_7
F22 C34 V6
56 QSA[7..0] MDA27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 QSA1 MDB26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 QSB0
D21 D29 V1 F6
DQMA#[7..0] MDA28 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 QSA2 MDB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 QSB1
56 DQMA#[7..0] A20 D25 V3 K3
MDA29 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 QSA3 MDB28 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 QSB2
F20 E20 Y6 P3
MDA[63..0] MDA30 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 QSA4 MDB29 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 QSB3
56 MDA[63..0] D19 E16 Y1 V5
MDA31 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 QSA5 MDB30 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 QSB4
E18 E12 Y3 AB5
MAA[13..0] MDA32 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 QSA6 MDB31 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 QSB5
56 MAA[13..0] C18 J10 Y5 AH1
MDA33 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 QSA7 MDB32 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 QSB6
A18 D7 AA4 AJ9
MDA34 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 MDB33 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 QSB7
F18 AB6 AM5
MDA35 DQA1_2/DQA_34 QSA#0 MDB34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
D17 A34 AB1
A_BA0 MDA36 DQA1_3/DQA_35 DDBIA0_0/QSA_0#/WDQSA_0 QSA#1 MDB35 DQB1_2/DQB_34 QSB#0
C
56 A_BA0 A16 E30 AB3 G7 C
A_BA1 MDA37 DQA1_4/DQA_36 DDBIA0_1/QSA_1#/WDQSA_1 QSA#2 MDB36 DQB1_3/DQB_35 DDBIB0_0/QSB_0#/WDQSB_0 QSB#1
56 A_BA1 F16 E26 AD6 K1
A_BA2 MDA38 DQA1_5/DQA_37 DDBIA0_2/QSA_2#/WDQSA_2 QSA#3 MDB37 DQB1_4/DQB_36 DDBIB0_1/QSB_1#/WDQSB_1 QSB#2
56 A_BA2 D15 C20 AD1 P1
MDA39 DQA1_6/DQA_38 DDBIA0_3/QSA_3#/WDQSA_3 QSA#4 MDB38 DQB1_5/DQB_37 DDBIB0_2/QSB_2#/WDQSB_2 QSB#3
E14 C16 AD3 W4
MDA40 DQA1_7/DQA_39 DDBIA1_0/QSA_4#/WDQSA_4 QSA#5 MDB39 DQB1_6/DQB_38 DDBIB0_3/QSB_3#/WDQSB_3 QSB#4
F14 C12 AD5 AC4
MDA41 DQA1_8/DQA_40 DDBIA1_1/QSA_5#/WDQSA_5 QSA#6 MDB40 DQB1_7/DQB_39 DDBIB1_0/QSB_4#/WDQSB_4 QSB#5
D13 J11 AF1 AH3
MDA42 DQA1_9/DQA_41 DDBIA1_2/QSA_6#/WDQSA_6 QSA#7 MDB41 DQB1_8/DQB_40 DDBIB1_1/QSB_5#/WDQSB_5 QSB#6
F12 F8 AF3 AJ8
MDA43 DQA1_10/DQA_42 DDBIA1_3/QSA_7#/WDQSA_7 MDB42 DQB1_9/DQB_41 DDBIB1_2/QSB_6#/WDQSB_6 QSB#7
A12 AF6 AM3
RASB0# MDA44 DQA1_11/DQA_43 ODTA0 MDB43 DQB1_10/DQB_42 DDBIB1_3/QSB_7#/WDQSB_7
57 RASB0# D11 J21 AG4
RASB1# MDA45 DQA1_12/DQA_44 ADBIA0/ODTA0 ODTA1 MDB44 DQB1_11/DQB_43 ODTB0
57 RASB1# F10 G19 AH5 T7
MDA46 DQA1_13/DQA_45 ADBIA1/ODTA1 MDB45 DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB1
A10 AH6 W7
CASB0# MDA47 DQA1_14/DQA_46 CLKA0 MDB46 DQB1_13/DQB_45 ADBIB1/ODTB1
57 CASB0# C10 H27 AJ4
CASB1# MDA48 DQA1_15/DQA_47 CLKA0 CLKA0# MDB47 DQB1_14/DQB_46 CLKB0
57 CASB1# G13 G27 AK3 L9
MDA49 DQA1_16/DQA_48 CLKA0# MDB48 DQB1_15/DQB_47 CLKB0 CLKB0#
H13 AF8 L8
WEB0# MDA50 DQA1_17/DQA_49 CLKA1 MDB49 DQB1_16/DQB_48 CLKB0#
57 WEB0# J13 J14 AF9
WEB1# MDA51 DQA1_18/DQA_50 CLKA1 CLKA1# MDB50 DQB1_17/DQB_49 CLKB1
57 WEB1# H11 H14 AG8 AD8
MDA52 DQA1_19/DQA_51 CLKA1# MDB51 DQB1_18/DQB_50 CLKB1 CLKB1#
G10 AG7 AD7
CSB0#_0 MDA53 DQA1_20/DQA_52 RASA0# MDB52 DQB1_19/DQB_51 CLKB1#
57 CSB0#_0 G8 K23 AK9
CSB1#_0 MDA54 DQA1_21/DQA_53 RASA0# RASA1# MDB53 DQB1_20/DQB_52 RASB0#
57 CSB1#_0 K9 K19 AL7 T10
MDA55 DQA1_22/DQA_54 RASA1# MDB54 DQB1_21/DQB_53 RASB0# RASB1#
K10 AM8 Y10
MDA56 DQA1_23/DQA_55 CASA0# MDB55 DQB1_22/DQB_54 RASB1#
G9 K20 AM7
+1.5V_REG MDA57 DQA1_24/DQA_56 CASA0# CASA1# MDB56 DQB1_23/DQB_55 CASB0#
A8 K17 AK1 W10
MDA58 DQA1_25/DQA_57 CASA1# +1.5V_REG MDB57 DQB1_24/DQB_56 CASB0# CASB1#
C8 AL4 AA10
CKEB0 MDA59 DQA1_26/DQA_58 CSA0#_0 MDB58 DQB1_25/DQB_57 CASB1#
57 CKEB0 E8 K24 AM6
1

CKEB1 MDA60 DQA1_27/DQA_59 CSA0#_0 MDB59 DQB1_26/DQB_58 CSB0#_0


57 CKEB1 A6 K27 AM1 P10
DQA1_28/DQA_60 CSA0#_1 DQB1_27/DQB_59 CSB0#_0

1
(S) R819 MDA61 C6 MDB60 AN4 L10
CLKB0 40D2R2F-GP MDA62 DQA1_29/DQA_61 CSA1#_0 R836 MDB61 DQB1_28/DQB_60 CSB0#_1
57 CLKB0 E6 M13 AP3
CLKB0# MDA63 DQA1_30/DQA_62 CSA1#_0 (S) 40D2R2F-GP MDB62 DQB1_29/DQB_61 CSB1#_0
57 CLKB0# A5 K16 AP1 AD10
DQA1_31/DQA_63 CSA1#_1 MDB63 DQB1_30/DQB_62 CSB1#_0
AP5 AC10
2

CLKB1 CKEA0 DQB1_31/DQB_63 CSB1#_1


57 CLKB1 L18 K21

2
CLKB1# +1.5V_REG MVREFDA CKEA0 CKEA1 CKEB0
57 CLKB1# L20 J20 U10
1

MVREFSA CKEA1 CKEB0 CKEB1


Y12 AA11
MVREFDB CKEB1
2

R815 (S) (S) 243R2F-2-GP 1 R797(S) 2 L27 K26 WEA0# AA12

2
QSB#[7..0] 100R2F-L1-GP-U C866 243R2F-2-GP 1 R832(S) 2 MEM_CALRN0 WEA0# WEA1# (S) MVREFSB WEB0# +1.5V_REG
N12 L15 N10
57 QSB#[7..0] SC1U10V2MX-GP 243R2F-2-GP 1 R838(S) 2 MEM_CALRN1 WEA1# (S) C874 WEB0# WEB1#
AG12 AB11
1

QSB[7..0] MEM_CALRN2 R826 SC1U10V2MX-GP WEB1#


2

1
57 QSB[7..0] 243R2F-2-GP 1 R837(S) 2 MAA13 100R2F-L1-GP-U
M12 H23
DQMB#[7..0] 243R2F-2-GP 1 R796(S) 2 MEM_CALRP1 MAA0_8 MAB13 R861
57 DQMB#[7..0] M27 J19 AD28 T8

2
B +1.5V_REG 243R2F-2-GP 1 R835(S) 2 MEM_CALRP0 MAA1_8 TESTEN MAB0_8 (S) 4K7R2J-2-GP B
GDDR5

AH12 W8 R860
MDB[63..0] MEM_CALRP2 TEST_MCLK MAB1_8
AK10

GDDR5
57 MDB[63..0] CLKTESTA
TEST_YCLK AL10 AH11 1 (S) 2 DRAM_RST

12
1

MAB[13..0] +1.5V_REG CLKTESTB DRAM_RST# 680R2J-3-GP


57 MAB[13..0]
R807 R864

2
(S) 40D2R2F-GP (S) (S) 4K7R2J-2-GP

1
C910

2
B_BA0 R833 (R) SC68P50V2JN-1GP
2

2
57 B_BA0 40D2R2F-GP
B_BA1 MADISON-PRO-GP C457 MADISON-PRO-GP
57 B_BA1
B_BA2 (S) SCD1U10V2KX-5GP
57 B_BA2

1
1

(S) (M71.MDSON.M03, P71.0PARK.M05) (M71.MDSON.M03, P71.0PARK.M05)

2
R808 C832 (R)
100R2F-L1-GP-U (S) SC1U10V2MX-GP C450
1

SCD1U10V2KX-5GP 09/10/07

1
1

1
(S)
JV50 pull down with 10K
2

ODTA0 56 (S) C865 R470


ODTA1 56 R827 SC1U10V2MX-GP (R) 51K1R2F-GP

1
100R2F-L1-GP-U 09/10/07
2 JV50 connect to TP

1
TESTEN
ODTB0 57 R464
ODTB1 57 Designator For M97-M2 For Mannhatton
(R) 51K1R2F-GP
3D3V_VGA
R779
R_MEM_1 10K 10K

2
DRAM_RST 56,57 (R) 2
1
5K11R2F-L1-GP
R_MEM_2 40R/Short 680R

1
09/09/29
(S) R780
If TESTEN = 0 V: Internal debug use only
1KR2F-3-GP R_MEM_3 DY DY
If TESTEN = 3.3 V: JTAG TRST# signal enabled

2
C_MEM 2.2nF 68pF

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI_Mad_MEMORY
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 55 of 59
5 4 3 2 1
5 4 3 2 1

55 MDA[63..0] CHANNEL A: 256MB/512MB DDR3


MDA0
MDA1
MDA2
72.51G63.C0U gDDRIII 64M*16 800MHz VRAM 54nm (Orion die) FBGA96P HYNIX H5TQ1G63BFR-12C
MDA3
MDA4
72.41164.H0U gDDR3 64M*16 800MHz VRAM E die FBGA 96P SAMSUNG K4W1G1646E-HC12
MDA5
MDA6 U45 U19 U49 U24
MDA7
MDA8 VREFC_U20 M8 E3 MDA20 VREFC_U21 M8 E3 MDA31 VREFC_U22 M8 E3 MDA35 VREFC_U23 M8 E3 MDA51
MDA9 VREFD_U20 VREFCA DQL0 MDA17 VREFD_U21 VREFCA DQL0 MDA24 VREFD_U22 VREFCA DQL0 MDA36 VREFD_U23 VREFCA DQL0 MDA52
H1 F7 H1 F7 H1 F7 H1 F7
MDA10 VREFDQ DQL1 MDA21 VREFDQ DQL1 MDA29 VREFDQ DQL1 MDA32 VREFDQ DQL1 MDA49
F2 F2 F2 F2
MDA11 MAA0 DQL2 MDA18 MAA0 DQL2 MDA26 MAA0 DQL2 MDA39 MAA0 DQL2 MDA53
N3 F8 N3 F8 N3 F8 N3 F8
MDA12 MAA1 A0 DQL3 MDA23 MAA1 A0 DQL3 MDA28 MAA1 A0 DQL3 MDA34 MAA1 A0 DQL3 MDA48
P7 H3 P7 H3 P7 H3 P7 H3
MDA13 MAA2 A1 DQL4 MDA16 MAA2 A1 DQL4 MDA27 MAA2 A1 DQL4 MDA38 MAA2 A1 DQL4 MDA54
P3 H8 P3 H8 P3 H8 P3 H8
MDA14 MAA3 A2 DQL5 MDA22 MAA3 A2 DQL5 MDA30 MAA3 A2 DQL5 MDA33 MAA3 A2 DQL5 MDA50
N2 G2 N2 G2 N2 G2 N2 G2
D
MDA15 MAA4 A3 DQL6 MDA19 MAA4 A3 DQL6 MDA25 MAA4 A3 DQL6 MDA37 MAA4 A3 DQL6 MDA55 D
P8 H7 P8 H7 P8 H7 P8 H7
MDA16 MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7
P2 P2 P2 P2
MDA17 MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
R8 R8 R8 R8
MDA18 MAA7 A6 MDA0 MAA7 A6 MDA15 MAA7 A6 MDA43 MAA7 A6 MDA63
R2 D7 R2 D7 R2 D7 R2 D7
MDA19 MAA8 A7 DQU0 MDA4 MAA8 A7 DQU0 MDA10 MAA8 A7 DQU0 MDA45 MAA8 A7 DQU0 MDA59
T8 C3 T8 C3 T8 C3 T8 C3
MDA20 MAA9 A8 DQU1 MDA1 MAA9 A8 DQU1 MDA14 MAA9 A8 DQU1 MDA40 MAA9 A8 DQU1 MDA62
R3 C8 R3 C8 R3 C8 R3 C8
MDA21 MAA10 A9 DQU2 MDA6 MAA10 A9 DQU2 MDA11 MAA10 A9 DQU2 MDA44 MAA10 A9 DQU2 MDA56
L7 C2 L7 C2 L7 C2 L7 C2
MDA22 MAA11 A10/AP DQU3 MDA3 MAA11 A10/AP DQU3 MDA12 MAA11 A10/AP DQU3 MDA42 MAA11 A10/AP DQU3 MDA60
R7 A7 R7 A7 R7 A7 R7 A7
MDA23 MAA12 A11 DQU4 MDA7 MAA12 A11 DQU4 MDA8 MAA12 A11 DQU4 MDA47 MAA12 A11 DQU4 MDA57
N7 A2 N7 A2 N7 A2 N7 A2
MDA24 MAA13 A12/BC DQU5 MDA2 MAA13 A12/BC DQU5 MDA13 MAA13 A12/BC DQU5 MDA41 MAA13 A12/BC DQU5 MDA61
T3 B8 T3 B8 T3 B8 T3 B8
MDA25 A13 DQU6 MDA5 A13 DQU6 MDA9 A13 DQU6 MDA46 A13 DQU6 MDA58
T7 A3 T7 A3 T7 A3 T7 A3
MDA26 A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
MDA27 A15 +1.5V_REG A15 +1.5V_REG A15 +1.5V_REG A15 +1.5V_REG
MDA28
MDA29 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2
MDA30 A_BA1 BA0 VDD#B2 A_BA1 BA0 VDD#B2 A_BA1 BA0 VDD#B2 A_BA1 BA0 VDD#B2
N8 D9 N8 D9 N8 D9 N8 D9
MDA31 A_BA2 BA1 VDD#D9 A_BA2 BA1 VDD#D9 A_BA2 BA1 VDD#D9 A_BA2 BA1 VDD#D9
M3 G7 M3 G7 M3 G7 M3 G7
MDA32 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
MDA33 VDD#K2 VDD#K2 VDD#K2 VDD#K2
K8 K8 K8 K8
MDA34 VDD#K8 VDD#K8 VDD#K8 VDD#K8
N1 N1 N1 N1
MDA35 CLKA0 VDD#N1 CLKA0 VDD#N1 CLKA1 VDD#N1 CLKA1 VDD#N1
J7 N9 J7 N9 J7 N9 J7 N9
MDA36 CLKA0# CK VDD#N9 CLKA0# CK VDD#N9 CLKA1# CK VDD#N9 CLKA1# CK VDD#N9
K7 R1 K7 R1 K7 R1 K7 R1
MDA37 CKEA0 CK VDD#R1 CKEA0 CK VDD#R1 CKEA1 CK VDD#R1 CKEA1 CK VDD#R1
K9 R9 K9 R9 K9 R9 K9 R9
MDA38 CKE VDD#R9 +1.5V_REG CKE VDD#R9 +1.5V_REG CKE VDD#R9 +1.5V_REG CKE VDD#R9 +1.5V_REG
MDA39
MDA40 ODTA0 K1 A1 ODTA0 K1 A1 ODTA1 K1 A1 ODTA1 K1 A1
MDA41 CSA0#_0 ODT VDDQ#A1 CSA0#_0 ODT VDDQ#A1 CSA1#_0 ODT VDDQ#A1 CSA1#_0 ODT VDDQ#A1
L2 A8 L2 A8 L2 A8 L2 A8
MDA42 RASA0# CS VDDQ#A8 RASA0# CS VDDQ#A8 RASA1# CS VDDQ#A8 RASA1# CS VDDQ#A8
J3 C1 J3 C1 J3 C1 J3 C1
MDA43 CASA0# RAS VDDQ#C1 CASA0# RAS VDDQ#C1 CASA1# RAS VDDQ#C1 CASA1# RAS VDDQ#C1
K3 C9 K3 C9 K3 C9 K3 C9
MDA44 WEA0# CAS VDDQ#C9 WEA0# CAS VDDQ#C9 WEA1# CAS VDDQ#C9 WEA1# CAS VDDQ#C9
L3 D2 L3 D2 L3 D2 L3 D2
MDA45 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
MDA46 VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
MDA47 QSA2 VDDQ#F1 QSA3 VDDQ#F1 QSA4 VDDQ#F1 QSA6 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
MDA48 QSA0 DQSL VDDQ#H2 QSA1 DQSL VDDQ#H2 QSA5 DQSL VDDQ#H2 QSA7 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
MDA49 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
MDA50
MDA51 DQMA#2 E7 A9 DQMA#3 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9
MDA52 DQMA#0 DML VSS#A9 DQMA#1 DML VSS#A9 DQMA#5 DML VSS#A9 DQMA#7 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3 B3 C
MDA53 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
MDA54 VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
MDA55 QSA#2 VSS#G8 QSA#3 VSS#G8 QSA#4 VSS#G8 QSA#6 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
MDA56 QSA#0 DQSL VSS#J2 QSA#1 DQSL VSS#J2 QSA#5 DQSL VSS#J2 QSA#7 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
MDA57 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
MDA58 VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
MDA59 VSS#M9 VSS#M9 VSS#M9 VSS#M9
P1 P1 P1 P1
MDA60 DRAM_RST VSS#P1 DRAM_RST VSS#P1 DRAM_RST VSS#P1 DRAM_RST VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
MDA61 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
MDA62 VSS#T1 VSS#T1 VSS#T1 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
1

1
MDA63 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 R781 Should be 240 R401 Should be 240 R834 Should be 240 R460
240R2F-1-GP B1 240R2F-1-GP B1 240R2F-1-GP B1 240R2F-1-GP B1
55 MAA[13..0] Ohms +-1% VSSQ#B1 Ohms +-1% VSSQ#B1 Ohms +-1% VSSQ#B1 Ohms +-1% VSSQ#B1
B9 B9 B9 B9
MAA0 VSSQ#B9 VSSQ#B9 VSSQ#B9 VSSQ#B9
D1 D1 D1 D1
2

2
MAA1 VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
D8 D8 D8 D8
MAA2 VSSQ#D8 VSSQ#D8 VSSQ#D8 VSSQ#D8
09/10/07 VSSQ#E2
E2
VSSQ#E2
E2
VSSQ#E2
E2
VSSQ#E2
E2
MAA3 (M) J1 E8 (M) J1 E8 (M) J1 E8 (M) J1 E8
MAA4 JV50 use 243 L1
NC#J1 VSSQ#E8
F9 L1
NC#J1 VSSQ#E8
F9 L1
NC#J1 VSSQ#E8
F9 L1
NC#J1 VSSQ#E8
F9
MAA5 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
MAA6 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
MAA7 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
MAA8 100-BALL 100-BALL 100-BALL 100-BALL
MAA9 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
MAA10 H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP
MAA11
MAA12 (M) (M) (M) (M)
MAA13

+1.5V_REG +1.5V_REG +1.5V_REG


55 DQMA#[7..0] +1.5V_REG 1

1
DQMA#0
1

DQMA#1 R414 R825 R457


DQMA#2 R803 09/10/07 4K99R2F-L-GP (M) 4K99R2F-L-GP (M) 4K99R2F-L-GP
DQMA#3 4K99R2F-L-GP
DQMA#4 JV50 use 1K05 and D01U
2

2
DQMA#5 VREFC_U21 VREFC_U22 VREFC_U23
2

B B
DQMA#6 VREFC_U20
1

1
DQMA#7 (M)
1

2
(M) R407 R829 (M) R454 (M)
55 QSA[7..0]
2

R802 4K99R2F-L-GP C395 (M) 4K99R2F-L-GP C879 (M) 4K99R2F-L-GP C436


QSA0 4K99R2F-L-GP C785 SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
1

1
QSA1 SCD1U10V2KX-5GP
1

2
QSA2
2

QSA3 (M)
QSA4 (M) (M)
QSA5 (M)
QSA6
QSA7 +1.5V_REG +1.5V_REG
+1.5V_REG +1.5V_REG
55 QSA#[7..0]
1

1
1

1
QSA#0 R793 R468
QSA#1 4K99R2F-L-GP R769 4K99R2F-L-GP R847
QSA#2 4K99R2F-L-GP 4K99R2F-L-GP
QSA#3
2

2
QSA#4 VREFD_U20 VREFD_U22
2

2
QSA#5 VREFD_U21 VREFD_U23
1

1
QSA#6 (M) (M)
2

1
QSA#7 R790 (M) R465 (M)
2

2
4K99R2F-L-GP C764 R773 4K99R2F-L-GP C442 R844
SCD1U10V2KX-5GP 4K99R2F-L-GP C744 SCD1U10V2KX-5GP 4K99R2F-L-GP C887
1

1
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2

1
2

2
CLKA0 (M) (M)
2

(M) (M) (M) (M)


55,57 DRAM_RST DRAM_RST R381 (M) (M)
56R2J-4-GP +1.5V_REG
55 A_BA0
55 A_BA1 1 2 C358
21

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP
55 A_BA2

1
R387 SCD01U16V2KX-3GP +1.5V_REG +1.5V_REG +1.5V_REG
(M) 56R2J-4-GP (M) C451 C913 C446 C885 C439
55 CLKA0 402
55 CLKA0#

2
SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP
CLKA0# 402 402 402 402 402
55 CKEA0
1

1
A A
C877 C409 C784 C799 C759 C827 C412 C341 C385 C820 C926 C440 C905 C414 C467
55 ODTA0
(M)
55 CSA0#_0
2

2
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
55 RASA0#
CLKA1
55 CASA0# <Core Design> (M) (M) (M) (M) (M)
2

55 WEA0# +1.5V_REG
R848
56R2J-4-GP +1.5V_REG
55
55
CLKA1
CLKA1# (M) (M) (M) (M) (M) (M) (M) (M) (M) (M) (M) (M) (M) (M) (M)
Wistron Corporation
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

55 CKEA1 1 2 C888 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


21

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
Taipei Hsien 221, Taiwan, R.O.C.
1

1
R845 SCD01U16V2KX-3GP C336 C376 C453 C411
55 ODTA1
(M) 56R2J-4-GP (M) C883 C426 C512 C919 C431 Title
55 CSA1#_0
2

55 RASA1# ATI_DDR3 64MX16 A


2

CLKA1#
55 CASA1#
1

Size Document Number Rev


55 WEA1#
C
(M) Catalina SA
Date: Tuesday, April 06, 2010 Sheet 56 of 59
5 4 3 2 1
(M) (M) (M) (M)
5 4 3 2 1

55 MDB[63..0]
MDB0
CHANNEL B: 256MB/512MB DDR3
MDB1
MDB2
MDB3
MDB4
72.51G63.C0U gDDRIII 64M*16 800MHz VRAM 54nm (Orion die) FBGA96P HYNIX H5TQ1G63BFR-12C
MDB5
MDB6
72.41164.H0U gDDR3 64M*16 800MHz VRAM E die FBGA 96P SAMSUNG K4W1G1646E-HC12
MDB7
MDB8 U54 U29
MDB9 U28 U55
MDB10 VREFC_U26 M8 E3 MDB34 VREFC_U27 M8 E3 MDB51
MDB11 VREFC_U24 MDB31 VREFC_U25 MDB20 VREFD_U26 VREFCA DQL0 MDB37 VREFD_U27 VREFCA DQL0 MDB52
M8 E3 M8 E3 H1 F7 H1 F7
MDB12 VREFD_U24 VREFCA DQL0 MDB24 VREFD_U25 VREFCA DQL0 MDB18 VREFDQ DQL1 MDB32 VREFDQ DQL1 MDB49
H1 F7 H1 F7 F2 F2
MDB13 VREFDQ DQL1 MDB30 VREFDQ DQL1 MDB22 MAB0 DQL2 MDB39 MAB0 DQL2 MDB55
F2 F2 N3 F8 N3 F8
MDB14 MAB0 DQL2 MDB26 MAB0 DQL2 MDB16 MAB1 A0 DQL3 MDB36 MAB1 A0 DQL3 MDB48
N3 F8 N3 F8 P7 H3 P7 H3
MDB15 MAB1 A0 DQL3 MDB28 MAB1 A0 DQL3 MDB21 MAB2 A1 DQL4 MDB38 MAB2 A1 DQL4 MDB54
P7 H3 P7 H3 P3 H8 P3 H8
D
MDB16 MAB2 A1 DQL4 MDB27 MAB2 A1 DQL4 MDB17 MAB3 A2 DQL5 MDB33 MAB3 A2 DQL5 MDB50 D
P3 H8 P3 H8 N2 G2 N2 G2
MDB17 MAB3 A2 DQL5 MDB29 MAB3 A2 DQL5 MDB23 MAB4 A3 DQL6 MDB35 MAB4 A3 DQL6 MDB53
N2 G2 N2 G2 P8 H7 P8 H7
MDB18 MAB4 A3 DQL6 MDB25 MAB4 A3 DQL6 MDB19 MAB5 A4 DQL7 MAB5 A4 DQL7
P8 H7 P8 H7 P2 P2
MDB19 MAB5 A4 DQL7 MAB5 A4 DQL7 MAB6 A5 MAB6 A5
P2 P2 R8 R8
MDB20 MAB6 A5 MAB6 A5 MAB7 A6 MDB43 MAB7 A6 MDB63
R8 R8 R2 D7 R2 D7
MDB21 MAB7 A6 MDB15 MAB7 A6 MDB1 MAB8 A7 DQU0 MDB45 MAB8 A7 DQU0 MDB59
R2 D7 R2 D7 T8 C3 T8 C3
MDB22 MAB8 A7 DQU0 MDB10 MAB8 A7 DQU0 MDB7 MAB9 A8 DQU1 MDB42 MAB9 A8 DQU1 MDB62
T8 C3 T8 C3 R3 C8 R3 C8
MDB23 MAB9 A8 DQU1 MDB14 MAB9 A8 DQU1 MDB0 MAB10 A9 DQU2 MDB44 MAB10 A9 DQU2 MDB56
R3 C8 R3 C8 L7 C2 L7 C2
MDB24 MAB10 A9 DQU2 MDB11 MAB10 A9 DQU2 MDB4 MAB11 A10/AP DQU3 MDB40 MAB11 A10/AP DQU3 MDB60
L7 C2 L7 C2 R7 A7 R7 A7
MDB25 MAB11 A10/AP DQU3 MDB12 MAB11 A10/AP DQU3 MDB3 MAB12 A11 DQU4 MDB47 MAB12 A11 DQU4 MDB57
R7 A7 R7 A7 N7 A2 N7 A2
MDB26 MAB12 A11 DQU4 MDB8 MAB12 A11 DQU4 MDB6 MAB13 A12/BC DQU5 MDB41 MAB13 A12/BC DQU5 MDB61
N7 A2 N7 A2 T3 B8 T3 B8
MDB27 MAB13 A12/BC DQU5 MDB13 MAB13 A12/BC DQU5 MDB2 A13 DQU6 MDB46 A13 DQU6 MDB58
T3 B8 T3 B8 T7 A3 T7 A3
MDB28 A13 DQU6 MDB9 A13 DQU6 MDB5 A14 DQU7 A14 DQU7
T7 A3 T7 A3 M7 M7
MDB29 A14 DQU7 A14 DQU7 A15 +1.5V_REG A15 +1.5V_REG
M7 M7
MDB30 A15 +1.5V_REG A15 +1.5V_REG
MDB31 B_BA0 M2 B2 B_BA0 M2 B2
MDB32 B_BA0 B_BA0 B_BA1 BA0 VDD#B2 B_BA1 BA0 VDD#B2
M2 B2 M2 B2 N8 D9 N8 D9
MDB33 B_BA1 BA0 VDD#B2 B_BA1 BA0 VDD#B2 B_BA2 BA1 VDD#D9 B_BA2 BA1 VDD#D9
N8 D9 N8 D9 M3 G7 M3 G7
MDB34 B_BA2 BA1 VDD#D9 B_BA2 BA1 VDD#D9 BA2 VDD#G7 BA2 VDD#G7
M3 G7 M3 G7 K2 K2
MDB35 BA2 VDD#G7 BA2 VDD#G7 VDD#K2 VDD#K2
K2 K2 K8 K8
MDB36 VDD#K2 VDD#K2 VDD#K8 VDD#K8
K8 K8 N1 N1
MDB37 VDD#K8 VDD#K8 CLKB1 VDD#N1 CLKB1 VDD#N1
N1 N1 J7 N9 J7 N9
MDB38 CLKB0 VDD#N1 CLKB0 VDD#N1 CLKB1# CK VDD#N9 CLKB1# CK VDD#N9
J7 N9 J7 N9 K7 R1 K7 R1
MDB39 CLKB0# CK VDD#N9 CLKB0# CK VDD#N9 CKEB1 CK VDD#R1 CKEB1 CK VDD#R1
K7 R1 K7 R1 K9 R9 K9 R9
MDB40 CKEB0 CK VDD#R1 CKEB0 CK VDD#R1 CKE VDD#R9 +1.5V_REG CKE VDD#R9 +1.5V_REG
K9 R9 K9 R9
MDB41 CKE VDD#R9 +1.5V_REG CKE VDD#R9 +1.5V_REG
MDB42 ODTB1 K1 A1 ODTB1 K1 A1
MDB43 ODTB0 ODTB0 CSB1#_0 ODT VDDQ#A1 CSB1#_0 ODT VDDQ#A1
K1 A1 K1 A1 L2 A8 L2 A8
MDB44 CSB0#_0 ODT VDDQ#A1 CSB0#_0 ODT VDDQ#A1 RASB1# CS VDDQ#A8 RASB1# CS VDDQ#A8
L2 A8 L2 A8 J3 C1 J3 C1
MDB45 RASB0# CS VDDQ#A8 RASB0# CS VDDQ#A8 CASB1# RAS VDDQ#C1 CASB1# RAS VDDQ#C1
J3 C1 J3 C1 K3 C9 K3 C9
MDB46 CASB0# RAS VDDQ#C1 CASB0# RAS VDDQ#C1 WEB1# CAS VDDQ#C9 WEB1# CAS VDDQ#C9
K3 C9 K3 C9 L3 D2 L3 D2
MDB47 WEB0# CAS VDDQ#C9 WEB0# CAS VDDQ#C9 WE VDDQ#D2 WE VDDQ#D2
L3 D2 L3 D2 E9 E9
MDB48 WE VDDQ#D2 WE VDDQ#D2 VDDQ#E9 VDDQ#E9
E9 E9 F1 F1
MDB49 VDDQ#E9 VDDQ#E9 QSB4 VDDQ#F1 QSB6 VDDQ#F1
F1 F1 F3 H2 F3 H2
MDB50 QSB3 VDDQ#F1 QSB2 VDDQ#F1 QSB5 DQSL VDDQ#H2 QSB7 DQSL VDDQ#H2
F3 H2 F3 H2 C7 H9 C7 H9
MDB51 QSB1 DQSL VDDQ#H2 QSB0 DQSL VDDQ#H2 DQSU VDDQ#H9 DQSU VDDQ#H9
C7 H9 C7 H9
MDB52 DQSU VDDQ#H9 DQSU VDDQ#H9
C MDB53 DQMB#4 E7 A9 DQMB#6 E7 A9 C
MDB54 DQMB#3 DQMB#2 DQMB#5 DML VSS#A9 DQMB#7 DML VSS#A9
E7 A9 E7 A9 D3 B3 D3 B3
MDB55 DQMB#1 DML VSS#A9 DQMB#0 DML VSS#A9 DMU VSS#B3 DMU VSS#B3
D3 B3 D3 B3 E1 E1
MDB56 DMU VSS#B3 DMU VSS#B3 VSS#E1 VSS#E1
E1 E1 G8 G8
MDB57 VSS#E1 VSS#E1 QSB#4 VSS#G8 QSB#6 VSS#G8
G8 G8 G3 J2 G3 J2
MDB58 QSB#3 VSS#G8 QSB#2 VSS#G8 QSB#5 DQSL VSS#J2 QSB#7 DQSL VSS#J2
G3 J2 G3 J2 B7 J8 B7 J8
MDB59 QSB#1 DQSL VSS#J2 QSB#0 DQSL VSS#J2 DQSU VSS#J8 DQSU VSS#J8
B7 J8 B7 J8 M1 M1
MDB60 DQSU VSS#J8 DQSU VSS#J8 VSS#M1 VSS#M1
Should be 240 VSS#M1
M1
VSS#M1
M1
VSS#M9
M9
VSS#M9
M9
MDB61 M9 M9 P1 P1
MDB62
Ohms +-1% VSS#M9 VSS#M9 VSS#P1 VSS#P1
P1 P1 55,56 DRAM_RST T2 P9 55,56 DRAM_RST T2 P9
MDB63 VSS#P1 VSS#P1 RESET VSS#P9 RESET VSS#P9
55,56 DRAM_RST T2 P9 55,56 DRAM_RST T2 P9 T1 T1
RESET VSS#P9 RESET VSS#P9 VSS#T1 VSS#T1
55 MAB[13..0] T1 T1 L8 T9 L8 T9
VSS#T1 VSS#T1 ZQ VSS#T9 ZQ VSS#T9

1
L8 T9 L8 T9 Should be 240
1

1
MAB0 ZQ VSS#T9 ZQ VSS#T9 R889 R520
Should be 240 Ohms +-1%
MAB1 Should be 240 R481 Should be 240 R912 240R2F-1-GP B1 240R2F-1-GP B1
MAB2 (S) 240R2F-1-GP (S) 240R2F-1-GP Ohms +-1% VSSQ#B1 VSSQ#B1
Ohms +-1% B1 Ohms +-1% B1 B9 B9
MAB3 VSSQ#B1 VSSQ#B1 VSSQ#B9 VSSQ#B9
B9 B9 D1 D1

2
MAB4 VSSQ#B9 VSSQ#B9 VSSQ#D1 VSSQ#D1
D1 D1 D8 D8
2

2
MAB5 VSSQ#D1 VSSQ#D1 VSSQ#D8 VSSQ#D8
D8 D8 E2 E2
MAB6 VSSQ#D8 VSSQ#D8 (S) VSSQ#E2 (S) VSSQ#E2
E2 E2 J1 E8 J1 E8
MAB7 VSSQ#E2 VSSQ#E2 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
J1 E8 J1 E8 L1 F9 L1 F9
MAB8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
L1 F9 L1 F9 J9 G1 J9 G1
MAB9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
J9 G1 J9 G1 L9 G9 L9 G9
MAB10 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
L9 G9 L9 G9
MAB11 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 100-BALL 100-BALL
MAB12 100-BALL 100-BALL SDRAM DDR3 SDRAM DDR3
MAB13 SDRAM DDR3 SDRAM DDR3 H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP
H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP (S) (S)
(S) (S)
+1.5V_REG
55 DQMB#[7..0]

1
+1.5V_REG
DQMB#0 +1.5V_REG R521

1
DQMB#1 +1.5V_REG (S) 4K99R2F-L-GP
1

DQMB#2 R891
1

DQMB#3 09/10/07 R918 4K99R2F-L-GP

2
DQMB#4 R483 (S) 4K99R2F-L-GP VREFC_U27
DQMB#5 (S) 4K99R2F-L-GP JV50 use 1K05 and D01U

1
B B
DQMB#6 VREFC_U26
2

2
DQMB#7 VREFC_U25 R522 (S)
2

1
VREFC_U24 (S) (S) 4K99R2F-L-GP C511
1

2
R890 SCD1U10V2KX-5GP
55 QSB[7..0]

1
1

R916 (S) 4K99R2F-L-GP C932

2
2

QSB0 R482 (S) (S) 4K99R2F-L-GP C939 SCD1U10V2KX-5GP

1
QSB1 (S) 4K99R2F-L-GP C477 SCD1U10V2KX-5GP
1

2
QSB2 SCD1U10V2KX-5GP
1

QSB3 (S)
2

QSB4 (S) +1.5V_REG


QSB5

1
QSB6
QSB7 R887
+1.5V_REG +1.5V_REG (S) 4K99R2F-L-GP
55 QSB#[7..0]
1

1
QSB#0 +1.5V_REG

2
QSB#1 R884 R518 VREFD_U27
1

QSB#2 (S) 4K99R2F-L-GP 4K99R2F-L-GP

1
QSB#3 R913

2
QSB#4 (S) 4K99R2F-L-GP R888 (S)
2

2
QSB#5 VREFD_U25 VREFD_U26 (S) 4K99R2F-L-GP C931
QSB#6 SCD1U10V2KX-5GP
2

1
1

1
QSB#7 VREFD_U24 (S)

2
2

2
R885 (S) R523
1

(S) 4K99R2F-L-GP C929 4K99R2F-L-GP C510


2

R908 (S) SCD1U10V2KX-5GP SCD1U10V2KX-5GP


1

1
(S) 4K99R2F-L-GP C937
2

2
SCD1U10V2KX-5GP
1

(S)
2

B_BA0 (S) +1.5V_REG


55 B_BA0
B_BA1
55 B_BA1
B_BA2 CLKB0
55 B_BA2
1

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP
+1.5V_REG

1
CLKB0 R510 +1.5V_REG +1.5V_REG
55 CLKB0
CLKB0# 56R2J-4-GP (S) C470 C471 C947 C499 C472
55 CLKB0#
SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP
CKEB0 C506(S)
55 CKEB0

2
1

1
SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

SC1U10V2MX-GP

402 1 2 402 402 402 402 402


12

A ODTB0 (S) (S) (S) (S) (S) (S) (S) (S) (S) (S) C944 C933 C473 C483 C948 A
55 ODTB0
CSB0#_0 R516 SCD01U50V2KX-1GP C930 C476 C766 C494 C509 C940 C491 C416 C475 C498
55 CSB0#_0
2

2
RASB0# 56R2J-4-GP (S) 402 402 402 402 402
55 RASB0#
2

CASB0# 402 402 402 402 402 402 402 402 402 402 402 402
55 CASB0#
WEB0# CLKB0#
55 WEB0# <Core Design>
1 2

CLKB1 (S) (S) (S) (S) (S)


CLKB1 +1.5V_REG +1.5V_REG
55 CLKB1
CLKB1# R910
55
55
CLKB1#
CKEB1
CKEB1 56R2J-4-GP (S) (S) (S) (S) (S) (S) Wistron Corporation
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

C942(S) 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


1

ODTB1 402 1 2 (S) (S) (S) Taipei Hsien 221, Taiwan, R.O.C.
12

55 ODTB1
CSB1#_0 C945 C899 C514 C478 C946 C513
55 CSB1#_0
RASB1# R914 SCD01U50V2KX-1GP Title
55 RASB1#
2

CASB1# 56R2J-4-GP (S)


55
55
CASB1#
WEB1#
WEB1# 402 402 ATI_DDR3 64MX16 B
CLKB1# Size Document Number Rev
2

C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 57 of 59
5 4 3 2 1
(S) (S) (S)
5 4 3 2 1

52 GPIO0

52 GPIO1
RECOMMENDED SETTINGS
52 GPIO2
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
3D3V_VGA ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, X = DESIGN DEPENDANT
52 GPIO8
PIN STRAPS NA = NOT APPLICABLE
52 GPIO9
THEY MUST NOT CONFLICT DURING RESET
Manufacturer Part Number Size CONFIG[2:0]
52 GPIO11 GPIO0 (S) 1 R853 2 10KR2J-3-GP
STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
D D
52 GPIO12 GPIO1 (S) 1 R856 2 10KR2J-3-GP STRAP ST Microelectronics M25P05A 512 kbit 100

52 GPIO13 GPIO2 (S) 1 R854 2 10KR2J-3-GP

GPIO8 (R) 1 R867 2 10KR2J-3-GP HSYNC


23,52 MXM_VSYNC
GPIO9 (R) 1 R463 2 10KR2J-3-GP VSYNC
23,52 MXM_HSYNC

52 GENERICC GPIO11 (R) 1 R858 2 10KR2J-3-GP Audio for both DisplayPort and HDMI. 11 TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 1

GPIO12 (R) 1 R859 2 10KR2J-3-GP STRAP TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 1
52 V2SYNC Audio for DisplayPort and HDMI 10
GPIO13 (R) 1 R855 2 10KR2J-3-GP if dongle is detected BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 1
52 H2SYNC

52 GPIO22 MXM_VSYNC (S) 1 R361 2 10KR2J-3-GP BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0


BIF_VGA DIS GPIO9 VGA ENABLED 0
52 GPIO5 MXM_HSYNC (S) 1 R362 2 10KR2J-3-GP BIF_RX_PLL_CALIB_BP GPIO21 BIF_RX_PLL_CALIB_BP 0

GENERICC (R) 1 R806 2 10KR2J-3-GP BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1

V2SYNC (R) 1 R801 2 10KR2J-3-GP ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 1 0 0

H2SYNC (R) 1 R795 2 10KR2J-3-GP VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0

GPIO22 (R) 1 R869 2 10KR2J-3-GP SMS_EN_HARD H2SYNC 0


CCBYPASS GENERICC 0
GPIO5 (S) 1 R857 2 10KR2J-3-GP AUD[1] HSYNC built-in HDMI connector 1
AUD[0] VSYNC Audio functiuon present 1

PCH_SMBCLK
,13,15,29 PCH_SMBCLK PCH_SMBDATA
3,15,29 PCH_SMBDATA

DGPU_PWROK
19,42,43 DGPU_PWROK

C GPU_SMBCLK C
52 GPU_SMBCLK
GPU_SMBDAT
52 GPU_SMBDAT AMD RESERVED CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
3D3V_VGA

H2SYNC GENERICC

1
(R)
R400
4K7R2J-2-GP PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
19,42,43 DGPU_PWROK
DGPU_PWROK 1 R393 2 0R2J-2-GP SM_EN THEY MUST NOT CONFLICT DURING RESET

2
(R)

GPIO_28_TDO GPIO21_BB_EN
3D3V_VGA 3D3V_VGA Q39

G
2N7002-11-GP
(R)
1

S D
R408 R424
4K7R2J-2-GP (R) (R) 4K7R2J-2-GP

(R)0R2J-2-GP
2

GPU_SMBCLK 1 R421 2 PCH_SMBCLK


52 GPU_SMBCLK PCH_SMBCLK 3,12,13,15,29
GPU_SMBDAT 1 R402 2 PCH_SMBDATA
52 GPU_SMBDAT PCH_SMBDATA 3,12,13,15,29
(R) 0R2J-2-GP

S D

(R) Q38
2N7002-11-GP
G

B B

SM_EN

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ATI_THERM & STRAPS


Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 58 of 59
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserve
Size Document Number Rev
C
Catalina SA
Date: Tuesday, April 06, 2010 Sheet 59 of 59
5 4 3 2 1

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